diff --git a/arch/riscv64/defs.h b/arch/riscv64/defs.h
index 3a550d9..72ffb47 100644
--- a/arch/riscv64/defs.h
+++ b/arch/riscv64/defs.h
@@ -5,12 +5,28 @@
 #define MCONTEXT_GREGS	(176)
 
 /* program counter is saved in x0 as well as x1, similar to mips */
-#define REG_PC_SAVE	(0)
-#define REG_PC		(1)
+#ifndef REG_PC
+#define REG_PC		(0)
+#endif
+
+#ifndef REG_RA
+#define REG_RA		(1)
+#endif
+
+#ifndef REG_SP
 #define REG_SP		(2)
+#endif
+
+#ifndef REG_S0
 #define REG_S0		(8)
+#endif
+
 #define REG_S1		(9)
+
+#ifndef REG_A0
 #define REG_A0		(10)
+#endif
+
 #define REG_A1		(11)
 #define REG_A2		(12)
 #define REG_A3		(13)
@@ -29,7 +45,7 @@
 #define REG_S10		(26)
 #define REG_S11		(27)
 
-#define PC_OFFSET	REG_OFFSET(REG_PC_SAVE)
+#define PC_OFFSET	REG_OFFSET(REG_PC)
 
 #include "common-defs.h"
 
diff --git a/arch/riscv64/getcontext.S b/arch/riscv64/getcontext.S
index e468a4d..ab13614 100644
--- a/arch/riscv64/getcontext.S
+++ b/arch/riscv64/getcontext.S
@@ -15,8 +15,8 @@
 ALIAS(getcontext, __getcontext)
 
 FUNC(__getcontext)
-	sd ra, PC_OFFSET(a0)
 	sd ra, REG_OFFSET(REG_PC)(a0)
+	sd ra, REG_OFFSET(REG_RA)(a0)
 	sd sp, REG_OFFSET(REG_SP)(a0)
 
 	/* first saved register block */
diff --git a/arch/riscv64/makecontext.c b/arch/riscv64/makecontext.c
index 8fd26ed..e983316 100644
--- a/arch/riscv64/makecontext.c
+++ b/arch/riscv64/makecontext.c
@@ -36,12 +36,12 @@ __makecontext(ucontext_t *ucp, void (*func)(void), int argc, ...)
 	sp = (greg_t *) (((uintptr_t) sp & -16L));
 
 	/* set up the ucontext structure */
-	ucp->uc_mcontext.__gregs[REG_PC] = (greg_t) __start_context;
+	ucp->uc_mcontext.__gregs[REG_RA] = (greg_t) __start_context;
 	ucp->uc_mcontext.__gregs[REG_S0] = 0;
 	ucp->uc_mcontext.__gregs[REG_S1] = (greg_t) func;
 	ucp->uc_mcontext.__gregs[REG_S2] = (greg_t) ucp->uc_link;
 	ucp->uc_mcontext.__gregs[REG_SP] = (greg_t) sp;
-	ucp->uc_mcontext.__gregs[REG_PC_SAVE] = 0;
+	ucp->uc_mcontext.__gregs[REG_PC] = 0;
 
 	va_start(va, argc);
 
diff --git a/arch/riscv64/setcontext.S b/arch/riscv64/setcontext.S
index ddd0601..fc10c14 100644
--- a/arch/riscv64/setcontext.S
+++ b/arch/riscv64/setcontext.S
@@ -19,7 +19,7 @@ FUNC(__setcontext)
 	mv t0, a0
 
 	ld t1, PC_OFFSET(t0)
-	ld ra, REG_OFFSET(REG_PC)(t0)
+	ld ra, REG_OFFSET(REG_RA)(t0)
 	ld sp, REG_OFFSET(REG_SP)(t0)
 
 	/* first saved register block */
diff --git a/arch/riscv64/swapcontext.S b/arch/riscv64/swapcontext.S
index 30efada..794abfc 100644
--- a/arch/riscv64/swapcontext.S
+++ b/arch/riscv64/swapcontext.S
@@ -18,8 +18,8 @@ FUNC(__swapcontext)
 	/* move $a1 to $t0 to avoid clobbering. */
 	mv t0, a1
 
-	sd ra, PC_OFFSET(a0)
 	sd ra, REG_OFFSET(REG_PC)(a0)
+	sd ra, REG_OFFSET(REG_RA)(a0)
 	sd sp, REG_OFFSET(REG_SP)(a0)
 
 	/* first saved register block */
@@ -43,8 +43,8 @@ FUNC(__swapcontext)
 	sd s11, REG_OFFSET(REG_S11)(a0)
 
 	/* restore the other context from $t0. */
-	ld t1, PC_OFFSET(t0)
-	ld ra, REG_OFFSET(REG_PC)(t0)
+	ld t1, REG_OFFSET(REG_PC)(t0)
+	ld ra, REG_OFFSET(REG_RA)(t0)
 	ld sp, REG_OFFSET(REG_SP)(t0)
 
 	/* first saved register block */