224 lines
8.3 KiB
Diff
224 lines
8.3 KiB
Diff
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From a8ad22b83fbced140cc2fda699af57de869e2063 Mon Sep 17 00:00:00 2001
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From: Angel Pons <th3fanbus@gmail.com>
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Date: Mon, 10 May 2021 22:40:59 +0200
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Subject: [PATCH 7/9] nb/intel/gm45: Make DDR2 raminit work
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List of changes:
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- Update some timing and ODT values
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- Patch RCOMP calibration to better match what MRC binaries do
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- Replay a hardcoded list of RCOMP codes after RcvEn
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This makes raminit work at DDR2-800 speeds and fixes S3 resume as well.
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Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs.
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Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c
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Signed-off-by: Angel Pons <th3fanbus@gmail.com>
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---
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src/northbridge/intel/gm45/gm45.h | 2 +-
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src/northbridge/intel/gm45/raminit.c | 90 +++++++++++++++++--
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.../intel/gm45/raminit_rcomp_calibration.c | 27 ++++--
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3 files changed, 106 insertions(+), 13 deletions(-)
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diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
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index d929533d92..997f8a0e5a 100644
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--- a/src/northbridge/intel/gm45/gm45.h
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+++ b/src/northbridge/intel/gm45/gm45.h
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@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
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int raminit_read_vco_index(void);
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u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
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-void raminit_rcomp_calibration(stepping_t stepping);
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+void raminit_rcomp_calibration(int ddr_type, stepping_t stepping);
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void raminit_reset_readwrite_pointers(void);
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void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
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void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
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diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
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index b7e013959a..df8f46fbbc 100644
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--- a/src/northbridge/intel/gm45/raminit.c
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+++ b/src/northbridge/intel/gm45/raminit.c
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@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping,
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}
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/* Perform RCOMP calibration for DDR3. */
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- raminit_rcomp_calibration(stepping);
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+ raminit_rcomp_calibration(spd_type, stepping);
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/* Run initial RCOMP. */
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mchbar_setbits32(0x418, 1 << 17);
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@@ -1117,7 +1117,7 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
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reg = (reg & ~(0xf << 10)) | (2 << 10);
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else
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reg = (reg & ~(0xf << 10)) | (3 << 10);
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- reg = (reg & ~(0x7 << 5)) | (3 << 5);
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+ reg = (reg & ~(0x7 << 5)) | (2 << 5);
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} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
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reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
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reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
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@@ -1286,11 +1286,11 @@ static void ddr2_odt_setup(const timings_t *const timings, const int sff)
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reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32));
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reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32));
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if (timings->mem_clock == MEM_CLOCK_667MT) {
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- reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32));
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- reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32));
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+ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32));
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+ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32));
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} else {
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- reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32));
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- reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32));
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+ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32));
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+ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32));
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}
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mchbar_write32(CxODT_HIGH(ch), reg);
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@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
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raminit_write_training(timings->mem_clock, dimms, s3resume);
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}
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+ /*
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+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
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+ * after receiver enable calibration, otherwise raminit sometimes
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+ * completes with non-working memory.
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+ */
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+ mchbar_write32(0x0530, 0x06060005);
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+ mchbar_write32(0x0680, 0x06060606);
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+ mchbar_write32(0x0684, 0x08070606);
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+ mchbar_write32(0x0688, 0x0e0e0c0a);
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+ mchbar_write32(0x068c, 0x0e0e0e0e);
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+ mchbar_write32(0x0698, 0x06060606);
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+ mchbar_write32(0x069c, 0x08070606);
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+ mchbar_write32(0x06a0, 0x0c0c0b0a);
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+ mchbar_write32(0x06a4, 0x0c0c0c0c);
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+
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+ mchbar_write32(0x06c0, 0x02020202);
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+ mchbar_write32(0x06c4, 0x03020202);
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+ mchbar_write32(0x06c8, 0x04040403);
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+ mchbar_write32(0x06cc, 0x04040404);
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+ mchbar_write32(0x06d8, 0x02020202);
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+ mchbar_write32(0x06dc, 0x03020202);
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+ mchbar_write32(0x06e0, 0x04040403);
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+ mchbar_write32(0x06e4, 0x04040404);
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+
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+ mchbar_write32(0x0700, 0x02020202);
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+ mchbar_write32(0x0704, 0x03020202);
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+ mchbar_write32(0x0708, 0x04040403);
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+ mchbar_write32(0x070c, 0x04040404);
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+ mchbar_write32(0x0718, 0x02020202);
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+ mchbar_write32(0x071c, 0x03020202);
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+ mchbar_write32(0x0720, 0x04040403);
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+ mchbar_write32(0x0724, 0x04040404);
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+
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+ mchbar_write32(0x0740, 0x02020202);
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+ mchbar_write32(0x0744, 0x03020202);
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+ mchbar_write32(0x0748, 0x04040403);
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+ mchbar_write32(0x074c, 0x04040404);
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+ mchbar_write32(0x0758, 0x02020202);
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+ mchbar_write32(0x075c, 0x03020202);
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+ mchbar_write32(0x0760, 0x04040403);
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+ mchbar_write32(0x0764, 0x04040404);
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+
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+ mchbar_write32(0x0780, 0x06060606);
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+ mchbar_write32(0x0784, 0x09070606);
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+ mchbar_write32(0x0788, 0x0e0e0c0b);
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+ mchbar_write32(0x078c, 0x0e0e0e0e);
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+ mchbar_write32(0x0798, 0x06060606);
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+ mchbar_write32(0x079c, 0x09070606);
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+ mchbar_write32(0x07a0, 0x0d0d0c0b);
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+ mchbar_write32(0x07a4, 0x0d0d0d0d);
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+
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+ mchbar_write32(0x07c0, 0x06060606);
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+ mchbar_write32(0x07c4, 0x09070606);
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+ mchbar_write32(0x07c8, 0x0e0e0c0b);
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+ mchbar_write32(0x07cc, 0x0e0e0e0e);
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+ mchbar_write32(0x07d8, 0x06060606);
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+ mchbar_write32(0x07dc, 0x09070606);
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+ mchbar_write32(0x07e0, 0x0d0d0c0b);
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+ mchbar_write32(0x07e4, 0x0d0d0d0d);
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+
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+ mchbar_write32(0x0840, 0x06060606);
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+ mchbar_write32(0x0844, 0x08070606);
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+ mchbar_write32(0x0848, 0x0e0e0c0a);
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+ mchbar_write32(0x084c, 0x0e0e0e0e);
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+ mchbar_write32(0x0858, 0x06060606);
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+ mchbar_write32(0x085c, 0x08070606);
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+ mchbar_write32(0x0860, 0x0c0c0b0a);
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+ mchbar_write32(0x0864, 0x0c0c0c0c);
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+
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+ mchbar_write32(0x0880, 0x02020202);
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+ mchbar_write32(0x0884, 0x03020202);
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+ mchbar_write32(0x0888, 0x04040403);
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+ mchbar_write32(0x088c, 0x04040404);
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+ mchbar_write32(0x0898, 0x02020202);
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+ mchbar_write32(0x089c, 0x03020202);
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+ mchbar_write32(0x08a0, 0x04040403);
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+ mchbar_write32(0x08a4, 0x04040404);
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+
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igd_compute_ggc(sysinfo);
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/* Program final memory map (with real values). */
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diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
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index aef863f05a..b74765fd9c 100644
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--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
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+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
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@@ -161,11 +161,13 @@ static void lookup_and_write(const int a1step,
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mchbar += 4;
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}
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}
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-void raminit_rcomp_calibration(const stepping_t stepping) {
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+void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
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const int a1step = stepping >= STEPPING_CONVERSION_A1;
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int i;
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+ char magic_comp[2] = {0};
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+
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enum {
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PULL_UP = 0,
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PULL_DOWN = 1,
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@@ -196,6 +198,10 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
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reg = mchbar_read32(0x518);
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lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
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lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
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+ if (i == 1) {
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+ magic_comp[0] = (reg >> 8) & 0x3f;
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+ magic_comp[1] = (reg >> 0) & 0x3f;
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+ }
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}
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/* Cleanup? */
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mchbar_setbits32(0x400, 1 << 3);
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@@ -216,13 +222,19 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
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for (channel = 0; channel < 2; ++channel) {
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for (group = 0; group < 6; ++group) {
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for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) {
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- lookup_and_write(
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- a1step,
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- lut_idx[channel][group][pu_pd] - 7,
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- ddr3_lookup_schedule[group][pu_pd],
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- mchbar);
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+ if (ddr_type == DDR3) {
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+ lookup_and_write(
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+ a1step,
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+ lut_idx[channel][group][pu_pd] - 7,
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+ ddr3_lookup_schedule[group][pu_pd],
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+ mchbar);
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+ }
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mchbar += 0x0018;
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}
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+ if (ddr_type == DDR2) {
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+ mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24);
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+ mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0);
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+ }
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mchbar += 0x0010;
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/* Channel B knows only the first two groups. */
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if ((1 == channel) && (1 == group))
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@@ -230,4 +242,7 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
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}
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mchbar += 0x0040;
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}
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+
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+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
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+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
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}
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--
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2.39.2
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