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coreboot/default: bump to 97bc693ab (2024-07-29) 

same as the recent update in lbmk, but adapted for cbmk,
e.g. the patches to disable microcode blobs by default.

i copied it from the lbmk update but updated nuke.list
and excluded certain patches not needed in canoeboot, such
as the new dell latitude patches and haswell nri

The coreboot/dell tree was also merged to /default, just
like in lbmk. This puts Canoeboot completely  in sync,
but with deblobbing as is customary for Canoeboot.

Signed-off-by: Leah Rowe <info@minifree.org>
master
Leah Rowe 2024-08-14 21:53:39 +01:00
parent e4d2c38903
commit 4564c44ebe
175 changed files with 3040 additions and 5963 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
config/coreboot/coreboot413/patches/0001-cbfstool-Make-use-of-spurious-null-termination.patch Normal file
View File

@ -0,0 +1,56 @@
From f22f408956bf02609a96b7d72fb3321da159bfc6 Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.huber@secunet.com>
Date: Tue, 22 Jun 2021 13:49:44 +0000
Subject: [PATCH 1/1] cbfstool: Make use of spurious null-termination
The null-termination of `filetypes` was added after the code was
written, obviously resulting in NULL dereferences. As some more
code has grown around the termination, it's hard to revert the
regression, so let's update the code that still used the array
length.
This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
which actually did fix something, but only one path while it broke
two others. We should be careful with fixes, they can always break
something else. Especially when a dumb tool triggered the patching
it seems likely that fewer people looked into related code.
Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
util/cbfstool/common.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index e2ed38ffc4..539d0baccf 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -168,10 +168,10 @@ void print_supported_architectures(void)
void print_supported_filetypes(void)
{
- int i, number = ARRAY_SIZE(filetypes);
+ int i;
- for (i=0; i<number; i++) {
- printf(" %s%c", filetypes[i].name, (i==(number-1))?'\n':',');
+ for (i=0; filetypes[i].name; i++) {
+ printf(" %s%c", filetypes[i].name, filetypes[i + 1].name ? ',' : '\n');
if ((i%8) == 7)
printf("\n");
}
@@ -180,7 +180,7 @@ void print_supported_filetypes(void)
uint64_t intfiletype(const char *name)
{
size_t i;
- for (i = 0; i < (sizeof(filetypes) / sizeof(struct typedesc_t)); i++)
+ for (i = 0; filetypes[i].name; i++)
if (strcmp(filetypes[i].name, name) == 0)
return filetypes[i].type;
return -1;
--
2.39.2

2
config/coreboot/coreboot413/target.cfg Normal file
View File

@ -0,0 +1,2 @@
tree="coreboot413"
rev="5c186c6777c9438ff4681929c9c25c98dee28bef"

34
config/coreboot/d510mo/config/libgfxinit_txtmode
View File

@ -6,7 +6,6 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
@ -26,7 +25,9 @@ CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
@ -35,7 +36,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -53,8 +53,8 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
@ -65,11 +65,13 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
@ -91,6 +93,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -121,11 +124,15 @@ CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
@ -140,14 +147,13 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@ -155,7 +161,9 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
@ -203,12 +211,13 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@ -248,6 +257,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x80000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -256,7 +266,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@ -291,6 +300,7 @@ CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -368,6 +378,7 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
# end of Chipset
#
@ -455,6 +466,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -507,7 +520,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console

34
config/coreboot/d510mo_16mb/config/libgfxinit_txtmode
View File

@ -6,7 +6,6 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
@ -26,7 +25,9 @@ CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
@ -35,7 +36,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -53,8 +53,8 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
@ -65,11 +65,13 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
@ -91,6 +93,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -121,11 +124,15 @@ CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
@ -140,14 +147,13 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@ -155,7 +161,9 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
@ -203,12 +211,13 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@ -248,6 +257,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x80000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -256,7 +266,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@ -291,6 +300,7 @@ CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -368,6 +378,7 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
# end of Chipset
#
@ -455,6 +466,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -507,7 +520,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console

34
config/coreboot/d945gclf_512kb/config/libgfxinit_txtmode
View File

@ -6,7 +6,6 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
@ -26,7 +25,9 @@ CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
@ -35,7 +36,6 @@ CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -53,8 +53,8 @@ CONFIG_TSEG_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
@ -65,11 +65,13 @@ CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
@ -91,6 +93,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -122,11 +125,15 @@ CONFIG_DEVICETREE="devicetree.cb"
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
@ -141,14 +148,13 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@ -156,7 +162,9 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
@ -201,13 +209,14 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
CONFIG_COREBOOT_ROMSIZE_KB_512=y
@ -247,6 +256,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -255,7 +265,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@ -290,6 +299,7 @@ CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -367,6 +377,7 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
# end of Chipset
#
@ -449,6 +460,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -501,7 +514,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console

34
config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode
View File

@ -6,7 +6,6 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
@ -26,7 +25,9 @@ CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
@ -35,7 +36,6 @@ CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -53,8 +53,8 @@ CONFIG_TSEG_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
@ -65,11 +65,13 @@ CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
@ -91,6 +93,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -122,11 +125,15 @@ CONFIG_DEVICETREE="devicetree.cb"
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
@ -141,14 +148,13 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@ -156,7 +162,9 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
@ -201,13 +209,14 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@ -247,6 +256,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -255,7 +265,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@ -290,6 +299,7 @@ CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -367,6 +377,7 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
# end of Chipset
#
@ -449,6 +460,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -501,7 +514,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console

8
config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
View File

@ -1,7 +1,7 @@
From 055aa5908de03c21989474c58e44de596b0a8cd1 Mon Sep 17 00:00:00 2001
From 2d9f38a12b883e1ddcdae5de107f204e522146e2 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@retroboot.org>
Date: Fri, 19 Mar 2021 05:54:58 +0000
Subject: [PATCH 01/16] apple/macbook21: Set default VRAM to 64MiB instead of
Subject: [PATCH 01/39] apple/macbook21: Set default VRAM to 64MiB instead of
8MiB
---
@ -9,10 +9,10 @@ Subject: [PATCH 01/16] apple/macbook21: Set default VRAM to 64MiB instead of
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
index cf1bc4566e..dc0df3b6d6 100644
index b744b11cda..9749e26547 100644
--- a/src/mainboard/apple/macbook21/cmos.default
+++ b/src/mainboard/apple/macbook21/cmos.default
@@ -5,4 +5,4 @@ boot_devices=''
@@ -7,4 +7,4 @@ boot_devices=''
boot_default=0x40
cmos_defaults_loaded=Yes
lpt=Enable

8
config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch
View File

@ -1,7 +1,7 @@
From dd21a7a6c1961d314db7fdabd6982d71930b0f1a Mon Sep 17 00:00:00 2001
From e60ec1c7304e3f167fd2bf762f28b7eacd0b169a Mon Sep 17 00:00:00 2001
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
Date: Wed, 27 Oct 2021 13:36:01 +0200
Subject: [PATCH 02/16] add c3 and clockgen to apple/macbook21
Subject: [PATCH 02/39] add c3 and clockgen to apple/macbook21
---
src/mainboard/apple/macbook21/Kconfig | 1 +
@ -10,10 +10,10 @@ Subject: [PATCH 02/16] add c3 and clockgen to apple/macbook21
3 files changed, 20 insertions(+)
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
index 5f5ffde588..27377b737c 100644
index 330d8efae2..cf10343554 100644
--- a/src/mainboard/apple/macbook21/Kconfig
+++ b/src/mainboard/apple/macbook21/Kconfig
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select I945_LVDS

8
config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
View File

@ -1,7 +1,7 @@
From b21dd52d01aa8d4d8984b4b4ec5b4e850d7a2637 Mon Sep 17 00:00:00 2001
From 9a0157b1459365cf52f90e66b78dd6b60a259587 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Sun, 3 Jan 2021 03:34:01 +0000
Subject: [PATCH 03/16] lenovo/x60: 64MiB Video RAM changed to default
Subject: [PATCH 03/39] lenovo/x60: 64MiB Video RAM changed to default
(previously it was 8MiB)
---
@ -9,10 +9,10 @@ Subject: [PATCH 03/16] lenovo/x60: 64MiB Video RAM changed to default
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
index 5c3576d1f3..88170a1aab 100644
index 58825c8a36..8e0aaf427d 100644
--- a/src/mainboard/lenovo/x60/cmos.default
+++ b/src/mainboard/lenovo/x60/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
@@ -17,4 +17,4 @@ trackpoint=Enable
sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable

8
config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
View File

@ -1,17 +1,17 @@
From 7b402976cb0047cf70dabf6b90e5625b4e9d2775 Mon Sep 17 00:00:00 2001
From 5b2a26e72bce37f7b0a92f1ed93fd607cea8de9b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Mon, 22 Feb 2021 22:16:59 +0000
Subject: [PATCH 04/16] lenovo/t60: make 64MiB VRAM the default in cmos.default
Subject: [PATCH 04/39] lenovo/t60: make 64MiB VRAM the default in cmos.default
---
src/mainboard/lenovo/t60/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
index af865f16da..7f03157df7 100644
index 283a5747ee..91f6c0e6e2 100644
--- a/src/mainboard/lenovo/t60/cmos.default
+++ b/src/mainboard/lenovo/t60/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
@@ -17,4 +17,4 @@ trackpoint=Enable
sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable

8
config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch
View File

@ -1,7 +1,7 @@
From d0abb102ec610a3314d9e8b6f9f8bf951fe5ab3d Mon Sep 17 00:00:00 2001
From 945d84782e706e8f3effab57edca68d9463d21fc Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:10:33 +0100
Subject: [PATCH 05/16] lenovo/t400: set VRAM to 256MiB VRAM by default
Subject: [PATCH 05/39] lenovo/t400: set VRAM to 256MiB VRAM by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
index a326e315b1..b907a3e2df 100644
index a16d386dd1..e7bb32306c 100644
--- a/src/mainboard/lenovo/t400/cmos.default
+++ b/src/mainboard/lenovo/t400/cmos.default
@@ -13,4 +13,4 @@ power_management_beeps=Enable
@@ -15,4 +15,4 @@ power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
hybrid_graphics_mode=Integrated Only

8
config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch
View File

@ -1,7 +1,7 @@
From 0262681a1871a70c66512182163bd7035f008f2f Mon Sep 17 00:00:00 2001
From 112470b4f7b046ec2656699336211ba63ff448fa Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:11:59 +0100
Subject: [PATCH 06/16] lenovo/x200: set VRAM to 256MiB by default
Subject: [PATCH 06/39] lenovo/x200: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
index bb4323836e..458b3f19c5 100644
index 434af5d227..443ef54e41 100644
--- a/src/mainboard/lenovo/x200/cmos.default
+++ b/src/mainboard/lenovo/x200/cmos.default
@@ -12,4 +12,4 @@ sticky_fn=Disable
@@ -14,4 +14,4 @@ sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI

8
config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch
View File

@ -1,7 +1,7 @@
From b8eaf580f5d8242692b78aa6b771ee3051f08278 Mon Sep 17 00:00:00 2001
From 37418629a56cb740cae2870317458ea52daad8c9 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:18:26 +0100
Subject: [PATCH 07/16] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
Subject: [PATCH 07/39] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
index 8372032119..bedad54d2a 100644
index fe79c83570..4a1f97a9d8 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
@@ -4,4 +4,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Enable
nmi=Enable

8
config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch
View File

@ -1,7 +1,7 @@
From 0c54eb497ee49b09be2aa6e7cba816f069dac31c Mon Sep 17 00:00:00 2001
From e785387dffe382a02d4c0cb006cced48c235484c Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:21:39 +0100
Subject: [PATCH 08/16] acer/g43t-am3: set VRAM to 256MiB by default
Subject: [PATCH 08/39] acer/g43t-am3: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
index 706f5dd551..e8b45ea22c 100644
index 23f0e55f3e..8d6c4db1ce 100644
--- a/src/mainboard/acer/g43t-am3/cmos.default
+++ b/src/mainboard/acer/g43t-am3/cmos.default
@@ -3,4 +3,4 @@ debug_level=Debug
@@ -5,4 +5,4 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI

4
config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch
View File

@ -1,7 +1,7 @@
From 8c47a1e2fe58a7f841f85bc48a2b3857f529e562 Mon Sep 17 00:00:00 2001
From 3659aec797baa40e4336e88361a705295fb72b0f Mon Sep 17 00:00:00 2001
From: persmule <persmule@gmail.com>
Date: Sun, 31 Oct 2021 23:33:26 +0000
Subject: [PATCH 09/16] lenovo/t400: Enable all SATA ports
Subject: [PATCH 09/39] lenovo/t400: Enable all SATA ports
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its

22
config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch Normal file
View File

@ -0,0 +1,22 @@
From 820c2d64a7415f7159fd7cdac4746049c91f89a2 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 20 Dec 2021 01:29:31 +0000
Subject: [PATCH 10/39] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
default
---
src/mainboard/lenovo/x230/cmos.default | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
index 732e214b32..3bb78960b9 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
@@ -18,3 +18,4 @@ backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
me_state=Normal
+gfx_uma_size=224M
--
2.39.2

39
config/coreboot/default/patches/0014-don-t-use-github-for-the-acpica-download.patch
View File

@ -1,39 +0,0 @@
From 259ee5e7e502bf741c91ebfd79e83e6a5c8db5ae Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 22 Oct 2023 15:02:25 +0100
Subject: [PATCH 14/16] don't use github for the acpica download
i have the tarball from a previous download, and i placed
it on libreboot rsync, which then got mirrored to princeton.
today, github's ssl cert was b0rking the hell out and i really
really wanted to finish a build, and didn't want to wait for
github to fix their httpd.
so i'm now hosting this specific acpica tarball on rsync.
this patch makes that URL be used, instead of the github one.
that's the 2nd time i've had to patch coreboot's acpica download!
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 23a5caf2bb..36565a906c 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2

6
config/coreboot/default/patches/0010-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch → config/coreboot/default/patches/0014-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
View File

@ -1,7 +1,7 @@
From 4c1d8640d9d7070220a2282ca922554fd1732b2d Mon Sep 17 00:00:00 2001
From c53e5035b612710595abc93f0b4c3c65ca61ebad Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
Subject: [PATCH 10/16] fix speedstep on x200/t400: Revert
Subject: [PATCH 14/39] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
@ -16,7 +16,7 @@ maintain this revert patch in Libreboot, from now on.
1 file changed, 9 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 315e7c36fc..1423fd72bc 100644
index d051e8915b..30ba2bf0c6 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)

6
config/coreboot/default/patches/0011-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch → config/coreboot/default/patches/0015-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
View File

@ -1,7 +1,7 @@
From a51465970b87d4d8464ae66affa144217c70b185 Mon Sep 17 00:00:00 2001
From dabe942b006082f6e592a26f1d0f13a2586b53d6 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 17 Apr 2023 15:49:57 +0100
Subject: [PATCH 11/16] GM45-type CPUs: don't enable alternative SMRR
Subject: [PATCH 15/39] GM45-type CPUs: don't enable alternative SMRR
This reverts the changes in coreboot revision:
df7aecd92643d207feaf7fd840f8835097346644
@ -42,7 +42,7 @@ Pragmatism is a good thing. I recommend it.
5 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 1423fd72bc..d1f98ca43a 100644
index 30ba2bf0c6..312046901a 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -8,6 +8,7 @@

36
config/coreboot/default/patches/0015-use-mirrorservice.org-for-gcc-downloads.patch
View File

@ -1,36 +0,0 @@
From a962fdfe4437b266540ff6d1696993827a16508d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 22:57:08 +0000
Subject: [PATCH 15/16] use mirrorservice.org for gcc downloads
the gnu.org 302 redirect often fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 36565a906c..4d4ca06113 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
# to the jenkins build as well, or the builder won't download it.
# GCC toolchain archive locations
-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2

6
config/coreboot/dell/patches/0003-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch → config/coreboot/default/patches/0016-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
View File

@ -1,8 +1,8 @@
From e2070df8fe94e3ad4b5d6a544fb7f7fc1b61c5f9 Mon Sep 17 00:00:00 2001
From 6426e07c7da50d588ee1ca30e0911040d89e4c96 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 6 May 2023 15:53:41 -0600
Subject: [PATCH 3/9] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU
models
Subject: [PATCH 16/39] mb/dell/e6400: Enable 01.0 device in devicetree for
dGPU models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>

8
config/coreboot/default/patches/0012-Remove-warning-for-coreboot-images-built-without-a-p.patch → config/coreboot/default/patches/0017-Remove-warning-for-coreboot-images-built-without-a-p.patch
View File

@ -1,7 +1,7 @@
From 79b5f92cd7fa77f9139268aaf6aa0c2bcf5c8e9f Mon Sep 17 00:00:00 2001
From 29a654eaaa7bf924f9681a2520dbabfe12619269 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
Subject: [PATCH 12/16] Remove warning for coreboot images built without a
Subject: [PATCH 17/39] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
@ -13,10 +13,10 @@ up. This has caused confusion and concern so just patch it out.
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
index a2336aa876..4f1692a873 100644
index 5f988dac1b..516133880f 100644
--- a/payloads/Makefile.mk
+++ b/payloads/Makefile.mk
@@ -49,16 +49,5 @@ distclean-payloads:
@@ -50,16 +50,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )

8
config/coreboot/default/patches/0013-HACK-Disable-coreboot-related-BL31-features.patch → config/coreboot/default/patches/0028-HACK-Disable-coreboot-related-BL31-features.patch
View File

@ -1,7 +1,7 @@
From ababcb1acecf09a736aaeb659e3ca4851b27341b Mon Sep 17 00:00:00 2001
From ea6e8749112dee4f458e9cf591e13e9097d56bab Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Date: Thu, 22 Jun 2023 16:44:27 +0300
Subject: [PATCH 13/16] HACK: Disable coreboot related BL31 features
Subject: [PATCH 28/39] HACK: Disable coreboot related BL31 features
I don't know why, but removing this BL31 make argument lets gru-kevin
power off properly when shut down from Linux. Needs investigation.
@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation.
1 file changed, 3 deletions(-)
diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
index 538d254ace..18e451d63c 100644
index cb43897efd..a9e5ff399a 100644
--- a/src/arch/arm64/Makefile.mk
+++ b/src/arch/arm64/Makefile.mk
@@ -159,9 +159,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
@@ -173,9 +173,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
# Always enable crash reporting, even on a release build
BL31_MAKEARGS += CRASH_REPORTING=1

29
config/coreboot/default/patches/0029-use-own-mirror-for-acpica-files.patch Normal file
View File

@ -0,0 +1,29 @@
From 5c385ef4b4424ed8c37e549a00866edda960563f Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Wed, 31 Jul 2024 00:03:02 +0100
Subject: [PATCH 29/39] use own mirror for acpica files
intel likes to break links for no reason,
so we host our own backups of acpica.
Signed-off-by: Leah Rowe <info@minifree.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index ad756652ed..5faff337b4 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -74,7 +74,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://downloadmirror.intel.com/783534"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2

8
config/coreboot/dell/patches/0006-use-mirrorservice.org-for-gcc-downloads.patch → config/coreboot/default/patches/0032-use-mirrorservice.org-for-gcc-downloads.patch
View File

@ -1,7 +1,7 @@
From 9f1f72d0c9eaeff4f70accffc22c1c2183ebf2e6 Mon Sep 17 00:00:00 2001
From adb6121970034aa63da8c6303292ff81f340d9db Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 22:57:08 +0000
Subject: [PATCH 6/9] use mirrorservice.org for gcc downloads
Subject: [PATCH 32/39] use mirrorservice.org for gcc downloads
the gnu.org 302 redirect often fails
@ -11,10 +11,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 36565a906c..4d4ca06113 100755
index 5faff337b4..2743f96903 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
@@ -69,11 +69,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
# to the jenkins build as well, or the builder won't download it.
# GCC toolchain archive locations

6
config/coreboot/default/patches/0045-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch → config/coreboot/default/patches/0037-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch
View File

@ -1,7 +1,7 @@
From a8c4f7004ea1c9b8268a87dd0b700c250ec4747d Mon Sep 17 00:00:00 2001
From 7e921212d3113320b2d28e66cd6a6788533fcab7 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 3 May 2024 11:03:32 -0600
Subject: [PATCH] ec/dell/mec5035: Add S3 suspend SMI handler
Subject: [PATCH 37/39] ec/dell/mec5035: Add S3 suspend SMI handler
Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@ -113,5 +113,5 @@ index 0000000000..1db834773d
+ }
+}
--
2.44.0
2.39.2

31
config/coreboot/default/patches/0038-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch Normal file
View File

@ -0,0 +1,31 @@
From 53bddae0fc8436fe262ca7fc2e19049afa7a38f8 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 3 May 2024 16:31:12 -0600
Subject: [PATCH 38/39] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes
This should fix S3 suspend on these systems
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++
1 file changed, 9 insertions(+)
create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c
diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
--
2.39.2

8
config/coreboot/dell/patches/0007-nb-intel-gm45-Make-DDR2-raminit-work.patch → config/coreboot/default/patches/0040-nb-intel-gm45-Make-DDR2-raminit-work.patch
View File

@ -1,7 +1,7 @@
From a8ad22b83fbced140cc2fda699af57de869e2063 Mon Sep 17 00:00:00 2001
From fe5e1655be8cdb8eff1659e5ce6acbd06b9a7620 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 10 May 2021 22:40:59 +0200
Subject: [PATCH 7/9] nb/intel/gm45: Make DDR2 raminit work
Subject: [PATCH 1/3] nb/intel/gm45: Make DDR2 raminit work
List of changes:
- Update some timing and ODT values
@ -20,10 +20,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
3 files changed, 106 insertions(+), 13 deletions(-)
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index d929533d92..997f8a0e5a 100644
index 5d9ac56606..338260ea7a 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
int raminit_read_vco_index(void);
u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);

240
config/coreboot/default/patches/0041-nb-intel-gm45-Make-DDR2-raminit-work.patch Normal file
View File

@ -0,0 +1,240 @@
From 88a9c562b77316f1217139e62425f9af1c351c6f Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Tue, 6 Aug 2024 00:50:24 +0100
Subject: [PATCH 41/59] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
We add this patch:
commit commit_id_here
Author: Angel Pons <th3fanbus@gmail.com>
Date: Mon May 10 22:40:59 2021 +0200
nb/intel/gm45: Make DDR2 raminit work
This patch was original applied, in lbmk, only on coreboot/dell,
separately from coreboot/default, which was wasteful because it
meant having an entire coreboot tree just for a single board. We
did this, because the DDR2 RCOMP fix happened to break DDR3 init
on other boards.
What *this* new patch does on top of Angel's patch, is make sure
that their changes only apply to DDR2, while DDR3 behaviour remains
unchanged. This means that the Dell Latitude E6400 can be supported
in the main coreboot tree, within lbmk.
Essentially, this patch restores the old behaviour, prior to applying
Angel's patch, only when DDR3 memory is used.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/northbridge/intel/gm45/raminit.c | 161 +++++++++---------
.../intel/gm45/raminit_rcomp_calibration.c | 9 +-
2 files changed, 88 insertions(+), 82 deletions(-)
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index df8f46fbbc..433db3a68c 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
reg = (reg & ~(0xf << 10)) | (2 << 10);
else
reg = (reg & ~(0xf << 10)) | (3 << 10);
- reg = (reg & ~(0x7 << 5)) | (2 << 5);
+ if (spd_type == DDR2)
+ reg = (reg & ~(0x7 << 5)) | (2 << 5);
+ else
+ reg = (reg & ~(0x7 << 5)) | (3 << 5);
} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
raminit_write_training(timings->mem_clock, dimms, s3resume);
}
- /*
- * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
- * after receiver enable calibration, otherwise raminit sometimes
- * completes with non-working memory.
- */
- mchbar_write32(0x0530, 0x06060005);
- mchbar_write32(0x0680, 0x06060606);
- mchbar_write32(0x0684, 0x08070606);
- mchbar_write32(0x0688, 0x0e0e0c0a);
- mchbar_write32(0x068c, 0x0e0e0e0e);
- mchbar_write32(0x0698, 0x06060606);
- mchbar_write32(0x069c, 0x08070606);
- mchbar_write32(0x06a0, 0x0c0c0b0a);
- mchbar_write32(0x06a4, 0x0c0c0c0c);
-
- mchbar_write32(0x06c0, 0x02020202);
- mchbar_write32(0x06c4, 0x03020202);
- mchbar_write32(0x06c8, 0x04040403);
- mchbar_write32(0x06cc, 0x04040404);
- mchbar_write32(0x06d8, 0x02020202);
- mchbar_write32(0x06dc, 0x03020202);
- mchbar_write32(0x06e0, 0x04040403);
- mchbar_write32(0x06e4, 0x04040404);
-
- mchbar_write32(0x0700, 0x02020202);
- mchbar_write32(0x0704, 0x03020202);
- mchbar_write32(0x0708, 0x04040403);
- mchbar_write32(0x070c, 0x04040404);
- mchbar_write32(0x0718, 0x02020202);
- mchbar_write32(0x071c, 0x03020202);
- mchbar_write32(0x0720, 0x04040403);
- mchbar_write32(0x0724, 0x04040404);
-
- mchbar_write32(0x0740, 0x02020202);
- mchbar_write32(0x0744, 0x03020202);
- mchbar_write32(0x0748, 0x04040403);
- mchbar_write32(0x074c, 0x04040404);
- mchbar_write32(0x0758, 0x02020202);
- mchbar_write32(0x075c, 0x03020202);
- mchbar_write32(0x0760, 0x04040403);
- mchbar_write32(0x0764, 0x04040404);
-
- mchbar_write32(0x0780, 0x06060606);
- mchbar_write32(0x0784, 0x09070606);
- mchbar_write32(0x0788, 0x0e0e0c0b);
- mchbar_write32(0x078c, 0x0e0e0e0e);
- mchbar_write32(0x0798, 0x06060606);
- mchbar_write32(0x079c, 0x09070606);
- mchbar_write32(0x07a0, 0x0d0d0c0b);
- mchbar_write32(0x07a4, 0x0d0d0d0d);
-
- mchbar_write32(0x07c0, 0x06060606);
- mchbar_write32(0x07c4, 0x09070606);
- mchbar_write32(0x07c8, 0x0e0e0c0b);
- mchbar_write32(0x07cc, 0x0e0e0e0e);
- mchbar_write32(0x07d8, 0x06060606);
- mchbar_write32(0x07dc, 0x09070606);
- mchbar_write32(0x07e0, 0x0d0d0c0b);
- mchbar_write32(0x07e4, 0x0d0d0d0d);
-
- mchbar_write32(0x0840, 0x06060606);
- mchbar_write32(0x0844, 0x08070606);
- mchbar_write32(0x0848, 0x0e0e0c0a);
- mchbar_write32(0x084c, 0x0e0e0e0e);
- mchbar_write32(0x0858, 0x06060606);
- mchbar_write32(0x085c, 0x08070606);
- mchbar_write32(0x0860, 0x0c0c0b0a);
- mchbar_write32(0x0864, 0x0c0c0c0c);
-
- mchbar_write32(0x0880, 0x02020202);
- mchbar_write32(0x0884, 0x03020202);
- mchbar_write32(0x0888, 0x04040403);
- mchbar_write32(0x088c, 0x04040404);
- mchbar_write32(0x0898, 0x02020202);
- mchbar_write32(0x089c, 0x03020202);
- mchbar_write32(0x08a0, 0x04040403);
- mchbar_write32(0x08a4, 0x04040404);
+ if (sysinfo->spd_type == DDR2) {
+ /*
+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
+ * after receiver enable calibration, otherwise raminit sometimes
+ * completes with non-working memory.
+ */
+ mchbar_write32(0x0530, 0x06060005);
+ mchbar_write32(0x0680, 0x06060606);
+ mchbar_write32(0x0684, 0x08070606);
+ mchbar_write32(0x0688, 0x0e0e0c0a);
+ mchbar_write32(0x068c, 0x0e0e0e0e);
+ mchbar_write32(0x0698, 0x06060606);
+ mchbar_write32(0x069c, 0x08070606);
+ mchbar_write32(0x06a0, 0x0c0c0b0a);
+ mchbar_write32(0x06a4, 0x0c0c0c0c);
+
+ mchbar_write32(0x06c0, 0x02020202);
+ mchbar_write32(0x06c4, 0x03020202);
+ mchbar_write32(0x06c8, 0x04040403);
+ mchbar_write32(0x06cc, 0x04040404);
+ mchbar_write32(0x06d8, 0x02020202);
+ mchbar_write32(0x06dc, 0x03020202);
+ mchbar_write32(0x06e0, 0x04040403);
+ mchbar_write32(0x06e4, 0x04040404);
+
+ mchbar_write32(0x0700, 0x02020202);
+ mchbar_write32(0x0704, 0x03020202);
+ mchbar_write32(0x0708, 0x04040403);
+ mchbar_write32(0x070c, 0x04040404);
+ mchbar_write32(0x0718, 0x02020202);
+ mchbar_write32(0x071c, 0x03020202);
+ mchbar_write32(0x0720, 0x04040403);
+ mchbar_write32(0x0724, 0x04040404);
+
+ mchbar_write32(0x0740, 0x02020202);
+ mchbar_write32(0x0744, 0x03020202);
+ mchbar_write32(0x0748, 0x04040403);
+ mchbar_write32(0x074c, 0x04040404);
+ mchbar_write32(0x0758, 0x02020202);
+ mchbar_write32(0x075c, 0x03020202);
+ mchbar_write32(0x0760, 0x04040403);
+ mchbar_write32(0x0764, 0x04040404);
+
+ mchbar_write32(0x0780, 0x06060606);
+ mchbar_write32(0x0784, 0x09070606);
+ mchbar_write32(0x0788, 0x0e0e0c0b);
+ mchbar_write32(0x078c, 0x0e0e0e0e);
+ mchbar_write32(0x0798, 0x06060606);
+ mchbar_write32(0x079c, 0x09070606);
+ mchbar_write32(0x07a0, 0x0d0d0c0b);
+ mchbar_write32(0x07a4, 0x0d0d0d0d);
+
+ mchbar_write32(0x07c0, 0x06060606);
+ mchbar_write32(0x07c4, 0x09070606);
+ mchbar_write32(0x07c8, 0x0e0e0c0b);
+ mchbar_write32(0x07cc, 0x0e0e0e0e);
+ mchbar_write32(0x07d8, 0x06060606);
+ mchbar_write32(0x07dc, 0x09070606);
+ mchbar_write32(0x07e0, 0x0d0d0c0b);
+ mchbar_write32(0x07e4, 0x0d0d0d0d);
+
+ mchbar_write32(0x0840, 0x06060606);
+ mchbar_write32(0x0844, 0x08070606);
+ mchbar_write32(0x0848, 0x0e0e0c0a);
+ mchbar_write32(0x084c, 0x0e0e0e0e);
+ mchbar_write32(0x0858, 0x06060606);
+ mchbar_write32(0x085c, 0x08070606);
+ mchbar_write32(0x0860, 0x0c0c0b0a);
+ mchbar_write32(0x0864, 0x0c0c0c0c);
+
+ mchbar_write32(0x0880, 0x02020202);
+ mchbar_write32(0x0884, 0x03020202);
+ mchbar_write32(0x0888, 0x04040403);
+ mchbar_write32(0x088c, 0x04040404);
+ mchbar_write32(0x0898, 0x02020202);
+ mchbar_write32(0x089c, 0x03020202);
+ mchbar_write32(0x08a0, 0x04040403);
+ mchbar_write32(0x08a4, 0x04040404);
+ }
igd_compute_ggc(sysinfo);
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
index b74765fd9c..5d4505e063 100644
--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
reg = mchbar_read32(0x518);
lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
- if (i == 1) {
+ if ((i == 1) && (ddr_type == DDR2)) {
magic_comp[0] = (reg >> 8) & 0x3f;
magic_comp[1] = (reg >> 0) & 0x3f;
}
@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
}
mchbar += 0x0040;
}
-
- mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
- mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
+ if (ddr_type == DDR2) {
+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
+ }
}
--
2.39.2

14
config/coreboot/dell/patches/0010-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch → config/coreboot/default/patches/0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
View File

@ -1,7 +1,7 @@
From 6f4968919cf4e801caacf8392492457b79efa9c6 Mon Sep 17 00:00:00 2001
From b42ca30081b25cbabfb2659adca9d935ef3a8399 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 20 May 2024 10:24:16 -0600
Subject: [PATCH] mb/dell/e6400: Use 100 MHz reference clock for display
Subject: [PATCH 3/3] mb/dell/e6400: Use 100 MHz reference clock for display
The E6400 uses a 100 MHz reference clock for spread spectrum support on
LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
@ -19,10 +19,10 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2 files changed, 7 insertions(+)
diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
index 034de4be2b..4cb16af697 100644
index 417d95fd5d..6fe1b1c456 100644
--- a/src/mainboard/dell/e6400/Kconfig
+++ b/src/mainboard/dell/e6400/Kconfig
@@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS
@@ -19,6 +19,9 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_GMA_HAVE_VBT
select EC_DELL_MEC5035
@ -33,10 +33,10 @@ index 034de4be2b..4cb16af697 100644
default "dell/e6400"
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 2a266b9771..2432c9d78e 100644
index 8059e7ee80..5df5a93296 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -13,6 +13,10 @@ config NORTHBRIDGE_INTEL_GM45
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45
if NORTHBRIDGE_INTEL_GM45
@ -48,5 +48,5 @@ index 2a266b9771..2432c9d78e 100644
select VBOOT_STARTS_IN_BOOTBLOCK
--
2.45.1
2.39.2

133
config/coreboot/default/patches/0046-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch
View File

@ -1,133 +0,0 @@
From 9ff35368733c5e5a852ebd6295f262710553913b Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 3 May 2024 16:31:12 -0600
Subject: [PATCH] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes
This should fix S3 suspend on these systems
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e5420/smihandler.c | 9 +++++++++
src/mainboard/dell/e5520/smihandler.c | 9 +++++++++
src/mainboard/dell/e5530/smihandler.c | 9 +++++++++
src/mainboard/dell/e6420/smihandler.c | 9 +++++++++
src/mainboard/dell/e6430/smihandler.c | 9 +++++++++
src/mainboard/dell/e6520/smihandler.c | 9 +++++++++
src/mainboard/dell/e6530/smihandler.c | 9 +++++++++
7 files changed, 63 insertions(+)
create mode 100644 src/mainboard/dell/e5420/smihandler.c
create mode 100644 src/mainboard/dell/e5520/smihandler.c
create mode 100644 src/mainboard/dell/e5530/smihandler.c
create mode 100644 src/mainboard/dell/e6420/smihandler.c
create mode 100644 src/mainboard/dell/e6430/smihandler.c
create mode 100644 src/mainboard/dell/e6520/smihandler.c
create mode 100644 src/mainboard/dell/e6530/smihandler.c
diff --git a/src/mainboard/dell/e5420/smihandler.c b/src/mainboard/dell/e5420/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e5420/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/e5520/smihandler.c b/src/mainboard/dell/e5520/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e5520/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/e5530/smihandler.c b/src/mainboard/dell/e5530/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e5530/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/e6420/smihandler.c b/src/mainboard/dell/e6420/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e6420/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/e6430/smihandler.c b/src/mainboard/dell/e6430/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e6430/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/e6520/smihandler.c b/src/mainboard/dell/e6520/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e6520/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/e6530/smihandler.c b/src/mainboard/dell/e6530/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e6530/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
--
2.44.0

52
config/coreboot/default/patches/0060-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch Normal file
View File

@ -0,0 +1,52 @@
From f52188b46ce60383b67aeea2bda7ec52d631c822 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Mon, 12 Aug 2024 02:15:24 +0100
Subject: [PATCH 1/1] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
set it to 96MHz. fixes the following build error when
building for x4x boards e.g. gigabyte ga-g41m-es2l:
hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config"
make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1
this error was introduced when merging coreboot/dell
into coreboot/default in lbmk. nicholas chin's fix in lbmk
was as follows:
commit 8629873a6043067affc137be275b7aa69cb1f10c
Author: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon May 20 10:46:25 2024 -0600
Fix E6400 display issue with 1440 x 900 panel
this currently corresponds to the patch in lbmk,
as of 12 august 2024:
0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
The assumption prior to Nicholas's fix was 96MHz, so set
it accordingly on x4x northbridge.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/northbridge/intel/x4x/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 9af063819b..93ba575b95 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X
if NORTHBRIDGE_INTEL_X4X
+config INTEL_GMA_DPLL_REF_FREQ
+ int
+ default 96000000
+
config CBFS_SIZE
default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
--
2.39.2

0
config/coreboot/default/patches/0016-never-enable-cpu-microcode-even-if-told-to.patch → config/coreboot/default/patches/0061-never-enable-cpu-microcode-even-if-told-to.patch
View File

0
config/coreboot/default/patches/0017-Never-download-blobs-even-if-USE_BLOBS-y.patch → config/coreboot/default/patches/0062-Never-download-blobs-even-if-USE_BLOBS-y.patch
View File

2
config/coreboot/default/target.cfg
View File

@ -1,2 +1,2 @@
tree="default"
rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"
rev="97bc693abc482139774a656212935387d43df8e2"

11
config/coreboot/dell/nuke.list
View File

@ -1,11 +0,0 @@
Documentation
3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin
3rdparty/chromeec/test/legacy_nvmem_dump.h
3rdparty/vboot/tests/futility/data/bios_link_mp.bin
3rdparty/vboot/tests/futility/data/bios_peppy_mp.bin
3rdparty/chromeec/third_party/bmi260/accelgyro_bmi260_config_tbin.h
3rdparty/vboot/tests/futility/data/bios_peppy_dev.bin
3rdparty/stm/Test/FrmPkg/Core/Init/Dmar.h

47
config/coreboot/dell/patches/0001-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
View File

@ -1,47 +0,0 @@
From 9615da65cc281155f71c9e59aafba03a5d2752a6 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
Subject: [PATCH 1/9] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
Enabling PECI without microcode updates loaded causes the CPUID feature set
to become corrupted. And one consequence is broken SpeedStep. At least, that's
my understanding looking at Intel Errata. This revert is not a fix, because
upstream is correct (upstream assumes microcode updates). We will simply
maintain this revert patch in Libreboot, from now on.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 315e7c36fc..1423fd72bc 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
}
-#define IA32_PECI_CTL 0x5a0
-
static void configure_misc(const int eist, const int tm2, const int emttm)
{
msr_t msr;
@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
}
-
- /* Enable PECI
- WARNING: due to Erratum AW67 described in Intel document #318733
- the microcode must be updated before this MSR is written to. */
- msr = rdmsr(IA32_PECI_CTL);
- msr.lo |= 1;
- wrmsr(IA32_PECI_CTL, msr);
}
#define PIC_SENS_CFG 0x1aa
--
2.39.2

173
config/coreboot/dell/patches/0002-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
View File

@ -1,173 +0,0 @@
From 7daaafae1b9cd78f324488132753e25bfdbfc9f7 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 17 Apr 2023 15:49:57 +0100
Subject: [PATCH 2/9] GM45-type CPUs: don't enable alternative SMRR
This reverts the changes in coreboot revision:
df7aecd92643d207feaf7fd840f8835097346644
While this fix is *technically correct*, the one in
coreboot, it breaks rebooting as tested on several
GM45 ThinkPads e.g. X200, T400, when microcode
updates are not applied.
Since November 2022, Libreboot includes microcode
updates by default, but it tells users how to remove
it from the ROM (with cbfstool) if they wish.
Well, with Libreboot 20221214, 20230319 and 20230413,
mitigations present in Libreboot 20220710 (which did
not have microcode updates) do not exist.
This patch, along with the other patch to remove PECI
support (which breaks speedstep when microcode updates
are not applied) have now been re-added to Libreboot.
It is still best to use microcode updates by default.
These patches in coreboot are not critically urgent,
and you can use the machines with or without them,
regardless of ucode.
I'll probably re-write this and the other patch at
some point, applying the change conditionally upon
whether or not microcode is applied.
Pragmatism is a good thing. I recommend it.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
5 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 1423fd72bc..d1f98ca43a 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -8,6 +8,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/common/common.h>
#define MSR_BBL_CR_CTL3 0x11e
@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states(quad);
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index bc53214310..72f40f6762 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
smm_initialize();
}
-#define SMRR_SUPPORTED (1 << 11)
-
static void per_cpu_smm_trigger(void)
{
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
- set_feature_ctrl_vmx();
- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
- /* We don't care if the lock is already setting
- as our smm relocation handler is able to handle
- setups where SMRR is not enabled here. */
- if (ia32_ft_ctrl.lo & (1 << 0)) {
- /* IA32_FEATURE_CONTROL locked. If we set it again we
- get an illegal instruction. */
- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
- } else {
- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
- printk(BIOS_INFO,
- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
- }
- } else {
- set_vmx_and_lock();
- }
-
/* Relocate the SMM handler. */
smm_relocate();
}
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 05f5f327cc..0450c2ad83 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 5bd1c32815..f3bb08cde3 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 535fb8fae7..f7b05facd2 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
--
2.39.2

39
config/coreboot/dell/patches/0004-Remove-warning-for-coreboot-images-built-without-a-p.patch
View File

@ -1,39 +0,0 @@
From 52dd181998f9f55b66d38ba05025a4833a1247ba Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
Subject: [PATCH 4/9] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
roms without a payload resulting in a no boot situation, but in
libreboot lbmk handles the payload and thus this warning always comes
up. This has caused confusion and concern so just patch it out.
---
payloads/Makefile.mk | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
index a2336aa876..4f1692a873 100644
--- a/payloads/Makefile.mk
+++ b/payloads/Makefile.mk
@@ -49,16 +49,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
-show_notices:: warn_no_payload
-endif
-
-warn_no_payload:
- printf "\n\t** WARNING **\n"
- printf "coreboot has been built without a payload. Writing\n"
- printf "a coreboot image without a payload to your board's\n"
- printf "flash chip will result in a non-booting system. You\n"
- printf "can use cbfstool to add a payload to the image.\n\n"
-
.PHONY: force-payload coreinfo nvramcui
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--
2.39.2

39
config/coreboot/dell/patches/0005-don-t-use-github-for-the-acpica-download.patch
View File

@ -1,39 +0,0 @@
From db85939c346436d2a77ad47586edc4cacd48105d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 22 Oct 2023 15:02:25 +0100
Subject: [PATCH 5/9] don't use github for the acpica download
i have the tarball from a previous download, and i placed
it on libreboot rsync, which then got mirrored to princeton.
today, github's ssl cert was b0rking the hell out and i really
really wanted to finish a build, and didn't want to wait for
github to fix their httpd.
so i'm now hosting this specific acpica tarball on rsync.
this patch makes that URL be used, instead of the github one.
that's the 2nd time i've had to patch coreboot's acpica download!
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 23a5caf2bb..36565a906c 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2

23
config/coreboot/dell/patches/0008-dell-e6400-crank-up-vram-to-256MB-max.patch
View File

@ -1,23 +0,0 @@
From 1d15c4659abe93d7c75be47a56fb69fcf2dfb46b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Nov 2023 16:33:11 +0000
Subject: [PATCH 8/9] dell/e6400: crank up vram to 256MB (max)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/e6400/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
index eeb6f47364..25dfa38cb5 100644
--- a/src/mainboard/dell/e6400/cmos.default
+++ b/src/mainboard/dell/e6400/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Disable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=256M
--
2.39.2

120
config/coreboot/dell/patches/0009-never-enable-cpu-microcode-even-if-told-to.patch
View File

@ -1,120 +0,0 @@
From e570de21e2463cfca9b2ab25ae67efd65f8e3315 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Thu, 12 Oct 2023 01:20:23 +0100
Subject: [PATCH 9/9] never enable cpu microcode, even if told to
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/cpu/Makefile.mk | 55 -----------------------------------
src/cpu/intel/fit/Makefile.mk | 31 --------------------
2 files changed, 86 deletions(-)
diff --git a/src/cpu/Makefile.mk b/src/cpu/Makefile.mk
index b1c1b1bb3e..571cd1d0e5 100644
--- a/src/cpu/Makefile.mk
+++ b/src/cpu/Makefile.mk
@@ -11,61 +11,6 @@ subdirs-$(CONFIG_ARCH_X86) += x86
subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86
subdirs-$(CONFIG_CPU_POWER9) += power9
-$(eval $(call create_class_compiler,cpu_microcode,x86_32))
-################################################################################
-## Rules for building the microcode blob in CBFS
-################################################################################
-
-cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin
-
-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
-cbfs-files-y += cpu_microcode_blob.bin
-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
-
-$(objgenerated)/microcode.bin: $(call strip_quotes,$(CONFIG_CPU_MICROCODE_HEADER_FILES))
- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
-endif
-
-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y)
-$(obj)/cpu_microcode_blob.bin: cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES))
-endif
-# otherwise `cpu_microcode_bins` should be filled by platform makefiles
-
-# We just mash all microcode binaries together into one binary to rule them all.
-# This approach assumes that the microcode binaries are properly padded, and
-# their headers specify the correct size. This works fairly well on isolatied
-# updates, such as Intel and some AMD microcode, but won't work very well if the
-# updates are wrapped in a container, like AMD's microcode update container. If
-# there is only one microcode binary (i.e. one container), then we don't have
-# this issue, and this rule will continue to work.
-$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) $(DOTCONFIG)
- for bin in $(cpu_microcode_bins); do \
- if [ ! -f "$$bin" ]; then \
- echo "Microcode error: $$bin does not exist"; \
- NO_MICROCODE_FILE=1; \
- fi; \
- done; \
- if [ -n "$$NO_MICROCODE_FILE" ]; then \
- if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \
- echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \
- fi; \
- false; \
- fi
- $(if $(cpu_microcode_bins),,false) # fail if no file is given at all
- @printf " MICROCODE $(subst $(obj)/,,$(@))\n"
- @echo $(cpu_microcode_bins)
- cat $(cpu_microcode_bins) > $@
-
-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
-cpu_microcode_blob.bin-type := microcode
-# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned.
-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
-cpu_microcode_blob.bin-align := 64
-else
-cpu_microcode_blob.bin-align := 16
-endif
-
ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
endif
diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk
index a86a22e6d6..edca120c14 100644
--- a/src/cpu/intel/fit/Makefile.mk
+++ b/src/cpu/intel/fit/Makefile.mk
@@ -19,35 +19,4 @@ $(call add_intermediate, set_fit_ptr, $(IFITTOOL))
FIT_ENTRY=$(call strip_quotes, $(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG))
-ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
-
-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE)$(CONFIG_CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS),y)
-
-$(call add_intermediate, add_mcu_fit, set_fit_ptr $(IFITTOOL))
- @printf " UPDATE-FIT Microcode\n"
- $(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT
-
-# Second FIT in TOP_SWAP bootblock
-ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
-
-$(call add_intermediate, set_ts_fit_ptr, $(IFITTOOL))
- @printf " UPDATE-FIT Top Swap: set FIT pointer to table\n"
- $(IFITTOOL) -f $< -F -n intel_fit_ts -r COREBOOT $(TS_OPTIONS)
-
-$(call add_intermediate, add_ts_mcu_fit, set_ts_fit_ptr $(IFITTOOL))
- @printf " UPDATE-FIT Top Swap: Microcode\n"
-ifneq ($(FIT_ENTRY),)
- $(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT
-endif # FIT_ENTRY
- $(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT
-
-cbfs-files-y += intel_fit_ts
-intel_fit_ts-file := fit_table.c:struct
-intel_fit_ts-type := intel_fit
-intel_fit_ts-align := 16
-
-endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
-
-endif # CONFIG_CPU_MICROCODE_CBFS_NONE
-
endif # CONFIG_UPDATE_IMAGE
--
2.39.2

47
config/coreboot/dell/patches/0010-Never-download-blobs-even-if-USE_BLOBS-y.patch
View File

@ -1,47 +0,0 @@
From c7d9dcec39fbda870b7cddbeb87771bac0fb68b8 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Fri, 3 May 2024 06:24:49 +0100
Subject: [PATCH 1/1] Never download blobs, even if USE_BLOBS=y
same idea as my never-microcode patches. i maintain
canoeboot and i like to re-use the same configs from
lbmk. with this and the never-microcode patch, it should
now be possible to re-use lbmk coreboot configs unmodified!
when those configs are used in cbmk, the relevant blobs
are never downloaded, ever.
Signed-off-by: Leah Rowe <info@minifree.org>
---
Makefile.mk | 15 ---------------
1 file changed, 15 deletions(-)
diff --git a/Makefile.mk b/Makefile.mk
index 87c6bcb247..3747eaa556 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -222,21 +222,6 @@ $(info Updating git submodules.)
forgetthis:=$(shell git submodule update --init $(quiet_errors))
# Checkout Cmocka repository
forgetthis:=$(shell git submodule update --init --checkout 3rdparty/cmocka $(quiet_errors))
-ifeq ($(CONFIG_USE_BLOBS),y)
-# These items are necessary because each has update=none in .gitmodules. They are ignored
-# until expressly requested and enabled with --checkout
-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors))
-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors))
-ifeq ($(CONFIG_FSP_USE_REPO),y)
-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors))
-endif
-ifeq ($(CONFIG_USE_AMD_BLOBS),y)
-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors))
-endif
-ifeq ($(CONFIG_USE_QC_BLOBS),y)
-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/qc_blobs $(quiet_errors))
-endif
-endif
UPDATED_SUBMODULES:=1
COREBOOT_EXPORTS += UPDATED_SUBMODULES
--
2.39.2

4
config/coreboot/dell/target.cfg
View File

@ -1,4 +0,0 @@
tree="dell"
tree_depend="default"
xtree="default"
rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"

41
config/coreboot/e6400_4mb/config/libgfxinit_corebootfb
View File

@ -6,7 +6,6 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
@ -26,7 +25,9 @@ CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
@ -35,7 +36,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -53,8 +53,8 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
@ -65,11 +65,13 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
@ -91,6 +93,7 @@ CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -123,17 +126,26 @@ CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
CONFIG_USBDEBUG_HCD_INDEX=1
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_USBDEBUG_HCD_INDEX=1
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_BOARD_DELL_E6400=y
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
# CONFIG_BOARD_DELL_XPS_8300 is not set
CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
@ -150,6 +162,7 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
@ -163,12 +176,13 @@ CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@ -209,8 +223,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
# CONFIG_USE_X86_64_SUPPORT is not set
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -219,7 +234,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@ -252,6 +266,7 @@ CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -322,7 +337,7 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_HAVE_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
@ -338,6 +353,7 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
# end of Chipset
#
@ -437,6 +453,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -489,7 +507,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console

41
config/coreboot/e6400_4mb/config/libgfxinit_txtmode
View File

@ -6,7 +6,6 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
@ -26,7 +25,9 @@ CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
@ -35,7 +36,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -53,8 +53,8 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
@ -65,11 +65,13 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
@ -91,6 +93,7 @@ CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -121,17 +124,26 @@ CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
CONFIG_USBDEBUG_HCD_INDEX=1
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_USBDEBUG_HCD_INDEX=1
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_BOARD_DELL_E6400=y
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
# CONFIG_BOARD_DELL_XPS_8300 is not set
CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
@ -148,6 +160,7 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
@ -161,12 +174,13 @@ CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@ -207,8 +221,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
# CONFIG_USE_X86_64_SUPPORT is not set
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -217,7 +232,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@ -250,6 +264,7 @@ CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -320,7 +335,7 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_HAVE_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
@ -336,6 +351,7 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
# end of Chipset
#
@ -433,6 +449,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -485,7 +503,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console

2
config/coreboot/e6400_4mb/target.cfg
View File

@ -1,4 +1,4 @@
tree="dell"
tree="default"
xarch="i386-elf"
payload_seabios="y"
payload_grub="y"

0
config/coreboot/fam15h_rdimm/nuke.list → config/coreboot/fam15h/nuke.list
View File

0
config/coreboot/fam15h_udimm/patches/0002-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch → config/coreboot/fam15h/patches/0002-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch
View File

0
config/coreboot/fam15h_udimm/patches/0003-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch → config/coreboot/fam15h/patches/0003-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch
View File

0
config/coreboot/fam15h_udimm/patches/0004-util-cbfstool-Makefile-support-distclean.patch → config/coreboot/fam15h/patches/0004-util-cbfstool-Makefile-support-distclean.patch
View File

0
config/coreboot/fam15h_udimm/patches/0005-crossgcc-patch-binutils-2.32-for-newer-hostcc.patch → config/coreboot/fam15h/patches/0005-crossgcc-patch-binutils-2.32-for-newer-hostcc.patch
View File

0
config/coreboot/fam15h_udimm/patches/0006-fix-crossgcc-acpica-build-on-newer-hostcc.patch → config/coreboot/fam15h/patches/0006-fix-crossgcc-acpica-build-on-newer-hostcc.patch
View File

0
config/coreboot/fam15h_udimm/patches/0007-coreboot-fam15h-use-new-upstream-for-acpica.patch → config/coreboot/fam15h/patches/0007-coreboot-fam15h-use-new-upstream-for-acpica.patch
View File

0
config/coreboot/fam15h_udimm/patches/0008-use-mirrorservire.org-for-gcc-downloads.patch → config/coreboot/fam15h/patches/0008-use-mirrorservire.org-for-gcc-downloads.patch
View File

0
config/coreboot/fam15h_udimm/patches/0009-buildgcc-don-t-treat-binutil-warnings-as-errors.patch → config/coreboot/fam15h/patches/0009-buildgcc-don-t-treat-binutil-warnings-as-errors.patch
View File

0
config/coreboot/fam15h_udimm/patches/0010-Do-not-use-microcode-updates-on-AMD-platforms.patch → config/coreboot/fam15h/patches/0010-Do-not-use-microcode-updates-on-AMD-platforms.patch
View File

0
config/coreboot/fam15h_udimm/patches/0011-Never-download-blobs-even-if-USE_BLOBS-y.patch → config/coreboot/fam15h/patches/0011-Never-download-blobs-even-if-USE_BLOBS-y.patch
View File

2
config/coreboot/fam15h_rdimm/target.cfg → config/coreboot/fam15h/target.cfg
View File

@ -1,2 +1,2 @@
tree="fam15h_rdimm"
tree="fam15h"
rev="1c13f8d85c7306213cd525308ee8973e5663a3f8"

38
config/coreboot/fam15h_rdimm/patches/0001-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch
View File

@ -1,38 +0,0 @@
From dede42141890bee0065c46b86a8e23952651239d Mon Sep 17 00:00:00 2001
From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
Date: Sun, 7 Feb 2021 16:40:05 +0100
Subject: [PATCH 1/9] Tweak cmos defaults for KCMA-D8 (for a little speed
boost)
63xx CPUs have the option to use a reduced latency value inside the crossbar.
Setting "experimental_memory_speed_boost=Enable" aparently only has an effect
on 63xx CPUs and may, in certain cases, yield a slight memory bandwidth
increase (according to Timothy Pearson), but maybe it also works for
43xx CPUs.
Setting "l3_cache_partitioning=Enable" will increase performance in certain
situations. See:
https://developer.arm.com/documentation/100453/0401/functional-description/l3-cache/l3-cache-partitioning?lang=en
---
src/mainboard/asus/kcma-d8/cmos.default | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default
index 306687157f..4e033d756f 100644
--- a/src/mainboard/asus/kcma-d8/cmos.default
+++ b/src/mainboard/asus/kcma-d8/cmos.default
@@ -21,9 +21,9 @@ sata_ahci_mode=Enable
sata_alpm=Disable
maximum_p_state_limit=0xf
probe_filter=Auto
-l3_cache_partitioning=Disable
+l3_cache_partitioning=Enable
gart=Enable
ehci_async_data_cache=Enable
-experimental_memory_speed_boost=Disable
+experimental_memory_speed_boost=Enable
power_on_after_fail=On
boot_option=Fallback
--
2.39.2

32
config/coreboot/fam15h_rdimm/patches/0002-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch
View File

@ -1,32 +0,0 @@
From b8520bb9440ff1c6145536c5519a86e6b4c64e69 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 7 May 2021 19:43:32 +0100
Subject: [PATCH 2/9] asus/kgpe-d16: enable lc_cache_partitioning and
experimental_memory_speed_boost
This really only benefits 63xx opterons which are less reliable in libreboot due
to lack of CPU microcode updates, but we might aswell enable this anyway.
---
src/mainboard/asus/kgpe-d16/cmos.default | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
index 7c496a50d7..8a25620e1d 100644
--- a/src/mainboard/asus/kgpe-d16/cmos.default
+++ b/src/mainboard/asus/kgpe-d16/cmos.default
@@ -21,10 +21,10 @@ sata_ahci_mode=Enable
sata_alpm=Disable
maximum_p_state_limit=0xf
probe_filter=Auto
-l3_cache_partitioning=Disable
+l3_cache_partitioning=Enable
ieee1394_controller=Enable
gart=Enable
ehci_async_data_cache=Enable
-experimental_memory_speed_boost=Disable
+experimental_memory_speed_boost=Enable
power_on_after_fail=On
boot_option=Fallback
--
2.39.2

41
config/coreboot/fam15h_rdimm/patches/0003-util-cbfstool-Makefile-support-distclean.patch
View File

@ -1,41 +0,0 @@
From b193eb189926be76a6e6979b158a3d4fe35c846a Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 9 Jul 2023 04:13:52 +0100
Subject: [PATCH 3/9] util/cbfstool Makefile: support distclean
it just does make-clean
this is so that this super-old coreboot revision
interfaces well with lbmk, which runs distclean
on cbfstool (which is supported, on modern cbfstool)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/cbfstool/Makefile | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index d5321f6959..b8424d7d87 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -26,7 +26,7 @@ ifittool: $(objutil)/cbfstool/ifittool
cbfs-compression-tool: $(objutil)/cbfstool/cbfs-compression-tool
-.PHONY: clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool
+.PHONY: distclean clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool
clean:
$(RM) fmd_parser.c fmd_parser.h fmd_scanner.c fmd_scanner.h
$(RM) $(objutil)/cbfstool/cbfstool $(cbfsobj)
@@ -55,6 +55,8 @@ install: all
$(INSTALL) ifittool $(DESTDIR)$(BINDIR)
$(INSTALL) cbfs-compression-tool $(DESTDIR)$(BINDIR)
+distclean: clean
+
ifneq ($(V),1)
.SILENT:
endif
--
2.39.2

37
config/coreboot/fam15h_rdimm/patches/0004-crossgcc-patch-binutils-2.32-for-newer-hostcc.patch
View File

@ -1,37 +0,0 @@
From 0040629068d6e0e340a6ba76a568c27b699c6913 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 9 Jul 2023 04:54:19 +0100
Subject: [PATCH 4/9] crossgcc: patch binutils 2.32 for newer hostcc
tested on debian sid as of 9 July 2023
implicit string declaration
easy peasy
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/patches/binutils-2.32_stringfix.patch | 11 +++++++++++
1 file changed, 11 insertions(+)
create mode 100644 util/crossgcc/patches/binutils-2.32_stringfix.patch
diff --git a/util/crossgcc/patches/binutils-2.32_stringfix.patch b/util/crossgcc/patches/binutils-2.32_stringfix.patch
new file mode 100644
index 0000000000..de27a2752a
--- /dev/null
+++ b/util/crossgcc/patches/binutils-2.32_stringfix.patch
@@ -0,0 +1,11 @@
+diff -u binutils-2.32/gold/errors.h binutils-2.32.patched/gold/errors.h
+--- binutils-2.32/gold/errors.h
++++ binutils-2.32.patched/gold/errors.h
+@@ -24,6 +24,7 @@
+ #define GOLD_ERRORS_H
+
+ #include <cstdarg>
++#include <string>
+
+ #include "gold-threads.h"
+
--
2.39.2

108
config/coreboot/fam15h_rdimm/patches/0005-fix-crossgcc-acpica-build-on-newer-hostcc.patch
View File

@ -1,108 +0,0 @@
From 200c943bb5f39d5455d9a6836116349773c86578 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 9 Jul 2023 19:37:39 +0100
Subject: [PATCH 5/9] fix crossgcc/acpica build on newer hostcc
Changes made to acpica/iasl:
remove superfluous YYSTYPE declaration
make LuxBuffer variables static, to avoid warnings
treated as errors about multiple definitions
AcpiGbl_DbOpt_NoRegionSupport - remove this definition
in source/tools/acpiexec/aemain.c because it's already
re-defined by acpiexec. otherwise the linker complains
about multiple definitions
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
.../acpica-unix2-20190703_mitigategcc.patch | 76 +++++++++++++++++++
1 file changed, 76 insertions(+)
create mode 100644 util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
diff --git a/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch b/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
new file mode 100644
index 0000000000..8de47245bd
--- /dev/null
+++ b/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
@@ -0,0 +1,76 @@
+From 66b927d923183ff62c9a757fafdeca9d1ac3fa87 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 9 Jul 2023 18:58:11 +0100
+Subject: [PATCH 1/1] fix building on newer hostcc (debian sid tested)
+
+remove superfluous YYSTYPE declaration
+
+make LuxBuffer variables static, to avoid warnings
+treated as errors about multiple definitions
+
+AcpiGbl_DbOpt_NoRegionSupport - remove this definition
+in source/tools/acpiexec/aemain.c because it's already
+re-defined by acpiexec. otherwise the linker complains
+about multiple definitions
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ source/compiler/aslcompiler.l | 1 -
+ source/compiler/dtparser.l | 2 +-
+ source/compiler/prparser.l | 2 +-
+ source/tools/acpiexec/aemain.c | 1 -
+ 4 files changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/source/compiler/aslcompiler.l b/source/compiler/aslcompiler.l
+index 1949b32..a24f028 100644
+--- a/source/compiler/aslcompiler.l
++++ b/source/compiler/aslcompiler.l
+@@ -48,7 +48,6 @@
+
+ #include <stdlib.h>
+ #include <string.h>
+-YYSTYPE AslCompilerlval;
+
+ /*
+ * Generation: Use the following command line:
+diff --git a/source/compiler/dtparser.l b/source/compiler/dtparser.l
+index 6517e52..d35181c 100644
+--- a/source/compiler/dtparser.l
++++ b/source/compiler/dtparser.l
+@@ -100,7 +100,7 @@ NewLine [\n]
+ /*
+ * Local support functions
+ */
+-YY_BUFFER_STATE LexBuffer;
++static YY_BUFFER_STATE LexBuffer;
+
+ /******************************************************************************
+ *
+diff --git a/source/compiler/prparser.l b/source/compiler/prparser.l
+index bcdef14..5a1b848 100644
+--- a/source/compiler/prparser.l
++++ b/source/compiler/prparser.l
+@@ -116,7 +116,7 @@ Identifier [a-zA-Z][0-9a-zA-Z]*
+ /*
+ * Local support functions
+ */
+-YY_BUFFER_STATE LexBuffer;
++static YY_BUFFER_STATE LexBuffer;
+
+
+ /******************************************************************************
+diff --git a/source/tools/acpiexec/aemain.c b/source/tools/acpiexec/aemain.c
+index 58640dd..cd0add6 100644
+--- a/source/tools/acpiexec/aemain.c
++++ b/source/tools/acpiexec/aemain.c
+@@ -84,7 +84,6 @@ BOOLEAN AcpiGbl_VerboseHandlers = FALSE;
+ UINT8 AcpiGbl_RegionFillValue = 0;
+ BOOLEAN AcpiGbl_IgnoreErrors = FALSE;
+ BOOLEAN AcpiGbl_AbortLoopOnTimeout = FALSE;
+-BOOLEAN AcpiGbl_DbOpt_NoRegionSupport = FALSE;
+ UINT8 AcpiGbl_UseHwReducedFadt = FALSE;
+ BOOLEAN AcpiGbl_DoInterfaceTests = FALSE;
+ BOOLEAN AcpiGbl_LoadTestTables = FALSE;
+--
+2.40.1
+
--
2.39.2

38
config/coreboot/fam15h_rdimm/patches/0006-coreboot-fam15h-use-new-upstream-for-acpica.patch
View File

@ -1,38 +0,0 @@
From 1071d59eb4d2a5cb36f3c670119aadb838eb6a85 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 16 Jul 2023 00:44:22 +0100
Subject: [PATCH 6/9] coreboot/fam15h: use new upstream for acpica
the original upstream died
i decided to host it myself, on libreboot rsync,
for use by mirrors.
this is also useful for GNU Boot, when downloading
acpica on coreboot 4.11_branch, for fam15h boards
this change is not necessary on other coreboot trees,
which adhere to new coreboot policy (newer coreboot
pulls acpica from github, which is fairly reliable)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index b75b90a877..4b838208bb 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -73,7 +73,7 @@ MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
-IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
+IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz"
EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
# CLANG toolchain archive locations
--
2.39.2

47
config/coreboot/fam15h_rdimm/patches/0007-use-mirrorservire.org-for-gcc-downloads.patch
View File

@ -1,47 +0,0 @@
From 68434f686e36d7e245e3d49c2851fcc4e319a857 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 23:08:43 +0000
Subject: [PATCH 7/9] use mirrorservire.org for gcc downloads
the gnu.org 302 redirect often fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 4b838208bb..438fb5a59f 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -67,12 +67,12 @@ NASM_VERSION=2.14.02
# These are sanitized by the jenkins toolchain test builder, so if
# a completely new URL is added here, it probably needs to be added
# to the jenkins build as well, or the builder won't download it.
-GMP_ARCHIVE="https://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.xz"
-MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz"
-MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
-GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
-BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
-GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
+GMP_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp/gmp-${GMP_VERSION}.tar.xz"
+MPFR_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr/mpfr-${MPFR_VERSION}.tar.xz"
+MPC_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc/mpc-${MPC_VERSION}.tar.gz"
+GCC_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
+BINUTILS_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
+GDB_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.xz"
IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz"
EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
@@ -81,7 +81,7 @@ LLVM_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/llvm-${CLANG_VERSION}.s
CFE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src.tar.xz"
CRT_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.tar.xz"
CTE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION}.src.tar.xz"
-MAKE_ARCHIVE="https://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2"
+MAKE_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/make/make-${MAKE_VERSION}.tar.bz2"
CMAKE_ARCHIVE="https://cmake.org/files/v3.15/cmake-${CMAKE_VERSION}.tar.gz"
NASM_ARCHIVE="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}/nasm-${NASM_VERSION}.tar.bz2"
--
2.39.2

35
config/coreboot/fam15h_rdimm/patches/0008-buildgcc-don-t-treat-binutil-warnings-as-errors.patch
View File

@ -1,35 +0,0 @@
From b11feca5893a2fdc3a0c0e6ccbd6084f60be6ab3 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sat, 13 Jan 2024 14:57:46 +0000
Subject: [PATCH 8/9] buildgcc: don't treat binutil warnings as errors
binutils 2.32 has too many build warnings on modern toolchains,
and newer gcc versions are much more pedantic about warnings,
treating them as errors by default.
instead of patching binutils like before, just let the warnings
persist. the warnings are benign. a user on gnuboot irc had serious
issues building binutils 2.32 specifically, on current gentoo as
of 13 January 2024. this patch mitigates those warning messages.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 438fb5a59f..0ad1980104 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -719,7 +719,7 @@ build_BINUTILS() {
--disable-werror --disable-nls --enable-lto --enable-gold \
--enable-interwork --enable-multilib \
--enable-plugins --enable-multilibs \
- CFLAGS="$HOSTCFLAGS" \
+ CFLAGS="$HOSTCFLAGS -Wno-error -w" \
CXXFLAGS="$HOSTCFLAGS" \
|| touch .failed
# shellcheck disable=SC2086
--
2.39.2

108
config/coreboot/fam15h_rdimm/patches/0009-Do-not-use-microcode-updates-on-AMD-platforms.patch
View File

@ -1,108 +0,0 @@
From 857b0f7beca46cc93b06d580f2b641a7742df597 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Thu, 6 May 2021 17:07:06 +0100
Subject: [PATCH 9/9] Do not use microcode updates on AMD platforms
Coreboot is hardcoding the use of microcode updates on some platforms.
Just nuke it from orbit. This is the libre branch of osboot, so microcode must
not be used.
---
src/cpu/Makefile.inc | 52 +------------------
src/cpu/amd/family_10h-family_15h/Kconfig | 1 -
.../amd/family_10h-family_15h/Makefile.inc | 10 +---
3 files changed, 2 insertions(+), 61 deletions(-)
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 66ee2f9169..dcf02d5f67 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -16,54 +16,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
## Rules for building the microcode blob in CBFS
################################################################################
-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
-cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin
-endif
-
-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
-cbfs-files-y += cpu_microcode_blob.bin
-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
-
-$(objgenerated)/microcode.bin: $(call strip_quotes,$(CONFIG_CPU_MICROCODE_HEADER_FILES))
- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
-endif
-
-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y)
-cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES))
-endif
-# otherwise `cpu_microcode_bins` should be filled by platform makefiles
-
-# We just mash all microcode binaries together into one binary to rule them all.
-# This approach assumes that the microcode binaries are properly padded, and
-# their headers specify the correct size. This works fairly well on isolatied
-# updates, such as Intel and some AMD microcode, but won't work very well if the
-# updates are wrapped in a container, like AMD's microcode update container. If
-# there is only one microcode binary (i.e. one container), then we don't have
-# this issue, and this rule will continue to work.
-$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins))
- for bin in $(cpu_microcode_bins); do \
- if [ ! -f "$$bin" ]; then \
- echo "Microcode error: $$bin does not exist"; \
- NO_MICROCODE_FILE=1; \
- fi; \
- done; \
- if [ -n "$$NO_MICROCODE_FILE" ]; then \
- if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \
- echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \
- fi; \
- false; \
- fi
- $(if $^,,false) # fail if no file is given at all
- @printf " MICROCODE $(subst $(obj)/,,$(@))\n"
- @echo $(cpu_microcode_bins)
- cat $^ > $@
-
-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
-cpu_microcode_blob.bin-type := microcode
-
-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
-cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-else
-cpu_microcode_blob.bin-align := 16
-endif
+# No microcode permitted in this version of coreboot.
diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
index ad4f5f4ba6..21150ab1a7 100644
--- a/src/cpu/amd/family_10h-family_15h/Kconfig
+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
@@ -8,7 +8,6 @@ config CPU_AMD_MODEL_10XXX
select TSC_SYNC_LFENCE
select UDELAY_LAPIC
select SUPPORT_CPU_UCODE_IN_CBFS
- select CPU_MICROCODE_MULTIPLE_FILES
select CAR_GLOBAL_MIGRATION
if CPU_AMD_MODEL_10XXX
diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
index 7035323026..e0029f562d 100644
--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
@@ -14,12 +14,4 @@ ramstage-y += ram_calc.c
ramstage-y += monotonic_timer.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
-# Microcode for Family 10h, 11h, 12h, and 14h
-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd.bin
-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
-microcode_amd.bin-type := microcode
-
-# Microcode for Family 15h
-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd_fam15h.bin
-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
-microcode_amd_fam15h.bin-type := microcode
+# Microcode deleted in this version of coreboot.
--
2.39.2

43
config/coreboot/fam15h_rdimm/patches/0010-Never-download-blobs-even-if-USE_BLOBS-y.patch
View File

@ -1,43 +0,0 @@
From 31cb9eefd880bd8011d18fa070f31c498a0265e5 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Fri, 3 May 2024 06:29:41 +0100
Subject: [PATCH 1/1] Never download blobs, even if USE_BLOBS=y
Same idea as my never-microcode patch. With this and that
other patch, I can now re-use lbmk coreboot configs reliably
without modifying them; i currently set CONFIG_USE_BLOBS=n
on the Canoeboot versions.
Thus, this patch will reduce the maintenance burden for cbmk.
Signed-off-by: Leah Rowe <info@minifree.org>
---
Makefile.inc | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index be198d6580..2b3718b67c 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -196,18 +196,6 @@ endif
ifneq ($(UPDATED_SUBMODULES),1)
# try to fetch non-optional submodules if the source is under git
forgetthis:=$(if $(GIT),$(shell git submodule update --init))
-ifeq ($(CONFIG_USE_BLOBS),y)
-# These items are necessary because each has update=none in .gitmodules. They are ignored
-# until expressly requested and enabled with --checkout
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode))
-ifeq ($(CONFIG_PLATFORM_USES_FSP1_0)$(CONFIG_PLATFORM_USES_FSP1_1)$(CONFIG_PLATFORM_USES_FSP2_0),y)
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp))
-endif
-ifeq ($(CONFIG_USE_AMD_BLOBS),y)
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs))
-endif
-endif
UPDATED_SUBMODULES:=1
COREBOOT_EXPORTS += UPDATED_SUBMODULES
endif
--
2.39.2

26
config/coreboot/fam15h_udimm/nuke.list
View File

@ -1,26 +0,0 @@
Documentation
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin
3rdparty/chromeec/test/legacy_nvmem_dump.h
3rdparty/vboot/tests/futility/data/bios_link_mp.bin
3rdparty/vboot/tests/futility/data/bios_peppy_mp.bin
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h
src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse.c
src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf
src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf
src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h

31
config/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch
View File

@ -1,31 +0,0 @@
From 80db97601779457d5044acbd085e85f05c46575d Mon Sep 17 00:00:00 2001
From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
Date: Sun, 7 Feb 2021 15:29:40 +0100
Subject: [PATCH 01/10] Revert "Revert "nb/amd/mct_ddr3: Fix RDIMM training
failure on Fam15h" (fixes a bug that prevent certain RAM modules from
booting)
This reverts commit 610d1c67b2298a9840681c2b4492b6d3fdf44a46.
After 610d1c67b2298a9840681c2b4492b6d3fdf44a46 many RAM modules wouldn't work and you couldn't even see any output on the screen.
---
src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
index ddaaaab8d5..3b07786b91 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
@@ -71,6 +71,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
misc2 |= ((cs_mux_67 & 0x1) << 27);
misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */
misc2 |= ((cs_mux_45 & 0x1) << 26);
+
+ if (pDCTstat->Status & (1 << SB_Registered))
+ misc2 |= 1 << SubMemclkRegDly;
} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
if (pDCTstat->Status & (1 << SB_Registered)) {
misc2 |= 1 << SubMemclkRegDly;
--
2.39.2

4
config/coreboot/fam15h_udimm/target.cfg
View File

@ -1,4 +0,0 @@
tree="fam15h_udimm"
tree_depend="fam15h_rdimm"
xtree="fam15h_rdimm"
rev="1c13f8d85c7306213cd525308ee8973e5663a3f8"

37
config/coreboot/g43t_am3/config/libgfxinit_txtmode
View File

@ -6,7 +6,6 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
@ -26,7 +25,9 @@ CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
@ -35,7 +36,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -53,8 +53,8 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
CONFIG_VENDOR_ACER=y
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
@ -65,11 +65,13 @@ CONFIG_VENDOR_ACER=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
@ -91,6 +93,7 @@ CONFIG_VENDOR_ACER=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -123,13 +126,18 @@ CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_PCIEXP_ASPM=y
# CONFIG_PCIEXP_L1_SUB_STATE is not set
CONFIG_PCIEXP_CLK_PM=y
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Acer"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@ -144,6 +152,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
@ -157,13 +166,14 @@ CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
CONFIG_D3COLD_SUPPORT=y
CONFIG_PCIEXP_ASPM=y
# CONFIG_PCIEXP_L1_SUB_STATE is not set
CONFIG_PCIEXP_CLK_PM=y
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_2048=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@ -202,8 +212,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
# CONFIG_USE_X86_64_SUPPORT is not set
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -212,7 +223,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@ -247,6 +257,7 @@ CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -295,6 +306,8 @@ CONFIG_RCBA_LENGTH=0x4000
# Super I/O
#
CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
CONFIG_SUPERIO_ITE_COMMON_GPIO_PRE_RAM=y
CONFIG_SUPERIO_ITE_COMMON_NUM_GPIO_SETS=8
CONFIG_SUPERIO_ITE_ENV_CTRL=y
CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
@ -315,7 +328,7 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_HAVE_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
@ -332,6 +345,7 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
# end of Chipset
#
@ -429,6 +443,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -480,7 +496,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console

37
config/coreboot/g43t_am3_16mb/config/libgfxinit_txtmode
View File

@ -6,7 +6,6 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
@ -26,7 +25,9 @@ CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
@ -35,7 +36,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -53,8 +53,8 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
CONFIG_VENDOR_ACER=y
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
@ -65,11 +65,13 @@ CONFIG_VENDOR_ACER=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
@ -91,6 +93,7 @@ CONFIG_VENDOR_ACER=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -123,13 +126,18 @@ CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_PCIEXP_ASPM=y
# CONFIG_PCIEXP_L1_SUB_STATE is not set
CONFIG_PCIEXP_CLK_PM=y
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Acer"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@ -144,6 +152,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
@ -157,13 +166,14 @@ CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
CONFIG_D3COLD_SUPPORT=y
CONFIG_PCIEXP_ASPM=y
# CONFIG_PCIEXP_L1_SUB_STATE is not set
CONFIG_PCIEXP_CLK_PM=y
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_2048=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@ -202,8 +212,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
# CONFIG_USE_X86_64_SUPPORT is not set
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -212,7 +223,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@ -247,6 +257,7 @@ CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -295,6 +306,8 @@ CONFIG_RCBA_LENGTH=0x4000
# Super I/O
#
CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
CONFIG_SUPERIO_ITE_COMMON_GPIO_PRE_RAM=y
CONFIG_SUPERIO_ITE_COMMON_NUM_GPIO_SETS=8
CONFIG_SUPERIO_ITE_ENV_CTRL=y
CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
@ -315,7 +328,7 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_HAVE_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
@ -332,6 +345,7 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
# end of Chipset
#
@ -429,6 +443,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -480,7 +496,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console

38
config/coreboot/ga_g41m_es2l/config/libgfxinit_txtmode
View File

@ -6,7 +6,6 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
@ -26,7 +25,9 @@ CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
@ -35,7 +36,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -53,8 +53,8 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
@ -65,11 +65,13 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
CONFIG_VENDOR_GIGABYTE=y
# CONFIG_VENDOR_GOOGLE is not set
@ -91,6 +93,7 @@ CONFIG_VENDOR_GIGABYTE=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -121,13 +124,18 @@ CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_L1_SUB_STATE=y
CONFIG_PCIEXP_CLK_PM=y
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="GIGABYTE"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@ -151,7 +159,9 @@ CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y
# CONFIG_BOARD_GIGABYTE_GA_H61M_DS2 is not set
# CONFIG_BOARD_GIGABYTE_GA_H61M_DS2V is not set
# CONFIG_BOARD_GIGABYTE_GA_H61MA_D3V is not set
# CONFIG_BOARD_GIGABYTE_GA_H61M_S2P_R3 is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
@ -164,13 +174,14 @@ CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
CONFIG_D3COLD_SUPPORT=y
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_L1_SUB_STATE=y
CONFIG_PCIEXP_CLK_PM=y
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@ -209,8 +220,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
# CONFIG_USE_X86_64_SUPPORT is not set
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -219,7 +231,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@ -257,6 +268,7 @@ CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -306,6 +318,8 @@ CONFIG_RCBA_LENGTH=0x4000
# Super I/O
#
CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
CONFIG_SUPERIO_ITE_COMMON_GPIO_PRE_RAM=y
CONFIG_SUPERIO_ITE_COMMON_NUM_GPIO_SETS=6
CONFIG_SUPERIO_ITE_ENV_CTRL=y
CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
@ -321,7 +335,7 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_HAVE_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
@ -338,6 +352,7 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
# end of Chipset
#
@ -435,6 +450,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -487,7 +504,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console

127
config/coreboot/gru_bob/config/libgfxinit_corebootfb
View File

@ -6,7 +6,6 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
@ -32,7 +31,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_CBMEM_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -50,8 +48,8 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
@ -62,11 +60,13 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
CONFIG_VENDOR_GOOGLE=y
@ -88,6 +88,7 @@ CONFIG_VENDOR_GOOGLE=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -116,11 +117,13 @@ CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
# CONFIG_CHROMEOS is not set
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=1
CONFIG_CONSOLE_SERIAL_UART_ADDRESS=0xFF1A0000
# CONFIG_CONSOLE_POST is not set
CONFIG_MEMLAYOUT_LD_FILE="src/soc/rockchip/rk3399/memlayout.ld"
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_ARM64_CURRENT_EL=3
CONFIG_SPI_FLASH_WINBOND=y
#
@ -153,6 +156,9 @@ CONFIG_SPI_FLASH_WINBOND=y
# Brox
#
# CONFIG_BOARD_GOOGLE_BROX is not set
# CONFIG_BOARD_GOOGLE_BROX_EC_ISH is not set
# CONFIG_BOARD_GOOGLE_LOTSO is not set
# CONFIG_BOARD_GOOGLE_GREENBAYUPOC is not set
#
# Brya
@ -160,6 +166,7 @@ CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_BOARD_GOOGLE_AGAH is not set
# CONFIG_BOARD_GOOGLE_ANAHERA is not set
# CONFIG_BOARD_GOOGLE_ANAHERA4ES is not set
# CONFIG_BOARD_GOOGLE_ANRAGGAR is not set
# CONFIG_BOARD_GOOGLE_AURASH is not set
# CONFIG_BOARD_GOOGLE_BANSHEE is not set
# CONFIG_BOARD_GOOGLE_BRASK is not set
@ -168,11 +175,14 @@ CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_BOARD_GOOGLE_CRAASKOV is not set
# CONFIG_BOARD_GOOGLE_CONSTITUTION is not set
# CONFIG_BOARD_GOOGLE_CROTA is not set
# CONFIG_BOARD_GOOGLE_DOCHI is not set
# CONFIG_BOARD_GOOGLE_DOMIKA is not set
# CONFIG_BOARD_GOOGLE_FELWINTER is not set
# CONFIG_BOARD_GOOGLE_GAELIN is not set
# CONFIG_BOARD_GOOGLE_GIMBLE is not set
# CONFIG_BOARD_GOOGLE_GIMBLE4ES is not set
# CONFIG_BOARD_GOOGLE_GLADIOS is not set
# CONFIG_BOARD_GOOGLE_GLASSWAY is not set
# CONFIG_BOARD_GOOGLE_GOTHRAX is not set
# CONFIG_BOARD_GOOGLE_HADES is not set
# CONFIG_BOARD_GOOGLE_KANO is not set
@ -185,6 +195,7 @@ CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_BOARD_GOOGLE_MOLI is not set
# CONFIG_BOARD_GOOGLE_NIVVIKS is not set
# CONFIG_BOARD_GOOGLE_NEREID is not set
# CONFIG_BOARD_GOOGLE_NOKRIS is not set
# CONFIG_BOARD_GOOGLE_OMNIGUL is not set
# CONFIG_BOARD_GOOGLE_OSIRIS is not set
# CONFIG_BOARD_GOOGLE_PIRRHA is not set
@ -193,11 +204,15 @@ CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_BOARD_GOOGLE_QUANDISO is not set
# CONFIG_BOARD_GOOGLE_REDRIX is not set
# CONFIG_BOARD_GOOGLE_REDRIX4ES is not set
# CONFIG_BOARD_GOOGLE_RIVEN is not set
# CONFIG_BOARD_GOOGLE_SKOLAS is not set
# CONFIG_BOARD_GOOGLE_SKOLAS4ES is not set
# CONFIG_BOARD_GOOGLE_TAEKO is not set
# CONFIG_BOARD_GOOGLE_TAEKO4ES is not set
# CONFIG_BOARD_GOOGLE_TANIKS is not set
# CONFIG_BOARD_GOOGLE_TEREID is not set
# CONFIG_BOARD_GOOGLE_TIVVIKS is not set
# CONFIG_BOARD_GOOGLE_TRULO is not set
# CONFIG_BOARD_GOOGLE_ULDREN is not set
# CONFIG_BOARD_GOOGLE_VELL is not set
# CONFIG_BOARD_GOOGLE_VOLMAR is not set
@ -205,10 +220,13 @@ CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_BOARD_GOOGLE_YAVIKS is not set
# CONFIG_BOARD_GOOGLE_YAVILLA is not set
# CONFIG_BOARD_GOOGLE_ZYDRON is not set
# CONFIG_BOARD_GOOGLE_NOKRIS is not set
# CONFIG_BOARD_GOOGLE_DOCHI is not set
# CONFIG_BOARD_GOOGLE_ANRAGGAR is not set
# CONFIG_BOARD_GOOGLE_XOL is not set
# CONFIG_BOARD_GOOGLE_NOVA is not set
# CONFIG_BOARD_GOOGLE_BUJIA is not set
# CONFIG_BOARD_GOOGLE_YAVISTA is not set
# CONFIG_BOARD_GOOGLE_SUNDANCE is not set
# CONFIG_BOARD_GOOGLE_PUJJOGA is not set
# CONFIG_BOARD_GOOGLE_ORISA is not set
#
# Butterfly
@ -226,22 +244,27 @@ CONFIG_SPI_FLASH_WINBOND=y
# Kingler
#
# CONFIG_BOARD_GOOGLE_KINGLER is not set
# CONFIG_BOARD_GOOGLE_KYOGRE is not set
# CONFIG_BOARD_GOOGLE_PONYTA is not set
# CONFIG_BOARD_GOOGLE_SQUIRTLE is not set
# CONFIG_BOARD_GOOGLE_STEELIX is not set
# CONFIG_BOARD_GOOGLE_VOLTORB is not set
# CONFIG_BOARD_GOOGLE_PONYTA is not set
#
# Krabby
#
# CONFIG_BOARD_GOOGLE_KRABBY is not set
# CONFIG_BOARD_GOOGLE_TENTACRUEL is not set
# CONFIG_BOARD_GOOGLE_MAGIKARP is not set
# CONFIG_BOARD_GOOGLE_CHINCHOU is not set
# CONFIG_BOARD_GOOGLE_KRABBY is not set
# CONFIG_BOARD_GOOGLE_MAGIKARP is not set
# CONFIG_BOARD_GOOGLE_SKITTY is not set
# CONFIG_BOARD_GOOGLE_TENTACRUEL is not set
# CONFIG_BOARD_GOOGLE_VELUZA is not set
#
# Staryu
#
# CONFIG_BOARD_GOOGLE_STARMIE is not set
# CONFIG_BOARD_GOOGLE_WUGTRIO is not set
#
# Cyan
@ -266,37 +289,38 @@ CONFIG_SPI_FLASH_WINBOND=y
#
# Dedede
#
# CONFIG_BOARD_GOOGLE_BEADRIX is not set
# CONFIG_BOARD_GOOGLE_BLIPPER is not set
# CONFIG_BOARD_GOOGLE_BOTEN is not set
# CONFIG_BOARD_GOOGLE_DIBBI is not set
# CONFIG_BOARD_GOOGLE_BOXY is not set
# CONFIG_BOARD_GOOGLE_BUGZZY is not set
# CONFIG_BOARD_GOOGLE_CAPPY2 is not set
# CONFIG_BOARD_GOOGLE_CORORI is not set
# CONFIG_BOARD_GOOGLE_CRET is not set
# CONFIG_BOARD_GOOGLE_DEDEDE is not set
# CONFIG_BOARD_GOOGLE_DEXI is not set
# CONFIG_BOARD_GOOGLE_DIBBI is not set
# CONFIG_BOARD_GOOGLE_DITA is not set
# CONFIG_BOARD_GOOGLE_DRAWCIA is not set
# CONFIG_BOARD_GOOGLE_DRIBLEE is not set
# CONFIG_BOARD_GOOGLE_GALTIC is not set
# CONFIG_BOARD_GOOGLE_GOOEY is not set
# CONFIG_BOARD_GOOGLE_HABOKI is not set
# CONFIG_BOARD_GOOGLE_MADOO is not set
# CONFIG_BOARD_GOOGLE_WADDLEDOO is not set
# CONFIG_BOARD_GOOGLE_WADDLEDEE is not set
# CONFIG_BOARD_GOOGLE_KRACKO is not set
# CONFIG_BOARD_GOOGLE_LALALA is not set
# CONFIG_BOARD_GOOGLE_LANTIS is not set
# CONFIG_BOARD_GOOGLE_MADOO is not set
# CONFIG_BOARD_GOOGLE_MAGOLOR is not set
# CONFIG_BOARD_GOOGLE_METAKNIGHT is not set
# CONFIG_BOARD_GOOGLE_LANTIS is not set
# CONFIG_BOARD_GOOGLE_GALTIC is not set
# CONFIG_BOARD_GOOGLE_SASUKE is not set
# CONFIG_BOARD_GOOGLE_STORO is not set
# CONFIG_BOARD_GOOGLE_SASUKETTE is not set
# CONFIG_BOARD_GOOGLE_KRACKO is not set
# CONFIG_BOARD_GOOGLE_BLIPPER is not set
# CONFIG_BOARD_GOOGLE_CRET is not set
# CONFIG_BOARD_GOOGLE_PIRIKA is not set
# CONFIG_BOARD_GOOGLE_CAPPY2 is not set
# CONFIG_BOARD_GOOGLE_BUGZZY is not set
# CONFIG_BOARD_GOOGLE_CORORI is not set
# CONFIG_BOARD_GOOGLE_DRIBLEE is not set
# CONFIG_BOARD_GOOGLE_GOOEY is not set
# CONFIG_BOARD_GOOGLE_BEADRIX is not set
# CONFIG_BOARD_GOOGLE_SASUKE is not set
# CONFIG_BOARD_GOOGLE_SASUKETTE is not set
# CONFIG_BOARD_GOOGLE_STORO is not set
# CONFIG_BOARD_GOOGLE_SHOTZO is not set
# CONFIG_BOARD_GOOGLE_TARANZA is not set
# CONFIG_BOARD_GOOGLE_BOXY is not set
# CONFIG_BOARD_GOOGLE_DEXI is not set
# CONFIG_BOARD_GOOGLE_DITA is not set
# CONFIG_BOARD_GOOGLE_WADDLEDEE is not set
# CONFIG_BOARD_GOOGLE_WADDLEDOO is not set
# CONFIG_BOARD_GOOGLE_AWASUKI is not set
#
# Drallion
@ -308,6 +332,11 @@ CONFIG_SPI_FLASH_WINBOND=y
#
# CONFIG_BOARD_GOOGLE_EVE is not set
#
# Fatcat
#
# CONFIG_BOARD_GOOGLE_FATCAT is not set
#
# Fizz
#
@ -546,6 +575,11 @@ CONFIG_BOARD_GOOGLE_BOB=y
# CONFIG_BOARD_GOOGLE_SWANKY is not set
# CONFIG_BOARD_GOOGLE_WINKY is not set
#
# Rauru
#
# CONFIG_BOARD_GOOGLE_RAURU is not set
#
# Reef
#
@ -558,18 +592,19 @@ CONFIG_BOARD_GOOGLE_BOB=y
#
# Rex
#
# CONFIG_BOARD_GOOGLE_REX0 is not set
# CONFIG_BOARD_GOOGLE_SCREEBO is not set
# CONFIG_BOARD_GOOGLE_SCREEBO4ES is not set
# CONFIG_BOARD_GOOGLE_KARIS is not set
# CONFIG_BOARD_GOOGLE_KARIS4ES is not set
# CONFIG_BOARD_GOOGLE_REX_EC_ISH is not set
# CONFIG_BOARD_GOOGLE_OVIS is not set
# CONFIG_BOARD_GOOGLE_OVIS4ES is not set
# CONFIG_BOARD_GOOGLE_DEKU is not set
# CONFIG_BOARD_GOOGLE_DEKU4ES is not set
# CONFIG_BOARD_GOOGLE_KARIS is not set
# CONFIG_BOARD_GOOGLE_KARIS4ES is not set
# CONFIG_BOARD_GOOGLE_OVIS is not set
# CONFIG_BOARD_GOOGLE_OVIS4ES is not set
# CONFIG_BOARD_GOOGLE_REX0 is not set
# CONFIG_BOARD_GOOGLE_REX_EC_ISH is not set
# CONFIG_BOARD_GOOGLE_REX4ES is not set
# CONFIG_BOARD_GOOGLE_REX4ES_EC_ISH is not set
# CONFIG_BOARD_GOOGLE_REX64 is not set
# CONFIG_BOARD_GOOGLE_SCREEBO is not set
# CONFIG_BOARD_GOOGLE_SCREEBO4ES is not set
#
# Sarien
@ -684,6 +719,7 @@ CONFIG_BOARD_GOOGLE_BOB=y
CONFIG_DRIVER_TPM_SPI_BUS=0x0
CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS=0x5
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_DRIVER_TPM_I2C_BUS=0x0
CONFIG_DRIVER_TPM_I2C_ADDR=0x20
CONFIG_PMIC_BUS=-1
@ -691,7 +727,6 @@ CONFIG_BOARD_GOOGLE_GRU_COMMON=y
CONFIG_GRU_HAS_TPM2=y
CONFIG_GRU_HAS_CENTERLOG_PWM=y
CONFIG_GRU_HAS_WLAN_RESET=y
CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME=""
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US=0
@ -700,7 +735,11 @@ CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_TTYS0_BAUD=115200
CONFIG_D3COLD_SUPPORT=y
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_DRIVER_TPM_SPI_CHIP=0
# CONFIG_TPM_MEASURED_BOOT is not set
CONFIG_BOARD_ROMSIZE_KB_8192=y
@ -769,9 +808,8 @@ CONFIG_EC_GOOGLE_CHROMEEC=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP=0x0
CONFIG_EC_GOOGLE_CHROMEEC_RTC=y
CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_NONE=y
# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL is not set
# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN is not set
# CONFIG_EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL is not set
CONFIG_MAINBOARD_HAS_CHROMEOS=y
#
@ -789,6 +827,7 @@ CONFIG_ARCH_VERSTAGE_ARMV8_64=y
CONFIG_ARCH_ROMSTAGE_ARMV8_64=y
CONFIG_ARCH_RAMSTAGE_ARMV8_64=y
CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE=y
# CONFIG_ARM64_BL31_OPTEE_WITH_SMC is not set
# end of Chipset
#
@ -861,7 +900,7 @@ CONFIG_CR50_RESET_CLEAR_EC_AP_IDLE_FLAG=y
#
# Trusted Platform Module
#
# CONFIG_NO_TPM is not set
# CONFIG_TPM1 is not set
CONFIG_TPM2=y
CONFIG_TPM=y
CONFIG_MAINBOARD_HAS_TPM2=y
@ -890,7 +929,6 @@ CONFIG_ACPI_CUSTOM_MADT=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
CONFIG_HEAP_SIZE=0x100000
#
# Console
@ -933,6 +971,7 @@ CONFIG_HAVE_MONOTONIC_TIMER=y
#
# System tables
#
# CONFIG_GENERATE_SMBIOS_TABLES is not set
# end of System tables
#

127
config/coreboot/gru_kevin/config/libgfxinit_corebootfb
View File

@ -6,7 +6,6 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
@ -32,7 +31,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_CBMEM_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -50,8 +48,8 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
@ -62,11 +60,13 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
CONFIG_VENDOR_GOOGLE=y
@ -88,6 +88,7 @@ CONFIG_VENDOR_GOOGLE=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -116,11 +117,13 @@ CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
# CONFIG_CHROMEOS is not set
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=1
CONFIG_CONSOLE_SERIAL_UART_ADDRESS=0xFF1A0000
# CONFIG_CONSOLE_POST is not set
CONFIG_MEMLAYOUT_LD_FILE="src/soc/rockchip/rk3399/memlayout.ld"
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_ARM64_CURRENT_EL=3
CONFIG_SPI_FLASH_WINBOND=y
#
@ -153,6 +156,9 @@ CONFIG_SPI_FLASH_WINBOND=y
# Brox
#
# CONFIG_BOARD_GOOGLE_BROX is not set
# CONFIG_BOARD_GOOGLE_BROX_EC_ISH is not set
# CONFIG_BOARD_GOOGLE_LOTSO is not set
# CONFIG_BOARD_GOOGLE_GREENBAYUPOC is not set
#
# Brya
@ -160,6 +166,7 @@ CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_BOARD_GOOGLE_AGAH is not set
# CONFIG_BOARD_GOOGLE_ANAHERA is not set
# CONFIG_BOARD_GOOGLE_ANAHERA4ES is not set
# CONFIG_BOARD_GOOGLE_ANRAGGAR is not set
# CONFIG_BOARD_GOOGLE_AURASH is not set
# CONFIG_BOARD_GOOGLE_BANSHEE is not set
# CONFIG_BOARD_GOOGLE_BRASK is not set
@ -168,11 +175,14 @@ CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_BOARD_GOOGLE_CRAASKOV is not set
# CONFIG_BOARD_GOOGLE_CONSTITUTION is not set
# CONFIG_BOARD_GOOGLE_CROTA is not set
# CONFIG_BOARD_GOOGLE_DOCHI is not set
# CONFIG_BOARD_GOOGLE_DOMIKA is not set
# CONFIG_BOARD_GOOGLE_FELWINTER is not set
# CONFIG_BOARD_GOOGLE_GAELIN is not set
# CONFIG_BOARD_GOOGLE_GIMBLE is not set
# CONFIG_BOARD_GOOGLE_GIMBLE4ES is not set
# CONFIG_BOARD_GOOGLE_GLADIOS is not set
# CONFIG_BOARD_GOOGLE_GLASSWAY is not set
# CONFIG_BOARD_GOOGLE_GOTHRAX is not set
# CONFIG_BOARD_GOOGLE_HADES is not set
# CONFIG_BOARD_GOOGLE_KANO is not set
@ -185,6 +195,7 @@ CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_BOARD_GOOGLE_MOLI is not set
# CONFIG_BOARD_GOOGLE_NIVVIKS is not set
# CONFIG_BOARD_GOOGLE_NEREID is not set
# CONFIG_BOARD_GOOGLE_NOKRIS is not set
# CONFIG_BOARD_GOOGLE_OMNIGUL is not set
# CONFIG_BOARD_GOOGLE_OSIRIS is not set
# CONFIG_BOARD_GOOGLE_PIRRHA is not set
@ -193,11 +204,15 @@ CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_BOARD_GOOGLE_QUANDISO is not set
# CONFIG_BOARD_GOOGLE_REDRIX is not set
# CONFIG_BOARD_GOOGLE_REDRIX4ES is not set
# CONFIG_BOARD_GOOGLE_RIVEN is not set
# CONFIG_BOARD_GOOGLE_SKOLAS is not set
# CONFIG_BOARD_GOOGLE_SKOLAS4ES is not set
# CONFIG_BOARD_GOOGLE_TAEKO is not set
# CONFIG_BOARD_GOOGLE_TAEKO4ES is not set
# CONFIG_BOARD_GOOGLE_TANIKS is not set
# CONFIG_BOARD_GOOGLE_TEREID is not set
# CONFIG_BOARD_GOOGLE_TIVVIKS is not set
# CONFIG_BOARD_GOOGLE_TRULO is not set
# CONFIG_BOARD_GOOGLE_ULDREN is not set
# CONFIG_BOARD_GOOGLE_VELL is not set
# CONFIG_BOARD_GOOGLE_VOLMAR is not set
@ -205,10 +220,13 @@ CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_BOARD_GOOGLE_YAVIKS is not set
# CONFIG_BOARD_GOOGLE_YAVILLA is not set
# CONFIG_BOARD_GOOGLE_ZYDRON is not set
# CONFIG_BOARD_GOOGLE_NOKRIS is not set
# CONFIG_BOARD_GOOGLE_DOCHI is not set
# CONFIG_BOARD_GOOGLE_ANRAGGAR is not set
# CONFIG_BOARD_GOOGLE_XOL is not set
# CONFIG_BOARD_GOOGLE_NOVA is not set
# CONFIG_BOARD_GOOGLE_BUJIA is not set
# CONFIG_BOARD_GOOGLE_YAVISTA is not set
# CONFIG_BOARD_GOOGLE_SUNDANCE is not set
# CONFIG_BOARD_GOOGLE_PUJJOGA is not set
# CONFIG_BOARD_GOOGLE_ORISA is not set
#
# Butterfly
@ -226,22 +244,27 @@ CONFIG_SPI_FLASH_WINBOND=y
# Kingler
#
# CONFIG_BOARD_GOOGLE_KINGLER is not set
# CONFIG_BOARD_GOOGLE_KYOGRE is not set
# CONFIG_BOARD_GOOGLE_PONYTA is not set
# CONFIG_BOARD_GOOGLE_SQUIRTLE is not set
# CONFIG_BOARD_GOOGLE_STEELIX is not set
# CONFIG_BOARD_GOOGLE_VOLTORB is not set
# CONFIG_BOARD_GOOGLE_PONYTA is not set
#
# Krabby
#
# CONFIG_BOARD_GOOGLE_KRABBY is not set
# CONFIG_BOARD_GOOGLE_TENTACRUEL is not set
# CONFIG_BOARD_GOOGLE_MAGIKARP is not set
# CONFIG_BOARD_GOOGLE_CHINCHOU is not set
# CONFIG_BOARD_GOOGLE_KRABBY is not set
# CONFIG_BOARD_GOOGLE_MAGIKARP is not set
# CONFIG_BOARD_GOOGLE_SKITTY is not set
# CONFIG_BOARD_GOOGLE_TENTACRUEL is not set
# CONFIG_BOARD_GOOGLE_VELUZA is not set
#
# Staryu
#
# CONFIG_BOARD_GOOGLE_STARMIE is not set
# CONFIG_BOARD_GOOGLE_WUGTRIO is not set
#
# Cyan
@ -266,37 +289,38 @@ CONFIG_SPI_FLASH_WINBOND=y
#
# Dedede
#
# CONFIG_BOARD_GOOGLE_BEADRIX is not set
# CONFIG_BOARD_GOOGLE_BLIPPER is not set
# CONFIG_BOARD_GOOGLE_BOTEN is not set
# CONFIG_BOARD_GOOGLE_DIBBI is not set
# CONFIG_BOARD_GOOGLE_BOXY is not set
# CONFIG_BOARD_GOOGLE_BUGZZY is not set
# CONFIG_BOARD_GOOGLE_CAPPY2 is not set
# CONFIG_BOARD_GOOGLE_CORORI is not set
# CONFIG_BOARD_GOOGLE_CRET is not set
# CONFIG_BOARD_GOOGLE_DEDEDE is not set
# CONFIG_BOARD_GOOGLE_DEXI is not set
# CONFIG_BOARD_GOOGLE_DIBBI is not set
# CONFIG_BOARD_GOOGLE_DITA is not set
# CONFIG_BOARD_GOOGLE_DRAWCIA is not set
# CONFIG_BOARD_GOOGLE_DRIBLEE is not set
# CONFIG_BOARD_GOOGLE_GALTIC is not set
# CONFIG_BOARD_GOOGLE_GOOEY is not set
# CONFIG_BOARD_GOOGLE_HABOKI is not set
# CONFIG_BOARD_GOOGLE_MADOO is not set
# CONFIG_BOARD_GOOGLE_WADDLEDOO is not set
# CONFIG_BOARD_GOOGLE_WADDLEDEE is not set
# CONFIG_BOARD_GOOGLE_KRACKO is not set
# CONFIG_BOARD_GOOGLE_LALALA is not set
# CONFIG_BOARD_GOOGLE_LANTIS is not set
# CONFIG_BOARD_GOOGLE_MADOO is not set
# CONFIG_BOARD_GOOGLE_MAGOLOR is not set
# CONFIG_BOARD_GOOGLE_METAKNIGHT is not set
# CONFIG_BOARD_GOOGLE_LANTIS is not set
# CONFIG_BOARD_GOOGLE_GALTIC is not set
# CONFIG_BOARD_GOOGLE_SASUKE is not set
# CONFIG_BOARD_GOOGLE_STORO is not set
# CONFIG_BOARD_GOOGLE_SASUKETTE is not set
# CONFIG_BOARD_GOOGLE_KRACKO is not set
# CONFIG_BOARD_GOOGLE_BLIPPER is not set
# CONFIG_BOARD_GOOGLE_CRET is not set
# CONFIG_BOARD_GOOGLE_PIRIKA is not set
# CONFIG_BOARD_GOOGLE_CAPPY2 is not set
# CONFIG_BOARD_GOOGLE_BUGZZY is not set
# CONFIG_BOARD_GOOGLE_CORORI is not set
# CONFIG_BOARD_GOOGLE_DRIBLEE is not set
# CONFIG_BOARD_GOOGLE_GOOEY is not set
# CONFIG_BOARD_GOOGLE_BEADRIX is not set
# CONFIG_BOARD_GOOGLE_SASUKE is not set
# CONFIG_BOARD_GOOGLE_SASUKETTE is not set
# CONFIG_BOARD_GOOGLE_STORO is not set
# CONFIG_BOARD_GOOGLE_SHOTZO is not set
# CONFIG_BOARD_GOOGLE_TARANZA is not set
# CONFIG_BOARD_GOOGLE_BOXY is not set
# CONFIG_BOARD_GOOGLE_DEXI is not set
# CONFIG_BOARD_GOOGLE_DITA is not set
# CONFIG_BOARD_GOOGLE_WADDLEDEE is not set
# CONFIG_BOARD_GOOGLE_WADDLEDOO is not set
# CONFIG_BOARD_GOOGLE_AWASUKI is not set
#
# Drallion
@ -308,6 +332,11 @@ CONFIG_SPI_FLASH_WINBOND=y
#
# CONFIG_BOARD_GOOGLE_EVE is not set
#
# Fatcat
#
# CONFIG_BOARD_GOOGLE_FATCAT is not set
#
# Fizz
#
@ -546,6 +575,11 @@ CONFIG_BOARD_GOOGLE_KEVIN=y
# CONFIG_BOARD_GOOGLE_SWANKY is not set
# CONFIG_BOARD_GOOGLE_WINKY is not set
#
# Rauru
#
# CONFIG_BOARD_GOOGLE_RAURU is not set
#
# Reef
#
@ -558,18 +592,19 @@ CONFIG_BOARD_GOOGLE_KEVIN=y
#
# Rex
#
# CONFIG_BOARD_GOOGLE_REX0 is not set
# CONFIG_BOARD_GOOGLE_SCREEBO is not set
# CONFIG_BOARD_GOOGLE_SCREEBO4ES is not set
# CONFIG_BOARD_GOOGLE_KARIS is not set
# CONFIG_BOARD_GOOGLE_KARIS4ES is not set
# CONFIG_BOARD_GOOGLE_REX_EC_ISH is not set
# CONFIG_BOARD_GOOGLE_OVIS is not set
# CONFIG_BOARD_GOOGLE_OVIS4ES is not set
# CONFIG_BOARD_GOOGLE_DEKU is not set
# CONFIG_BOARD_GOOGLE_DEKU4ES is not set
# CONFIG_BOARD_GOOGLE_KARIS is not set
# CONFIG_BOARD_GOOGLE_KARIS4ES is not set
# CONFIG_BOARD_GOOGLE_OVIS is not set
# CONFIG_BOARD_GOOGLE_OVIS4ES is not set
# CONFIG_BOARD_GOOGLE_REX0 is not set
# CONFIG_BOARD_GOOGLE_REX_EC_ISH is not set
# CONFIG_BOARD_GOOGLE_REX4ES is not set
# CONFIG_BOARD_GOOGLE_REX4ES_EC_ISH is not set
# CONFIG_BOARD_GOOGLE_REX64 is not set
# CONFIG_BOARD_GOOGLE_SCREEBO is not set
# CONFIG_BOARD_GOOGLE_SCREEBO4ES is not set
#
# Sarien
@ -684,6 +719,7 @@ CONFIG_BOARD_GOOGLE_KEVIN=y
CONFIG_DRIVER_TPM_SPI_BUS=0x0
CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS=0x5
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_DRIVER_TPM_I2C_BUS=0x0
CONFIG_DRIVER_TPM_I2C_ADDR=0x20
CONFIG_PMIC_BUS=-1
@ -691,7 +727,6 @@ CONFIG_BOARD_GOOGLE_GRU_COMMON=y
# CONFIG_GRU_HAS_TPM2 is not set
CONFIG_GRU_HAS_CENTERLOG_PWM=y
CONFIG_GRU_HAS_WLAN_RESET=y
CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME=""
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US=0
@ -700,7 +735,11 @@ CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_TTYS0_BAUD=115200
CONFIG_D3COLD_SUPPORT=y
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
# CONFIG_TPM_MEASURED_BOOT is not set
CONFIG_BOARD_ROMSIZE_KB_8192=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@ -768,9 +807,8 @@ CONFIG_EC_GOOGLE_CHROMEEC=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP=0x0
CONFIG_EC_GOOGLE_CHROMEEC_RTC=y
CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_NONE=y
# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL is not set
# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN is not set
# CONFIG_EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL is not set
CONFIG_MAINBOARD_HAS_CHROMEOS=y
#
@ -788,6 +826,7 @@ CONFIG_ARCH_VERSTAGE_ARMV8_64=y
CONFIG_ARCH_ROMSTAGE_ARMV8_64=y
CONFIG_ARCH_RAMSTAGE_ARMV8_64=y
CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE=y
# CONFIG_ARM64_BL31_OPTEE_WITH_SMC is not set
# end of Chipset
#
@ -857,8 +896,8 @@ CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
#
# Trusted Platform Module
#
# CONFIG_NO_TPM is not set
CONFIG_TPM1=y
# CONFIG_TPM2 is not set
CONFIG_TPM=y
CONFIG_MAINBOARD_HAS_TPM1=y
# CONFIG_TPM_DEACTIVATE is not set
@ -887,7 +926,6 @@ CONFIG_ACPI_CUSTOM_MADT=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
CONFIG_HEAP_SIZE=0x100000
#
# Console
@ -930,6 +968,7 @@ CONFIG_HAVE_MONOTONIC_TIMER=y
#
# System tables
#
# CONFIG_GENERATE_SMBIOS_TABLES is not set
# end of System tables
#

47
config/coreboot/i945/nuke.list
View File

@ -1,47 +0,0 @@
3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin
3rdparty/chromeec/test/legacy_nvmem_dump.h
3rdparty/chromeec/third_party/bmi260/accelgyro_bmi260_config_tbin.h
3rdparty/vboot/tests/futility/data/bios_link_mp.bin
3rdparty/vboot/tests/futility/data/bios_peppy_dev.bin
3rdparty/vboot/tests/futility/data/bios_peppy_mp.bin
src/coreboot/default/3rdparty/stm/Test/FrmPkg/Core/Init/Dmar.h
src/coreboot/fam15h_rdimm/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf
src/coreboot/fam15h_rdimm/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf
src/coreboot/fam15h_udimm/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf
src/coreboot/fam15h_udimm/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_err.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gattc.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatt.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatts.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_hci.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_ranges.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_types.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_sdm.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_soc.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_nvic.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_sdm.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_soc.h
src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_svc.h
src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h

23
config/coreboot/i945/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
View File

@ -1,23 +0,0 @@
From 4d85316e931a83ccf4929551c1d200d80d1d3c3d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@retroboot.org>
Date: Fri, 19 Mar 2021 05:54:58 +0000
Subject: [PATCH 01/10] apple/macbook21: Set default VRAM to 64MiB instead of
8MiB
---
src/mainboard/apple/macbook21/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
index cf1bc4566e..dc0df3b6d6 100644
--- a/src/mainboard/apple/macbook21/cmos.default
+++ b/src/mainboard/apple/macbook21/cmos.default
@@ -5,4 +5,4 @@ boot_devices=''
boot_default=0x40
cmos_defaults_loaded=Yes
lpt=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.2

68
config/coreboot/i945/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch
View File

@ -1,68 +0,0 @@
From 6663cf5197c5eb8034e7bc6048fda6183674816e Mon Sep 17 00:00:00 2001
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
Date: Wed, 27 Oct 2021 13:36:01 +0200
Subject: [PATCH 02/10] add c3 and clockgen to apple/macbook21
---
src/mainboard/apple/macbook21/Kconfig | 1 +
src/mainboard/apple/macbook21/cstates.c | 13 +++++++++++++
src/mainboard/apple/macbook21/devicetree.cb | 6 ++++++
3 files changed, 20 insertions(+)
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
index 5f5ffde588..27377b737c 100644
--- a/src/mainboard/apple/macbook21/Kconfig
+++ b/src/mainboard/apple/macbook21/Kconfig
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select I945_LVDS
+ select DRIVERS_I2C_CK505
config MAINBOARD_DIR
default "apple/macbook21"
diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c
index 13d06f0839..88b8669c61 100644
--- a/src/mainboard/apple/macbook21/cstates.c
+++ b/src/mainboard/apple/macbook21/cstates.c
@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = {
.addrh = 0,
}
},
+ {
+ .ctype = 3,
+ .latency = 17,
+ .power = 250,
+ .resource = {
+ .space_id = ACPI_ADDRESS_SPACE_FIXED,
+ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+ .access_size = ACPI_ACCESS_SIZE_UNDEFINED,
+ .addrl = 0x20,
+ .addrh = 0,
+ }
+ },
};
int get_cst_entries(const acpi_cstate_t **entries)
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
index dd701da7ed..5587c48d1f 100644
--- a/src/mainboard/apple/macbook21/devicetree.cb
+++ b/src/mainboard/apple/macbook21/devicetree.cb
@@ -100,7 +100,13 @@ chip northbridge/intel/i945
end
device pci 1f.3 on # SMBUS
subsystemid 0x8086 0x7270
+ chip drivers/i2c/ck505
+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }"
+ register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }"
+ device i2c 69 on end
+ end
end
+
end
end
end
--
2.39.2

23
config/coreboot/i945/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
View File

@ -1,23 +0,0 @@
From d3c5a8dfd1965b241fe07fb505e63692512c147d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Sun, 3 Jan 2021 03:34:01 +0000
Subject: [PATCH 03/10] lenovo/x60: 64MiB Video RAM changed to default
(previously it was 8MiB)
---
src/mainboard/lenovo/x60/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
index 5c3576d1f3..88170a1aab 100644
--- a/src/mainboard/lenovo/x60/cmos.default
+++ b/src/mainboard/lenovo/x60/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.2

22
config/coreboot/i945/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
View File

@ -1,22 +0,0 @@
From db5eb56166860265dd2f7ecb4af89a5ca95d02c8 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Mon, 22 Feb 2021 22:16:59 +0000
Subject: [PATCH 04/10] lenovo/t60: make 64MiB VRAM the default in cmos.default
---
src/mainboard/lenovo/t60/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
index af865f16da..7f03157df7 100644
--- a/src/mainboard/lenovo/t60/cmos.default
+++ b/src/mainboard/lenovo/t60/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.2

34
config/coreboot/i945/patches/0005-buildgcc-use-mirrorservice-for-gnu-toolchains.patch
View File

@ -1,34 +0,0 @@
From 42db605ad6a12153c7659c204ca77a741dced59c Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Fri, 26 Apr 2024 09:16:57 +0100
Subject: [PATCH 05/10] buildgcc: use mirrorservice for gnu toolchains
Signed-off-by: Leah Rowe <info@minifree.org>
---
util/crossgcc/buildgcc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 0de27ed6e8..0faea86894 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -66,11 +66,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
# to the jenkins build as well, or the builder won't download it.
# GCC toolchain archive locations
-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2

56
config/coreboot/i945/patches/0006-drivers-pc80-rtc-option.c-Stop-resetting-CMOS-during.patch
View File

@ -1,56 +0,0 @@
From 539ea838d5aa0a51dcc518ec8b0ad1ad2b51c2ea Mon Sep 17 00:00:00 2001
From: Bill XIE <persmule@hardenedlinux.org>
Date: Sat, 7 Oct 2023 01:32:51 +0800
Subject: [PATCH 06/10] drivers/pc80/rtc/option.c: Stop resetting CMOS during
s3 resume
After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS
defaults to extend to bank 1"), Thinkpad X200 with
CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via
bisect).
Further inspection shows that DRAM training result of GM45 is stored
in CMOS above 128 bytes in raminit_read_write_training.c, for s3 resume
to restore, but it will be erased by sanitize_cmos(), which now clears
both bank 0 and bank 1, leaving only "untrained" result restored, so s3
resume will fail.
However, resetting CMOS seems unnecessary during s3 resume. Now,
cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true.
Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from
s3 again with these changes.
Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78288
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
src/drivers/pc80/rtc/option.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c
index e8e2345133..e6cfa175ad 100644
--- a/src/drivers/pc80/rtc/option.c
+++ b/src/drivers/pc80/rtc/option.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h>
#include <console/console.h>
#include <string.h>
#include <cbfs.h>
@@ -200,7 +201,8 @@ void sanitize_cmos(void)
{
const unsigned char *cmos_default;
const bool cmos_need_reset =
- CONFIG(STATIC_OPTION_TABLE) || cmos_error() || !cmos_lb_cks_valid();
+ (CONFIG(STATIC_OPTION_TABLE) || cmos_error() || !cmos_lb_cks_valid())
+ && !acpi_is_wakeup_s3();
size_t length = 128;
size_t i;
--
2.39.2

51
config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch
View File

@ -1,51 +0,0 @@
From 8d00bf577d12c9d64595ca2cd1ceec6f49bd57a4 Mon Sep 17 00:00:00 2001
From: Bill XIE <persmule@hardenedlinux.org>
Date: Fri, 3 Nov 2023 12:34:01 +0800
Subject: [PATCH 07/10] drivers/pc80/rtc/option.c: Reset only CMOS range
covered by checksum
Proposed in the comment of commit 29030d0f3dad
("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"),
during sanitize_cmos(), only reset CMOS range covered by checksum and
the checksum itself from the file cmos.default in CBFS, in order to
prevent other runtime data in CMOS (e.g. the DRAM training data on
GM45 platforms for s3 resume) being erased.
Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig:
Bring HEAP_SIZE to a common, large value"), which is already
before my commit 29030d0f3dad , Thinkpad X200 with
CONFIG(STATIC_OPTION_TABLE) can resume from s3 again,
indicating that DRAM training data are no longer erased.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Co-authored-by: Jonathon Hall <jonathon.hall@puri.sm>
Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
---
src/drivers/pc80/rtc/option.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c
index e6cfa175ad..cb18e14ae9 100644
--- a/src/drivers/pc80/rtc/option.c
+++ b/src/drivers/pc80/rtc/option.c
@@ -213,8 +213,12 @@ void sanitize_cmos(void)
return;
u8 control_state = cmos_disable_rtc();
- for (i = 14; i < MIN(128, length); i++)
+ /* Copy checked range and the checksum from the default */
+ for (i = LB_CKS_RANGE_START; i < MIN(LB_CKS_RANGE_END + 1, length); i++)
cmos_write_inner(cmos_default[i], i);
+ /* CMOS checksum takes 2 bytes */
+ cmos_write_inner(cmos_default[LB_CKS_LOC], LB_CKS_LOC);
+ cmos_write_inner(cmos_default[LB_CKS_LOC + 1], LB_CKS_LOC + 1);
cmos_restore_rtc(control_state);
}
}
--
2.39.2

39
config/coreboot/i945/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch
View File

@ -1,39 +0,0 @@
From 7686b9576cb5b1464c74c0a4ce4fb9044caea932 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
Subject: [PATCH 08/10] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
roms without a payload resulting in a no boot situation, but in
libreboot lbmk handles the payload and thus this warning always comes
up. This has caused confusion and concern so just patch it out.
---
payloads/Makefile.inc | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
index e735443a76..4f1692a873 100644
--- a/payloads/Makefile.inc
+++ b/payloads/Makefile.inc
@@ -49,16 +49,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
-files_added:: warn_no_payload
-endif
-
-warn_no_payload:
- printf "\n\t** WARNING **\n"
- printf "coreboot has been built without a payload. Writing\n"
- printf "a coreboot image without a payload to your board's\n"
- printf "flash chip will result in a non-booting system. You\n"
- printf "can use cbfstool to add a payload to the image.\n\n"
-
.PHONY: force-payload coreinfo nvramcui
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--
2.39.2

28
config/coreboot/i945/patches/0009-use-mirrorservice.org-for-iasl-downloads.patch
View File

@ -1,28 +0,0 @@
From f4d1d81877bc1720a9af76b0b03bc80d077f7ede Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sun, 28 Apr 2024 01:59:30 +0100
Subject: [PATCH 09/10] use mirrorservice.org for iasl downloads
github is unreliable. i mirror these files myself.
Signed-off-by: Leah Rowe <info@minifree.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 0faea86894..6779a20425 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -71,7 +71,7 @@ MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2

122
config/coreboot/i945/patches/0010-never-add-microcode-updates-even-if-told-to.patch
View File

@ -1,122 +0,0 @@
From fd7e1a29eb14d4387adfaac63034ed144eb103d7 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Fri, 3 May 2024 05:33:41 +0100
Subject: [PATCH 10/10] never add microcode updates, even if told to
because gnu free system distribution guidelines
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/cpu/Makefile.inc | 55 ----------------------------------
src/cpu/intel/fit/Makefile.inc | 31 -------------------
2 files changed, 86 deletions(-)
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 12c682d43d..e5fb13b33d 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -9,61 +9,6 @@ subdirs-$(CONFIG_ARCH_X86) += x86
subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86
subdirs-$(CONFIG_CPU_POWER9) += power9
-$(eval $(call create_class_compiler,cpu_microcode,x86_32))
-################################################################################
-## Rules for building the microcode blob in CBFS
-################################################################################
-
-cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin
-
-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
-cbfs-files-y += cpu_microcode_blob.bin
-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
-
-$(objgenerated)/microcode.bin: $(call strip_quotes,$(CONFIG_CPU_MICROCODE_HEADER_FILES))
- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
-endif
-
-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y)
-$(obj)/cpu_microcode_blob.bin: cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES))
-endif
-# otherwise `cpu_microcode_bins` should be filled by platform makefiles
-
-# We just mash all microcode binaries together into one binary to rule them all.
-# This approach assumes that the microcode binaries are properly padded, and
-# their headers specify the correct size. This works fairly well on isolatied
-# updates, such as Intel and some AMD microcode, but won't work very well if the
-# updates are wrapped in a container, like AMD's microcode update container. If
-# there is only one microcode binary (i.e. one container), then we don't have
-# this issue, and this rule will continue to work.
-$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) $(DOTCONFIG)
- for bin in $(cpu_microcode_bins); do \
- if [ ! -f "$$bin" ]; then \
- echo "Microcode error: $$bin does not exist"; \
- NO_MICROCODE_FILE=1; \
- fi; \
- done; \
- if [ -n "$$NO_MICROCODE_FILE" ]; then \
- if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \
- echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \
- fi; \
- false; \
- fi
- $(if $(cpu_microcode_bins),,false) # fail if no file is given at all
- @printf " MICROCODE $(subst $(obj)/,,$(@))\n"
- @echo $(cpu_microcode_bins)
- cat $(cpu_microcode_bins) > $@
-
-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
-cpu_microcode_blob.bin-type := microcode
-# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned.
-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
-cpu_microcode_blob.bin-align := 64
-else
-cpu_microcode_blob.bin-align := 16
-endif
-
ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
endif
diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc
index d3f12e43e6..c31102872e 100644
--- a/src/cpu/intel/fit/Makefile.inc
+++ b/src/cpu/intel/fit/Makefile.inc
@@ -17,35 +17,4 @@ $(call add_intermediate, set_fit_ptr, $(IFITTOOL))
FIT_ENTRY=$(call strip_quotes, $(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG))
-ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
-
-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y)
-
-$(call add_intermediate, add_mcu_fit, set_fit_ptr $(IFITTOOL))
- @printf " UPDATE-FIT Microcode\n"
- $(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT
-
-# Second FIT in TOP_SWAP bootblock
-ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
-
-$(call add_intermediate, set_ts_fit_ptr, $(IFITTOOL))
- @printf " UPDATE-FIT Top Swap: set FIT pointer to table\n"
- $(IFITTOOL) -f $< -F -n intel_fit_ts -r COREBOOT $(TS_OPTIONS)
-
-$(call add_intermediate, add_ts_mcu_fit, set_ts_fit_ptr $(IFITTOOL))
- @printf " UPDATE-FIT Top Swap: Microcode\n"
-ifneq ($(FIT_ENTRY),)
- $(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT
-endif # FIT_ENTRY
- $(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT
-
-cbfs-files-y += intel_fit_ts
-intel_fit_ts-file := fit_table.c:struct
-intel_fit_ts-type := intel_fit
-intel_fit_ts-align := 16
-
-endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
-
-endif # CONFIG_CPU_MICROCODE_CBFS_NONE
-
endif # CONFIG_UPDATE_IMAGE
--
2.39.2

54
config/coreboot/i945/patches/0011-never-download-blobs-even-if-USE_BLOBS-y.patch
View File

@ -1,54 +0,0 @@
From 72a2762b7b7cadac1dfd628a908af17fb907df9c Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Fri, 3 May 2024 06:33:05 +0100
Subject: [PATCH 1/1] never download blobs even if USE_BLOBS=y
With this and the existing never-add-microcode patch,
I can re-use lbmk coreboot configs without modifying them.
I already don't disable microcode in those configs when
porting them to canoeboot, because Canoeboot modifies
coreboot to never download/handle microcode, even when
microcode is enabled in a coreboot config.
This patch does the same thing, but for disabling the download
of 3rdparty blob repositories.
Therefore, I can now keep canoeboot's coreboot configs more
closely in sync with those of Libreboot, reducing the
maintenance burden for each Canoeboot release.
Signed-off-by: Leah Rowe <info@minifree.org>
---
Makefile.inc | 15 ---------------
1 file changed, 15 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 96121d4019..6e8f7ec581 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -199,21 +199,6 @@ $(info Updating git submodules.)
forgetthis:=$(shell git submodule update --init $(quiet_errors))
# Checkout Cmocka repository
forgetthis:=$(shell git submodule update --init --checkout 3rdparty/cmocka $(quiet_errors))
-ifeq ($(CONFIG_USE_BLOBS),y)
-# These items are necessary because each has update=none in .gitmodules. They are ignored
-# until expressly requested and enabled with --checkout
-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors))
-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors))
-ifeq ($(CONFIG_FSP_USE_REPO),y)
-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors))
-endif
-ifeq ($(CONFIG_USE_AMD_BLOBS),y)
-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors))
-endif
-ifeq ($(CONFIG_USE_QC_BLOBS),y)
-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/qc_blobs $(quiet_errors))
-endif
-endif
UPDATED_SUBMODULES:=1
COREBOOT_EXPORTS += UPDATED_SUBMODULES
--
2.39.2

2
config/coreboot/i945/target.cfg
View File

@ -1,2 +0,0 @@
tree="i945"
rev="e70bc423f9a2e1d13827f2703efe1f9c72549f20"

11
config/coreboot/kcma_d8-udimm_16mb/target.cfg
View File

@ -1,11 +0,0 @@
tree="fam15h_udimm"
xtree="fam15h_rdimm"
xarch="i386-elf"
payload_seabios="y"
payload_grub="y"
payload_memtest="y"
xlang="c"
grub_timout=10
grub_scan_disk="nvme ahci"
grubtree="nvme"
build_depend="seabios/default grub/nvme memtest86plus"

3
config/coreboot/kcma_d8-udimm_16mb/config/libgfxinit_txtmode → config/coreboot/kcma_d8_16mb/config/libgfxinit_txtmode
View File

@ -21,7 +21,8 @@ CONFIG_COMPRESS_RAMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_NO_RELOCATABLE_RAMSTAGE=y

2
config/coreboot/kgpe_d16_rdimm_16mb/target.cfg → config/coreboot/kcma_d8_16mb/target.cfg
View File

@ -1,4 +1,4 @@
tree="fam15h_rdimm"
tree="fam15h"
xarch="i386-elf"
payload_seabios="y"
payload_grub="y"

3
config/coreboot/kcma_d8_rdimm_2mb/config/libgfxinit_txtmode → config/coreboot/kcma_d8_2mb/config/libgfxinit_txtmode
View File

@ -21,7 +21,8 @@ CONFIG_COMPRESS_RAMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_NO_RELOCATABLE_RAMSTAGE=y

2
config/coreboot/kcma_d8_rdimm_16mb/target.cfg → config/coreboot/kcma_d8_2mb/target.cfg
View File

@ -1,4 +1,4 @@
tree="fam15h_rdimm"
tree="fam15h"
xarch="i386-elf"
payload_seabios="y"
payload_grub="y"

704
config/coreboot/kcma_d8_rdimm_16mb/config/libgfxinit_txtmode
View File

@ -1,704 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_NO_RELOCATABLE_RAMSTAGE=y
# CONFIG_RELOCATABLE_RAMSTAGE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_ADI is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_ADVANSUS is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
CONFIG_VENDOR_ASUS=y
# CONFIG_VENDOR_AVALUE is not set
# CONFIG_VENDOR_BAP is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_ELMEX is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ESD is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GIZMOSPHERE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IEI is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_JETWAY is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIPPERT is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SCALEWAY is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TYAN is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="asus/kcma-d8"
CONFIG_MAINBOARD_PART_NUMBER="KCMA-D8"
CONFIG_MAX_CPUS=16
CONFIG_CBFS_SIZE=0x1000000
CONFIG_UART_FOR_CONSOLE=0
CONFIG_MAINBOARD_VENDOR="ASUS"
CONFIG_APIC_ID_OFFSET=0x0
CONFIG_HW_MEM_HOLE_SIZEK=0x100000
CONFIG_MAX_PHYSICAL_CPUS=2
CONFIG_HT_CHAIN_END_UNITID_BASE=0x20
CONFIG_HT_CHAIN_UNITID_BASE=0x0
CONFIG_IRQ_SLOT_COUNT=13
CONFIG_VGA_BIOS_ID="1000,0072"
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
CONFIG_DIMM_SPD_SIZE=256
CONFIG_VGA_BIOS=y
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
CONFIG_VGA_BIOS_FILE="/dev/null"
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS"
CONFIG_DEVICETREE="devicetree.cb"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
# CONFIG_BOARD_ASUS_AM1I_A is not set
# CONFIG_BOARD_ASUS_F2A85_M is not set
# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set
# CONFIG_BOARD_ASUS_F2A85_M_LE is not set
# CONFIG_BOARD_ASUS_H61M_CS is not set
CONFIG_BOARD_ASUS_KCMA_D8=y
# CONFIG_BOARD_ASUS_KFSN4_DRE is not set
# CONFIG_BOARD_ASUS_KGPE_D16 is not set
# CONFIG_BOARD_ASUS_M4A78_EM is not set
# CONFIG_BOARD_ASUS_M4A785M is not set
# CONFIG_BOARD_ASUS_M4A785TM is not set
# CONFIG_BOARD_ASUS_M5A88_V is not set
# CONFIG_BOARD_ASUS_MAXIMUS_IV_GENE_Z is not set
# CONFIG_BOARD_ASUS_P2B_D is not set
# CONFIG_BOARD_ASUS_P2B_DS is not set
# CONFIG_BOARD_ASUS_P2B_F is not set
# CONFIG_BOARD_ASUS_P2B_LS is not set
# CONFIG_BOARD_ASUS_P2B is not set
# CONFIG_BOARD_ASUS_P3B_F is not set
# CONFIG_BOARD_ASUS_P5GC_MX is not set
# CONFIG_BOARD_ASUS_P5QC is not set
# CONFIG_BOARD_ASUS_P5Q_PRO is not set
# CONFIG_BOARD_ASUS_P5QL_PRO is not set
# CONFIG_BOARD_ASUS_P5QL_EM is not set
# CONFIG_BOARD_ASUS_P5QPL_AM is not set
# CONFIG_BOARD_ASUS_P5G41T_M_LX is not set
# CONFIG_BOARD_ASUS_P8H61_M_LX is not set
# CONFIG_BOARD_ASUS_P8H61_M_PRO is not set
# CONFIG_BOARD_ASUS_P8Z77_M_PRO is not set
CONFIG_POST_IO=y
CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/asus/kcma-d8/bootblock.c"
CONFIG_DCACHE_RAM_BASE=0xc2000
CONFIG_DCACHE_RAM_SIZE=0x1e000
CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD=0x3f
CONFIG_MAX_REBOOT_CNT=10
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_FMDFILE=""
# CONFIG_VBOOT is not set
CONFIG_MMCONF_BASE_ADDRESS=0xc0000000
CONFIG_POST_DEVICE=y
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_DRIVERS_UART_8250IO=y
CONFIG_DIMM_MAX=4
CONFIG_TTYS0_LCS=3
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KCMA-D8"
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
# CONFIG_USBDEBUG is not set
CONFIG_MAINBOARD_VERSION="1.0"
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_PCIEXP_L1_SUB_STATE=y
# CONFIG_NO_POST is not set
CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03
CONFIG_HEAP_SIZE=0xc0000
# CONFIG_CONSOLE_POST is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_BOARD_ROMSIZE_KB_2048=y
# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=16384
CONFIG_ROM_SIZE=0x1000000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
# CONFIG_SYSTEM_TYPE_LAPTOP is not set
# CONFIG_SYSTEM_TYPE_TABLET is not set
# CONFIG_SYSTEM_TYPE_DETACHABLE is not set
# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set
# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set
#
# Chipset
#
#
# SoC
#
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_CPU_ADDR_BITS=48
CONFIG_MMCONF_BUS_NUMBER=256
CONFIG_EHCI_BAR=0xfef00000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d"
# CONFIG_SOC_CAVIUM_CN81XX is not set
CONFIG_ARCH_ARMV8_EXTENSION=0
CONFIG_STACK_SIZE=0x1000
# CONFIG_SOC_CAVIUM_COMMON is not set
# CONFIG_SOC_INTEL_GLK is not set
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_PCIEXP_CLK_PM=y
CONFIG_TTYS0_BASE=0x3f8
CONFIG_HPET_MIN_TICKS=0x14
CONFIG_UART_PCI_ADDR=0x0
# CONFIG_SOC_MEDIATEK_MT8173 is not set
# CONFIG_SOC_MEDIATEK_MT8183 is not set
# CONFIG_SOC_NVIDIA_TEGRA124 is not set
# CONFIG_SOC_NVIDIA_TEGRA210 is not set
# CONFIG_SOC_QUALCOMM_COMMON is not set
# CONFIG_SOC_QC_IPQ40XX is not set
# CONFIG_SOC_QC_IPQ806X is not set
# CONFIG_SOC_QUALCOMM_QCS405 is not set
# CONFIG_SOC_QUALCOMM_SC7180 is not set
# CONFIG_SOC_QUALCOMM_SDM845 is not set
# CONFIG_SOC_ROCKCHIP_RK3288 is not set
# CONFIG_SOC_ROCKCHIP_RK3399 is not set
# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set
# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set
# CONFIG_SOC_UCB_RISCV is not set
#
# CPU
#
CONFIG_CPU_SOCKET_TYPE=0x14
# CONFIG_EXT_RT_TBL_SUPPORT is not set
CONFIG_CBB=0x0
CONFIG_CDB=0x18
CONFIG_XIP_ROM_SIZE=0x80000
CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA=y
CONFIG_CPU_AMD_MODEL_10XXX=y
CONFIG_USE_LARGE_DCACHE=y
CONFIG_NUM_IPI_STARTS=1
CONFIG_DCACHE_BSP_TOP_STACK_SIZE=0x4000
CONFIG_DCACHE_BSP_TOP_STACK_SLUSH=0x4000
CONFIG_DCACHE_AP_STACK_SIZE=0x500
CONFIG_SET_FIDVID=y
CONFIG_LIFT_BSP_APIC_ID=y
CONFIG_SET_FIDVID_DEBUG=y
CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST=y
# CONFIG_SET_FIDVID_CORE0_ONLY is not set
CONFIG_SET_FIDVID_CORE_RANGE=0
CONFIG_UDELAY_LAPIC_FIXED_FSB=200
# CONFIG_CPU_AMD_AGESA is not set
# CONFIG_CPU_AMD_PI is not set
# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set
CONFIG_SSE2=y
# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set
# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set
# CONFIG_CPU_TI_AM335X is not set
CONFIG_PARALLEL_CPU_INIT=y
# CONFIG_PARALLEL_MP is not set
CONFIG_UDELAY_LAPIC=y
# CONFIG_LAPIC_MONOTONIC_TIMER is not set
# CONFIG_UDELAY_TSC is not set
CONFIG_TSC_SYNC_LFENCE=y
# CONFIG_TSC_SYNC_MFENCE is not set
# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set
CONFIG_LOGICAL_CPUS=y
# CONFIG_HAVE_SMI_HANDLER is not set
# CONFIG_NO_SMM is not set
# CONFIG_SMM_ASEG is not set
CONFIG_SMM_TSEG=y
CONFIG_SMM_MODULE_HEAP_SIZE=0x4000
CONFIG_SMM_STUB_STACK_SIZE=0x400
# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set
# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set
CONFIG_X86_AMD_FIXED_MTRRS=y
# CONFIG_X86_AMD_INIT_SIPI is not set
# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set
# CONFIG_SOC_SETS_MSRS is not set
CONFIG_CAR_GLOBAL_MIGRATION=y
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
# CONFIG_USES_MICROCODE_HEADER_FILES is not set
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y
CONFIG_AGP_APERTURE_SIZE=0x4000000
CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c"
CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=y
# CONFIG_HT_CHAIN_DISTRIBUTE is not set
# CONFIG_DIMM_DDR2 is not set
CONFIG_DIMM_DDR3=y
CONFIG_DIMM_REGISTERED=y
CONFIG_DIMM_VOLTAGE_SET_SUPPORT=y
# CONFIG_SVI_HIGH_FREQ is not set
#
# HyperTransport setup
#
# CONFIG_LIMIT_HT_DOWN_WIDTH_8 is not set
CONFIG_LIMIT_HT_DOWN_WIDTH_16=y
# CONFIG_LIMIT_HT_UP_WIDTH_8 is not set
CONFIG_LIMIT_HT_UP_WIDTH_16=y
# CONFIG_NORTHBRIDGE_AMD_PI is not set
#
# Southbridge
#
CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y
CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/sb700/bootblock.c"
# CONFIG_AMD_SB_CIMX is not set
# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
CONFIG_SOUTHBRIDGE_AMD_SB700=y
CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y
CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100=y
# CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT is not set
CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA=y
CONFIG_SOUTHBRIDGE_AMD_SR5650=y
CONFIG_EXT_CONF_SUPPORT=y
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set
# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG is not set
# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set
#
# Super I/O
#
# CONFIG_SUPERIO_ASPEED_AST2400 is not set
# CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM is not set
# CONFIG_SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND is not set
# CONFIG_SUPERIO_FINTEK_FAN_CONTROL is not set
CONFIG_SUPERIO_WINBOND_COMMON_PRE_RAM=y
CONFIG_SUPERIO_WINBOND_W83667HG_A=y
#
# Embedded Controllers
#
# CONFIG_EC_GOOGLE_WILCO is not set
# CONFIG_CAVIUM_BDK is not set
# CONFIG_MAINBOARD_HAS_CHROMEOS is not set
# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set
# CONFIG_UEFI_2_4_BINDING is not set
# CONFIG_UDK_2015_BINDING is not set
# CONFIG_UDK_2017_BINDING is not set
# CONFIG_USE_SIEMENS_HWILIB is not set
# CONFIG_ARM_LPAE is not set
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
# CONFIG_ARCH_POSTCAR_X86_32 is not set
CONFIG_ARCH_RAMSTAGE_X86_32=y
# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set
# CONFIG_ARCH_VERSTAGE_X86_64 is not set
# CONFIG_ARCH_ROMSTAGE_X86_64 is not set
# CONFIG_ARCH_POSTCAR_X86_64 is not set
# CONFIG_ARCH_RAMSTAGE_X86_64 is not set
# CONFIG_USE_MARCH_586 is not set
# CONFIG_AP_IN_SIPI_WAIT is not set
# CONFIG_SIPI_VECTOR_IN_ROM is not set
CONFIG_RAMBASE=0xe00000
CONFIG_RAMTOP=0x1000000
# CONFIG_CBMEM_TOP_BACKUP is not set
CONFIG_PC80_SYSTEM=y
# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
# CONFIG_HPET_ADDRESS_OVERRIDE is not set
CONFIG_HPET_ADDRESS=0xfed00000
CONFIG_ID_SECTION_OFFSET=0x80
# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set
# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
CONFIG_ACPI_HAVE_PCAT_8259=y
# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
# CONFIG_PAGING_IN_CACHE_AS_RAM is not set
# CONFIG_IDT_IN_EVERY_STAGE is not set
# CONFIG_PIRQ_ROUTE is not set
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y
# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_SMBUS_HAS_AUX_CHANNELS=y
CONFIG_PCI=y
# CONFIG_NO_MMCONF_SUPPORT is not set
CONFIG_MMCONF_SUPPORT=y
CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_VGA_BIOS_DGPU=y
CONFIG_VGA_BIOS_DGPU_FILE="/dev/null"
CONFIG_VGA_BIOS_DGPU_ID="1000,3050"
# CONFIG_SOFTWARE_I2C is not set
#
# Generic Drivers
#
# CONFIG_DRIVERS_AS3722_RTC is not set
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_MAINBOARD_HAS_CRB_TPM is not set
# CONFIG_GIC is not set
# CONFIG_IPMI_KCS is not set
# CONFIG_DRIVERS_LENOVO_WACOM is not set
# CONFIG_RT8168_GET_MAC_FROM_VPD is not set
# CONFIG_RT8168_SET_LED_MODE is not set
# CONFIG_SMMSTORE_IN_CBFS is not set
CONFIG_SPI_FLASH=y
# CONFIG_SPI_SDCARD is not set
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set
# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set
# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set
CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set
# CONFIG_NO_UART_ON_SUPERIO is not set
# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set
# CONFIG_UART_OVERRIDE_REFCLK is not set
# CONFIG_DRIVERS_UART_8250MEM is not set
# CONFIG_DRIVERS_UART_8250MEM_32 is not set
# CONFIG_HAVE_UART_SPECIAL is not set
# CONFIG_DRIVERS_UART_OXPCIE is not set
# CONFIG_DRIVERS_UART_PL011 is not set
# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_WIFI is not set
# CONFIG_DRIVERS_AMD_PI is not set
CONFIG_DRIVERS_ASPEED_AST2050=y
CONFIG_DRIVERS_ASPEED_AST_COMMON=y
# CONFIG_DRIVERS_I2C_MAX98373 is not set
# CONFIG_DRIVERS_I2C_MAX98927 is not set
# CONFIG_DRIVERS_I2C_PCA9538 is not set
# CONFIG_DRIVERS_I2C_PCF8523 is not set
# CONFIG_DRIVERS_I2C_PTN3460 is not set
# CONFIG_DRIVERS_I2C_RT1011 is not set
# CONFIG_DRIVERS_I2C_RT5663 is not set
# CONFIG_DRIVERS_I2C_RTD2132 is not set
# CONFIG_DRIVERS_I2C_RX6110SA is not set
# CONFIG_DRIVERS_I2C_SX9310 is not set
# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set
# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set
# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set
CONFIG_DRIVERS_I2C_W83795=y
# CONFIG_PLATFORM_USES_FSP1_0 is not set
# CONFIG_PLATFORM_USES_FSP2_0 is not set
# CONFIG_PLATFORM_USES_FSP2_1 is not set
# CONFIG_INTEL_DDI is not set
# CONFIG_INTEL_EDID is not set
# CONFIG_INTEL_INT15 is not set
# CONFIG_INTEL_GMA_ACPI is not set
# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set
# CONFIG_INTEL_GMA_SWSMISCI is not set
# CONFIG_DRIVER_INTEL_I210 is not set
# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set
# CONFIG_HAVE_INTEL_PTT is not set
# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set
# CONFIG_DRIVER_MAXIM_MAX77686 is not set
# CONFIG_DRIVER_PARADE_PS8625 is not set
# CONFIG_DRIVER_PARADE_PS8640 is not set
CONFIG_DRIVERS_MC146818=y
# CONFIG_LPC_TPM is not set
# CONFIG_MAINBOARD_HAS_LPC_TPM is not set
CONFIG_VGA=y
# CONFIG_DRIVERS_RICOH_RCE822 is not set
# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set
# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set
# CONFIG_DRIVERS_SIL_3114 is not set
# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set
# CONFIG_DRIVER_TI_TPS65090 is not set
# CONFIG_DRIVERS_TI_TPS65913 is not set
# CONFIG_DRIVERS_TI_TPS65913_RTC is not set
# CONFIG_DRIVERS_USB_ACPI is not set
# CONFIG_COMMONLIB_STORAGE is not set
#
# Security
#
#
# Verified Boot (vboot)
#
#
# Trusted Platform Module
#
CONFIG_USER_NO_TPM=y
#
# Memory initialization
#
# CONFIG_STM is not set
# CONFIG_ACPI_SATA_GENERATOR is not set
# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set
# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set
# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set
# CONFIG_RTC is not set
#
# Console
#
CONFIG_SQUELCH_EARLY_SMP=y
CONFIG_CONSOLE_SERIAL=y
#
# I/O mapped, 8250-compatible
#
#
# Serial port base address = 0x3f8
#
# CONFIG_CONSOLE_SERIAL_921600 is not set
# CONFIG_CONSOLE_SERIAL_460800 is not set
# CONFIG_CONSOLE_SERIAL_230400 is not set
CONFIG_CONSOLE_SERIAL_115200=y
# CONFIG_CONSOLE_SERIAL_57600 is not set
# CONFIG_CONSOLE_SERIAL_38400 is not set
# CONFIG_CONSOLE_SERIAL_19200 is not set
# CONFIG_CONSOLE_SERIAL_9600 is not set
CONFIG_TTYS0_BAUD=115200
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set
CONFIG_HWBASE_DEBUG_CB=y
CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y
CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y
CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y
# CONFIG_NO_MONOTONIC_TIMER is not set
CONFIG_HAVE_MONOTONIC_TIMER=y
# CONFIG_TIMER_QUEUE is not set
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_PCI_IO_CFG_EXT=y
CONFIG_IOAPIC=y
# CONFIG_USE_WATCHDOG_ON_BOOT is not set
# CONFIG_GFXUMA is not set
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_HAVE_MP_TABLE=y
CONFIG_HAVE_PIRQ_TABLE=y
# CONFIG_COMMON_FADT is not set
# CONFIG_ACPI_NHLT is not set
#
# System tables
#
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_SMBIOS_TABLES=y
# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# CONFIG_PAYLOAD_ELF is not set
# CONFIG_PAYLOAD_BAYOU is not set
# CONFIG_PAYLOAD_FILO is not set
# CONFIG_PAYLOAD_GRUB2 is not set
# CONFIG_PAYLOAD_LINUXBOOT is not set
# CONFIG_PAYLOAD_SEABIOS is not set
# CONFIG_PAYLOAD_UBOOT is not set
# CONFIG_PAYLOAD_YABITS is not set
# CONFIG_PAYLOAD_LINUX is not set
# CONFIG_PAYLOAD_TIANOCORE is not set
CONFIG_PAYLOAD_OPTIONS=""
# CONFIG_PXE is not set
# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set
CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
#
# Secondary Payloads
#
# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
# CONFIG_TINT_SECONDARY_PAYLOAD is not set
#
# Debugging
#
#
# CPU Debug Settings
#
CONFIG_HAVE_DEBUG_CAR=y
# CONFIG_DEBUG_CAR is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_GDB_STUB is not set
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
# CONFIG_DEBUG_PIRQ is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_TRACE is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
# CONFIG_HAVE_EM100_SUPPORT is not set
CONFIG_ENABLE_APIC_EXT_ID=y
CONFIG_WARNINGS_ARE_ERRORS=y
# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
# CONFIG_REG_SCRIPT is not set
# CONFIG_NO_XIP_EARLY_STAGES is not set
# CONFIG_EARLY_CBMEM_LIST is not set
CONFIG_RELOCATABLE_MODULES=y
CONFIG_NO_STAGE_CACHE=y
CONFIG_BOOTBLOCK_CUSTOM=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y

704
config/coreboot/kcma_d8_udimm_2mb/config/libgfxinit_txtmode
View File

@ -1,704 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_NO_RELOCATABLE_RAMSTAGE=y
# CONFIG_RELOCATABLE_RAMSTAGE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_ADI is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_ADVANSUS is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
CONFIG_VENDOR_ASUS=y
# CONFIG_VENDOR_AVALUE is not set
# CONFIG_VENDOR_BAP is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_ELMEX is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ESD is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GIZMOSPHERE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IEI is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_JETWAY is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIPPERT is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SCALEWAY is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TYAN is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="asus/kcma-d8"
CONFIG_MAINBOARD_PART_NUMBER="KCMA-D8"
CONFIG_MAX_CPUS=16
CONFIG_CBFS_SIZE=0x200000
CONFIG_UART_FOR_CONSOLE=0
CONFIG_MAINBOARD_VENDOR="ASUS"
CONFIG_APIC_ID_OFFSET=0x0
CONFIG_HW_MEM_HOLE_SIZEK=0x100000
CONFIG_MAX_PHYSICAL_CPUS=2
CONFIG_HT_CHAIN_END_UNITID_BASE=0x20
CONFIG_HT_CHAIN_UNITID_BASE=0x0
CONFIG_IRQ_SLOT_COUNT=13
CONFIG_VGA_BIOS_ID="1000,0072"
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
CONFIG_DIMM_SPD_SIZE=256
CONFIG_VGA_BIOS=y
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
CONFIG_VGA_BIOS_FILE="/dev/null"
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS"
CONFIG_DEVICETREE="devicetree.cb"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
# CONFIG_BOARD_ASUS_AM1I_A is not set
# CONFIG_BOARD_ASUS_F2A85_M is not set
# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set
# CONFIG_BOARD_ASUS_F2A85_M_LE is not set
# CONFIG_BOARD_ASUS_H61M_CS is not set
CONFIG_BOARD_ASUS_KCMA_D8=y
# CONFIG_BOARD_ASUS_KFSN4_DRE is not set
# CONFIG_BOARD_ASUS_KGPE_D16 is not set
# CONFIG_BOARD_ASUS_M4A78_EM is not set
# CONFIG_BOARD_ASUS_M4A785M is not set
# CONFIG_BOARD_ASUS_M4A785TM is not set
# CONFIG_BOARD_ASUS_M5A88_V is not set
# CONFIG_BOARD_ASUS_MAXIMUS_IV_GENE_Z is not set
# CONFIG_BOARD_ASUS_P2B_D is not set
# CONFIG_BOARD_ASUS_P2B_DS is not set
# CONFIG_BOARD_ASUS_P2B_F is not set
# CONFIG_BOARD_ASUS_P2B_LS is not set
# CONFIG_BOARD_ASUS_P2B is not set
# CONFIG_BOARD_ASUS_P3B_F is not set
# CONFIG_BOARD_ASUS_P5GC_MX is not set
# CONFIG_BOARD_ASUS_P5QC is not set
# CONFIG_BOARD_ASUS_P5Q_PRO is not set
# CONFIG_BOARD_ASUS_P5QL_PRO is not set
# CONFIG_BOARD_ASUS_P5QL_EM is not set
# CONFIG_BOARD_ASUS_P5QPL_AM is not set
# CONFIG_BOARD_ASUS_P5G41T_M_LX is not set
# CONFIG_BOARD_ASUS_P8H61_M_LX is not set
# CONFIG_BOARD_ASUS_P8H61_M_PRO is not set
# CONFIG_BOARD_ASUS_P8Z77_M_PRO is not set
CONFIG_POST_IO=y
CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/asus/kcma-d8/bootblock.c"
CONFIG_DCACHE_RAM_BASE=0xc2000
CONFIG_DCACHE_RAM_SIZE=0x1e000
CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD=0x3f
CONFIG_MAX_REBOOT_CNT=10
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_FMDFILE=""
# CONFIG_VBOOT is not set
CONFIG_MMCONF_BASE_ADDRESS=0xc0000000
CONFIG_POST_DEVICE=y
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_DRIVERS_UART_8250IO=y
CONFIG_DIMM_MAX=4
CONFIG_TTYS0_LCS=3
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KCMA-D8"
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
# CONFIG_USBDEBUG is not set
CONFIG_MAINBOARD_VERSION="1.0"
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_PCIEXP_L1_SUB_STATE=y
# CONFIG_NO_POST is not set
CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03
CONFIG_HEAP_SIZE=0xc0000
# CONFIG_CONSOLE_POST is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_BOARD_ROMSIZE_KB_2048=y
# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
CONFIG_COREBOOT_ROMSIZE_KB_2048=y
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=2048
CONFIG_ROM_SIZE=0x200000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
# CONFIG_SYSTEM_TYPE_LAPTOP is not set
# CONFIG_SYSTEM_TYPE_TABLET is not set
# CONFIG_SYSTEM_TYPE_DETACHABLE is not set
# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set
# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set
#
# Chipset
#
#
# SoC
#
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_CPU_ADDR_BITS=48
CONFIG_MMCONF_BUS_NUMBER=256
CONFIG_EHCI_BAR=0xfef00000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d"
# CONFIG_SOC_CAVIUM_CN81XX is not set
CONFIG_ARCH_ARMV8_EXTENSION=0
CONFIG_STACK_SIZE=0x1000
# CONFIG_SOC_CAVIUM_COMMON is not set
# CONFIG_SOC_INTEL_GLK is not set
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_PCIEXP_CLK_PM=y
CONFIG_TTYS0_BASE=0x3f8
CONFIG_HPET_MIN_TICKS=0x14
CONFIG_UART_PCI_ADDR=0x0
# CONFIG_SOC_MEDIATEK_MT8173 is not set
# CONFIG_SOC_MEDIATEK_MT8183 is not set
# CONFIG_SOC_NVIDIA_TEGRA124 is not set
# CONFIG_SOC_NVIDIA_TEGRA210 is not set
# CONFIG_SOC_QUALCOMM_COMMON is not set
# CONFIG_SOC_QC_IPQ40XX is not set
# CONFIG_SOC_QC_IPQ806X is not set
# CONFIG_SOC_QUALCOMM_QCS405 is not set
# CONFIG_SOC_QUALCOMM_SC7180 is not set
# CONFIG_SOC_QUALCOMM_SDM845 is not set
# CONFIG_SOC_ROCKCHIP_RK3288 is not set
# CONFIG_SOC_ROCKCHIP_RK3399 is not set
# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set
# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set
# CONFIG_SOC_UCB_RISCV is not set
#
# CPU
#
CONFIG_CPU_SOCKET_TYPE=0x14
# CONFIG_EXT_RT_TBL_SUPPORT is not set
CONFIG_CBB=0x0
CONFIG_CDB=0x18
CONFIG_XIP_ROM_SIZE=0x80000
CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA=y
CONFIG_CPU_AMD_MODEL_10XXX=y
CONFIG_USE_LARGE_DCACHE=y
CONFIG_NUM_IPI_STARTS=1
CONFIG_DCACHE_BSP_TOP_STACK_SIZE=0x4000
CONFIG_DCACHE_BSP_TOP_STACK_SLUSH=0x4000
CONFIG_DCACHE_AP_STACK_SIZE=0x500
CONFIG_SET_FIDVID=y
CONFIG_LIFT_BSP_APIC_ID=y
CONFIG_SET_FIDVID_DEBUG=y
CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST=y
# CONFIG_SET_FIDVID_CORE0_ONLY is not set
CONFIG_SET_FIDVID_CORE_RANGE=0
CONFIG_UDELAY_LAPIC_FIXED_FSB=200
# CONFIG_CPU_AMD_AGESA is not set
# CONFIG_CPU_AMD_PI is not set
# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set
CONFIG_SSE2=y
# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set
# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set
# CONFIG_CPU_TI_AM335X is not set
CONFIG_PARALLEL_CPU_INIT=y
# CONFIG_PARALLEL_MP is not set
CONFIG_UDELAY_LAPIC=y
# CONFIG_LAPIC_MONOTONIC_TIMER is not set
# CONFIG_UDELAY_TSC is not set
CONFIG_TSC_SYNC_LFENCE=y
# CONFIG_TSC_SYNC_MFENCE is not set
# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set
CONFIG_LOGICAL_CPUS=y
# CONFIG_HAVE_SMI_HANDLER is not set
# CONFIG_NO_SMM is not set
# CONFIG_SMM_ASEG is not set
CONFIG_SMM_TSEG=y
CONFIG_SMM_MODULE_HEAP_SIZE=0x4000
CONFIG_SMM_STUB_STACK_SIZE=0x400
# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set
# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set
CONFIG_X86_AMD_FIXED_MTRRS=y
# CONFIG_X86_AMD_INIT_SIPI is not set
# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set
# CONFIG_SOC_SETS_MSRS is not set
CONFIG_CAR_GLOBAL_MIGRATION=y
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
# CONFIG_USES_MICROCODE_HEADER_FILES is not set
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y
CONFIG_AGP_APERTURE_SIZE=0x4000000
CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c"
CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=y
# CONFIG_HT_CHAIN_DISTRIBUTE is not set
# CONFIG_DIMM_DDR2 is not set
CONFIG_DIMM_DDR3=y
CONFIG_DIMM_REGISTERED=y
CONFIG_DIMM_VOLTAGE_SET_SUPPORT=y
# CONFIG_SVI_HIGH_FREQ is not set
#
# HyperTransport setup
#
# CONFIG_LIMIT_HT_DOWN_WIDTH_8 is not set
CONFIG_LIMIT_HT_DOWN_WIDTH_16=y
# CONFIG_LIMIT_HT_UP_WIDTH_8 is not set
CONFIG_LIMIT_HT_UP_WIDTH_16=y
# CONFIG_NORTHBRIDGE_AMD_PI is not set
#
# Southbridge
#
CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y
CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/sb700/bootblock.c"
# CONFIG_AMD_SB_CIMX is not set
# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
CONFIG_SOUTHBRIDGE_AMD_SB700=y
CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y
CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100=y
# CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT is not set
CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA=y
CONFIG_SOUTHBRIDGE_AMD_SR5650=y
CONFIG_EXT_CONF_SUPPORT=y
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set
# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set
# CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG is not set
# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set
#
# Super I/O
#
# CONFIG_SUPERIO_ASPEED_AST2400 is not set
# CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM is not set
# CONFIG_SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND is not set
# CONFIG_SUPERIO_FINTEK_FAN_CONTROL is not set
CONFIG_SUPERIO_WINBOND_COMMON_PRE_RAM=y
CONFIG_SUPERIO_WINBOND_W83667HG_A=y
#
# Embedded Controllers
#
# CONFIG_EC_GOOGLE_WILCO is not set
# CONFIG_CAVIUM_BDK is not set
# CONFIG_MAINBOARD_HAS_CHROMEOS is not set
# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set
# CONFIG_UEFI_2_4_BINDING is not set
# CONFIG_UDK_2015_BINDING is not set
# CONFIG_UDK_2017_BINDING is not set
# CONFIG_USE_SIEMENS_HWILIB is not set
# CONFIG_ARM_LPAE is not set
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
# CONFIG_ARCH_POSTCAR_X86_32 is not set
CONFIG_ARCH_RAMSTAGE_X86_32=y
# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set
# CONFIG_ARCH_VERSTAGE_X86_64 is not set
# CONFIG_ARCH_ROMSTAGE_X86_64 is not set
# CONFIG_ARCH_POSTCAR_X86_64 is not set
# CONFIG_ARCH_RAMSTAGE_X86_64 is not set
# CONFIG_USE_MARCH_586 is not set
# CONFIG_AP_IN_SIPI_WAIT is not set
# CONFIG_SIPI_VECTOR_IN_ROM is not set
CONFIG_RAMBASE=0xe00000
CONFIG_RAMTOP=0x1000000
# CONFIG_CBMEM_TOP_BACKUP is not set
CONFIG_PC80_SYSTEM=y
# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
# CONFIG_HPET_ADDRESS_OVERRIDE is not set
CONFIG_HPET_ADDRESS=0xfed00000
CONFIG_ID_SECTION_OFFSET=0x80
# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set
# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
CONFIG_ACPI_HAVE_PCAT_8259=y
# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
# CONFIG_PAGING_IN_CACHE_AS_RAM is not set
# CONFIG_IDT_IN_EVERY_STAGE is not set
# CONFIG_PIRQ_ROUTE is not set
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y
# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_SMBUS_HAS_AUX_CHANNELS=y
CONFIG_PCI=y
# CONFIG_NO_MMCONF_SUPPORT is not set
CONFIG_MMCONF_SUPPORT=y
CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_VGA_BIOS_DGPU=y
CONFIG_VGA_BIOS_DGPU_FILE="/dev/null"
CONFIG_VGA_BIOS_DGPU_ID="1000,3050"
# CONFIG_SOFTWARE_I2C is not set
#
# Generic Drivers
#
# CONFIG_DRIVERS_AS3722_RTC is not set
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_MAINBOARD_HAS_CRB_TPM is not set
# CONFIG_GIC is not set
# CONFIG_IPMI_KCS is not set
# CONFIG_DRIVERS_LENOVO_WACOM is not set
# CONFIG_RT8168_GET_MAC_FROM_VPD is not set
# CONFIG_RT8168_SET_LED_MODE is not set
# CONFIG_SMMSTORE_IN_CBFS is not set
CONFIG_SPI_FLASH=y
# CONFIG_SPI_SDCARD is not set
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set
# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set
# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set
CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set
# CONFIG_NO_UART_ON_SUPERIO is not set
# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set
# CONFIG_UART_OVERRIDE_REFCLK is not set
# CONFIG_DRIVERS_UART_8250MEM is not set
# CONFIG_DRIVERS_UART_8250MEM_32 is not set
# CONFIG_HAVE_UART_SPECIAL is not set
# CONFIG_DRIVERS_UART_OXPCIE is not set
# CONFIG_DRIVERS_UART_PL011 is not set
# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_WIFI is not set
# CONFIG_DRIVERS_AMD_PI is not set
CONFIG_DRIVERS_ASPEED_AST2050=y
CONFIG_DRIVERS_ASPEED_AST_COMMON=y
# CONFIG_DRIVERS_I2C_MAX98373 is not set
# CONFIG_DRIVERS_I2C_MAX98927 is not set
# CONFIG_DRIVERS_I2C_PCA9538 is not set
# CONFIG_DRIVERS_I2C_PCF8523 is not set
# CONFIG_DRIVERS_I2C_PTN3460 is not set
# CONFIG_DRIVERS_I2C_RT1011 is not set
# CONFIG_DRIVERS_I2C_RT5663 is not set
# CONFIG_DRIVERS_I2C_RTD2132 is not set
# CONFIG_DRIVERS_I2C_RX6110SA is not set
# CONFIG_DRIVERS_I2C_SX9310 is not set
# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set
# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set
# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set
CONFIG_DRIVERS_I2C_W83795=y
# CONFIG_PLATFORM_USES_FSP1_0 is not set
# CONFIG_PLATFORM_USES_FSP2_0 is not set
# CONFIG_PLATFORM_USES_FSP2_1 is not set
# CONFIG_INTEL_DDI is not set
# CONFIG_INTEL_EDID is not set
# CONFIG_INTEL_INT15 is not set
# CONFIG_INTEL_GMA_ACPI is not set
# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set
# CONFIG_INTEL_GMA_SWSMISCI is not set
# CONFIG_DRIVER_INTEL_I210 is not set
# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set
# CONFIG_HAVE_INTEL_PTT is not set
# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set
# CONFIG_DRIVER_MAXIM_MAX77686 is not set
# CONFIG_DRIVER_PARADE_PS8625 is not set
# CONFIG_DRIVER_PARADE_PS8640 is not set
CONFIG_DRIVERS_MC146818=y
# CONFIG_LPC_TPM is not set
# CONFIG_MAINBOARD_HAS_LPC_TPM is not set
CONFIG_VGA=y
# CONFIG_DRIVERS_RICOH_RCE822 is not set
# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set
# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set
# CONFIG_DRIVERS_SIL_3114 is not set
# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set
# CONFIG_DRIVER_TI_TPS65090 is not set
# CONFIG_DRIVERS_TI_TPS65913 is not set
# CONFIG_DRIVERS_TI_TPS65913_RTC is not set
# CONFIG_DRIVERS_USB_ACPI is not set
# CONFIG_COMMONLIB_STORAGE is not set
#
# Security
#
#
# Verified Boot (vboot)
#
#
# Trusted Platform Module
#
CONFIG_USER_NO_TPM=y
#
# Memory initialization
#
# CONFIG_STM is not set
# CONFIG_ACPI_SATA_GENERATOR is not set
# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set
# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set
# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set
# CONFIG_RTC is not set
#
# Console
#
CONFIG_SQUELCH_EARLY_SMP=y
CONFIG_CONSOLE_SERIAL=y
#
# I/O mapped, 8250-compatible
#
#
# Serial port base address = 0x3f8
#
# CONFIG_CONSOLE_SERIAL_921600 is not set
# CONFIG_CONSOLE_SERIAL_460800 is not set
# CONFIG_CONSOLE_SERIAL_230400 is not set
CONFIG_CONSOLE_SERIAL_115200=y
# CONFIG_CONSOLE_SERIAL_57600 is not set
# CONFIG_CONSOLE_SERIAL_38400 is not set
# CONFIG_CONSOLE_SERIAL_19200 is not set
# CONFIG_CONSOLE_SERIAL_9600 is not set
CONFIG_TTYS0_BAUD=115200
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set
CONFIG_HWBASE_DEBUG_CB=y
CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y
CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y
CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y
# CONFIG_NO_MONOTONIC_TIMER is not set
CONFIG_HAVE_MONOTONIC_TIMER=y
# CONFIG_TIMER_QUEUE is not set
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_PCI_IO_CFG_EXT=y
CONFIG_IOAPIC=y
# CONFIG_USE_WATCHDOG_ON_BOOT is not set
# CONFIG_GFXUMA is not set
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_HAVE_MP_TABLE=y
CONFIG_HAVE_PIRQ_TABLE=y
# CONFIG_COMMON_FADT is not set
# CONFIG_ACPI_NHLT is not set
#
# System tables
#
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_SMBIOS_TABLES=y
# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# CONFIG_PAYLOAD_ELF is not set
# CONFIG_PAYLOAD_BAYOU is not set
# CONFIG_PAYLOAD_FILO is not set
# CONFIG_PAYLOAD_GRUB2 is not set
# CONFIG_PAYLOAD_LINUXBOOT is not set
# CONFIG_PAYLOAD_SEABIOS is not set
# CONFIG_PAYLOAD_UBOOT is not set
# CONFIG_PAYLOAD_YABITS is not set
# CONFIG_PAYLOAD_LINUX is not set
# CONFIG_PAYLOAD_TIANOCORE is not set
CONFIG_PAYLOAD_OPTIONS=""
# CONFIG_PXE is not set
# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set
CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
#
# Secondary Payloads
#
# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
# CONFIG_TINT_SECONDARY_PAYLOAD is not set
#
# Debugging
#
#
# CPU Debug Settings
#
CONFIG_HAVE_DEBUG_CAR=y
# CONFIG_DEBUG_CAR is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_GDB_STUB is not set
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
# CONFIG_DEBUG_PIRQ is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_TRACE is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
# CONFIG_HAVE_EM100_SUPPORT is not set
CONFIG_ENABLE_APIC_EXT_ID=y
CONFIG_WARNINGS_ARE_ERRORS=y
# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
# CONFIG_REG_SCRIPT is not set
# CONFIG_NO_XIP_EARLY_STAGES is not set
# CONFIG_EARLY_CBMEM_LIST is not set
CONFIG_RELOCATABLE_MODULES=y
CONFIG_NO_STAGE_CACHE=y
CONFIG_BOOTBLOCK_CUSTOM=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y

10
config/coreboot/kcma_d8_udimm_2mb/target.cfg
View File

@ -1,10 +0,0 @@
tree="fam15h_udimm"
xtree="fam15h_rdimm"
xarch="i386-elf"
payload_seabios="y"
payload_grub="y"
payload_memtest="y"
xlang="c"
grub_scan_disk="nvme ahci"
grubtree="nvme"
build_depend="seabios/default grub/nvme memtest86plus"

3
config/coreboot/kfsn4_dre_1mb/config/libgfxinit_txtmode
View File

@ -21,7 +21,8 @@ CONFIG_COMPRESS_RAMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
# CONFIG_USE_BLOBS is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_NO_RELOCATABLE_RAMSTAGE=y

2
config/coreboot/kfsn4_dre_1mb/target.cfg
View File

@ -1,4 +1,4 @@
tree="fam15h_udimm"
tree="fam15h"
xarch="i386-elf"
payload_seabios="y"
payload_memtest="y"

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