diff --git a/config/coreboot/next/patches/0001-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/next/patches/0001-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch index e6af410..e75f8fb 100644 --- a/config/coreboot/next/patches/0001-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch +++ b/config/coreboot/next/patches/0001-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch @@ -1,7 +1,7 @@ -From 8b951349f2ef77916633c817ad2fc1decd5c0920 Mon Sep 17 00:00:00 2001 +From 8761e8ff502e7df30ce7f5950e227c4aa3119c44 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Mon, 30 Sep 2024 20:44:38 -0400 -Subject: [PATCH 1/3] mb/dell: Add Optiplex 780 MT (x4x/ICH10) +Subject: [PATCH 1/7] mb/dell: Add Optiplex 780 MT (x4x/ICH10) Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c Signed-off-by: Nicholas Chin diff --git a/config/coreboot/next/patches/0003-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/next/patches/0002-Remove-warning-for-coreboot-images-built-without-a-p.patch similarity index 91% rename from config/coreboot/next/patches/0003-Remove-warning-for-coreboot-images-built-without-a-p.patch rename to config/coreboot/next/patches/0002-Remove-warning-for-coreboot-images-built-without-a-p.patch index 31bf5a4..d0c02e9 100644 --- a/config/coreboot/next/patches/0003-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/next/patches/0002-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,7 +1,7 @@ -From ddc7390d7750eb3b29a6d6fe7bf2400121d639b5 Mon Sep 17 00:00:00 2001 +From bfe4ae1951bf43f3f4a8512c16bbc10a55397461 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH 3/3] Remove warning for coreboot images built without a +Subject: [PATCH 2/7] Remove warning for coreboot images built without a payload I added this in upstream to prevent people from accidentally flashing diff --git a/config/coreboot/next/patches/0002-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/next/patches/0002-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch deleted file mode 100644 index 5b77c0e..0000000 --- a/config/coreboot/next/patches/0002-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch +++ /dev/null @@ -1,205 +0,0 @@ -From 1b230f671ebc6e355a001ac7ffc9b031329de019 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sun, 19 Feb 2023 18:21:43 +0000 -Subject: [PATCH 2/3] util/ifdtool: add --nuke flag (all 0xFF on region) - -When this option is used, the region's contents are overwritten -with all ones (0xFF). - -Example: - -./ifdtool --nuke gbe coreboot.rom -./ifdtool --nuke bios coreboot.com -./ifdtool --nuke me coreboot.com - -Rebased since the last revision update in lbmk. - -Signed-off-by: Leah Rowe ---- - util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++----------- - 1 file changed, 83 insertions(+), 31 deletions(-) - -diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index 36477eef66..3ebef74042 100644 ---- a/util/ifdtool/ifdtool.c -+++ b/util/ifdtool/ifdtool.c -@@ -2217,6 +2217,7 @@ static void print_usage(const char *name) - " tgl - Tiger Lake\n" - " wbg - Wellsburg\n" - " -S | --setpchstrap Write a PCH strap\n" -+ " -N | --nuke Overwrite the specified region with 0xFF (all ones)\n" - " -V | --newvalue The new value to write into PCH strap specified by -S\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" -@@ -2225,6 +2226,60 @@ static void print_usage(const char *name) - "\n"); - } - -+static int -+get_region_type_string(const char *region_type_string) -+{ -+ if (!strcasecmp("Descriptor", region_type_string)) -+ return 0; -+ else if (!strcasecmp("BIOS", region_type_string)) -+ return 1; -+ else if (!strcasecmp("ME", region_type_string)) -+ return 2; -+ else if (!strcasecmp("GbE", region_type_string)) -+ return 3; -+ else if (!strcasecmp("Platform Data", region_type_string)) -+ return 4; -+ else if (!strcasecmp("Device Exp1", region_type_string)) -+ return 5; -+ else if (!strcasecmp("Secondary BIOS", region_type_string)) -+ return 6; -+ else if (!strcasecmp("Reserved", region_type_string)) -+ return 7; -+ else if (!strcasecmp("EC", region_type_string)) -+ return 8; -+ else if (!strcasecmp("Device Exp2", region_type_string)) -+ return 9; -+ else if (!strcasecmp("IE", region_type_string)) -+ return 10; -+ else if (!strcasecmp("10GbE_0", region_type_string)) -+ return 11; -+ else if (!strcasecmp("10GbE_1", region_type_string)) -+ return 12; -+ else if (!strcasecmp("PTT", region_type_string)) -+ return 15; -+ return -1; -+} -+ -+static void -+nuke(const char *filename, char *image, int size, int region_type) -+{ -+ int i; -+ struct region region; -+ const struct frba *frba = find_frba(image, size); -+ if (!frba) -+ exit(EXIT_FAILURE); -+ -+ region = get_region(frba, region_type); -+ if (region.size > 0) { -+ for (i = region.base; i <= region.limit; i++) { -+ if ((i + 1) > (size)) -+ break; -+ image[i] = 0xFF; -+ } -+ write_image(filename, image, size); -+ } -+} -+ - int main(int argc, char *argv[]) - { - int opt, option_index = 0; -@@ -2232,6 +2287,7 @@ int main(int argc, char *argv[]) - int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; - int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; - int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; -+ int mode_nuke = 0; - int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0; - char *region_type_string = NULL, *region_fname = NULL; - const char *layout_fname = NULL; -@@ -2267,6 +2323,7 @@ int main(int argc, char *argv[]) - {"validate", 0, NULL, 't'}, - {"setpchstrap", 1, NULL, 'S'}, - {"newvalue", 1, NULL, 'V'}, -+ {"nuke", 1, NULL, 'N'}, - {0, 0, 0, 0} - }; - -@@ -2316,35 +2373,8 @@ int main(int argc, char *argv[]) - region_fname++; - // Descriptor, BIOS, ME, GbE, Platform - // valid type? -- if (!strcasecmp("Descriptor", region_type_string)) -- region_type = 0; -- else if (!strcasecmp("BIOS", region_type_string)) -- region_type = 1; -- else if (!strcasecmp("ME", region_type_string)) -- region_type = 2; -- else if (!strcasecmp("GbE", region_type_string)) -- region_type = 3; -- else if (!strcasecmp("Platform Data", region_type_string)) -- region_type = 4; -- else if (!strcasecmp("Device Exp1", region_type_string)) -- region_type = 5; -- else if (!strcasecmp("Secondary BIOS", region_type_string)) -- region_type = 6; -- else if (!strcasecmp("Reserved", region_type_string)) -- region_type = 7; -- else if (!strcasecmp("EC", region_type_string)) -- region_type = 8; -- else if (!strcasecmp("Device Exp2", region_type_string)) -- region_type = 9; -- else if (!strcasecmp("IE", region_type_string)) -- region_type = 10; -- else if (!strcasecmp("10GbE_0", region_type_string)) -- region_type = 11; -- else if (!strcasecmp("10GbE_1", region_type_string)) -- region_type = 12; -- else if (!strcasecmp("PTT", region_type_string)) -- region_type = 15; -- if (region_type == -1) { -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { - fprintf(stderr, "No such region type: '%s'\n\n", - region_type_string); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); -@@ -2521,6 +2551,22 @@ int main(int argc, char *argv[]) - case 't': - mode_validate = 1; - break; -+ case 'N': -+ region_type_string = strdup(optarg); -+ if (!region_type_string) { -+ fprintf(stderr, "No region specified\n"); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { -+ fprintf(stderr, "No such region type: '%s'\n\n", -+ region_type_string); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ mode_nuke = 1; -+ break; - case 'v': - print_version(); - exit(EXIT_SUCCESS); -@@ -2540,7 +2586,8 @@ int main(int argc, char *argv[]) - if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | - mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + -- (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) { -+ (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status + -+ mode_nuke) > 1) { - fprintf(stderr, "You may not specify more than one mode.\n\n"); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); - exit(EXIT_FAILURE); -@@ -2549,7 +2596,8 @@ int main(int argc, char *argv[]) - if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + - mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + - mode_locked + mode_unlocked + mode_density + mode_altmedisable + -- mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) { -+ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status + -+ mode_nuke) == 0) { - fprintf(stderr, "You need to specify a mode.\n\n"); - fprintf(stderr, "run '%s -h' for usage\n", argv[0]); - exit(EXIT_FAILURE); -@@ -2662,6 +2710,10 @@ int main(int argc, char *argv[]) - write_image(new_filename, image, size); - } - -+ if (mode_nuke) { -+ nuke(new_filename, image, size, region_type); -+ } -+ - if (mode_altmedisable) { - struct fpsba *fpsba = find_fpsba(image, size); - struct fmsba *fmsba = find_fmsba(image, size); --- -2.39.5 - diff --git a/config/coreboot/next/patches/0004-mb-dell-optiplex_780-Add-USFF-variant.patch b/config/coreboot/next/patches/0003-mb-dell-optiplex_780-Add-USFF-variant.patch similarity index 98% rename from config/coreboot/next/patches/0004-mb-dell-optiplex_780-Add-USFF-variant.patch rename to config/coreboot/next/patches/0003-mb-dell-optiplex_780-Add-USFF-variant.patch index 875a4b2..3f8c4dc 100644 --- a/config/coreboot/next/patches/0004-mb-dell-optiplex_780-Add-USFF-variant.patch +++ b/config/coreboot/next/patches/0003-mb-dell-optiplex_780-Add-USFF-variant.patch @@ -1,7 +1,7 @@ -From 300f73eae58bfcde26f82814a5e295585b3e3a2a Mon Sep 17 00:00:00 2001 +From 173989476c90e3d15c0f5f7e669b16bc496349aa Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Wed, 30 Oct 2024 20:55:25 -0600 -Subject: [PATCH 1/1] mb/dell/optiplex_780: Add USFF variant +Subject: [PATCH 3/7] mb/dell/optiplex_780: Add USFF variant Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103 Signed-off-by: Nicholas Chin diff --git a/config/coreboot/next/patches/0005-never-enable-cpu-microcode-even-if-told-to.patch b/config/coreboot/next/patches/0004-never-enable-cpu-microcode-even-if-told-to.patch similarity index 97% rename from config/coreboot/next/patches/0005-never-enable-cpu-microcode-even-if-told-to.patch rename to config/coreboot/next/patches/0004-never-enable-cpu-microcode-even-if-told-to.patch index 58d6725..0693756 100644 --- a/config/coreboot/next/patches/0005-never-enable-cpu-microcode-even-if-told-to.patch +++ b/config/coreboot/next/patches/0004-never-enable-cpu-microcode-even-if-told-to.patch @@ -1,7 +1,7 @@ -From 146f8792f57ee237d07e4ca506fb77c93ed27932 Mon Sep 17 00:00:00 2001 +From 268e6e585e38493fcb772b4bea967023fdaca413 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 12 Oct 2023 01:20:23 +0100 -Subject: [PATCH 1/2] never enable cpu microcode, even if told to +Subject: [PATCH 4/7] never enable cpu microcode, even if told to Signed-off-by: Leah Rowe --- diff --git a/config/coreboot/next/patches/0006-Never-download-blobs-even-if-USE_BLOBS-y.patch b/config/coreboot/next/patches/0005-Never-download-blobs-even-if-USE_BLOBS-y.patch similarity index 93% rename from config/coreboot/next/patches/0006-Never-download-blobs-even-if-USE_BLOBS-y.patch rename to config/coreboot/next/patches/0005-Never-download-blobs-even-if-USE_BLOBS-y.patch index 24a4030..3a92bf7 100644 --- a/config/coreboot/next/patches/0006-Never-download-blobs-even-if-USE_BLOBS-y.patch +++ b/config/coreboot/next/patches/0005-Never-download-blobs-even-if-USE_BLOBS-y.patch @@ -1,7 +1,7 @@ -From 7d63d1b21650238300250f7408335d650447c3d6 Mon Sep 17 00:00:00 2001 +From ff1c1618fbdca6d53aa348c5970069ba1bae1de6 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 3 May 2024 06:24:49 +0100 -Subject: [PATCH 2/2] Never download blobs, even if USE_BLOBS=y +Subject: [PATCH 5/7] Never download blobs, even if USE_BLOBS=y same idea as my never-microcode patches. i maintain canoeboot and i like to re-use the same configs from diff --git a/config/coreboot/next/patches/0006-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/next/patches/0006-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch new file mode 100644 index 0000000..72334bf --- /dev/null +++ b/config/coreboot/next/patches/0006-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch @@ -0,0 +1,47 @@ +From eabfef6cdd2d10e8c5097839fb24a65d8ffedaed Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 1 Dec 2021 02:53:00 +0000 +Subject: [PATCH 6/7] fix speedstep on x200/t400: Revert + "cpu/intel/model_1067x: enable PECI" + +This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f. + +Enabling PECI without microcode updates loaded causes the CPUID feature set +to become corrupted. And one consequence is broken SpeedStep. At least, that's +my understanding looking at Intel Errata. This revert is not a fix, because +upstream is correct (upstream assumes microcode updates). We will simply +maintain this revert patch in Libreboot, from now on. +--- + src/cpu/intel/model_1067x/model_1067x_init.c | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c +index d051e8915b..30ba2bf0c6 100644 +--- a/src/cpu/intel/model_1067x/model_1067x_init.c ++++ b/src/cpu/intel/model_1067x/model_1067x_init.c +@@ -141,8 +141,6 @@ static void configure_emttm_tables(void) + wrmsr(MSR_EMTTM_CR_TABLE(5), msr); + } + +-#define IA32_PECI_CTL 0x5a0 +- + static void configure_misc(const int eist, const int tm2, const int emttm) + { + msr_t msr; +@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm) + msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLE, msr); + } +- +- /* Enable PECI +- WARNING: due to Erratum AW67 described in Intel document #318733 +- the microcode must be updated before this MSR is written to. */ +- msr = rdmsr(IA32_PECI_CTL); +- msr.lo |= 1; +- wrmsr(IA32_PECI_CTL, msr); + } + + #define PIC_SENS_CFG 0x1aa +-- +2.39.5 + diff --git a/config/coreboot/next/patches/0007-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/config/coreboot/next/patches/0007-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch new file mode 100644 index 0000000..b16e0dc --- /dev/null +++ b/config/coreboot/next/patches/0007-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch @@ -0,0 +1,173 @@ +From 015cb964c94d46a2d06bf3add34031e2be40b260 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 17 Apr 2023 15:49:57 +0100 +Subject: [PATCH 7/7] GM45-type CPUs: don't enable alternative SMRR + +This reverts the changes in coreboot revision: +df7aecd92643d207feaf7fd840f8835097346644 + +While this fix is *technically correct*, the one in +coreboot, it breaks rebooting as tested on several +GM45 ThinkPads e.g. X200, T400, when microcode +updates are not applied. + +Since November 2022, Libreboot includes microcode +updates by default, but it tells users how to remove +it from the ROM (with cbfstool) if they wish. + +Well, with Libreboot 20221214, 20230319 and 20230413, +mitigations present in Libreboot 20220710 (which did +not have microcode updates) do not exist. + +This patch, along with the other patch to remove PECI +support (which breaks speedstep when microcode updates +are not applied) have now been re-added to Libreboot. + +It is still best to use microcode updates by default. +These patches in coreboot are not critically urgent, +and you can use the machines with or without them, +regardless of ucode. + +I'll probably re-write this and the other patch at +some point, applying the change conditionally upon +whether or not microcode is applied. + +Pragmatism is a good thing. I recommend it. +--- + src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++ + src/cpu/intel/model_1067x/mp_init.c | 26 -------------------- + src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++ + src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++ + src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++ + 5 files changed, 16 insertions(+), 26 deletions(-) + +diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c +index 30ba2bf0c6..312046901a 100644 +--- a/src/cpu/intel/model_1067x/model_1067x_init.c ++++ b/src/cpu/intel/model_1067x/model_1067x_init.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + + #define MSR_BBL_CR_CTL3 0x11e + +@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu) + fill_processor_name(processor_name); + printk(BIOS_INFO, "CPU: %s.\n", processor_name); + ++ /* Set virtualization based on Kconfig option */ ++ set_vmx_and_lock(); ++ + /* Configure C States */ + configure_c_states(quad); + +diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c +index bc53214310..72f40f6762 100644 +--- a/src/cpu/intel/model_1067x/mp_init.c ++++ b/src/cpu/intel/model_1067x/mp_init.c +@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void) + smm_initialize(); + } + +-#define SMRR_SUPPORTED (1 << 11) +- + static void per_cpu_smm_trigger(void) + { +- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); +- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) { +- set_feature_ctrl_vmx(); +- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL); +- /* We don't care if the lock is already setting +- as our smm relocation handler is able to handle +- setups where SMRR is not enabled here. */ +- if (ia32_ft_ctrl.lo & (1 << 0)) { +- /* IA32_FEATURE_CONTROL locked. If we set it again we +- get an illegal instruction. */ +- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n"); +- printk(BIOS_DEBUG, "SMRR status: %senabled\n", +- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not "); +- } else { +- if (!CONFIG(SET_IA32_FC_LOCK_BIT)) +- printk(BIOS_INFO, +- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n"); +- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); +- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl); +- } +- } else { +- set_vmx_and_lock(); +- } +- + /* Relocate the SMM handler. */ + smm_relocate(); + } +diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c +index 05f5f327cc..0450c2ad83 100644 +--- a/src/cpu/intel/model_106cx/model_106cx_init.c ++++ b/src/cpu/intel/model_106cx/model_106cx_init.c +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + + #define HIGHEST_CLEVEL 3 + static void configure_c_states(void) +@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu) + fill_processor_name(processor_name); + printk(BIOS_INFO, "CPU: %s.\n", processor_name); + ++ /* Set virtualization based on Kconfig option */ ++ set_vmx_and_lock(); ++ + /* Configure C States */ + configure_c_states(); + +diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c +index 5bd1c32815..f3bb08cde3 100644 +--- a/src/cpu/intel/model_6ex/model_6ex_init.c ++++ b/src/cpu/intel/model_6ex/model_6ex_init.c +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + + #define HIGHEST_CLEVEL 3 + static void configure_c_states(void) +@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu) + /* Setup Page Attribute Tables (PAT) */ + // TODO set up PAT + ++ /* Set virtualization based on Kconfig option */ ++ set_vmx_and_lock(); ++ + /* Configure C States */ + configure_c_states(); + +diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c +index 535fb8fae7..f7b05facd2 100644 +--- a/src/cpu/intel/model_6fx/model_6fx_init.c ++++ b/src/cpu/intel/model_6fx/model_6fx_init.c +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + + #define HIGHEST_CLEVEL 3 + static void configure_c_states(void) +@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu) + /* Setup Page Attribute Tables (PAT) */ + // TODO set up PAT + ++ /* Set virtualization based on Kconfig option */ ++ set_vmx_and_lock(); ++ + /* Configure C States */ + configure_c_states(); + +-- +2.39.5 +