diff --git a/build b/build index c607527..647b8d6 100755 --- a/build +++ b/build @@ -8,6 +8,9 @@ [ "x${DEBUG+set}" = 'xset' ] && set -v set -u -e +export LC_COLLATE=C +export LC_ALL=C + . "include/err.sh" . "include/option.sh" diff --git a/config/coreboot/d510mo/config/libgfxinit_txtmode b/config/coreboot/d510mo/config/libgfxinit_txtmode index 6b75d92..e57c6ed 100644 --- a/config/coreboot/d510mo/config/libgfxinit_txtmode +++ b/config/coreboot/d510mo/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -209,6 +209,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -499,7 +500,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/d510mo_16mb/config/libgfxinit_txtmode b/config/coreboot/d510mo_16mb/config/libgfxinit_txtmode index 227d426..db50e6a 100644 --- a/config/coreboot/d510mo_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/d510mo_16mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -209,6 +209,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -499,7 +500,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/d945gclf_512kb/config/libgfxinit_txtmode b/config/coreboot/d945gclf_512kb/config/libgfxinit_txtmode new file mode 100644 index 0000000..724641b --- /dev/null +++ b/config/coreboot/d945gclf_512kb/config/libgfxinit_txtmode @@ -0,0 +1,591 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +CONFIG_VENDOR_INTEL=y +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="D945GCLF" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="intel/d945gclf" +CONFIG_VGA_BIOS_ID="8086,2772" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Intel" +CONFIG_CBFS_SIZE=0x00080000 +CONFIG_MAX_CPUS=4 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xfefc0000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_DRIVERS_INTEL_WIFI is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_VBT_DATA_SIZE_KB=8 +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_INTEL_ADLRVP_P is not set +# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set +# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set +# CONFIG_BOARD_INTEL_ADLRVP_M is not set +# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set +# CONFIG_BOARD_INTEL_ADLRVP_N is not set +# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set +# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set +# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set +# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set +# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set +# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set +# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set +# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set + +# +# Coffeelake RVP +# +# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set +# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set +# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set +# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set +# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set +# CONFIG_BOARD_INTEL_D510MO is not set +CONFIG_BOARD_INTEL_D945GCLF=y +# CONFIG_BOARD_INTEL_DCP847SKE is not set +# CONFIG_BOARD_INTEL_DG41WV is not set +# CONFIG_BOARD_INTEL_DG43GT is not set +# CONFIG_BOARD_INTEL_DQ67SW is not set +# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set +# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set +# CONFIG_BOARD_INTEL_GLKRVP is not set +# CONFIG_BOARD_INTEL_HARCUVAR is not set +# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set +# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set +# CONFIG_BOARD_INTEL_KBLRVP3 is not set +# CONFIG_BOARD_INTEL_KBLRVP7 is not set +# CONFIG_BOARD_INTEL_KBLRVP8 is not set +# CONFIG_BOARD_INTEL_KBLRVP11 is not set +# CONFIG_BOARD_INTEL_KUNIMITSU is not set +# CONFIG_BOARD_INTEL_LEAFHILL is not set +# CONFIG_BOARD_INTEL_MINNOW3 is not set +# CONFIG_BOARD_INTEL_MTLRVP_P is not set +# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set +# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set +# CONFIG_BOARD_INTEL_SKLSDLBRK is not set +# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set +# CONFIG_BOARD_INTEL_STRAGO is not set +# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set +# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set +# CONFIG_BOARD_INTEL_WTM2 is not set +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF" +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_D3COLD_SUPPORT=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_512=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +CONFIG_COREBOOT_ROMSIZE_KB_512=y +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=512 +CONFIG_ROM_SIZE=0x00080000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_COMMON_CLOCK is not set +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_CBFS_CACHE_ALIGN=8 +CONFIG_INTEL_HAS_TOP_SWAP=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set +CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 + +# +# CPU +# +CONFIG_CPU_INTEL_MODEL_106CX=y +CONFIG_CPU_INTEL_SOCKET_441=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_SETUP_XIP_CACHE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_I945=y +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_LPC47M15X=y + +# +# Embedded Controllers +# +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_AP_IN_SIPI_WAIT=y +CONFIG_SIPI_VECTOR_IN_ROM=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR2=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_NULL=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_DEBUG_PIRQ is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/d945gclf_512kb/target.cfg b/config/coreboot/d945gclf_512kb/target.cfg new file mode 100644 index 0000000..4b9708e --- /dev/null +++ b/config/coreboot/d945gclf_512kb/target.cfg @@ -0,0 +1,9 @@ +tree="default" +romtype="normal" +arch="x86_32" +payload_grub="n" +payload_grub_withseabios="n" +payload_seabios="y" +payload_memtest="n" +vendorfiles="n" +microcode_required="n" diff --git a/config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode b/config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode new file mode 100644 index 0000000..50a935f --- /dev/null +++ b/config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode @@ -0,0 +1,591 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +CONFIG_VENDOR_INTEL=y +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="D945GCLF" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="intel/d945gclf" +CONFIG_VGA_BIOS_ID="8086,2772" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Intel" +CONFIG_CBFS_SIZE=0x00800000 +CONFIG_MAX_CPUS=4 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xfefc0000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_DRIVERS_INTEL_WIFI is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_VBT_DATA_SIZE_KB=8 +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_BOARD_INTEL_ADLRVP_P is not set +# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set +# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set +# CONFIG_BOARD_INTEL_ADLRVP_M is not set +# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set +# CONFIG_BOARD_INTEL_ADLRVP_N is not set +# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set +# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set +# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set +# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set +# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set +# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set +# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set +# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set + +# +# Coffeelake RVP +# +# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set +# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set +# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set +# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set +# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set +# CONFIG_BOARD_INTEL_D510MO is not set +CONFIG_BOARD_INTEL_D945GCLF=y +# CONFIG_BOARD_INTEL_DCP847SKE is not set +# CONFIG_BOARD_INTEL_DG41WV is not set +# CONFIG_BOARD_INTEL_DG43GT is not set +# CONFIG_BOARD_INTEL_DQ67SW is not set +# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set +# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set +# CONFIG_BOARD_INTEL_GLKRVP is not set +# CONFIG_BOARD_INTEL_HARCUVAR is not set +# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set +# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set +# CONFIG_BOARD_INTEL_KBLRVP3 is not set +# CONFIG_BOARD_INTEL_KBLRVP7 is not set +# CONFIG_BOARD_INTEL_KBLRVP8 is not set +# CONFIG_BOARD_INTEL_KBLRVP11 is not set +# CONFIG_BOARD_INTEL_KUNIMITSU is not set +# CONFIG_BOARD_INTEL_LEAFHILL is not set +# CONFIG_BOARD_INTEL_MINNOW3 is not set +# CONFIG_BOARD_INTEL_MTLRVP_P is not set +# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set +# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set +# CONFIG_BOARD_INTEL_SKLSDLBRK is not set +# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set +# CONFIG_BOARD_INTEL_STRAGO is not set +# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set +# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set +# CONFIG_BOARD_INTEL_WTM2 is not set +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF" +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_D3COLD_SUPPORT=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_512=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x00800000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_COMMON_CLOCK is not set +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_CBFS_CACHE_ALIGN=8 +CONFIG_INTEL_HAS_TOP_SWAP=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set +CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 + +# +# CPU +# +CONFIG_CPU_INTEL_MODEL_106CX=y +CONFIG_CPU_INTEL_SOCKET_441=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_SETUP_XIP_CACHE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_I945=y +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_LPC47M15X=y + +# +# Embedded Controllers +# +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_AP_IN_SIPI_WAIT=y +CONFIG_SIPI_VECTOR_IN_ROM=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR2=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_NULL=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_DEBUG_PIRQ is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/d945gclf_8mb/target.cfg b/config/coreboot/d945gclf_8mb/target.cfg new file mode 100644 index 0000000..4b9708e --- /dev/null +++ b/config/coreboot/d945gclf_8mb/target.cfg @@ -0,0 +1,9 @@ +tree="default" +romtype="normal" +arch="x86_32" +payload_grub="n" +payload_grub_withseabios="n" +payload_seabios="y" +payload_memtest="n" +vendorfiles="n" +microcode_required="n" diff --git a/config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch b/config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch new file mode 100644 index 0000000..cca8901 --- /dev/null +++ b/config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch @@ -0,0 +1,341 @@ +From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 29 Oct 2023 01:18:50 +0000 +Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large + value" + +This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6. + +NOTE: + +this is done instead of merging: +https://review.coreboot.org/c/coreboot/+/78623 + +which is still under review for now + +the patch i'm reverting is this one: +https://review.coreboot.org/c/coreboot/+/78270 + +this was actually only merged the day before i +updated coreboot revs in lbmk to the 12 october rev, +so there's no harm in quickly reverting this for now + +however, later on, we will rely on the other patch +--- + src/Kconfig | 3 ++- + src/cpu/qemu-x86/Kconfig | 3 +++ + src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++ + src/northbridge/amd/pi/Kconfig | 4 ++++ + src/soc/amd/picasso/Kconfig | 4 ++++ + src/soc/amd/stoneyridge/Kconfig | 4 ++++ + src/soc/cavium/cn81xx/Kconfig | 3 +++ + src/soc/intel/alderlake/Kconfig | 5 +++++ + src/soc/intel/apollolake/Kconfig | 4 ++++ + src/soc/intel/cannonlake/Kconfig | 4 ++++ + src/soc/intel/elkhartlake/Kconfig | 4 ++++ + src/soc/intel/jasperlake/Kconfig | 4 ++++ + src/soc/intel/meteorlake/Kconfig | 5 +++++ + src/soc/intel/skylake/Kconfig | 4 ++++ + src/soc/intel/tigerlake/Kconfig | 4 ++++ + src/soc/intel/xeon_sp/Kconfig | 4 ++++ + src/soc/intel/xeon_sp/cpx/Kconfig | 4 ++++ + src/soc/intel/xeon_sp/skx/Kconfig | 4 ++++ + src/soc/intel/xeon_sp/spr/Kconfig | 4 ++++ + src/soc/qualcomm/ipq40xx/Kconfig | 4 ++++ + 20 files changed, 77 insertions(+), 1 deletion(-) + +diff --git a/src/Kconfig b/src/Kconfig +index ae8024089e..1549719dd0 100644 +--- a/src/Kconfig ++++ b/src/Kconfig +@@ -751,7 +751,8 @@ config RTC + + config HEAP_SIZE + hex +- default 0x100000 ++ default 0x100000 if FLATTENED_DEVICE_TREE ++ default 0x4000 + + config STACK_SIZE + hex +diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig +index 0fa999e1ac..f3e2c4cea9 100644 +--- a/src/cpu/qemu-x86/Kconfig ++++ b/src/cpu/qemu-x86/Kconfig +@@ -35,4 +35,7 @@ config MAX_CPUS + default 32 if SMM_TSEG + default 4 + ++config HEAP_SIZE ++ default 0x8000 ++ + endif +diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig +index 7bc3b0bcbb..7f9300f2a7 100644 +--- a/src/mainboard/sifive/hifive-unleashed/Kconfig ++++ b/src/mainboard/sifive/hifive-unleashed/Kconfig +@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS + select FLATTENED_DEVICE_TREE + select SPI_SDCARD + ++config HEAP_SIZE ++ default 0x10000 ++ + config MAINBOARD_DIR + default "sifive/hifive-unleashed" + +diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig +index 4ffe82a15f..4518db149b 100644 +--- a/src/northbridge/amd/pi/Kconfig ++++ b/src/northbridge/amd/pi/Kconfig +@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + ++config HEAP_SIZE ++ hex ++ default 0xc0000 ++ + endif # NORTHBRIDGE_AMD_PI +diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig +index c33f287067..796fe4eb13 100644 +--- a/src/soc/amd/picasso/Kconfig ++++ b/src/soc/amd/picasso/Kconfig +@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN + bool + default n + ++config HEAP_SIZE ++ hex ++ default 0xc0000 ++ + config SERIRQ_CONTINUOUS_MODE + bool + default n +diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig +index 6ff135e6a8..9af7455bae 100644 +--- a/src/soc/amd/stoneyridge/Kconfig ++++ b/src/soc/amd/stoneyridge/Kconfig +@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN + bool + default n + ++config HEAP_SIZE ++ hex ++ default 0xc0000 ++ + config EHCI_BAR + hex + default 0xfef00000 +diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig +index 77ca97202b..368581f8f1 100644 +--- a/src/soc/cavium/cn81xx/Kconfig ++++ b/src/soc/cavium/cn81xx/Kconfig +@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION + int + default 1 + ++config HEAP_SIZE ++ default 0x10000 ++ + config STACK_SIZE + default 0x2000 + +diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig +index 4b960c1d22..82ec8f263e 100644 +--- a/src/soc/intel/alderlake/Kconfig ++++ b/src/soc/intel/alderlake/Kconfig +@@ -215,6 +215,11 @@ config IED_REGION_SIZE + hex + default 0x400000 + ++config HEAP_SIZE ++ hex ++ default 0x80000 if BMP_LOGO ++ default 0x10000 ++ + config GFX_GMA_DEFAULT_MMIO + default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT + +diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig +index 78ec2987ce..bce935d800 100644 +--- a/src/soc/intel/apollolake/Kconfig ++++ b/src/soc/intel/apollolake/Kconfig +@@ -252,6 +252,10 @@ config IFWI_FILE_NAME + help + Name of file to store in the IFWI region. + ++config HEAP_SIZE ++ hex ++ default 0x8000 ++ + config MAX_ROOT_PORTS + int + default 6 +diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig +index a42a3c365b..80237f9810 100644 +--- a/src/soc/intel/cannonlake/Kconfig ++++ b/src/soc/intel/cannonlake/Kconfig +@@ -160,6 +160,10 @@ config IED_REGION_SIZE + hex + default 0x400000 + ++config HEAP_SIZE ++ hex ++ default 0x8000 ++ + config NHLT_DMIC_1CH_16B + bool + depends on ACPI_NHLT +diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig +index 3361c0ddb9..7f1c767379 100644 +--- a/src/soc/intel/elkhartlake/Kconfig ++++ b/src/soc/intel/elkhartlake/Kconfig +@@ -104,6 +104,10 @@ config IED_REGION_SIZE + hex + default 0x0 + ++config HEAP_SIZE ++ hex ++ default 0x8000 ++ + config MAX_ROOT_PORTS + int + default 7 +diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig +index 3d84991e09..ff5def3263 100644 +--- a/src/soc/intel/jasperlake/Kconfig ++++ b/src/soc/intel/jasperlake/Kconfig +@@ -106,6 +106,10 @@ config IED_REGION_SIZE + hex + default 0x400000 + ++config HEAP_SIZE ++ hex ++ default 0x8000 ++ + config MAX_ROOT_PORTS + int + default 8 +diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig +index 590e8b80e1..48030a1911 100644 +--- a/src/soc/intel/meteorlake/Kconfig ++++ b/src/soc/intel/meteorlake/Kconfig +@@ -197,6 +197,11 @@ config IED_REGION_SIZE + hex + default 0x400000 + ++config HEAP_SIZE ++ hex ++ default 0x80000 if BMP_LOGO ++ default 0x10000 ++ + # Intel recommends reserving the PCIe TBT root port resources as below: + # - 42 buses + # - 194 MiB Non-prefetchable memory +diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig +index e0df501460..d6a11363ee 100644 +--- a/src/soc/intel/skylake/Kconfig ++++ b/src/soc/intel/skylake/Kconfig +@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE + help + If you set this option to n, will not use native SD controller. + ++config HEAP_SIZE ++ hex ++ default 0x80000 ++ + config IED_REGION_SIZE + hex + default 0x400000 +diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig +index c07a0d8365..0a4b7bfdb8 100644 +--- a/src/soc/intel/tigerlake/Kconfig ++++ b/src/soc/intel/tigerlake/Kconfig +@@ -152,6 +152,10 @@ config IED_REGION_SIZE + config INTEL_TME + default n + ++config HEAP_SIZE ++ hex ++ default 0x10000 ++ + config MAX_ROOT_PORTS + int + default 24 if SOC_INTEL_TIGERLAKE_PCH_H +diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig +index e63bee5451..63ced01067 100644 +--- a/src/soc/intel/xeon_sp/Kconfig ++++ b/src/soc/intel/xeon_sp/Kconfig +@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS + config ECAM_MMCONF_BUS_NUMBER + default 256 + ++config HEAP_SIZE ++ hex ++ default 0x80000 ++ + config HPET_MIN_TICKS + hex + default 0x80 +diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig +index ac166c3038..f54f7716b6 100644 +--- a/src/soc/intel/xeon_sp/cpx/Kconfig ++++ b/src/soc/intel/xeon_sp/cpx/Kconfig +@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN + hex + default 0x7C00 + ++config HEAP_SIZE ++ hex ++ default 0x80000 ++ + config STACK_SIZE + hex + default 0x4000 +diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig +index 5d843878e1..c2c3d4e2e8 100644 +--- a/src/soc/intel/xeon_sp/skx/Kconfig ++++ b/src/soc/intel/xeon_sp/skx/Kconfig +@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN + hex + default 0x7C00 + ++config HEAP_SIZE ++ hex ++ default 0x80000 ++ + config IED_REGION_SIZE + hex + default 0x400000 +diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig +index 43b87ade14..b1c4c783b7 100644 +--- a/src/soc/intel/xeon_sp/spr/Kconfig ++++ b/src/soc/intel/xeon_sp/spr/Kconfig +@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN + hex + default 0x8c00 + ++config HEAP_SIZE ++ hex ++ default 0x80000 ++ + config STACK_SIZE + hex + default 0x4000 +diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig +index 0ce92731c0..0eabb00752 100644 +--- a/src/soc/qualcomm/ipq40xx/Kconfig ++++ b/src/soc/qualcomm/ipq40xx/Kconfig +@@ -57,4 +57,8 @@ config SBL_UTIL_PATH + help + Path for utils to combine SBL_ELF and bootblock + ++config HEAP_SIZE ++ hex ++ default 0x8000 ++ + endif +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch new file mode 100644 index 0000000..454e3e7 --- /dev/null +++ b/config/coreboot/default/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch @@ -0,0 +1,216 @@ +From e047dc3c95063f27517cd6754e9cbe496ac9313d Mon Sep 17 00:00:00 2001 +From: Angel Pons +Date: Mon, 10 May 2021 22:40:59 +0200 +Subject: [PATCH] [NOT FOR MERGE] nb/intel/gm45: Make DDR2 raminit work + +List of changes: + - Update some timing and ODT values + - Patch RCOMP calibration to better match what MRC binaries do + - Replay a hardcoded list of RCOMP codes after RcvEn + +This makes raminit work at DDR2-800 speeds and fixes S3 resume as well. +Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs. + +Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c +Signed-off-by: Angel Pons +--- + +diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h +index f28c6d1..bdf0432 100644 +--- a/src/northbridge/intel/gm45/gm45.h ++++ b/src/northbridge/intel/gm45/gm45.h +@@ -419,7 +419,7 @@ + int raminit_read_vco_index(void); + u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank); + +-void raminit_rcomp_calibration(stepping_t stepping); ++void raminit_rcomp_calibration(int ddr_type, stepping_t stepping); + void raminit_reset_readwrite_pointers(void); + void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *); + void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume); +diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c +index ecada7b..2b8c44e 100644 +--- a/src/northbridge/intel/gm45/raminit.c ++++ b/src/northbridge/intel/gm45/raminit.c +@@ -1049,7 +1049,7 @@ + } + + /* Perform RCOMP calibration for DDR3. */ +- raminit_rcomp_calibration(stepping); ++ raminit_rcomp_calibration(spd_type, stepping); + + /* Run initial RCOMP. */ + mchbar_setbits32(0x418, 1 << 17); +@@ -1119,7 +1119,7 @@ + reg = (reg & ~(0xf << 10)) | (2 << 10); + else + reg = (reg & ~(0xf << 10)) | (3 << 10); +- reg = (reg & ~(0x7 << 5)) | (3 << 5); ++ reg = (reg & ~(0x7 << 5)) | (2 << 5); + } else if (timings->mem_clock != MEM_CLOCK_1067MT) { + reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); + reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); +@@ -1288,11 +1288,11 @@ + reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32)); + reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32)); + if (timings->mem_clock == MEM_CLOCK_667MT) { +- reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32)); +- reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32)); ++ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32)); ++ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32)); + } else { +- reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32)); +- reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32)); ++ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32)); ++ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32)); + } + mchbar_write32(CxODT_HIGH(ch), reg); + +@@ -2217,6 +2217,84 @@ + raminit_write_training(timings->mem_clock, dimms, s3resume); + } + ++ /* ++ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done ++ * after receiver enable calibration, otherwise raminit sometimes ++ * completes with non-working memory. ++ */ ++ mchbar_write32(0x0530, 0x06060005); ++ mchbar_write32(0x0680, 0x06060606); ++ mchbar_write32(0x0684, 0x08070606); ++ mchbar_write32(0x0688, 0x0e0e0c0a); ++ mchbar_write32(0x068c, 0x0e0e0e0e); ++ mchbar_write32(0x0698, 0x06060606); ++ mchbar_write32(0x069c, 0x08070606); ++ mchbar_write32(0x06a0, 0x0c0c0b0a); ++ mchbar_write32(0x06a4, 0x0c0c0c0c); ++ ++ mchbar_write32(0x06c0, 0x02020202); ++ mchbar_write32(0x06c4, 0x03020202); ++ mchbar_write32(0x06c8, 0x04040403); ++ mchbar_write32(0x06cc, 0x04040404); ++ mchbar_write32(0x06d8, 0x02020202); ++ mchbar_write32(0x06dc, 0x03020202); ++ mchbar_write32(0x06e0, 0x04040403); ++ mchbar_write32(0x06e4, 0x04040404); ++ ++ mchbar_write32(0x0700, 0x02020202); ++ mchbar_write32(0x0704, 0x03020202); ++ mchbar_write32(0x0708, 0x04040403); ++ mchbar_write32(0x070c, 0x04040404); ++ mchbar_write32(0x0718, 0x02020202); ++ mchbar_write32(0x071c, 0x03020202); ++ mchbar_write32(0x0720, 0x04040403); ++ mchbar_write32(0x0724, 0x04040404); ++ ++ mchbar_write32(0x0740, 0x02020202); ++ mchbar_write32(0x0744, 0x03020202); ++ mchbar_write32(0x0748, 0x04040403); ++ mchbar_write32(0x074c, 0x04040404); ++ mchbar_write32(0x0758, 0x02020202); ++ mchbar_write32(0x075c, 0x03020202); ++ mchbar_write32(0x0760, 0x04040403); ++ mchbar_write32(0x0764, 0x04040404); ++ ++ mchbar_write32(0x0780, 0x06060606); ++ mchbar_write32(0x0784, 0x09070606); ++ mchbar_write32(0x0788, 0x0e0e0c0b); ++ mchbar_write32(0x078c, 0x0e0e0e0e); ++ mchbar_write32(0x0798, 0x06060606); ++ mchbar_write32(0x079c, 0x09070606); ++ mchbar_write32(0x07a0, 0x0d0d0c0b); ++ mchbar_write32(0x07a4, 0x0d0d0d0d); ++ ++ mchbar_write32(0x07c0, 0x06060606); ++ mchbar_write32(0x07c4, 0x09070606); ++ mchbar_write32(0x07c8, 0x0e0e0c0b); ++ mchbar_write32(0x07cc, 0x0e0e0e0e); ++ mchbar_write32(0x07d8, 0x06060606); ++ mchbar_write32(0x07dc, 0x09070606); ++ mchbar_write32(0x07e0, 0x0d0d0c0b); ++ mchbar_write32(0x07e4, 0x0d0d0d0d); ++ ++ mchbar_write32(0x0840, 0x06060606); ++ mchbar_write32(0x0844, 0x08070606); ++ mchbar_write32(0x0848, 0x0e0e0c0a); ++ mchbar_write32(0x084c, 0x0e0e0e0e); ++ mchbar_write32(0x0858, 0x06060606); ++ mchbar_write32(0x085c, 0x08070606); ++ mchbar_write32(0x0860, 0x0c0c0b0a); ++ mchbar_write32(0x0864, 0x0c0c0c0c); ++ ++ mchbar_write32(0x0880, 0x02020202); ++ mchbar_write32(0x0884, 0x03020202); ++ mchbar_write32(0x0888, 0x04040403); ++ mchbar_write32(0x088c, 0x04040404); ++ mchbar_write32(0x0898, 0x02020202); ++ mchbar_write32(0x089c, 0x03020202); ++ mchbar_write32(0x08a0, 0x04040403); ++ mchbar_write32(0x08a4, 0x04040404); ++ + igd_compute_ggc(sysinfo); + + /* Program final memory map (with real values). */ +diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +index aef863f..b74765f 100644 +--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c ++++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +@@ -161,11 +161,13 @@ + mchbar += 4; + } + } +-void raminit_rcomp_calibration(const stepping_t stepping) { ++void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) { + const int a1step = stepping >= STEPPING_CONVERSION_A1; + + int i; + ++ char magic_comp[2] = {0}; ++ + enum { + PULL_UP = 0, + PULL_DOWN = 1, +@@ -196,6 +198,10 @@ + reg = mchbar_read32(0x518); + lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; + lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; ++ if (i == 1) { ++ magic_comp[0] = (reg >> 8) & 0x3f; ++ magic_comp[1] = (reg >> 0) & 0x3f; ++ } + } + /* Cleanup? */ + mchbar_setbits32(0x400, 1 << 3); +@@ -216,13 +222,19 @@ + for (channel = 0; channel < 2; ++channel) { + for (group = 0; group < 6; ++group) { + for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) { +- lookup_and_write( +- a1step, +- lut_idx[channel][group][pu_pd] - 7, +- ddr3_lookup_schedule[group][pu_pd], +- mchbar); ++ if (ddr_type == DDR3) { ++ lookup_and_write( ++ a1step, ++ lut_idx[channel][group][pu_pd] - 7, ++ ddr3_lookup_schedule[group][pu_pd], ++ mchbar); ++ } + mchbar += 0x0018; + } ++ if (ddr_type == DDR2) { ++ mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24); ++ mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0); ++ } + mchbar += 0x0010; + /* Channel B knows only the first two groups. */ + if ((1 == channel) && (1 == group)) +@@ -230,4 +242,7 @@ + } + mchbar += 0x0040; + } ++ ++ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26); ++ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20); + } diff --git a/config/coreboot/default/patches/0028-dell-e6400-crank-up-vram-to-256MB-max.patch b/config/coreboot/default/patches/0028-dell-e6400-crank-up-vram-to-256MB-max.patch new file mode 100644 index 0000000..2c23ab0 --- /dev/null +++ b/config/coreboot/default/patches/0028-dell-e6400-crank-up-vram-to-256MB-max.patch @@ -0,0 +1,23 @@ +From 1116145917035a92cc92a34e6a914a9506d17680 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 1 Nov 2023 16:33:11 +0000 +Subject: [PATCH 1/1] dell/e6400: crank up vram to 256MB (max) + +Signed-off-by: Leah Rowe +--- + src/mainboard/dell/e6400/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default +index eeb6f47364..25dfa38cb5 100644 +--- a/src/mainboard/dell/e6400/cmos.default ++++ b/src/mainboard/dell/e6400/cmos.default +@@ -2,4 +2,4 @@ boot_option=Fallback + debug_level=Debug + power_on_after_fail=Disable + sata_mode=AHCI +-gfx_uma_size=32M ++gfx_uma_size=256M +-- +2.39.2 + diff --git a/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb b/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb index 467eb45..54a11c0 100644 --- a/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -169,6 +169,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -481,7 +482,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/e6400_4mb/config/libgfxinit_txtmode b/config/coreboot/e6400_4mb/config/libgfxinit_txtmode index ab4ac8d..fce2e9d 100644 --- a/config/coreboot/e6400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6400_4mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -167,6 +167,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -477,7 +478,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/e6400_4mb/target.cfg b/config/coreboot/e6400_4mb/target.cfg index 566e4db..f89463d 100644 --- a/config/coreboot/e6400_4mb/target.cfg +++ b/config/coreboot/e6400_4mb/target.cfg @@ -5,4 +5,6 @@ payload_grub="n" payload_grub_withseabios="n" payload_seabios="y" payload_memtest="y" +payload_seabios_withgrub="y" +payload_seabios_grubonly="y" grub_scan_disk="ahci" diff --git a/config/coreboot/g43t-am3/config/libgfxinit_txtmode b/config/coreboot/g43t-am3/config/libgfxinit_txtmode index 68e983d..cefcdfd 100644 --- a/config/coreboot/g43t-am3/config/libgfxinit_txtmode +++ b/config/coreboot/g43t-am3/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -165,6 +165,7 @@ CONFIG_PCIEXP_CLK_PM=y CONFIG_GFX_GMA_PANEL_1_ON_EDP=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -473,7 +474,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/g43t-am3_16mb/config/libgfxinit_txtmode b/config/coreboot/g43t-am3_16mb/config/libgfxinit_txtmode index 3dc407a..a18ae41 100644 --- a/config/coreboot/g43t-am3_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/g43t-am3_16mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -165,6 +165,7 @@ CONFIG_PCIEXP_CLK_PM=y CONFIG_GFX_GMA_PANEL_1_ON_EDP=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -473,7 +474,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode b/config/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode index 62d0ce3..0d80d7f 100644 --- a/config/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode +++ b/config/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -172,6 +172,7 @@ CONFIG_PCIEXP_CLK_PM=y CONFIG_GFX_GMA_PANEL_1_ON_EDP=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -480,7 +481,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/gru_bob/config/libgfxinit_corebootfb b/config/coreboot/gru_bob/config/libgfxinit_corebootfb index 7990fb0..9502be1 100644 --- a/config/coreboot/gru_bob/config/libgfxinit_corebootfb +++ b/config/coreboot/gru_bob/config/libgfxinit_corebootfb @@ -675,6 +675,7 @@ CONFIG_PS2M_EISAID="PNP0F13" CONFIG_TTYS0_BAUD=115200 CONFIG_D3COLD_SUPPORT=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_DRIVER_TPM_SPI_CHIP=0 # CONFIG_TPM_MEASURED_BOOT is not set @@ -864,7 +865,6 @@ CONFIG_ACPI_CUSTOM_MADT=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y CONFIG_RTC=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/gru_kevin/config/libgfxinit_corebootfb b/config/coreboot/gru_kevin/config/libgfxinit_corebootfb index 61835e7..cf36cf3 100644 --- a/config/coreboot/gru_kevin/config/libgfxinit_corebootfb +++ b/config/coreboot/gru_kevin/config/libgfxinit_corebootfb @@ -675,6 +675,7 @@ CONFIG_PS2M_EISAID="PNP0F13" CONFIG_TTYS0_BAUD=115200 CONFIG_D3COLD_SUPPORT=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 # CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_8192=y @@ -861,7 +862,6 @@ CONFIG_ACPI_CUSTOM_MADT=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y CONFIG_RTC=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/macbook11/config/libgfxinit_corebootfb b/config/coreboot/macbook11/config/libgfxinit_corebootfb index e0a1334..efc4f99 100644 --- a/config/coreboot/macbook11/config/libgfxinit_corebootfb +++ b/config/coreboot/macbook11/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -162,6 +162,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -458,7 +459,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/macbook11/config/libgfxinit_txtmode b/config/coreboot/macbook11/config/libgfxinit_txtmode index a84410d..740cac5 100644 --- a/config/coreboot/macbook11/config/libgfxinit_txtmode +++ b/config/coreboot/macbook11/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -162,6 +162,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -456,7 +457,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb b/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb index 3984fbe..6e5b91a 100644 --- a/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb @@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -161,6 +161,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -457,7 +458,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode b/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode index 36b30bb..50f27c8 100644 --- a/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode @@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -161,6 +161,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -455,7 +456,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/macbook21/config/libgfxinit_corebootfb b/config/coreboot/macbook21/config/libgfxinit_corebootfb index a9d168a..dde5c19 100644 --- a/config/coreboot/macbook21/config/libgfxinit_corebootfb +++ b/config/coreboot/macbook21/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -162,6 +162,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -458,7 +459,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/macbook21/config/libgfxinit_txtmode b/config/coreboot/macbook21/config/libgfxinit_txtmode index 68a0e4f..5f99046 100644 --- a/config/coreboot/macbook21/config/libgfxinit_txtmode +++ b/config/coreboot/macbook21/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -162,6 +162,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -456,7 +457,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb b/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb index 3df9fd7..08a21f4 100644 --- a/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb @@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -161,6 +161,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -457,7 +458,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode b/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode index 2e83d09..563271e 100644 --- a/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode @@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -161,6 +161,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -455,7 +456,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/qemu_arm64_12mb/config/libgfxinit_corebootfb b/config/coreboot/qemu_arm64_12mb/config/libgfxinit_corebootfb index 710cd39..45c86d2 100644 --- a/config/coreboot/qemu_arm64_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/qemu_arm64_12mb/config/libgfxinit_corebootfb @@ -143,6 +143,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_16384=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -312,7 +313,6 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_CUSTOM_MADT=y CONFIG_BOOT_DEVICE_NOT_SPI_FLASH=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/qemu_x86_12mb/config/libgfxinit_corebootfb b/config/coreboot/qemu_x86_12mb/config/libgfxinit_corebootfb index b981db3..f0b3113 100644 --- a/config/coreboot/qemu_x86_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/qemu_x86_12mb/config/libgfxinit_corebootfb @@ -162,6 +162,7 @@ CONFIG_PCIEXP_ASPM=y # CONFIG_PCIEXP_CLK_PM is not set CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x8000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -375,7 +376,6 @@ CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_NOT_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/qemu_x86_12mb/config/libgfxinit_txtmode b/config/coreboot/qemu_x86_12mb/config/libgfxinit_txtmode index 16e1436..29ae73a 100644 --- a/config/coreboot/qemu_x86_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/qemu_x86_12mb/config/libgfxinit_txtmode @@ -162,6 +162,7 @@ CONFIG_PCIEXP_ASPM=y # CONFIG_PCIEXP_CLK_PM is not set CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x8000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -371,7 +372,6 @@ CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_NOT_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/r400_16mb/config/libgfxinit_corebootfb b/config/coreboot/r400_16mb/config/libgfxinit_corebootfb index 122b998..8749f30 100644 --- a/config/coreboot/r400_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_16mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -528,7 +529,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/r400_16mb/config/libgfxinit_txtmode b/config/coreboot/r400_16mb/config/libgfxinit_txtmode index c7d7763..abfd383 100644 --- a/config/coreboot/r400_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_16mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -524,7 +525,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb index d014223..c5cff8b 100644 --- a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -528,7 +529,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/r400_4mb/config/libgfxinit_txtmode b/config/coreboot/r400_4mb/config/libgfxinit_txtmode index 3d41ac6..73e6eaf 100644 --- a/config/coreboot/r400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_4mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -524,7 +525,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb index f5bf4a1..06bf07d 100644 --- a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -528,7 +529,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/r400_8mb/config/libgfxinit_txtmode b/config/coreboot/r400_8mb/config/libgfxinit_txtmode index c679504..97b9350 100644 --- a/config/coreboot/r400_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_8mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -524,7 +525,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/r500_4mb/config/libgfxinit_corebootfb b/config/coreboot/r500_4mb/config/libgfxinit_corebootfb index da9b16f..d787f18 100644 --- a/config/coreboot/r500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r500_4mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/r500_4mb/config/libgfxinit_txtmode b/config/coreboot/r500_4mb/config/libgfxinit_txtmode index 6ce4e06..15f8f6d 100644 --- a/config/coreboot/r500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/r500_4mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -203,6 +203,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -521,7 +522,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t400_16mb/config/libgfxinit_corebootfb b/config/coreboot/t400_16mb/config/libgfxinit_corebootfb index fdacdc2..59473ba 100644 --- a/config/coreboot/t400_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_16mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -528,7 +529,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t400_16mb/config/libgfxinit_txtmode b/config/coreboot/t400_16mb/config/libgfxinit_txtmode index 9f2620d..9bacbe5 100644 --- a/config/coreboot/t400_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_16mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -524,7 +525,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t400_4mb/config/libgfxinit_corebootfb b/config/coreboot/t400_4mb/config/libgfxinit_corebootfb index bc9abca..d3ca1b9 100644 --- a/config/coreboot/t400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_4mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -528,7 +529,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t400_4mb/config/libgfxinit_txtmode b/config/coreboot/t400_4mb/config/libgfxinit_txtmode index 9f8a4ab..4debefe 100644 --- a/config/coreboot/t400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_4mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -524,7 +525,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t400_8mb/config/libgfxinit_corebootfb b/config/coreboot/t400_8mb/config/libgfxinit_corebootfb index c35f835..a61b136 100644 --- a/config/coreboot/t400_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_8mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -528,7 +529,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t400_8mb/config/libgfxinit_txtmode b/config/coreboot/t400_8mb/config/libgfxinit_txtmode index bf7b628..2711c92 100644 --- a/config/coreboot/t400_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_8mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -524,7 +525,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t500_16mb/config/libgfxinit_corebootfb b/config/coreboot/t500_16mb/config/libgfxinit_corebootfb index 5cacf0f..cef041a 100644 --- a/config/coreboot/t500_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_16mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -528,7 +529,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t500_16mb/config/libgfxinit_txtmode b/config/coreboot/t500_16mb/config/libgfxinit_txtmode index 42ef5f5..3b36e51 100644 --- a/config/coreboot/t500_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_16mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -524,7 +525,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t500_4mb/config/libgfxinit_corebootfb b/config/coreboot/t500_4mb/config/libgfxinit_corebootfb index 2b59d66..a278c18 100644 --- a/config/coreboot/t500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_4mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -528,7 +529,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t500_4mb/config/libgfxinit_txtmode b/config/coreboot/t500_4mb/config/libgfxinit_txtmode index 98a39f0..2021d6c 100644 --- a/config/coreboot/t500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_4mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -524,7 +525,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t500_8mb/config/libgfxinit_corebootfb b/config/coreboot/t500_8mb/config/libgfxinit_corebootfb index bb590dd..911facc 100644 --- a/config/coreboot/t500_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_8mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -528,7 +529,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t500_8mb/config/libgfxinit_txtmode b/config/coreboot/t500_8mb/config/libgfxinit_txtmode index 94d1c4b..000e8ca 100644 --- a/config/coreboot/t500_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_8mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -524,7 +525,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb index a43706c..f530878 100644 --- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb +++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -198,6 +198,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -504,7 +505,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode index 3f2f4dc..bd16b2f 100644 --- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode +++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -198,6 +198,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -502,7 +503,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb b/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb index edc5427..40cbcf9 100644 --- a/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb +++ b/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -198,6 +198,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -504,7 +505,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode b/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode index 6b81acc..a7a17b7 100644 --- a/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode +++ b/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -198,6 +198,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -502,7 +503,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/w500_16mb/config/libgfxinit_corebootfb b/config/coreboot/w500_16mb/config/libgfxinit_corebootfb index 5d193e2..64a1eb1 100644 --- a/config/coreboot/w500_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_16mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -528,7 +529,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/w500_16mb/config/libgfxinit_txtmode b/config/coreboot/w500_16mb/config/libgfxinit_txtmode index 911e82e..dd86513 100644 --- a/config/coreboot/w500_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_16mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -524,7 +525,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/w500_4mb/config/libgfxinit_corebootfb b/config/coreboot/w500_4mb/config/libgfxinit_corebootfb index eb2600f..6adfb7b 100644 --- a/config/coreboot/w500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_4mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -528,7 +529,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/w500_4mb/config/libgfxinit_txtmode b/config/coreboot/w500_4mb/config/libgfxinit_txtmode index 82bc4b1..f965c75 100644 --- a/config/coreboot/w500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_4mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -524,7 +525,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/w500_8mb/config/libgfxinit_corebootfb b/config/coreboot/w500_8mb/config/libgfxinit_corebootfb index 85248a6..a4ec6ad 100644 --- a/config/coreboot/w500_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_8mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -528,7 +529,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/w500_8mb/config/libgfxinit_txtmode b/config/coreboot/w500_8mb/config/libgfxinit_txtmode index 513e6fa..1a1f277 100644 --- a/config/coreboot/w500_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_8mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -524,7 +525,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x200_16mb/config/libgfxinit_corebootfb b/config/coreboot/x200_16mb/config/libgfxinit_corebootfb index 5a39c85..c344f2a 100644 --- a/config/coreboot/x200_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_16mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x200_16mb/config/libgfxinit_txtmode b/config/coreboot/x200_16mb/config/libgfxinit_txtmode index 363cda1..a61c718 100644 --- a/config/coreboot/x200_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_16mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x200_4mb/config/libgfxinit_corebootfb b/config/coreboot/x200_4mb/config/libgfxinit_corebootfb index f258f74..f4c4888 100644 --- a/config/coreboot/x200_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_4mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x200_4mb/config/libgfxinit_txtmode b/config/coreboot/x200_4mb/config/libgfxinit_txtmode index 18957cb..48b0739 100644 --- a/config/coreboot/x200_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_4mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x200_8mb/config/libgfxinit_corebootfb b/config/coreboot/x200_8mb/config/libgfxinit_corebootfb index 7e56175..92a3915 100644 --- a/config/coreboot/x200_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_8mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x200_8mb/config/libgfxinit_txtmode b/config/coreboot/x200_8mb/config/libgfxinit_txtmode index 48064ea..6c8538c 100644 --- a/config/coreboot/x200_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_8mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x301_16mb/config/libgfxinit_corebootfb b/config/coreboot/x301_16mb/config/libgfxinit_corebootfb index 1aa96bc..07f46e6 100644 --- a/config/coreboot/x301_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x301_16mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x301_16mb/config/libgfxinit_txtmode b/config/coreboot/x301_16mb/config/libgfxinit_txtmode index 80d4bd9..5da2129 100644 --- a/config/coreboot/x301_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x301_16mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x301_4mb/config/libgfxinit_corebootfb b/config/coreboot/x301_4mb/config/libgfxinit_corebootfb index 0de8133..2941895 100644 --- a/config/coreboot/x301_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x301_4mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x301_4mb/config/libgfxinit_txtmode b/config/coreboot/x301_4mb/config/libgfxinit_txtmode index 315d90b..549ca9e 100644 --- a/config/coreboot/x301_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/x301_4mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x301_8mb/config/libgfxinit_corebootfb b/config/coreboot/x301_8mb/config/libgfxinit_corebootfb index 4305387..e88abf3 100644 --- a/config/coreboot/x301_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x301_8mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x301_8mb/config/libgfxinit_txtmode b/config/coreboot/x301_8mb/config/libgfxinit_txtmode index ac7f1d2..b78a36f 100644 --- a/config/coreboot/x301_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/x301_8mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x60/config/libgfxinit_corebootfb b/config/coreboot/x60/config/libgfxinit_corebootfb index 6128450..32354fe 100644 --- a/config/coreboot/x60/config/libgfxinit_corebootfb +++ b/config/coreboot/x60/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -199,6 +199,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -510,7 +511,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x60/config/libgfxinit_txtmode b/config/coreboot/x60/config/libgfxinit_txtmode index c0636e6..044fa0a 100644 --- a/config/coreboot/x60/config/libgfxinit_txtmode +++ b/config/coreboot/x60/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -199,6 +199,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -508,7 +509,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x60_16mb/config/libgfxinit_corebootfb b/config/coreboot/x60_16mb/config/libgfxinit_corebootfb index e964a23..1916287 100644 --- a/config/coreboot/x60_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x60_16mb/config/libgfxinit_corebootfb @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -199,6 +199,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -510,7 +511,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/coreboot/x60_16mb/config/libgfxinit_txtmode b/config/coreboot/x60_16mb/config/libgfxinit_txtmode index 9206be1..c49cee0 100644 --- a/config/coreboot/x60_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x60_16mb/config/libgfxinit_txtmode @@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y # CONFIG_UBSAN is not set CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set @@ -199,6 +199,7 @@ CONFIG_D3COLD_SUPPORT=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -508,7 +509,6 @@ CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console diff --git a/config/git/www b/config/git/www index 1afe644..36f30e1 100644 --- a/config/git/www +++ b/config/git/www @@ -1,5 +1,5 @@ {www}{ - rev: deaec646fed873056707d3661655268a3c5aa78d + rev: 4c776bbea725e44c5683d90e2bd1c838ff816852 loc: www url: https://codeberg.org/canoeboot/cbwww bkup_url: https://git.disroot.org/canoeboot/cbwww diff --git a/config/grub/config/grub.cfg b/config/grub/config/grub.cfg index fdf5d5f..8a12406 100644 --- a/config/grub/config/grub.cfg +++ b/config/grub/config/grub.cfg @@ -169,13 +169,16 @@ menuentry 'Load Operating System (incl. fully encrypted disks) [o]' --hotkey='o true # Prevent pager requiring to accept each line instead of whole screen } -menuentry 'Search ISOLINUX menu (AHCI) [a]' --hotkey='a' { - search_isolinux ahci +menuentry 'Find and load GRUB config from USB drive [s]' --hotkey='s' { + search_grub usb } -menuentry 'Search ISOLINUX menu (USB) [u]' --hotkey='u' { +menuentry 'Find and load ISOLINUX/EXTLINUX from USB drive [u]' --hotkey='u' { search_isolinux usb } -menuentry 'Search ISOLINUX menu (ATA/IDE) [d]' --hotkey='d' { +menuentry 'Find and load ISOLINUX/EXTLINUX menu via AHCI [a]' --hotkey='a' { + search_isolinux ahci +} +menuentry 'Find and load ISOLINUX/EXTLINUX menu via ATA/IDE [d]' --hotkey='d' { search_isolinux ata } if [ -f (cbfsdisk)/grubtest.cfg ]; then @@ -186,9 +189,6 @@ menuentry 'Load test configuration (grubtest.cfg) inside of CBFS [t]' --hotkey= fi } fi -menuentry 'Search for GRUB2 configuration on external media [s]' --hotkey='s' { - search_grub usb -} if [ -f (cbfsdisk)/seabios.elf ]; then menuentry 'Load SeaBIOS (payload) [b]' --hotkey='b' { set root='cbfsdisk' diff --git a/config/grub/patches/0001-borderfix/0002-say-the-name-libreboot-in-the-grub-menu.patch b/config/grub/patches/0001-borderfix/0002-say-the-name-libreboot-in-the-grub-menu.patch index 44b4cd6..31db212 100644 --- a/config/grub/patches/0001-borderfix/0002-say-the-name-libreboot-in-the-grub-menu.patch +++ b/config/grub/patches/0001-borderfix/0002-say-the-name-libreboot-in-the-grub-menu.patch @@ -16,7 +16,7 @@ index bd4431000..31308e16a 100644 grub_term_cls (term); - msg_formatted = grub_xasprintf (_("GNU GRUB version %s"), PACKAGE_VERSION); -+ msg_formatted = grub_xasprintf (_("Canoeboot 20231026 release, based on Libreboot 20231021. https://canoeboot.org/")); ++ msg_formatted = grub_xasprintf (_("Canoeboot 20231101 release, based on Libreboot 20231101. https://canoeboot.org/")); if (!msg_formatted) return; diff --git a/config/grub/patches/0003-keyboardfix/0001-at_keyboard-coreboot-force-scancodes2-translate.patch b/config/grub/patches/0003-keyboardfix/0001-at_keyboard-coreboot-force-scancodes2-translate.patch new file mode 100644 index 0000000..21e8630 --- /dev/null +++ b/config/grub/patches/0003-keyboardfix/0001-at_keyboard-coreboot-force-scancodes2-translate.patch @@ -0,0 +1,107 @@ +From 96c0bbe5d406b616360a7fce7cee67d7692c0d6d Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 30 Oct 2023 22:19:21 +0000 +Subject: [PATCH 1/1] at_keyboard coreboot: force scancodes2+translate + +Scan code set 2 with translation should be assumed in +every case, as the default starting position. + +However, GRUB is trying to detect and use other modes +such as set 2 without translation, or set 1 without +translation from set 2; it also detects no-mode and +assumes mode 1, on really old keyboards. + +The current behaviour has been retained, for everything +except GRUB_MACHINE_COREBOOT; for the latter, scan code +set 2 with translation is hardcoded, and forced in code. + +This is required to make keyboard initialisation work on +the MEC5035 EC used by the Dell Latitude E6400, when +running GRUB as a coreboot payload on that laptop. The +EC reports scancode set 2 with translation when probed, +but actually only outputs scancode set 1. + +Since GRUB is attempting to use it without translation, +and since the machine reports set 2 with translation, +but only ever outputs set 1 scancodes, this results in +wrong keypresses for every key. + +This fix fixed that, by forcing set 2 with translation, +treating it as set 1, but only on coreboot. This is the +same behaviour used in GNU+Linux systems and SeaBIOS. +With this change, GRUB keyboard initialisation now works +just fine on those machines. + +This has *also* been tested on other coreboot machines +running GRUB; several HP EliteBooks, ThinkPads and +Dell Precision T1650. All seems to work just fine. + +Signed-off-by: Leah Rowe +--- + grub-core/term/at_keyboard.c | 20 ++++++++++++++++++-- + 1 file changed, 18 insertions(+), 2 deletions(-) + +diff --git a/grub-core/term/at_keyboard.c b/grub-core/term/at_keyboard.c +index f8a129eb7..8207225c2 100644 +--- a/grub-core/term/at_keyboard.c ++++ b/grub-core/term/at_keyboard.c +@@ -138,6 +138,7 @@ write_mode (int mode) + return (i != GRUB_AT_TRIES); + } + ++#if !defined (GRUB_MACHINE_COREBOOT) + static int + query_mode (void) + { +@@ -161,10 +162,12 @@ query_mode (void) + return 3; + return 0; + } ++#endif + + static void + set_scancodes (void) + { ++#if !defined (GRUB_MACHINE_COREBOOT) + /* You must have visited computer museum. Keyboard without scancode set + knowledge. Assume XT. */ + if (!grub_keyboard_orig_set) +@@ -173,20 +176,33 @@ set_scancodes (void) + ps2_state.current_set = 1; + return; + } ++#endif + + #if !USE_SCANCODE_SET + ps2_state.current_set = 1; + return; +-#else ++#endif + ++#if defined (GRUB_MACHINE_COREBOOT) ++ /* enable translation */ ++ grub_keyboard_controller_write (grub_keyboard_controller_orig ++ & ~KEYBOARD_AT_DISABLE); ++#else ++ /* if not coreboot, disable translation and try mode 2 first, before 1 */ + grub_keyboard_controller_write (grub_keyboard_controller_orig + & ~KEYBOARD_AT_TRANSLATE + & ~KEYBOARD_AT_DISABLE); ++#endif + + keyboard_controller_wait_until_ready (); + grub_outb (KEYBOARD_COMMAND_ENABLE, KEYBOARD_REG_DATA); +- + write_mode (2); ++ ++#if defined (GRUB_MACHINE_COREBOOT) ++ /* mode 2 with translation, so make grub treat as set 1 */ ++ ps2_state.current_set = 1; ++#else ++ /* if not coreboot, translation isn't set; test 2 and fall back to 1 */ + ps2_state.current_set = query_mode (); + grub_dprintf ("atkeyb", "returned set %d\n", ps2_state.current_set); + if (ps2_state.current_set == 2) +-- +2.39.2 + diff --git a/config/grub/patches/0003-keyboardfix/0002-keylayouts-don-t-print-Unknown-key-message.patch b/config/grub/patches/0003-keyboardfix/0002-keylayouts-don-t-print-Unknown-key-message.patch new file mode 100644 index 0000000..fbef86a --- /dev/null +++ b/config/grub/patches/0003-keyboardfix/0002-keylayouts-don-t-print-Unknown-key-message.patch @@ -0,0 +1,38 @@ +From 0a6abeb40ac4284fbff6ef5958989d561b6290a7 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Tue, 31 Oct 2023 10:33:28 +0000 +Subject: [PATCH 1/1] keylayouts: don't print "Unknown key" message + +on keyboards with stuck keys, this results in GRUB just +spewing it repeatedly, preventing use of GRUB. + +in such cases, it's still possible to use the keyboard, +and we should let the user at least boot. + +it often appears when people plug in faulty usb keyboards, +but can appear for laptop keyboards too; one of my e6400 +has stuck keys. + +with this patch, grub should be a bit more reliable in +terms of user experience, when the keyboard is faulty. + +Signed-off-by: Leah Rowe +--- + grub-core/commands/keylayouts.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/grub-core/commands/keylayouts.c b/grub-core/commands/keylayouts.c +index aa3ba34f2..445fa0601 100644 +--- a/grub-core/commands/keylayouts.c ++++ b/grub-core/commands/keylayouts.c +@@ -174,7 +174,6 @@ grub_term_map_key (grub_keyboard_key_t code, int status) + key = map_key_core (code, status, &alt_gr_consumed); + + if (key == 0 || key == GRUB_TERM_SHIFT) { +- grub_printf ("Unknown key 0x%x detected\n", code); + return GRUB_TERM_NO_KEY; + } + +-- +2.39.2 + diff --git a/include/git.sh b/include/git.sh index 925d3be..b932d55 100755 --- a/include/git.sh +++ b/include/git.sh @@ -132,7 +132,9 @@ git_am_patches() for patch in "${patchdir}/"*; do [ -L "${patch}" ] && continue [ -f "${patch}" ] || continue - if ! git am "${patch}"; then + patchfail="n" + git am "${patch}" || patchfail="y" + if [ "${patchfail}" = "y" ]; then git am --abort || err "${sdir}: !git am --abort" err "!git am ${patch} -> ${sdir}" fi diff --git a/script/build/roms b/script/build/roms index e6d06e4..266d2bd 100755 --- a/script/build/roms +++ b/script/build/roms @@ -21,7 +21,7 @@ kmapdir="config/grub/keymap" # Disable all payloads by default. # target.cfg files have to specifically enable [a] payload(s) pv="payload_grub payload_grub_withseabios payload_seabios payload_memtest" -pv="${pv} payload_seabios_withgrub payload_uboot memtest_bin" +pv="${pv} payload_seabios_withgrub payload_seabios_grubonly payload_uboot memtest_bin" v="romdir cbrom initmode displaymode cbcfg targetdir tree arch" v="${v} grub_timeout ubdir board grub_scan_disk uboot_config" eval "$(setvars "n" ${pv})" @@ -93,6 +93,10 @@ check_target() eval "$(setvars "y" payload_seabios payload_seabios_withgrub)" [ "${payload_seabios_withgrub}" = "y" ] && \ payload_seabios="y" + if [ "${payload_seabios_grubonly}" = "y" ]; then + payload_seabios="y" + payload_seabios_withgrub="y" + fi # The reverse logic must not be applied. If SeaBIOS-with-GRUB works, # that doesn't mean GRUB-withSeaBIOS will. For example, the board @@ -113,7 +117,8 @@ check_target() [ -z "${_payload}" ] && return 0 printf "setting payload to: %s\n" "${_payload}" eval "$(setvars "n" payload_grub payload_memtest payload_seabios \ - payload_seabios_withgrub payload_uboot payload_grub_withseabios)" + payload_seabios_withgrub payload_uboot payload_grub_withseabios \ + payload_seabios_grubonly)" eval "payload_${_payload}=y" } @@ -155,7 +160,8 @@ build_dependency_seabios() build_dependency_grub() { [ "${payload_grub}" != "y" ] && \ - [ "${payload_seabios_withgrub}" != "y" ] && return 0 + [ "${payload_seabios_withgrub}" != "y" ] && \ + [ "${payload_seabios_grubonly}" != "y" ] && return 0 rebuild_grub="n" [ -f "${grubelf}" ] || rebuild_grub="y" @@ -306,6 +312,8 @@ build_grub_roms() newrom="${romdir}/${payload1}_${board}_" && \ newrom="${newrom}${initmode}_${keymap}.rom" x_ moverom "${tmpgrubrom}" "${newrom}" + [ "${payload_seabios_grubonly}" = "y" ] && \ + mkSeabiosGrubonlyRom "${tmpgrubrom}" "${newrom}" x_ rm -f "${tmpgrubrom}" done } @@ -347,6 +355,25 @@ mkSeabiosRom() { printf "%s\n" "${tmprom}" } +# SeaGRUB configuration +mkSeabiosGrubonlyRom() +{ + _grubrom="${1}" + _newrom="${2}" + + tmpbootorder=$(mktemp -t coreboot_rom.XXXXXXXXXX) + + # only load grub, by inserting a custom bootorder file + printf "/rom@img/grub2\n" > "${tmpbootorder}" || err "printf bootorder" + x_ "${cbfstool}" "${_grubrom}" \ + add -f "${tmpbootorder}" -n bootorder -t raw + x_ rm -f "${tmpbootorder}" + + x_ "${cbfstool}" "${_grubrom}" add-int -i 0 -n etc/show-boot-menu + + x_ moverom "${_grubrom}" "${_newrom%.rom}_grubonly.rom" +} + build_uboot_roms() { tmprom="$(mkUbootRom "${cbrom}" "fallback/payload")" diff --git a/script/update/release b/script/update/release index 2a72dbb..fb5d49c 100755 --- a/script/update/release +++ b/script/update/release @@ -201,7 +201,7 @@ mktarball() [ "${2%/*}" = "${2}" ] || mkdir -p "${2%/*}" || err "mk, !mkdir -p \"${2%/*}\"" if [ "${tar_implementation% *}" = "tar (GNU tar)" ]; then tar --sort=name --owner=root:0 --group=root:0 \ - --mtime="UTC 2023-10-21" -c "${1}" | xz -T0 -9e > "${2}" || \ + --mtime="UTC 2023-11-01" -c "${1}" | xz -T0 -9e > "${2}" || \ err "mktarball 1, ${1}" else # TODO: reproducible tarballs on non-GNU systems