commit 6a52fb9f579a9117219e9f96bd9bba9d138a838c Author: Leah Rowe Date: Mon Jul 10 16:43:08 2023 +0100 Censored Libreboot 20230710 website Signed-off-by: Leah Rowe diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..7454e90 --- /dev/null +++ b/.gitignore @@ -0,0 +1,8 @@ +*.html +/site/news/index* +/site/sitemap.md +/site/push +*feed.xml +*.sha1sum +*.hash +*.date diff --git a/site.cfg b/site.cfg new file mode 100644 index 0000000..e72b674 --- /dev/null +++ b/site.cfg @@ -0,0 +1,5 @@ +TITLE="-T Censored-libreboot" +DOMAIN="https://censored.libreboot.org/" +BLOGDIR="news/" # leave as empty string if you want the blog to be the homepage +CSS="--css /global.css" +LAZY="y" diff --git a/site/COPYING b/site/COPYING new file mode 100644 index 0000000..bf128be --- /dev/null +++ b/site/COPYING @@ -0,0 +1,451 @@ + + GNU Free Documentation License + Version 1.3, 3 November 2008 + + + Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. + + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + +0. PREAMBLE + +The purpose of this License is to make a manual, textbook, or other +functional and useful document "free" in the sense of freedom: to +assure everyone the effective freedom to copy and redistribute it, +with or without modifying it, either commercially or noncommercially. +Secondarily, this License preserves for the author and publisher a way +to get credit for their work, while not being considered responsible +for modifications made by others. + +This License is a kind of "copyleft", which means that derivative +works of the document must themselves be free in the same sense. It +complements the GNU General Public License, which is a copyleft +license designed for free software. + +We have designed this License in order to use it for manuals for free +software, because free software needs free documentation: a free +program should come with manuals providing the same freedoms that the +software does. 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In +order to do this, many pages, and sources of information, were removed or +heavily re-worded (censored) in this version, compared to regular Libreboot. The +censored information/code would have never been permitted, under Libreboot's +previous [Binary Blob Extermination Policy](https://web.archive.org/web/20221107235850/https://libreboot.org/news/policy.html) + +Support for many mainboards has been removed, in this censored version. The +website that you're reading +is based on the regular Libreboot website at the time of the +[Libreboot 20230625 release](https://libreboot.org/news/libreboot20230625.html). + +Changes made in *Censored Libreboot* +==================================== + +Almost all of the website changes can be seen here, in this diff: + + +The changes are so vast (about 8000 lines of text removed), that not all of them +show by default in the above link, but you can click "Show More" at the bottom +of that page. Codeberg is Libreboot's hosting provider for Git repositories, and +the website is hosted in Git. + +For a list of code changes, you can refer to the [Censored Libreboot c20230710 +release announcement](https://libreboot.org/news/censored-libreboot20230710.html) + +The above link, and this page, demonstrate the *damage* that could be done to +Libreboot, in the name of cult-like ideological purity. Libreboot's policy is +simply to help as many people as possible install coreboot, with as few (or no) +binary blobs as possible. + +Deleted web pages, in *Censored Libreboot*: +------------------------------------------- + +All of these pages, which exist in the regular Libreboot website, +do not exist in the *censored* Libreboot website: + +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* + +Heavily modified pages (not deleted) +------------------------------------ + +These pages have been modified heavily (a few of these aren't pages, but are +instead files like pandoc templates, used by Libreboot's static site +generator, namely the [Untitled Static Site Generator](https://untitled.vimuser.org)): + +* [/contrib.md](/contrib.html) (censored version), versus original: +* [/contrib.uk.md](/contrib.uk.html) (censored version), versus original: +* [/docs/bsd/index.md](/docs/bsd/index.html) (censored version), versus original: +* [/docs/build/index.md](/docs/build/index.html) (censored version), versus original: +* [/docs/build/index.uk.md](/docs/build/index.uk.html) (censored version), versus original: +* [/docs/hardware/e6400.md](/docs/hardware/e6400.html) (censored version), versus original: +* [/docs/hardware/ga-g41m-es2l.md](/docs/hardware/ga-g41m-es2l.html) (censored version), versus original: +* [/docs/hardware/index.md](/docs/hardware/index.html) (censored version), versus original: +* [/docs/hardware/kgpe-d16.md](/docs/hardware/kgpe-d16.html) (censored version), versus original: +* [/docs/hardware/mac\_address.md](/docs/hardware/mac_address.html) (censored version), versus original: +* [/docs/install/chromebooks.md](/docs/install/chromebooks.html) (censored version), versus original: +* [/docs/install/e6400.md](/docs/install/e6400.html) (censored version), versus original: +* [/docs/install/index.md](/docs/install/index.html) (censored version), versus original: +* [/docs/install/kgpe-d16.md](/docs/install/kgpe-d16.html) (censored version), versus original: +* [/docs/install/nvmutil.md](/docs/install/nvmutil.html) (censored version), versus original: +* [/docs/install/spi.md](/docs/install/spi.html) (censored version), versus original: +* [/docs/install/spi\_generic.md](/docs/install/spi_generic.html) (censored version), versus original: +* [/docs/linux/index.md](/docs/linux/index.html) (censored version), versus original: +* [/docs/maintain/index.md](/docs/maintain/index.html) (censored version), versus original: +* [/docs/maintain/testing.md](/docs/maintain/testing.html) (censored version), versus original: +* [/docs/uboot/index.md](/docs/uboot/index.html) (censored version), versus original: +* [/docs/uboot/uboot-archlinux.md](/docs/uboot/uboot-archlinux.html) (censored version), versus original: +* [/download.md](/download.html) (censored version), versus original: +* [/download.uk.md](/download.uk.html) (censored version), versus original: +* [/faq.md](/faq.html) (censored version), versus original: +* [/faq.uk.md](/faq.uk.html) (censored version), versus original: +* [/footer.de.include](/footer.de.include) (censored version), versus original: +* [/footer.include](/footer.include) (censored version), versus original: +* [/footer.uk.include](/footer.uk.include) (censored version), versus original: +* [/footer.zh-cn.include](/footer.zh-cn.include) (censored version), versus original: +* [/index.de.md](/index.de.html) (censored version), versus original: +* [/index.fr.md](/index.fr.html) (censored version), versus original: +* [/index.md](/index.html) (censored version), versus original: +* [/index.uk.md](/index.uk.html) (censored version), versus original: +* [/index.zh-cn.md](/index.zh-cn.html) (censored version), versus original: +* [/news/MANIFEST](/news/MANIFEST) (censored version), versus original: +* [/news/audit.md](/news/audit.html) (censored version), versus original: +* [/news/e6400.md](/news/e6400.html) (censored version), versus original: +* [/news/e6400.uk.md](/news/e6400.uk.html) (censored version), versus original: +* [/news/usa-libre-part2.md](/news/usa-libre-part2.html) (censored version), versus original: +* [/template.de.include](/template.de.include) (censored version), versus original: +* [/template.include](/template.include) (censored version), versus original: +* [/template.uk.include](/template.uk.include) (censored version), versus original: +* [/template.zh-cn.include](/template.zh-cn.include) (censored version), versus original: + diff --git a/site/contact.de.md b/site/contact.de.md new file mode 100644 index 0000000..255f39a --- /dev/null +++ b/site/contact.de.md @@ -0,0 +1,72 @@ +--- +title: Kontakt +x-toc-enable: true +... + +**TODO: mailing lists, mastodon server and peertube account.** + +User support +============ + +IRC oder Reddit werden bevorzugt, sofern Du eine Support Anfrage hast (IRC empfohlen). +Für Informationen bzgl. IRC and Reddit siehe unten. + +Entwicklungs Diskussion +====================== + +Eine Mailing Liste ist für die Zukunft in Planung. Bis dahin, siehe unter +[der Git Seite](git.md) für Informationen wie Du dich an der Entwicklung beteiligen kannst. + +Hier finden sich ebenso Anleitungen zum Senden von Patches (via Pull-Requests). + +IRC Chatraum +============ + +IRC ist hauptsächlich der Weg um Kontakt Libreboot Projekt aufzunehmen. `#libreboot` auf Libera +IRC. + +Webchat: + + +Libera ist eines der grössten IRC Netzwerke, welches für Libre Software Projekte verwendet wird. +Mehr Infos gibt es hier: + +Wenn Du dich mit deinem bevorzugten IRC Klienten verbinden möchtest (z.B. weechat or irssi), +anbei die Verbindungsdetails: + +* Server: `irc.libera.chat` +* Channel: `#libreboot` +* Port (TLS): `6697` +* Port (non-TLS): `6667` + +Wir empfehlen, dass Du Port `6697` mit aktivierter TLS Verschlüsselung verwendest. + +Es wird empfohlen SASL für die Authentifizierung zu verwenden. Diese Seiten auf der Libera +Website erläutern wie dies funktioniert: + +* WeeChat SASL Anleitung: +* Irssi SASL Anleitung: +* HexChat SASL Anleitung: + +Grundsätzlich solltest Du die Dokumentation der von Dir verwendeten IRC Software konsultieren. + +Soziale Medien +============ + +Libreboot existiert offiziell an vielen Orten. + +Mastodon +-------- + +Gründerin und Haupt-Entwicklerin, Leah Rowe, ist auf Mastodon: + +* + +Leah kann zudem unter dieser eMail kontaktiert werden: +[leah@libreboot.org](mailto:leah@libreboot.org) + +Reddit +------ + +Hauptsächlich verwendet als Support Kanal und für Veröffentlichung von Neuigkeiten: + diff --git a/site/contact.md b/site/contact.md new file mode 100644 index 0000000..54c40d1 --- /dev/null +++ b/site/contact.md @@ -0,0 +1,72 @@ +--- +title: Contact +x-toc-enable: true +... + +**TODO: mailing lists, mastodon server and peertube account.** + +User support +============ + +IRC or Reddit are recommended, if you wish to ask for support (IRC recommended). +See below for information about IRC and Reddit. + +Development discussion +====================== + +Mailing lists are planned for the future. For now, see notes +on [the Git page](git.md) for information about how to assist with development. + +Instructions are also on that page for sending patches (via pull requests). + +IRC chatroom +============ + +IRC is the main way to contact the libreboot project. `#libreboot` on Libera +IRC. + +Webchat: + + +Libera is one of the largest IRC networks, used for Libre Software projects. +Find more about them here: + +If you wish to connect using your preferred client (such as weechat or irssi), +the connection info is as follows: + +* Server: `irc.libera.chat` +* Channel: `#libreboot` +* Port (TLS): `6697` +* Port (non-TLS): `6667` + +We recommend that you use port `6697` with TLS encryption enabled. + +It is recommend that you use SASL for authentication. These pages on the Libera +website tells you how: + +* WeeChat SASL guide: +* Irssi SASL guide: +* HexChat SASL guide: + +In general, you should check the documentation provided by your IRC software. + +Social media +============ + +libreboot exists officially on many places. + +Mastodon +-------- + +The founder and lead developer, Leah Rowe, is on Mastodon: + +* + +Leah can also be contacted by this email address: +[leah@libreboot.org](mailto:leah@libreboot.org) + +Reddit +------ + +Mostly used as a support channel, and also for news announcements: + diff --git a/site/contact.uk.md b/site/contact.uk.md new file mode 100644 index 0000000..b300d45 --- /dev/null +++ b/site/contact.uk.md @@ -0,0 +1,72 @@ +--- +title: Зв'язок +x-toc-enable: true +... + +**TODO: списки розсилки, сервер mastodon та обліковий запис peertube.** + +Підтримка користувачів +============ + +IRC або Reddit рекомендовані, якщо ви бажаєте попросити про допомогу (найкраще IRC). +Дивіться інформацію нижче щодо IRC та Reddit. + +Обговорення розробки +====================== + +Списки розсилки плануються на майбутнє. Зараз, подивіться нотатки +на [сторінці Git](git.md) для інформації щодо допомоги з розробкою. + +На цій сторінці також знаходяться інструкції по відправці патчів (через pull request'и). + +Кімната IRC +============ + +IRC це головний спосіб зв'язку з проектом Libreboot. `#libreboot` на Libera +IRC. + +Веб-версія: + + +Libera є однією з найбільших мереж IRC, використовуємих для проектів вільного програмного +забезпечення. Знайти про них більше можна тут: + +Якщо ви бажаєте під'єднатися за допомогою вашого улюбленного клієнта (такого як weechat або irssi), +інформація для під'єднання наступна: + +* Сервер: `irc.libera.chat` +* Канал: `#libreboot` +* Порт (TLS): `6697` +* Порт (не TLS): `6667` + +Ми радимо вам використовувати порт `6697` з увімкненим TLS шифруванням. + +Рекомендовано використовувати SASL для аутентифікації. Ці сторінки на веб-сайті Libera +пояснять вам як: + +* Керівництво WeeChat SASL: +* Керівництво Irssi SASL: +* Керівництво HexChat SASL: + +Взагалі, вам варто перевірити документацію, яка передбачена вашою програмою IRC. + +Соціальні мережі +============ + +Libreboot офіційно існує в багатьох місцях. + +Mastodon +-------------------- + +Засновник та головний розробник, Лія Роу, є в Mastodon: + +* + +Також можливо зв'язатися з Лією за ії електронною адресою: +[leah@libreboot.org](mailto:leah@libreboot.org) + +Reddit +------ + +Найбільше використовується як канал підтримки, та також для оголошення новин: + diff --git a/site/contrib.md b/site/contrib.md new file mode 100644 index 0000000..cda4a8a --- /dev/null +++ b/site/contrib.md @@ -0,0 +1,453 @@ +--- +title: Project contributors +x-toc-enable: true +... + +This list does not necessarily reflect who is currently working on the project, +but it lists some people who have contributed to the project in meaningful ways. + +If we forgot to mention you here, let us know and we'll add you. (or if +you don't want to be mentioned, let us know and we'll remove your +entry) + +Information about who works on libreboot, and how the project is run, can +be found on this page: [who.md](who.md) + +You can know the history of the libreboot project, simply by reading this page. +It goes into detail about all of the major contributions to the project, and in +general how the project was created (and who helped create it). + +Leah Rowe +--------- + +**Founder of the Libreboot project, and currently the lead developer.** Leah +works on all aspects of libreboot, such as: + +* General management. Leah handles all outside contributions to libreboot, + reviews pull requests, deals with bug reports, delegates tasks when necessary + or desirable. Leah controls the libreboot.org server infrastructure, hosted + in her lab. +* Leah has the final say on all decisions, taking input via discussion with + members of the public, mostly on IRC. Leah oversees releases of libreboot, + and generally keeps the project going. Without Leah, there would be no Libreboot! +* The build system (lbmk, short for libreboot Make). This is the automated build + system that sits at the heart of libreboot; it downloads, patches, configures + and compiles the relevant components like coreboot, GRUB and generates + the libreboot ROM images that you can find in release archives. +* Upstream work on coreboot, when necessary (and other projects that libreboot + uses). This means also working with people from outside of the libreboot + project, to get patches merged (among other things) on the upstream projects + that libreboot uses +* Providing user support on IRC + +Caleb La Grange +--------------- + +**Secondary developer, number two to Leah.** Caleb is a full time libreboot developer +with a narrower focus. Caleb focuses on several areas of development: + +* Build system. Caleb is responsible for improving and fixing the libreboot Make build +system. Specifically: binary blob management, automation, and reproducibility. +* Hardware modification. Caleb has a passion for hardware alteration; soldering, +desoldering, and testing libreboot software on the resulting hardware. +* Board porting. Anything supported in Coreboot can be ported to libreboot, Caleb +will test and port any board he can get his hands on. Additionally, anyone can +contact Caleb to generate libreboot roms for testing on their board. +* Documentation. Caleb actively maintains documentation on the above areas of +interest. Additionally, Caleb is responsible for disassembly guides with his own +pictures and diagrams for several boards. +* User support. Caleb is active on irc and willing to help any user interested in +using libreboot or in need of help. +* Project goals. Caleb collaborates with Leah on determining project goals. +Leah has the final say in every decision. + +External projects +================= + +Coreboot project +---------------- + +Without coreboot, the libreboot project simply would not be possible. + +The people and companies that work on coreboot are numerous, and they make the +libreboot project what it is. The libreboot project makes heavy use of coreboot, to +provide hardware initialization. + +GRUB +-------- + +GRUB is the bootloader used by libreboot. It goes without saying that the GRUB +developers enable libreboot, through their work. + +SeaBIOS +------- + +The libreboot firmware provides SeaBIOS as a payload option. SeaBIOS provides a +legacy x86 BIOS implementation. + +U-Boot +------ + +Libreboot uses U-Boot as the coreboot payload on supported ARM Chromebooks. + +Contributors in alphabetical order +================================== + +Alper Nebi Yasak +---------------- + +Contributed the build system integration and documentation for using +U-Boot as payload, and initial Libreboot ports of some ARM Chromebooks +based on that. + +Alper also does upstream development on U-Boot, e.g. continued an almost +complete port of the `gru-kevin` board and got it merged upstream. + +Alyssa Rosenzweig +----------------- + +Switched the website to use markdown in lieu of handwritten HTML and custom +PHP. **Former libreboot project maintainer (sysadmin for libreboot.org).** + +Alyssa wrote the original static site generator (shell scripts converting +markdown to html, via pandoc) for libreboot.org. This static site generator has +now been heavily modified and forked into a formal project, by Leah Rowe: + + (untitled is Leah's work, not Alyssa's, but it's based on +Alyssa's original work on the static site generator that Libreboot used to use; +the Libreboot website is now built with Untitled) + +Andrew Robbins +-------------- + +Worked on large parts of Libreboot's old build system and related documentation. +Andrew joined the Libreboot project as a full time developer during June 2017, +until his departure in March 2021. + +I, Leah Rowe, am very grateful to Andrew Robbins for his numerous contributions +over the years. + +Arthur Heymans +-------------- + +Merged a patch from coreboot into libreboot, enabling C3 and C4 power +states to work correctly on GM45 laptops. This was a long-standing issue +before Arthur's contribution. Arthur also fixed VRAM size on i945 on +GM45 systems, allowing maximum VRAM allocation for the onboard GPUs on +these systems, another longstanding issue in libreboot. + +Arthur also did work on the Libreboot build system, when he was a member of the +project. He still works on coreboot, to this day, and Libreboot greatly +benefits from his work. His contributions to the coreboot project, and Libreboot, +are invaluable. + +Damien Zammit +------------- + +Maintains the Gigabyte GA-G41M-ES2L coreboot port, which is integrated +in libreboot. Also works on other hardware for the benefit of the +libreboot project. + +Damien didn't work directly on Libreboot itself, but he worked heavily with +Leah Rowe, integrating patches and new board ports into Libreboot, based on +Damien's upstream work on coreboot. + +Denis Carikli +------------- + +Based on the work done by Peter Stuge, Vladimir Serbinenko and others in +the coreboot project, got native graphics initialization to work on the +ThinkPad X60, allowing it to be supported in libreboot. Denis gave +a lot of advice and helped found the libreboot project. + +Denis was a mentor to Leah Rowe in the early days, when she founded the +Libreboot project. A lot of the decisions taken, especially with the +Libreboot build system (lbmk), were inspired from talks with Denis. + +Denis taught Leah about registers used by Intel GPUs for backlight control. In +the early days, the ThinkPad X60 and T60 laptops in Libreboot did not have +backlight control working, so the brightness was always 100%. With Denis's help, +Leah was able to get backlight controls working by reverse engineering the +correct values to write in those registers. Based on this, a simple fix was +written in coreboot; however, the fix just wrote directly to the register and +didn't work with ACPI based brightness controls. Others in coreboot later +improved it, making ACPI-based backlight controls work properly, based on this +earlier work. + +Ferass El Hafidi +-------- + +Added cstate 3 support on macbook21, enabling higher battery life and cooler +CPU temperatures on idle usage. + +Also has a series of extensive improvements to the entire Libreboot system; +for example, Ferass made the entire build system use POSIX `sh`, removing +bashisms that previously plagued it. + +This is IRC nick `f_` on Libreboot IRC. Cool guy! + +Jeroen Quint +------------ + +Contributed several fixes to the libreboot documentation, relating to +installing on Arch-based systems with full disk encryption on libreboot +systems. + +Joshua Gay +---------- + +Joshua is former FSF staff. + +Joshua helped with the early founding of the Libreboot project, in his capacity +(at that time) as the FSF's licensing and compliance manager. It was his job to +review products sent into to the FSF for review; the FSF has a certification +program called *Respects Your Freedom* (RYF) where the FSF will promote your +company's products if it comes with all Free Software. + +I, Leah Rowe, was initially just selling ThinkPad X60 laptops with regular +coreboot on them, and this included CPU microcode updates. At the time, I didn't +think much of that. Joshua contacted me, in his capacity at the FSF, and asked +if I would be interested in the FSF's RYF program; I was very surprised that the +FSF would take me seriously, and I said yes. This is what started the early +work on Libreboot. Joshua showed me all the problems my products had, and from +that, the solution was clear: + +A project needed to exist, providing a fully free version of coreboot, without +any binary blobs. At the time (and this is still true today), coreboot was not +entirely libre software and shipped with binary blobs by default. In particular, +CPU microcode updates were included by default, on all x86 machines. Working +with Joshua who reviewed my work, I created a fully free version of coreboot. +At first, it wasn't called Libreboot, and the work was purely intended for my +company (at that time called Gluglug) to be promoted by the FSF. + +Joshua used his media connections at the FSF to heavily promote my work, and +on December 13th, 2013, the Libreboot project was born (but not called that). +Joshua made sure that everyone knew what I was doing! + +A few months later, the name *Libreboot* was coined, and the domain name +*libreboot.org* was registered. At that point, the Libreboot project (in early +2014) was officially born. Once again, Joshua provided every bit of help he +could, heavily promoting the project and he even wrote this article on the FSF +website, announcing it: + + + +Klemens Nanni +------------- + +Made many fixes and improvements to the GRUB configuration used in +libreboot, and several tweaks to the build system. + +Lisa Marie Maginnis +------------------- + +Lisa is a former sysadmin at the Free Software Foundation. In the early days of +the project, she provided Leah with a lot of technical advice. She initially +created Libreboot IRC channel, when Leah did not know how to +use IRC, and also handed +F founder status to Leah for the channel. As an FSF +sysadmin, it was Lisa's job to maintain a lot of the infrastructure used by +Libreboot; at the time, mailing lists on the Savannah website were used by +the Libreboot project. When Paul Kocialkowski was a member of the project in +2016, she helped him get help from the FSF; he was the leader of the Replicant +project at the time, which had funding from the FSF, and the FSF authorized him +to use some of that funding for his work on Libreboot, thanks to Lisa's +encouragement while she worked at the FSF. + +Lisa also stepped in when Leah Rowe missed her LibrePlanet 2016 talk. Leah was +scheduled to do a talk about Libreboot, but didn't show up in time. Lisa, along +with Patrick McDermott (former Libreboot developer, who was present at that +conference) did the talk in Leah's place. The talk was never recorded, but the +Free Software Foundation has these photos of that talk on their LibrePlanet +website (the woman with the blue hair is Lisa, and the long-haired dude with the +moustache is Patrick): + + + + + +Fun fact: Patrick is also the lead developer of ProteanOS, an FSF-endorsed +embedded OS project: (uses BusyBox and Linux-libre) + +Leah Rowe ran *2* LibrePlanet workshops; one in 2015 and another in 2016, while +visiting Boston, MA, USA on both occasions to attend these conferences. These +workshops were for Libreboot installations. People came to both workshops, to +have Libreboot installed onto their computers. As FSF sysadmin, at that time, +Lisa provided all of the infrastructure and equipment used at those workshops. +Without her help, those workshops would have not been possible. + +When the ASUS KGPE-D16 mainboard (high-end server board) was ported to Libreboot, +Leah, working with Timothy Pearson (the one who ported it), shared patches back +and forth with Lisa around mid 2016, mostly raminit patches, to get the board +running at the FSF offices. This work ultimately lead to a most wonderful +achievement: + +The FSF and GNU websites now run on +Librebooted ASUS KGPE-D16 based servers, on a fully free GNU+Linux distro. This +means that the FSF now has full software freedom for their hosting infrastructure. + +The FSF also provides access to this infrastructure for many other projects +(besides GNU projects); for example, Trisquel uses a D16 provided by the FSF +for their development server used for building Trisquel releases and testing +changes to the Trisquel GNU+Linux distribution. Trisquel is a fully free +GNU+Linux distribution, heavily promoted by the FSF. + +Lisa was a strong supporter of Libreboot in the very early days of the project, +and her contributions were invaluable. I, Leah Rowe, owe her a debt of gratitude. + +Marcus Moeller +-------------- + +Made the libreboot logo. + +Nicholas Chin +------------- + +[Ported Dell Latitude E6400 to Libreboot](news/e6400.md). + +Patrick "P. J." McDermott +--------------------------- + +Patrick also did a lot of research and wrote the libreboot FAQ section +relating to the [Intel Management Engine](../faq.md#intelme), in addition +to making several improvements to the build system in libreboot. **Former +libreboot project maintainer.** + +In 2016, Leah Rowe ran a Libreboot installation workshop at the FSF's +LibrePlanet conference. Working alongside Leah, Patrick helped run the workshop +and assisted with installing Libreboot onto people's machines. + +Paul Kocialkowski +----------------- + +Ported the ARM (Rockchip RK3288 SoC) based *Chromebook* laptops to +libreboot. Also one of the main [Replicant](http://www.replicant.us/) +developers. + +Paul Menzel +----------- + +Investigated and fixed a bug in coreboot on the ThinkPad X60/T60 exposed +by Linux kernel 3.12 and up, which caused 3D acceleration to stop +working and video generally to become unstable. The issue was that coreboot, +when initializing the Intel video chipset, was mapping *GTT Stolen Memory* in +the wrong place, because the code was based on kernel code and the Linux kernel +had the same bug. When Linux fixed it, it exposed the same bug in coreboot. + +Paul worked with Libreboot on +this, sending patches to test periodically until the bug was fixed +in coreboot, and then helped her integrate the fix in libreboot. + +Peter Stuge +----------- + +Helped write the [FAQ section about DMA](../faq.md#hddssd-firmware), and provided +general advice in the early days of the project. Peter was a coreboot developer +in those days, and a major developer in the *libusb* project (which flashrom +makes heavy use of). + +Peter also wrote the *bucts* utility used to set Backup Control (BUC) Top Swap +(TS) bit on i945 laptops such as ThinkPad X60/T60, which is useful for a +workaround to flash Libreboot without using external hardware; on this machine, +with Lenovo BIOS present, it's possible to flash everything except the main +bootblock, but Intel platforms have 2 bootblocks, and you specify which one is +to be used by setting the TS bit. You then boot with only one bootblock flashed +(by the coreboot project's bootblock on that machine), and afterwards you reset +bucts before flashing the ROM again, to flash the main bootblock. Libreboot +hosts a copy of his work, because his website hosting bucts is no longer +responsive. + +Steve Shenton +------------- + +Steve did the early reverse engineering work on the Intel Flash Descriptor used +by ICH9M machines such as ThinkPad X200. He created a C struct defining (using +bitfields in C) this descriptor region. With some clever tricks, he was able to +discover the existence of a bit in the descriptor for *disabling* the Intel ME +(management engine) on those platforms. + +His initial proof of concept only defined the descriptor, and would do this: + +* Read the default descriptor and GbE regions from a Lenovo X200 ROM (default + firmware, not coreboot) +* Disable the ME, by setting 2 bits in the descriptor +* Disable the ME region +* Move descriptor+GbE (12KiB in total) next to each other +* Allocate the remaining flash space to the BIOS region +* Generated the 12KiB descriptor+GbE region, based on this, to insert into a + coreboot ROM image. + +In the early days, before Libreboot supported GM45+ICH9M platforms such as +ThinkPad X200/T400, you could use those machines but to avoid the Intel ME you +had to flash it without a descriptor region. This worked fine in those days, +because the ME only handled TPM and AMT on those machines, and the system would +work normally, but that Intel Flash Descriptor also handles the Intel GbE NVM +region in flash, which is used for the Intel Gigabit Ethernet interface. + +So you either had Intel ME, or no ethernet support. Steve figured out how to +disable the Intel ME via 2 toggle bits in the descriptor, and also how to +remove the Intel ME region from flash. + +Based on his research, I, Leah Rowe, working alongside Steve, also reverse +engineered the layout of the Intel GbE NVM (non-volatile memory) region in the +boot flash. This region defines configuration options for the onboard Intel +GbE NIC, if present. + +Based on this, I was able to take Steve's initial proof of concept and write +the `ich9gen` utility, which generates an Intel Flash Descriptor and GbE NVM +region, from scratch, without an Intel ME region defined. It is this tool, +the `ich9gen` tool, that Libreboot uses to provide ROM images for GM45+ICH9M +platforms (such as ThinkPad X200/T400/T500/W500), with a fully functional +descriptor and functional Gigabit Ethernet, but *without* needing Intel +Management Engine (ME) firmware, thus making those machines *libre* (the ME +is fully disabled, when you use a descriptor+gbe image generated by `ich9gen`). + +With *my* `ich9gen` tool (Steve's tool was called `ich9deblob`), you didn't +need a dump of the original Lenovo BIOS firmware anymore! I could not have +written this tool, without Steve's initial proof of concept. I worked with him, +extensively, for many months. All GM45+ICH9M support (X200, T400, etc) in +Libreboot is made possible because of the work he did, back in 2014. + +Swift Geek +---------- + +Contributed a patch for ich9gen to generate 16MiB descriptors. + +After that, Swift Geek slowly became more involved until he became a full time +developer. Swift Geeks contributions were never really in the form of *code*, +but what he lacked in code, he made up for in providing excellent support, both +to users and other developers, helping others learn more about technology at a +low level. + +When Swift Geek was a member of the project, his role was largely providing +user support (in the IRC channel), and conducting research. Swift Geek knows a +lot about hardware. Swift Geek also did some upstream development on GRUB. + +Swift Geek has provided technical advice on numerous occasions, to Leah Rowe, +and helped her to improve her soldering skills in addition to teaching her +some repair skills, to the point where she can now repair most faults on +ThinkPad mainboards (while looking at the schematics and boardview). + +Swiftgeek left the project in March 2021. I, Leah Rowe, wish him all the best +in his endeavours, and I'm very grateful to his numerous contributions over the +years. + +Timothy Pearson +--------------- + +Ported the ASUS KGPE-D16 board to coreboot for the company Raptor +Engineering of which Timothy is the CEO. +Timothy maintains this code in coreboot, +helping the project with the libreboot integration for it. This person's +contact details are on the raptor site. + +Vladimir Serbinenko +------------------- + +Ported many of the thinkpads supported in libreboot, to coreboot, and +made many fixes in coreboot which benefited the libreboot project. + +Vladimir wrote a lot of the original video initialization code used by various +Intel platforms in Libreboot, when flashing it (now rewritten +by others in Ada, for libgfxinit in coreboot, but originally it was written in +C and included directly in coreboot; libgfxinit is a 3rdparty submodule of +coreboot). diff --git a/site/contrib.uk.md b/site/contrib.uk.md new file mode 100644 index 0000000..500d456 --- /dev/null +++ b/site/contrib.uk.md @@ -0,0 +1,449 @@ +--- +title: Учасники проекту +x-toc-enable: true +... + +У цьому списку не обов'язково вказується, хто зараз працює над проектом, +але в ньому вказано людей, які зробили значний внесок у проект. + +Якщо ми забули вас тут згадати, повідомте нам, і ми вас додамо. (або якщо +ви не хочете, щоб вас згадували, повідомте нас, і ми видалимо ваш +запис) + +Інформацію про те, хто працює над libreboot і як працює проект, можна +знайти на цій сторінці: [who.md](who.md) + +Ви можете дізнатися історію проекту libreboot, просто прочитавши цю сторінку. +Тут докладно розповідається про всі основні внески в проект і +загалом про те, як створювався проект (і хто допоміг його створити). + +Лія Роу +--------- + +**Засновник проекту Libreboot, а зараз провідний розробник** Лія +працює над усіма аспектами libreboot, такими як: + +* Загальне керівництво. Лія обробляє всі зовнішні внески до libreboot, + переглядає пул реквести, має справу із звітами про помилки, делегує завдання, коли це необхідно + або бажано. Лія контролює серверну інфраструктуру libreboot.org, розміщену + в її лабораторії. +* Лія має останнє слово щодо всіх рішень, беручи внесок через обговорення з + представниками громадськості, переважно на IRC. Лія контролює випуски libreboot + і загалом підтримує проект. Без Лії не було би Libreboot! +* Система збірки (lbmk, скорочення від libreboot Make). Це автоматизована + система збирання, яка лежить в серці libreboot; він завантажує, патчить, налаштовує + та компілює відповідні компоненти, такі як coreboot, GRUB, і генерує образи ROM + libreboot, які ви можете знайти в архівах випусків. +* Апстрім робота над coreboot, коли необхідно (та іншими проектами, які libreboot + використовує). Це також означає роботу з людьми поза межами проекту libreboot, + щоб об'єднати виправлення (між іншим) в апстрім проектах, + які libreboot використовує +* Надання підтримки користувачів на IRC + +Калеб Ла Гранж +--------------- + +**Вторинний розробник, номер два для Лії.** Калеб - розробник libreboot на повний робочий день +з вузьким фокусом. Калеб зосереджується на кількох напрямках розвитку: + +* Система побудови. Калеб відповідає за вдосконалення та виправлення системи побудови libreboot Make. +Зокрема, управління бінарними блобами, автоматизація та відтворюваність. +* Апаратна модифікація. Калеб має пристрасть до переробки апаратного забезпечення; паяння, +розпаювання, та тестування libreboot на отриманому обладнанні. +* Перенесення плати. Все, що підтримується в Coreboot, можна перенести на libreboot, Калеб +перевірить і перенесе будь-яку плату, до якої зможе потрапити. Крім того, будь-хто може +зв'язатись з Калебом, щоб створити образи libreboot для тестування на своїй платі. +* Документація. Калеб активно веде документацію щодо зазначених вище сфер +інтересу. Додатково, Калеб відповідає за посібники з розбирання з власними +малюнками та діаграмами для кількох плат. +* Підтримка користувачів. Калеб активний в irc і готовий допомогти будь-якому користувачеві, який зацікавлений в +використанні libreboot або потребує допомоги. +* Цілі проекту. Калеб співпрацює з Лією над визначенням цілей проекту. +Лія має останнє слово в кожному рішенні. + +Зовнішні проекти +================ + +Проект Coreboot +---------------- + +Без coreboot проект libreboot був би просто неможливий. + +Людей і компаній, які працюють над coreboot, багато, і вони роблять +проект libreboot таким, яким він є. Проект libreboot активно використовує coreboot +для ініціалізації обладнання. + +GRUB +-------- + +GRUB - це завантажувач, який використовується libreboot. Само собою зрозуміло, що +розробники GRUB стимулюють libreboot своєю роботою. + +SeaBIOS +------- + +Прошивка libreboot надає SeaBIOS як опцію корисного навантаження. SeaBIOS забезпечує +застарілу реалізацію BIOS x86. + +U-Boot +------ + +Libreboot використовує U-Boot як корисне навантаження coreboot на ноутбуках +ARM Chromebook з підтримкою coreboot. + +Внески в алфавітному порядку +============================ + +Алісса Розенцвейг +----------------- + +Переключила веб-сайт на використання розмітки замість рукописного HTML та користувацького +PHP. **Колишній супроводжувач проекту libreboot (системний адміністратор libreboot.org).** + +Алісса написала оригінальний генератор статичних сайтів (скрипти `sh`, що перетворюють +markdown в html, через pandoc) для libreboot.org. Цей генератор статичних сайтів +був значно змінений і відгалужений Лією Роу у формальний проект: + + (untitled - це робота Лії, а не Алісси, але вона базується на +оригінальній роботі Аліси над генератором статичних сайтів, який раніше використовував Libreboot; +веб-сайт Libreboot тепер створено за допомогою Untitled) + +Альпер Небі Ясак +---------------- + +Надав інтеграцію системи збірки та документацію для використання +U-Boot в якості корисного навантаження, та початкові порти Libreboot деяких ARM Chromebook +виходячи з того. + +Альпер також займається розробкою на U-Boot, напр. продовжив майже завершений +порт плати `gru-kevin` і об'єднав його з апстрімом. + +Артур Хейманс +-------------- + +Об'єднав патч із coreboot у libreboot, дозволяючи режимам живлення C3 та C4 +правильно працювати на ноутбуках GM45. Це була давня проблема до внеску +Артура. Артур також виправив розмір відеопам'яті на i945 на системах +GM45, що дозволило максимально розподілити VRAM для вбудованих графічних процесорів +у цих системах, ще одна давня проблема в libreboot. + +Артур також працював над системою збірки Libreboot, коли він був учасником +проекту. Він досі працює над coreboot, і Libreboot отримує велику +користь від його роботи. Його внесок у проект coreboot і Libreboot +неоціненний. + +Володимир Сербіненко +------------------- + +Перенес багато thinkpad, які підтримуються в libreboot, на coreboot, а +також зробив багато виправлень у coreboot, які принесли користь проекту libreboot. + +Володимир написав багато вихідного коду ініціалізації відео, який використовується різними +платформами Intel у Libreboot, під час прошивки (зараз переписаний +іншими в Ada, для libgfxinit в coreboot, але спочатку він був написаний на +C і включений безпосередньо в coreboot; libgfxinit є субмодуль третьої сторони). + +Демієн Замміт +------------- + +Підтримує порт coreboot Gigabyte GA-G41M-ES2L, інтегрований у +libreboot. Також працює над іншим апаратним забезпеченням на користь +проекту libreboot. + +Демієн не працював безпосередньо над самим Libreboot, але він багато працював з +Лією Роу, інтегруючи патчі та нові порти плати в Libreboot на основі +попередньої роботи Демієна над coreboot. + +Денис Каріклі +------------- + +На основі роботи, виконаної Пітером Стюджем, Володимиром Сербіненко та іншими +в проекті coreboot, вдалось налагодити нативну ініціалізацію графіки для роботи +на ThinkPad X60, що дозволяє підтримувати її в libreboot. Денис дав +багато порад і допоміг створити проект libreboot. + +Денис був наставником Лії Роу в ранні дні, коли вона заснувала проект +Libreboot. Багато прийнятих рішень, особливо щодо системи збірки +Libreboot (lbmk), були натхненні розмовами з Денисом. + +Денис навчив Лію про регістри, які використовуються графічним процесором Intel для керування підсвічуванням. +В ранні дні, ноутбуки ThinkPad X60 та T60 в Libreboot не мали працюючого +контроля підсвічуванням, тому яскравість завжди була 100%. За допомогою Дениса, +Лія змогла налаштувати керування підсвічуванням шляхом зворотньої розробки +правильних значень для запису в ці регістри. На основі цього в coreboot +було написано просте виправлення; однак виправлення перезаписувало безпосередньо регістр +і не працювало з елементами керування яскравістю на основі ACPI. Інші в coreboot +пізніше вдосконалили його, змусивши елементи керування підсвічуванням на основі ACPI працювати належним чином, на основі цієї +попередньої роботи. + +Джерун Квінт +------------ + +Додав кілька виправлень до документації libreboot, пов'язаної зі +встановленням Arch з повним дисковим шифруванням у системах libreboot. + +Джошуа Гей +---------- + +Джошуа колишній співробітник FSF. + +Джошуа допоміг із раннім заснуванням проекту Libreboot, будучи +(на той час) менеджером з ліцензування та відповідності FSF. Його роботою було +переглядати продукти, надіслані до FSF для перевірки; FSF має програму +сертифікації, під назвою *Поважає Вашу Свободу* (Respects Your Freedom), за якою FSF рекламуватиме +продукти вашої компанії, якщо вони постачаються з усім вільним програмним +забезпеченням. + +Я, Лія Роу, спочатку просто продавала ноутбуки ThinkPad X60 із звичайним +coreboot, і це включало оновлення мікрокоду ЦП. У той час +я не дуже про це думала. Джошуа зв'язався зі мною, в своїх повноваженнях FSF, і спитав, +чи зацікавить мене програма RYF FSF; Я була дуже здивована, що FSF +сприйме мене серйозно, і я сказала так. Саме з цього почалася рання робота +над Libreboot. Джошуа показав мені всі проблеми з моїми продуктами, і з +цього, рішення було очевидним: + +Необхідно, щоб існував проект із повністю вільною версією coreboot без будь-яких +бінарних блобів. У той час (і це актуально й сьогодні) coreboot не був +повністю вільним програмним забезпеченням і за замовчуванням постачався з двійковими блобами. Зокрема, +оновлення мікрокоду ЦП включено за замовчуванням на всіх машинах x86. Працюючи +з Джошуа, я створила повністю вільну версію coreboot. +Спочатку він не називався Libreboot, і робота була призначена виключно для моєї +компанії (на той час вона називалася Gluglug), яку просувала FSF. + +Джошуа використовував свої медійні зв'язки в FSF, щоб активно рекламувати мою роботу, і +13 грудня 2013 року народився проект Libreboot (але не названий так). +Джошуа переконався, щоб всі знали, що я роблю! + +Через кілька місяців було створено назву *Libreboot* і зареєстровано доменне ім'я +*libreboot.org*. У цей момент офіційно народився проект Libreboot (на початку +2014 року). Знову Джошуа надав всю можливу допомогу, +активно просуваючи проект, і навіть написав цю статтю на веб-сайті FSF +оголосивши про це: + + + +Ендрю Роббінс +-------------- + +Працював над великими частинами старої системи збірки Libreboot і пов'язаною документацією. +Ендрю приєднався до проекту Libreboot як штатний розробник у червні 2017, +до моменту свого відходу в березні 2021 року. + +Я, Лія Роу, дуже вдячна Ендрю Роббінсу за його численні внески +протягом багатьох років. + +Клеменс Нанні +------------- + +Внесено багато виправлень і покращень у конфігурацію GRUB, яка використовується в +libreboot, а також кілька змін у системі збірки. + +Ліза Марі Магінніс +------------------- + +Ліза - колишній системний адміністратор Free Software Foundation. На перших днях +проекту вона давала Лії багато технічних порад. Спочатку вона створила +IRC-канал Libreboot, коли Лія не знала, як користуватися +IRC, а також передала +F статус засновника для каналу. Як системний +адміністратор FSF, роботою Лізи було підтримувати велику частину інфраструктури, +яку використовує Libreboot; на той час списки розсилки на веб-сайті Savannah +використовувалися проектом Libreboot. Коли Пол Коціалковскі був +учасником проекту в 2016 році, вона допомогла йому отримати допомогу від FSF; на той час він був +керівником проекту Replicant, який фінансував FSF, і FSF дозволив +йому використати частину цього фінансування для його роботи над Libreboot, завдяки Лізи +підтримці, коли вона працювала у FSF. + +Ліза також втрутилася, коли Лія Роу пропустила виступ на LibrePlanet 2016. Лія мала +виступити з доповіддю про Libreboot, але не з'явилася вчасно. Ліза разом +із Патріком Макдермоттом (колишнім розробником Libreboot, який був присутній +на тій конференції) виступили замість Лії. Розмова ніколи не була записана, але +Фонд вільного програмного забезпечення має ці фотографії цієї розмови на веб-сайті LibrePlanet +(жінка з блакитним волоссям - Ліза, а довговолосий хлопець із вусами - +Патрік): + + + + + +Цікавий факт: Патрік також є провідним розробником ProteanOS, проекту вбудованої +ОС, схваленого FSF: (використовує BusyBox і Linux-libre) + +Лія Роу провела *2* семінари LibrePlanet; один у 2015 році та інший у 2016 році, +відвідуючи Бостон, Массачусетс, США в обох випадках для участі в цих конференціях. Ці +семінари стосувалися встановлення Libreboot. Люди приходили на обидва семінари, щоб +встановити Libreboot на свої комп'ютери. Як системний адміністратор FSF, на той час, +Ліза забезпечила всю інфраструктуру та обладнання, яке використовувалося на цих семінарах. +Без її допомоги ці майстер-класи були б неможливими. + +Коли материнська плата ASUS KGPE-D16 (серверна плата високого класу) була перенесена на Libreboot, +Лія, працюючи з Тімоті Пірсоном (той, хто її переніс), +приблизно в середині 2016 року поділилася з Лізою виправленнями, в основному виправленнями raminit, щоб отримати плату, яка працює в офісах FSF. Ця робота +зрештою призвела до чудового досягнення: + +Веб-сайти FSF і GNU тепер працюють на, з встановленим Libreboot, +заснованих на ASUS KGPE-D16 серверах, на повністю вільному GNU+Linux дистрибутиві. Це +означає, що FSF тепер має повну свободу програмного забезпечення для своєї +інфраструктури хостингу. + +FSF також надає доступ до цієї інфраструктури для багатьох інших проектів +(крім проектів GNU); наприклад, Trisquel використовує D16, наданий FSF +для свого сервера розробки, який використовується для створення випусків Trisquel і тестування +змін у дистрибутиві Trisquel GNU+Linux. Trisquel - це повністю вільний +GNU+Linux дистрибутив, активно просуваний FSF. + +Ліза була сильною прихильницею Libreboot на перших днях проекту, +і її внесок був неоціненним. Я, Лія Роу, у боргу перед нею. + +Маркус Мьоллер +-------------- + +Зробив логотип libreboot. + +Nicholas Chin +------------- + +[Ported Dell Latitude E6400 to Libreboot](news/e6400.md). + +Патрік "П. Дж." Макдермотт +--------------------------- + +Патрік також провів багато досліджень і написав розділ поширених запитань libreboot, +пов'язаний із [Intel Management Engine](../faq.md#intelme), а також зробив кілька покращень у +системі збірки libreboot. **Колишній супроводжувач проекту +libreboot.** + +У 2016 році Лія Роу провела семінар зі встановлення Libreboot на конференції FSF +LibrePlanet. Працюючи разом з Лією, Патрік допомагав вести семінар +та допомагав установлювати Libreboot на комп'ютери людей. + +Пітер Стюдж +----------- + +Допоміг написати [розділ поширених запитань про DMA](../faq.md#hddssd-firmware), та надав +загальні поради на перших днях проекту. У той час Пітер був розробником coreboot +і головним розробником проекту *libusb* (який flashrom +активно використовує). + +Пітер також написав утиліту *bucts*, яка використовується для встановлення біта Top Swap +(TS) для керування резервним копіюванням (BUC) на ноутбуках i945, таких як ThinkPad X60/T60, яка є корисною для +обхідного шляху для прошивки Libreboot без використання зовнішнього обладнання; на цій машині, +з Lenovo BIOS, можна перепрошити все, крім головного завантажувального +блоку, але платформи Intel мають 2 завантажувальні блоки, і ви вказуєте, який із них +використовувати, встановленням біта TS. Потім ви завантажуєтеся лише з одним прошитим завантажувальним блоком +(завантажувальним блоком проекту coreboot на цій машині), а потім скидаєте +bucts перед повторною прошивкою ROM, щоб прошити основний завантажувальний блок. Libreboot +розміщує копію його роботи, оскільки його веб-сайт, на якому розміщено bucts, +більше не відповідає. + +Пол Коціалковський +----------------- + +Переніс ноутбуки Chromebook на основі ARM (Rockchip RK3288 SoC) до +libreboot. Також один із головних розробників [Replicant](http://www.replicant.us/). + +Пол Менцель +----------- + +Дослідив та виправив помилку в coreboot на ThinkPad X60/T60, яку виявляло +ядро Linux 3.12 і новіших версій, через яку прискорення 3D не +працювало, а відео загалом ставало нестабільним. Проблема полягала в тому, що +coreboot під час ініціалізації відеочіпсета Intel, відображав *GTT Stolen Memory* в +не тому місці, оскільки код базувався на коді ядра, а в ядрі Linux +була така сама помилка. Коли Linux це виправив, він виявив ту саму помилку в coreboot. + +Пол працював над цим із Libreboot, +періодично надсилаючи патчі для тестування, доки помилку не було виправлено +в coreboot, а потім допоміг ій інтегрувати виправлення в libreboot. + +Стів Шентон +------------- + +Стів виконав першу роботу зі зворотньої розробки Intel Flash Descriptor, який використовується +на машинах ICH9M, таких як ThinkPad X200. Він створив структуру C, що визначає (використовуючи +бітові поля в C) цю область дескриптора. За допомогою деяких хитрих трюків він зміг +виявити існування біта в дескрипторі для *вимкнення* Intel ME +(management engine) на цих платформах. + +Його початкове підтвердження концепції визначило лише дескриптор, і зробило би це: + +* Читання дескриптора за замовчуванням і регіонів GbE з ROM Lenovo X200 (прошивка + за замовчуванням, не coreboot) +* Вимкнення ME, встановивши 2 біти в дескрипторі +* Вимкнення регіона ME +* Переміщення дескриптора+GbE (загалом 12КБ) поруч +* Виділення решти флеш-пам'яті для регіону BIOS +* На основі цього створено 12КБ регіон дескриптор+область GBE для вставки + в образ ROM coreboot. + +У перші дні, до того, як Libreboot підтримував платформи GM45+ICH9M, такі як +ThinkPad X200/T400, ви могли використовувати ці машини, але щоб уникнути +Intel ME, вам доводилося виконувати прошивку без області дескриптора. У ті часи це працювало нормально, +тому що ME обробляв лише TPM та AMT на цих машинах, і система +працювала нормально, але Intel Flash Descriptor також обробляє область Intel GbE NVM +у флеш-пам'яті, яка використовується для інтерфейсу Intel Gigabit Ethernet. + +Отже, ви або мали Intel ME, або не підтримували ethernet. Стів зрозумів, як +вимкнути Intel ME за допомогою 2 бітів перемикання в дескрипторі, а також як видалити область +Intel ME з флеш-пам'яті. + +Ґрунтуючись на його дослідженні, я, Лія Роу, працюючи разом зі Стівом, також виконала зворотню розробку +області Intel GbE NVM (енергонезалежна пам'ять) у +завантажувальній флеш-пам'яті. Цей регіон визначає параметри конфігурації для вбудованої мережевої карти Intel +GbE, якщо присутня. + +На основі цього я змогла взяти початкове підтвердження концепції та написати +утиліту `ich9gen`, яка генерує Intel Flash Descriptor та регіон GbE NVM, +з нуля, без визначення регіону Intel ME. Саме цей інструмент, +інструмент `ich9gen`, використовує Libreboot для надання образів ROM для GM45+ICH9M +платформ (таких як ThinkPad X200/T400/T500/W500), із повнофункціональним +дескриптором та функціональним Gigabit Ethernet, але *без* необхідності мікропрограми Intel +Management Engine (ME), що робить ці машини *вільними* (ME +повністю вимкнено, коли ви використовуєте образ дескриптора+gbe, створене `ich9gen`). + +З *моїм* інструментом `ich9gen` (інструмент Стіва називався `ich9deblob`), вам більше +не потрібен був дамп оригінальної мікропрограми Lenovo BIOS! Я не могла би написати цей інструмент +без первинного підтвердження концепції Стіва. Я працювала з ним +протягом багатьох місяців. Вся GM45+ICH9M підтримка (X200, T400 і так далі) в +Libreboot стала можливою завдяки його роботі у 2014 році. + +Тімоті Пірсон +--------------- + +Перенес плату ASUS KGPE-D16 до coreboot для компанії Raptor +Engineering, генеральним директором якої є Тімоті. +Тімоті підтримує цей код у coreboot, допомогаючи проекту, +з його інтеграцією з libreboot. Контактні +дані цієї людини є на сайті raptor. + +**Підтримку D16 було припинено 19 листопада 2022 року. Ви все ще можете використовувати +старіші версії Libreboot, і старіші випуски.** + +Swift Geek +---------- + +Додав патч для ich9gen для створення дескрипторів розміром 16MiB. + +Після цього Swift Geek повільно почав долучатися, поки не став розробником на повний +робочий день. Внески Swift Geek насправді ніколи не були у формі *коду*, +але те, що йому не вистачало в коді, він компенсував чудовою підтримкою як для користувачів, +так і для інших розробників, допомагаючи іншим дізнатися більше про технології на +низькому рівні. + +Коли Swift Geek був учасником проекту, його роль здебільшого полягала в +наданні підтримки користувачам (на каналі IRC) і проведенні досліджень. Swift Geek знає +багато про апаратне забезпечення. Swift Geek також зробив деяку апстрім розробку GRUB. + +Swift Geek неодноразово надавав технічні поради Лії Роу +та допоміг їй покращити її навички паяння, а також навчив її +деяким навичкам ремонту, до того моменту, коли вона тепер може виправляти більшість несправностей +на материнських платах ThinkPad (під час перегляду схем та бордв'ю). + +Swiftgeek залишив проект у березні 2021 року. Я, Лія Роу, бажаю його всього найкращого в його +починаннях і дуже вдячна за його численні внески протягом багатьох +років. + +vitali64 +-------- + +Додав підтримку cstate 3 на macbook21, що забезпечує тривалий термін служби батареї +та нижчу температуру процесора під час простою. vitali64 на irc diff --git a/site/docs/bsd/index.md b/site/docs/bsd/index.md new file mode 100644 index 0000000..5fb5c49 --- /dev/null +++ b/site/docs/bsd/index.md @@ -0,0 +1,171 @@ +--- +title: BSD operating systems +x-toc-enable: true +... + +Guide last updated on 16 November 2022. + +NOTE: This guide pertains to x86 hosts, and does not cover supported CrOS/ARM +chromebooks. For ARM targets, you should refer to u-boot documentation. + +libreboot is capable of booting many BSD systems. This section mostly documents +the peculiarities of libreboot as it pertains to BSD; you can otherwise refer to +the official documentation for whatever BSD system you would like to use. + +Kernel Mode Setting +=================== + +Your BSD system *must* support Kernel Mode Setting for your graphics +device (most of them do nowadays). The reasons will become apparent, as +you read this article. + +Boot BSD, using SeaBIOS +======================= + +On x86 platforms, Libreboot provides the choice of GRUB and/or +SeaBIOS payload. GRUB can technically boot BSD kernels, but the code is +poorly maintained and unreliable for this use-case scenario; on BIOS systems, +GRUB can chainload BSD bootloaders, but on bare metal (as coreboot payload), +GRUB can only chainload other coreboot payloads or boot Linux/BSD kernels +directly (but direct booting is only really reliable for Linux, in GRUB). + +It is recommended that you boot in text mode, with SeaBIOS. You can literally +just follow the official installation guides for your BSD system, whether it +be FreeBSD, OpenBSD or others. + +If you don't plan to set up Xorg/Wayland, then that's all you really need to +do. For example, you might want to run a headless server, in which case you +probably don't mind running in text mode all the time. + +OpenBSD and corebootfb +---------------------- + +It's still recommended to use SeaBIOS in text mode, but OpenBSD specifically +can work with SeaBIOS booting in a coreboot framebuffer, with SeaVGABIOS. In +Libreboot ROM images, this would be SeaBIOS images with `corebootfb` in the +file name. + +Make sure to select MBR-style partitioning on the installer, and it will +Just Work. + +If you're using the GRUB payload but SeaBIOS is available in the boot menu, +you can just select SeaBIOS at said menu, and OpenBSD will work fine. + +FreeBSD and corebootfb +---------------------- + +Assumed broken, so please ensure that you boot with SeaBIOS payload in text +mode (lbmk ROM images with `txtmode` in the file name, not `corebootfb`). + +Warnings for X11 users +---------------------- + +One important peculiarity of most libreboot and libreboot systems is: VGA mode +support exists, if booting with corebootfb (coreboot's own framebuffer) and +the SeaVGABIOS option ROM used in the SeaBIOS payload; however, the ability +to switch modes is not present, which means you can't switch to text mode +either. + +Coreboot can start in framebuffer (corebootfb) or INT10H text mode, and it +stays in whatever mode was set, unless KMS is used to change the mode. It +should be noted that the coreboot framebuffer is not a VGA mode, but instead +coreboot implements minimal drivers for hardware that it supports, providing +a framebuffer directly in memory, which software (such as GRUB) can simply +use. + +The BSD bootloaders on x86, in BIOS systems, typically expect text mode +startup. It is usually possible to set the console to higher VGA modes, +on most systems, but not on most coreboot systems with native video +initialisation used, due to the quirks already described. If you see any +documentation (in BSD land) pertaining to VESA modes, ignore it entirely; +unless you're using the proprietary VGA ROM for your device, it won't work, +and Libreboot doesn't distribute these (instead, coreboot's own video +initialisation is used where possible, or a headless SeaBIOS payload setup +is provided, where you would either run it headless or install a graphics +card). + +Now, this would otherwise mean: no X11/Wayland. If you start in corebootfb +mode with SeaVGABIOS, you won't get a display in BSD bootloaders, and if you +boot in text mode, you can't set VESA modes from BSD. However, you're in luck: + +At least OpenBSD and FreeBSD (possibly others) all have excellent KMS +support nowadays; short for `Kernel Mode Setting`. This avoids the inefficiency +of BIOS/UEFI methods, by having the kernel set modes directly. It is based on +KMS drivers that the BSD projects ported over from the Linux kernel. With this, +you can use X11/Wayland in FreeBSD (and just X11 in OpenBSD, for now). + +For example: on FreeBSD, you can install `graphics/drm-kmod` as a package +or from ports, and (for Intel GPUs) do this: + + sysrc kld_list+="i915kms" + +This creates the following entry in `/etc/rc.conf`: + + kld_list="i915kms" + +On FreeBSD it is also recommended that you switch to KMS on the console/TTY; +add this to `/boot/loader.conf` so that you can still use the console after +terminating Xorg: + + kern.vty=vt + +You should not rely on the above instruction (for FreeBSD), because the exact +step might change, and it does not go into full detail either. Refer to the +documentation provided by your system, to know how KMS is configured. + +ALWAYS READ THE MANUAL +---------------------- + +All of the BSDs have *excellent* documentation; it's one of the defining +characteristics, versus typical Linux distros. + +Aside from this quirk in coreboot, regarding *BIOS* video modes, the BSDs +otherwise work in exactly the same way as you would expect, and you can +follow along to their official documentation without much fuss. + +No specific or detailed guides will be provided here, because SeaBIOS is +fairly self-explanatory; you can otherwise refer to the SeaBIOS +documentation. + +If you're flashing a ROM for a machine where `seabios_withgrub` +and `seabios_grubfirst` ROMs are available, choose `seabios_withgrub`. + +DO NOT USE ROM IMAGES WITH `seabios_grubfirst` IN THE FILE NAME! These were +present in older Libreboot releases, and supported in previous revisions +of the build system, but they did not work for the intended purpose. More +info is written on the [Libreboot installation guide](../install/). ROM +images with `seabios_grubfirst` in the filename will NOT be included in +future Libreboot releases. + +Dubious mention: Tianocore +-------------------------- + +Tianocore is extremely bloated, and unauditable, so it is not included +in Libreboot firmware, but it is the reference UEFI implementation by +Intel and contributors. It can boot most BSD systems very well. + +More robust ways to provide UEFI services in Libreboot are to be investigated. +Tianocore integration will not be provided officially, in any current or future +releases of Libreboot. + +Desktop users +------------- + +Desktop users on Libreboot should just install a graphics card, +and again boot with SeaBIOS in text mode; however, when you do this, +SeaBIOS will execute the VGA option ROM on the card which will provide +early video initialisation instead of coreboot's initialisation, and that +VGA ROM will usually implement full INT10H modes, including the ability +to set modes in the BIOS (using interrupts), in which case you don't +need to worry about Kernel Mode Setting, but you should still use KMS +anyway. + +The reason to use KMS is because it's more efficient. The INT10H service can +only be called in Real Mode or Virtual 8086 mode; v8086 is unavailable in +long mode (x86\_64) and switching into Real Mode just to set VGA modes is +extremely expensive computationally speaking. This is why modern kernels +(Linux and BSD one) do mode setting themselves. + +You can learn more about INT10H text/VGA modes here: + + diff --git a/site/docs/build/index.md b/site/docs/build/index.md new file mode 100644 index 0000000..e901dca --- /dev/null +++ b/site/docs/build/index.md @@ -0,0 +1,284 @@ +--- +title: Build from source +x-toc-enable: true +... + +libreboot's build system is named `lbmk`, short for `Libreboot Make`, and this +document describes how to use it. With this guide, you can know how to compile +libreboot from the available source code. +This version, if hosted live on libreboot.org, assumes that you are using +the `lbmk` git repository, which +you can download using the instructions on [the code review page](../../git.md). + +If you're using a release archive of libreboot, please refer to the +documentation included with *that* release. libreboot releases are only intended +as *snapshots*, not for development. For proper development, you should always +be working directly in the libreboot git repository. + +The following document describes how `lbmk` works, and how you can make changes +to it: [libreboot maintenance manual](../maintain/) + +Git +=== + +Libreboot's build system uses Git, extensively. You should perform the steps +below, *even if you're using a release archive*. + +Before you use the build system, please know: the build system itself uses +Git extensively, when downloading software like coreboot and patching it. + +You should make sure to initialize your Git properly, before you begin or else +the build system will not work properly. Do this: + + git config --global user.name "John Doe" + git config --global user.email johndoe@example.com + +Change the name and email address to whatever you want, when doing this. + +You may also want to follow more of the steps here: + + +Python +====== + +Python2 is unused by lbmk or anything that it pulls down as modules. You +should ensure that the `python` command runs python 3, on your system. + +Make +======== + +libreboot Make includes a file called `Makefile`. You can still use +the `lbmk` build system directly, or you can use Make. The `Makefile` +simply runs `lbmk` commands. However, using `lbmk` directly will offer you +much more flexibility; for example, the Makefile currently cannot build single +ROM images (it just builds all of them, for all boards). + +You must ensure that all build dependencies are installed. If you're running +Ubuntu or similar distribution (Debian, Arch, etc) you can do this: + + sudo make install-dependencies-ubuntu + +One exists specifically for Debian: + + sudo make install-dependencies-debian + +Another exists for Arch: + + sudo make install-dependencies-arch + +Now, simply build the coreboot images like so: + + make + +This single command will build ROM images for *every* board integrated in +libreboot. If you only wish to build a limited set, you can use `lbmk` directly: + + ./build boot roms x200_8mb + +You can specify more than one argument: + + ./build boot roms x200_8mb x60 + +ROM images appear under the newly created `bin/` directory in the build system. + +For other commands, simply read the `Makefile` in your favourite text editor. +The `Makefile` is simple, because it merely runs `lbmk` commands, so it's very +easy to know what commands are available by simply reading it. + +Standard `clean` command available (cleans all modules except `crossgcc`): + + make clean + +To clean your `crossgcc` builds: + + make crossgcc-clean + +To build release archives: + + make release + +Build without using Make +============================ + +The `Makefile` is included just for *compatibility*, so that someone who +instictively types `make` will get a result. + +Actual development/testing is always done using `lbmk` directly, and this +includes when building from source. Here are some instructions to get you +started: + +First, install build dependencies +--------------------------------- + +libreboot includes a script that automatically installs apt-get dependencies +in Ubuntu 20.04: + + sudo ./build dependencies ubuntu2004 + +Separate scripts also exist: + + sudo ./build dependencies debian + + sudo ./build dependencies arch + + sudo ./build dependencies void + +Technically, any Linux distribution can be used to build libreboot. +However, you will have to write your own script for installing build +dependencies. + +libreboot Make (lbmk) automatically runs all necessary commands; for +example, `./build payload grub` will automatically run `./build module grub` +if the required utilities for GRUB are not built, to produce payloads. + +As a result, you can now (after installing the correct build dependencies) run +just a single command, from a fresh Git clone, to build the ROM images: + + ./build boot roms + +or even just build specific ROM images, e.g.: + + ./build boot roms x60 + +If you wish to build payloads, you can also do that. For example: + + ./build payload grub + + ./build payload seabios + + ./build payload u-boot qemu_x86_12mb + +Previous steps will be performed automatically. However, you can *still* run +individual parts of the build system manually, if you choose. This may be +beneficial when you're making changes, and you wish to test a specific part of +lbmk. + +Therefore, if you only want to build ROM images, just do the above. Otherwise, +please continue reading! + +Second, download all of the required software components +-------------------------------------------------------- + +If you didn't simply run `./build boot roms` (with or without extra +arguments), you can still perform the rest of the build process manually. Read +on! You can read about all available scripts in `lbmk` by reading +the [libreboot maintenance manual](../maintain/); lbmk is designed to be modular +which means that each script *can* be used on its own (if that's not true, for +any script, it's a bug that should be fixed). + +It's as simple as that: + + ./download all + +The above command downloads all modules defined in the libreboot build system. +However, you can download modules individually. + +This command shows you the list of available modules: + + ./download list + +Example of downloading an individual module: + + ./download coreboot + + ./download seabios + + ./download grub + + ./download flashrom + + ./download u-boot + +Third, build all of the modules: +-------------------------------- + +Building a module means that it needs to have already been downloaded. +Currently, the build system does not automatically do pre-requisite steps +such as this, so you must verify this yourself. + +Again, very simple: + + ./build module all + +This builds every module defined in the libreboot build system, but you can +build modules individually. + +The following command lists available modules: + + ./build module list + +Example of building specific modules: + + ./build module grub + + ./build module seabios + + ./build module flashrom + +Commands are available to *clean* a module, which basically runs make-clean. +You can list these commands: + + ./build clean list + +Clean all modules like so: + + ./build clean all + +Example of cleaning specific modules: + + ./build clean grub + + ./build clean cbutils + +Fourth, build all of the payloads: +--------------------------------- + +Very straight forward: + + ./build payload all + +You can list available payloads like so: + + ./build payload list + +Example of building specific payloads: + + ./build payload grub + + ./build payload seabios + +Each board has its own U-Boot build configuration in `lbmk` under +`resources/u-boot`. To build U-Boot payloads, you need to specify the +target board and maybe a cross compiler for its CPU architecture. These +are handled automatically when building ROM images, but for example: + + ./build payload u-boot qemu_x86_12mb # on x86 hosts + + CROSS_COMPILE=aarch64-linux-gnu- ./build payload u-boot gru_kevin + + CROSS_COMPILE=arm-linux-gnueabi- ./build payload u-boot veyron_speedy + +The build-payload command is is a prerequsite for building ROM images. + +Fifth, build the ROMs! +---------------------- + +Run this command: + + ./build boot roms + +Each board has its own configuration in `lbmk` under `resources/coreboot/` +which specifies which payloads are supported. + +By default, all ROM images are built, for all boards. If you wish to build just +a specific board, you can specify the board name based on the directory name +for it under `resources/coreboot/`. For example: + + ./build boot roms x60 + +Board names, like above, are the same as the directory names for each board, +under `resources/coreboot/` in the build system. + +That's it! + +If all went well, ROM images should be available to you under bin/ diff --git a/site/docs/build/index.uk.md b/site/docs/build/index.uk.md new file mode 100644 index 0000000..d29a52b --- /dev/null +++ b/site/docs/build/index.uk.md @@ -0,0 +1,284 @@ +--- +title: Побудова з джерельного коду +x-toc-enable: true +... + +Система побудови libreboot, називається `lbmk`, скорочення від `Libreboot Make`, і цей +документ описує те, як використовувати її. З цим керівництвом ви можете узнати те, як побудувати +libreboot з доступного джерельного коду. +Ця версія, якщо розміщена наживо на libreboot.org, передбачає, що ви використовуєте +сховище git `lbmk`, яке +ви можете завантажити, використовуючи інструкції на [сторінці огляду коду](../../git.uk.md). + +Якщо ви використовуєте архів випуску libreboot, будь ласка, зверніться до +документації, включеної до *того* випуску. Випуски libreboot розраховані тільки, +як *знімки*, не для розробки. Для належної розробки ви маєте завжди +працювати безпосередньо в сховищі git libreboot. + +Наступний документ описує те, як працює `lbmk`, і як ви можете робити зміни +до нього: [керівництво обслуговування libreboot](../maintain/) + +Git +=== + +Система побудови Libreboot використовує Git, обширно. Ви маєте виконати кроки +знизу, *навіть, якщо ви використовуєте архів випуску*. + +Перед тим, як вам використовувати систему побудови, будь ласка, знайте: система побудови, сама по собі, +використовує Git обширно, коли завантажує програмне забезпечення, таке як coreboot, та проводить застосування виправлень. + +Ви маєте переконатись в тому, щоб ініціалізувати ваш Git належним чином, перед тим, як почати, або інакше +система побудови не буде працювати належно. Зробіть це: + + git config --global user.name "John Doe" + git config --global user.email johndoe@example.com + +Змініть ім'я та адресу електронної пошти на будь-яку, що забажаєте, коли робите це. + +Ви також можете захотіти прослідувати більшій кількості етапів тут: + + +Python +====== + +Python2 не використовується lbmk або будь-чим, що завантажується в якості модулів. Ви +маєте переконатись, що команда `python` виконує python 3 на вашій системі. + +Make +======== + +libreboot Make включає файл, який названо `Makefile`. Ви досі можете +використовувати систему побудови `lbmk` безпосередньо, або ви можете використовувати Make. `Makefile` +просто виконує команди `lbmk`. Однак, використання `lbmk` безпосередньо запропонує вам +набагато більше гнучкості; наприклад, Makefile наразі не може побудувати один +образ ROM (він лише будує всі з них, для всіх плат). + +Ви мусите переконатись, що всі залежності побудови встановлено. Якщо ви використовуєте +Ubuntu або подібний дистрибутив (Debian, Arch і тому подібні), можете виконати це: + + sudo make install-dependencies-ubuntu + +Існує конкретно для Debian: + + sudo make install-dependencies-debian + +Інша існує для Arch: + + sudo make install-dependencies-arch + +Тепер, просто побудуйте образи coreboot подібним чином: + + make + +Ця єдина команда побудує образи ROM для *кожної* плати, інтегрованої до +libreboot. Якщо ви тільки хочете побудувати обмежену вибірку, можете використовувати `lbmk` безпосередньо: + + ./build boot roms x200_8mb + +Ви можете вказати більше одного аргумента: + + ./build boot roms x200_8mb x60 + +Образи ROM з'явяться під щойно створеною директорією `bin/` в системі побудови. + +Для інших команд просто прочитайте `Makefile` в своєму улюбленому текстовому редакторі. +`Makefile` є простим, тому що він виконує виключно команди `lbmk`, таким чином дуже +просто знати те, які команди є в доступності, просто читаючи його. + +Стандартна команда `clean` доступна (чистить всі модулі, окрім `crossgcc`): + + make clean + +Щоб почистити ваші побудови `crossgcc`: + + make crossgcc-clean + +Для побудови архівів випуску: + + make release + +Побудова без використання Make +============================ + +`Makefile` включено лише для *сумісності*, щоб якщо хтось +інстиктивно пише `make`, то було отримано результат. + +Фактична розробка/тестування завжди виконується безпосередньо за допомогою `lbmk`, і це також +стосується збирання з джерельного коду. Ось кілька інструкцій, щоб +почати: + +Спочатку встановіть залежності побудови +--------------------------------- + +libreboot включає сценарій, який автоматично встановлює apt-get залежності +в Ubuntu 20.04: + + sudo ./build dependencies ubuntu2004 + +Окремі сценарії також існують: + + sudo ./build dependencies debian + + sudo ./build dependencies arch + + sudo ./build dependencies void + +Технічно, будь-який дистрибутив Linux може бути використано для побудови libreboot. +Однак, вам потрібно буде написано свій власний сценарій для встановлення залежностей +побудови. + +libreboot Make (lbmk) автоматично виконує всі необхідні команди; наприклад, +`./build payload grub` автоматично виконає `./build module grub`, +якщо затребувані утиліти для GRUB не збудовано, для виготовлення корисних навантажень. + +В якості результату, ви тепер можете (після встановлення правильних залежностей побудови) виконати +лише одну команду, з свіжого Git clone, для побудови образів ROM: + + ./build boot roms + +або навіть побудувати конкретні образи ROM, такі як: + + ./build boot roms x60 + +Якщо ви бажаєте побудувати корисні навантаження, можете зробити це. Наприклад: + + ./build payload grub + + ./build payload seabios + + ./build payload u-boot qemu_x86_12mb + +Попередні кроки буде виконано автоматично. Однак, ви можете *досі* виконати +окремі частини системи побудови власноруч, якщо виберете. Це може бути +вигідно, коли ви робите зміни, та бажаєте протестувати конкретну частину +lbmk. + +Отже, якщо ви лише хочете побудувати образи ROM, просто зробіть наведене вище. В іншому випадку, +будь ласка, продовжіть читати! + +Друге, завантажити всі програмні компоненти, які вимагаються +-------------------------------------------------------- + +Якщо ви не виконали просто `./build boot roms` (з або без надлишкових +аргументів), ви все одно можете виконати залишок процесу побудови власноруч. Читайте +далі! Ви можете прочитати про всі доступні сценарії в `lbmk`, читаючи +[керівництво обслуговування libreboot](../maintain/); lbmk розроблено бути модулярним, +що означає те, що кожен сценарій *може* бути використано самостійно (якщо це не є правдою, для +будь-якого сценарія, це є помилкою, яка має бути виправлена). + +Це настільки просто, як це: + + ./download all + +Вищезазначена команда завантажує всі модулі, які означено в системі побудови libreboot. +Однак, ви можете завантажити модулі індивідуально. + +Ця команда показує вам список доступних модулів: + + ./download list + +Приклад завантаження індивідуального модуля: + + ./download coreboot + + ./download seabios + + ./download grub + + ./download flashrom + + ./download u-boot + +Третє, побудова кожного з модулів: +-------------------------------- + +Побудова модуля означає, що він має вже бути завантаженим. +В цей момент, система побудови не виконує автоматично кроки передумови, +такі як цей, тому ви мусите перевірити це власноруч. + +Знову, дуже просто: + + ./build module all + +Це будує кожен модуль, означений в системі побудови libreboot, але ви можете +будувати модулі індивідуально. + +Наступна команда перелічує доступні модулі: + + ./build module list + +Приклад побудови конкретних модулів: + + ./build module grub + + ./build module seabios + + ./build module flashrom + +Команди доступні для *очищення* модуля, які, по суті, виконують make-clean. +Ви можете перелічити ці команди: + + ./build clean list + +Видаліть всі модулі таким чином: + + ./build clean all + +Приклад видалення конкретних модулів: + + ./build clean grub + + ./build clean cbutils + +Четверте, побудуйте всі корисні навантаження: +--------------------------------- + +Дуже просто: + + ./build payload all + +Ви можете перелічити доступні корисні навантаження таким чином: + + ./build payload list + +Приклад побудови конкретних корисних навантажень: + + ./build payload grub + + ./build payload seabios + +Кожна плата має свою власну конфігурацію побудови U-Boot в `lbmk` під +`resources/u-boot`. Для побудови корисних навантажень U-Boot, вам потрібно вказати +цільову плату і мабуть крос-компілятор для її архітектури ЦП. Вони +керуються автоматично під час побудови образів ROM, але для прикладу: + + ./build payload u-boot qemu_x86_12mb # на хостах x86 + + CROSS_COMPILE=aarch64-linux-gnu- ./build payload u-boot gru_kevin + + CROSS_COMPILE=arm-linux-gnueabi- ./build payload u-boot veyron_speedy + +Команда build-payload є попередньою умовою для побудови образів ROM. + +П'яте, побудуйте ROM! +---------------------- + +Виконайте цю команду: + + ./build boot roms + +Кожна плата має свою власну конфігурацію в `lbmk` під `resources/coreboot/`, +яка вказує, які корисні навантаження підтримуються. + +За замовчуванням, всі образи ROM будуються, для всіх плат. Якщо ви бажаєте побудувати лише +конкретну плату, ви можете вказати назву плати, засновану на імені директорії +для неї під `resources/coreboot/`. Наприклад: + + ./build boot roms x60 + +Імена плат, як вище, такі самі, як імена директорій для кожної плати, +під `resources/coreboot/` в системі побудови. + +Ось так! + +Якщо все пройшло добре, образи ROM мають бути доступними вам під bin/ diff --git a/site/docs/grub/index.md b/site/docs/grub/index.md new file mode 100644 index 0000000..f2af59a --- /dev/null +++ b/site/docs/grub/index.md @@ -0,0 +1,52 @@ +--- +title: GRUB payload +x-toc-enable: true +... + +TODO: this guide should be reviewed and updated. Some info might be out of +date. + +GNU GRUB already has excellent +documentation, but there are aspects of libreboot that deserve special +treatment. libreboot provides the option to boot GRUB directly, running on +bare metal (instead of using BIOS or UEFI services). + +[The Linux section](../linux/) also has libreboot-specific guides for +dealing with Linux distributions when using GRUB directly, in this +setup. [A similar section exists for BSD operating systems](../bsd/) + +GRUB keyboard layouts +===================== + +It is possible to use *any* keymap in GRUB. + +Custom keyboard layout +---------------------- + +Keymaps are stored in `resources/grub/keymap/` + +You can use the `ckbcomp` program to generate a keymap, based on Xorg keymap +files: + + ckbcomp fr > frazerty + +When you build GRUB from source, you can use the `grub-mklayout` program to +create a special keymap file for GRUB. [Learn how to build GRUB](../build/) + +When you've built GRUB, using `lbmk` (libreboot build system), take your kepmap +file (generated by ckbcomp) and run it through `grub-mklayout` like so: + + cat frazerty | ./grub/grub-mklayout -o frazerty.gkb + +Place the newly created `.gkb` file under `resources/grub/keymap` in lbmk. When +you build libreboot, a ROM image with GRUB payload and your newly created +keymap will be available under the `bin/` directory. +[Learn how to build libreboot ROM images](../build/) + +Many keymaps exist in the libreboot build system, but sometimes you must +manually tweak the file created by `ckbcomp`, adjusting the scan codes in that +file, before converting to a GRUB keymap file. Therefore, it would be unwise to +automatically add all keymaps in GRUB. + +If you've added a keymap to lbmk, and it works, +[please submit a patch!](../../git.md) diff --git a/site/docs/hardware/acer_g43t-am3.md b/site/docs/hardware/acer_g43t-am3.md new file mode 100644 index 0000000..7c9ce3f --- /dev/null +++ b/site/docs/hardware/acer_g43t-am3.md @@ -0,0 +1,21 @@ +--- +title: Acer G43T-AM3 notes +x-toc-enable: true +... + +This is similar to Gigabyte GA-G41M-ES2L but uses an Intel NIC rather than +Realtek. Some problems with Linux on this NIC, on this board, with Libreboot, +were observed; see: + + + +That page (on notabug) has some notes about workarounds. It links to this: + + + +This page has some guidance on how to either correct the checksum (in GbE +config) or skip checksum validation in Linux, to get the onboard NIC working. +Although it's talking about different hardware, the steps should be the same. + +TODO: factory BIOS on this board works fine with the onboard NIC. study what +that is doing diff --git a/site/docs/hardware/c201.md b/site/docs/hardware/c201.md new file mode 100644 index 0000000..1e8188b --- /dev/null +++ b/site/docs/hardware/c201.md @@ -0,0 +1,9 @@ +--- +title: ASUS Chromebook C201 +x-toc-enable: true +... + +This page is absolete. Refer to these pages instead: + +* [C201 flashing instructions](../install/c201.md) +* [Chromebook flashing instructions](../install/chromebooks.md) diff --git a/site/docs/hardware/d510mo.md b/site/docs/hardware/d510mo.md new file mode 100644 index 0000000..2d8a6df --- /dev/null +++ b/site/docs/hardware/d510mo.md @@ -0,0 +1,61 @@ +--- +title: Intel D510MO and D410PT desktop boards +... + +
+
+![Intel D510MO]() +
+ +| ***Specifications*** | | +|----------------------------|------------------------------------------------| +| **Manufacturer** | Intel | +| **Name** | D510MO/D410PT | +| **Released** | 2010 | +| **Chipset** | Intel NM10 Express (Mount Olive) | +| **CPU** | Intel Atom | +| **Graphics** | Integrated | +| **Display** | None. | +| **Memory** | Up to 4GB | +| **Architecture** | x86_64 | +| **Original boot firmware** | Intel BIOS | +| **Intel ME/AMD PSP** | Not present. | +| **Flash chip** | ? | + +``` +W+: Works without blobs; +N: Doesn't work; +W*: Works with blobs; +U: Untested; +P+: Partially works; +P*: Partially works with blobs +``` + +| ***Features*** | | +|----------------|---------------------------------------| +| **Internal flashing with original boot firmware** | N | +| **Display** | - | +| **Audio** | W+ | +| **RAM Init** | P+ | +| **External output** | P+ | +| **Display brightness** | - | + +| ***Payloads supported*** | | +|---------------------------|-------| +| **GRUB** | Works | +| **SeaBIOS** | Works | +| **SeaBIOS with GRUB** | Works | +
+This is a desktop board using intel hardware (circa \~2009, ICH7 +southbridge, similar performance-wise to the ThinkPad X200. It can make +for quite a nifty desktop. Powered by libreboot. + +NOTE: D410PT is another name and it's the same board. Flash the exact same +ROM and it should work. + +NOTE: This board has a working framebuffer in Grub, but in Linux in +native resolution the display is unusable due to some raminit issues. +This board can however be used for building a headless server. + +Flashing instructions can be found at +[../install/d510mo.md](../install/d510mo.md) diff --git a/site/docs/hardware/d945gclf.md b/site/docs/hardware/d945gclf.md new file mode 100644 index 0000000..69edfd5 --- /dev/null +++ b/site/docs/hardware/d945gclf.md @@ -0,0 +1,124 @@ +--- +title: Intel D945GCLF desktop board +x-toc-enable: true +... + +
+
+D945GCLF +
+ +| ***Specifications*** | | +|----------------------------|------------------------------------------------| +| **Manufacturer** | Intel | +| **Name** | D945GCLF/D945GCLF2D | +| **Released** | 2008 | +| **Chipset** | Intel Calistoga 945GC | +| **CPU** | Intel Atom | +| **Graphics** | ? | +| **Display** | None. | +| **Memory** | Up to 2GB | +| **Architecture** | x86_64 | +| **Original boot firmware** | Intel BIOS | +| **Intel ME/AMD PSP** | Not present. | +| **Flash chip** | SOIC-8 512KiB | + +``` +W+: Works without blobs; +N: Doesn't work; +W*: Works with blobs; +U: Untested; +P+: Partially works; +P*: Partially works with blobs +``` + +| ***Features*** | | Notes | +|----------------|---------------------------------------|-------| +| **Internal flashing with original boot firmware** | N | | +| **Display** | - | | +| **Audio** | W+ | | +| **RAM Init** | W+ | | +| **External output** | W+ | | +| **Display brightness** | - | | + +| ***Payloads supported*** | | +|---------------------------|--------------| +| **GRUB** | Doesn't work | +| **SeaBIOS** | Works | +| **SeaBIOS with GRUB** | Doesn't work | +
+If you just want flashing instructions, go to +[../install/d945gclf.md](../install/d945gclf.md) + +D945GCLF2D also reported working by a user. + +Introduction +============ + +This board is a mini-itx desktop board for 2008. It uses an atom 230, +which is a singe core CPU but it is hyperthreaded so it appears to have +2 thread to the OS. The flash chip is very small, 512KiB, so grub2 does +not fit, which is why libreboot has to use seabios on this target. Full +disk encryption like on other supported targets will not be possible, so +plan accordingly. + +This board has a 945gc chipset which is the desktop equivalent of 945gm +which can be found in the Lenovo x60/t60 or macbook2,1. This chipset +features an ICH7 southbridge. It has 1 DIMM slot that can accommodate up +to 2G of DDR2 RAM. + +Connectivity-wise it has 1 PCI slot, a 10/100 ethernet port, 4 usb slot +and 4 usb ports, with one internal header and 2 SATA ports. + +The D945GCLF2 is an upgraded version of this board. The differences are: +1 more USB header, 10/100/1000 ethernet and a dual core cpu (also +hyperthreaded). Since the board is almost identical (and coreboot code +seem to indicate that it works, since MAX\_CPU=4 is set), it is believed +that it should also work but this is untested. + +Remarks about vendor bios: +-------------------------- + +- Without coreboot/libreboot this board is completely useless, since the + vendor bios is very bad. It cannot boot from any HDD whether it is + connected to the SATA port or USB. With libreboot it works just + fine. + +- The vendor bios write protects the flash so it requires external + flashing to install libreboot on this device. Once libreboot is + flashed there is no problem to update the firmware internally + +Here is an image of the board:\ +![](https://av.libreboot.org/d945gclf/d945gclf.jpg)\ +Here is an image of the D945GCLF2 board:\ +![](https://av.libreboot.org/d945gclf/20160923_141521.jpg){width="80%" height="80%"}\ +And SPI SOIC8 flash chip\ +![](https://av.libreboot.org/d945gclf/20160923_141550.jpg){width="50%" height="50%"} + +How to replace thermal paste and fan +------------------------------------ + +This board comes with very crappy disposable loud fan, that one has no +bearings, which can not be repaired or oiled properly, do not waste your +time trying to fix it, just buy one chinese same size fan\ +![](https://av.libreboot.org/d945gclf/20160923_141620.jpg){width="50%" height="50%"} +![](https://av.libreboot.org/d945gclf/20160923_141614.jpg){width="50%" height="50%"}\ +Make sure that new one has same wiring\ +![](https://av.libreboot.org/d945gclf/20160923_142618.jpg){width="50%" height="50%"}\ +This is a new one, with bearing and maintenable\ +![](https://av.libreboot.org/d945gclf/20160923_141738.jpg){width="50%" height="50%"} +![](https://av.libreboot.org/d945gclf/20160923_141814.jpg){width="50%" height="50%"}\ +Now remove the both coolers rotating them a bit, slowly, then clean both +silicons and both coolers (removing cmos battery first is recommended)\ +![](https://av.libreboot.org/d945gclf/20160923_141601.jpg){width="50%" height="50%"}\ +Put a little bit of non conductive thermal paste on both silicons (only +cpu silicon iis shown on that image)\ +![](https://av.libreboot.org/d945gclf/20160923_142031.jpg){width="50%" height="50%"}\ + +Before assembling new fan, some need new longer screws, make sure having +these (on the left is original one, too short for new fan)\ +![](https://av.libreboot.org/d945gclf/20160923_141659.jpg){width="50%" height="50%"}\ +After that, assemble your new fan into CPU cooler\ +![](https://av.libreboot.org/d945gclf/20160923_141635.jpg){width="50%" height="50%"}\ +Finally assemle both coolers on both chips, do not forget put in the CPU +fan connector back, and you are done. diff --git a/site/docs/hardware/e6400.md b/site/docs/hardware/e6400.md new file mode 100644 index 0000000..fc047b2 --- /dev/null +++ b/site/docs/hardware/e6400.md @@ -0,0 +1,116 @@ +--- +title: Dell Latitude E6400 +x-toc-enable: true +... + +
+
+Dell Latitude E6400 Dell Latitude E6400 XFR +
+ +| ***Specifications*** | | +|----------------------------|------------------------------------------------| +| **Manufacturer** | Dell | +| **Name** | Latitude E6400 | +| **Variants** | E6400, E6400 XFR and E6400 ATG are supported | +| **Released** | 2009 | +| **Chipset** | Intel Cantiga GM45(Intel GPU) | +| **CPU** | Intel Core 2 Duo (Penryn family). A Quad-core + mod exists, replacing the Core 2 Duo with a Core Quad | +| **Graphics** | Intel GMA 4500MHD | +| **Display** | 1280x800/1440x900 TFT | +| **Memory** | 2 or 4GB (Upgradable to 8GB) | +| **Architecture** | x86_64 | +| **EC** | SMSC MEC5035 with proprietary firmware | +| **Original boot firmware** | Dell BIOS | +| **Intel ME/AMD PSP** | Present. Can be completely disabled. | +| **Flash chip** | SOIC-8 4MiB or 2MiB+4MiB | + + +``` +W+: Works without blobs; +N: Doesn't work; +W*: Works with blobs; +U: Untested; +P+: Partially works; +P*: Partially works with blobs +``` + +| ***Features*** | | +|---------------------------------------------------|----| +| **Internal flashing with original boot firmware** | W+ | +| **Display (Intel GPU)** | W+ | +| **Audio** | W+ | +| **RAM Init** | W+ | +| **External output** | W+ | +| **Display brightness** | P+ | + +| ***Payloads supported*** | | +|---------------------------|-----------| +| **GRUB** | Works | +| **SeaBIOS** | Works | +| **SeaBIOS with GRUB** | Works | +
+Introduction +============ + +Known supported variants: E6400, E6400 XFR and E6400 ATG. + +ONLY the Intel GPU variants are supported, at present. The Nvidia ones are +not compatible, with this censored version of Libreboot. + +**To install Libreboot, see: [E6400 installation +instructions](../install/e6400.md)** + +ROM images for Dell Latitude E6400 are available for flashing in Libreboot +releases, or you can compile a ROM image for installation via +lbmk, see: [build instructions](../build/) + +There are two possible flash chip sizes for the E6400: 4MiB (32Mbit) or 2+4MiB +(16Mbit+32MBit). Libreboot presently supports the 4MiB version, and provides +8MiB images for those who upgrade their flash to 8MiB or 16MiB. There appears +to be several possible mainboard PCBs for the E6400, which we believe mostly +affects the GPU configuration and the number of available SPI flash footprints: + +- LA-3801P: iGPU, possibly dual SPI (however only one may be populated) +- LA-3803P: dGPU, dual SPI (however only one may be populated) +- LA-3805P: iGPU, single SPI flash (4MiB) +- LA-3806P: dGPU, unknown SPI configuration (likely at least 4MiB) + +These PCB numbers can be found either under the black plastic in the RAM slots +on the bottom (CPU side) of the board, the top left corner near the VGA port +(top side, under the keyboard and palmrest), or near the CPU backplate (only +requires removal of the keyboard). + +We believe that all boards will have at least a single 4MiB flash chip, +regardless of the number of SPI footprints. This is likely the most common +configuration on most available systems. The 2+4MiB configuration likely +would have only been used on systems with full Intel ME firmware with AMT +functionality, though this configuration has not yet been encountered. + +Most people will want to use the 4MiB images. + +Intel GPU: Blob-free setup (no-ME possible) +--------------- + +This is a GM45/PM45 platform, so completely libre initialisation in +coreboot is possible, provided by default in Libreboot. + +Intel GPU variants are GM45, and Nvidia ones are PM45. + +Management Engine (ME) firmware removed +------------------------- + +This port in Libreboot makes use of `ich9gen` from ich9utils, which +you can read about in the [ich9utils manual](../install/ich9utils.md) - this +creates a no-ME setup. The Intel Management Engine firmware (ME) is completely +removed, and the ME disabled, just like on ThinkPad X200, T400 and so on. + +*The E6400 laptops may come with the ME (and sometimes AMT in addition) before +flashing libreboot. Dell also sold configurations with the ME completely +disabled, identifiable by a yellow sticker reading "3 ME Disabled" inside the +bottom panel. This config sets the MeDisable bit in the IFD and sets the ME +region almost entirely to 1's, with the occasional 32-bit value (likely not +executable). libreboot disables and removes it by using a modified descriptor: +see [../install/ich9utils.md](../install/ich9utils.md)* +(contains notes, plus instructions) diff --git a/site/docs/hardware/ga-g41m-es2l.md b/site/docs/hardware/ga-g41m-es2l.md new file mode 100644 index 0000000..bcd4c5a --- /dev/null +++ b/site/docs/hardware/ga-g41m-es2l.md @@ -0,0 +1,104 @@ +--- +title: Gigabyte GA-G41M-ES2L desktop board +... + +
+
+![GA-G41M-ES2L]() +
+ +| ***Specifications*** | | +|----------------------------|------------------------------------------------| +| **Manufacturer** | Gigabyte | +| **Name** | GA-G41M-ES2L | +| **Released** | 2009 | +| **Chipset** | Intel G41 | +| **CPU** | Intel Core 2 Extreme/Quad/Duo, + Pentium Extreme/D/4 Extreme/4/Celeron | +| **Graphics** | Integrated | +| **Display** | None. | +| **Memory** | Up to 16GB | +| **Architecture** | x86_64 | +| **Original boot firmware** | AWARD BIOS | +| **Intel ME/AMD PSP** | Present. Can be disabled | +| **Flash chip** | 2x8Mbit | + +``` +W+: Works without blobs; +N: Doesn't work; +W*: Works with blobs; +U: Untested; +P+: Partially works; +P*: Partially works with blobs +``` + +| ***Features*** | | +|----------------|---------------------------------------| +| **Internal flashing with original boot firmware** | W+ | +| **Display** | - | +| **Audio** | W+ | +| **RAM Init** | P+ | +| **External output** | P+ | +| **Display brightness** | - | + +| ***Payloads supported*** | | +|---------------------------|-------| +| **GRUB** | Slow! | +| **SeaBIOS** | Works | +| **SeaBIOS with GRUB** | Works | +
+This is a desktop board using intel hardware (circa \~2009, ICH7 +southbridge, similar performance-wise to the ThinkPad X200. It can make +for quite a nifty desktop. Powered by libreboot. + +In recent Libreboot releases, only SeaBIOS payload is provided in ROMs +for this board. According to user reports, they work quite well. GRUB was +always buggy on this board, so it was removed from lbmk. + +IDE on the board is untested, but it might be possible to use a SATA HDD +using an IDE SATA adapter. The SATA ports do work, but it's IDE emulation. The +emulation is slow in DMA mode sia SeaBIOS, so SeaBIOS is configured to use PIO +mode on this board. This SeaBIOS configuration does not affect the Linux kernel. + +You need to set a custom MAC address in Linux for the NIC to work. +In /etc/network/interfaces on debian-based systems like Debian or +Devuan, this would be in the entry for your NIC:\ +hwaddress ether macaddressgoeshere + +Alternatively: + + cbfstool libreboot.rom extract -n rt8168-macaddress -f rt8168-macaddress + +Modify the MAC address in the file `rt8168-macaddress` and then: + + cbfstool libreboot.rom remove -n rt8168-macaddress + cbfstool libreboot.rom add -f rt8168-macaddress -n rt8168-macaddress -t raw + +Now you have a different MAC address hardcoded. In the above example, the ROM +image is named `libreboot.rom` for your board. You can find cbfstool +under `coreboot/default/util/cbfstool/` after running the following command +in the build system: + + ./build module cbutils + +You can learn more about using the build system, lbmk, here:\ +[libreboot build instructions](../build/) + +Flashing instructions can be found at +[../install/](../install/) + +RAM +--- + +**This board is very picky with RAM. If it doesn't boot, try an EHCI debug +dongle, serial usb adapter and null modem cable, or spkmodem, to get a +coreboot log to see if it passed raminit.** + +Kingston 8 GiB Kit KVR800D2N6/8G with Elpida Chips E2108ABSE-8G-E + +this is a 2x4GB setup and these work quite well, according to a user on IRC. + +Nanya NT2GT64U8HD0BY-AD with 2 GiB of NT5TU128M8DE-AD chips works too. + +Many other modules will probably work just fine, but raminit is very picky on +this board. Your mileage *will* fluctuate, wildly. diff --git a/site/docs/hardware/hwdumps/x200/biosdecode.err.log b/site/docs/hardware/hwdumps/x200/biosdecode.err.log new file mode 100644 index 0000000..e69de29 diff --git a/site/docs/hardware/hwdumps/x200/biosdecode.log b/site/docs/hardware/hwdumps/x200/biosdecode.log new file mode 100644 index 0000000..bfeaba3 --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/biosdecode.log @@ -0,0 +1,24 @@ +# biosdecode 2.12 +VPD present. + BIOS Build ID: 6DET65WW + Box Serial Number: L3AAR0B + Motherboard Serial Number: 1ZFDS89N4DD + Machine Type/Model: 7459GW4 +SMBIOS 2.4 present. + Structure Table Length: 2464 bytes + Structure Table Address: 0x000E0010 + Number Of Structures: 68 + Maximum Structure Size: 120 bytes +BIOS32 Service Directory present. + Revision: 0 + Calling Interface Address: 0x000FDC80 +ACPI 2.0 present. + OEM Identifier: LENOVO + RSD Table 32-bit Address: 0x79B5B843 + XSD Table 64-bit Address: 0x0000000079B5B8AB +PNP BIOS 1.0 present. + Event Notification: Not Supported + Real Mode 16-bit Code Address: E2CA:1868 + Real Mode 16-bit Data Address: 0040:0000 + 16-bit Protected Mode Code Address: 0x000F97BD + 16-bit Protected Mode Data Address: 0x00000400 diff --git a/site/docs/hardware/hwdumps/x200/codec#0 b/site/docs/hardware/hwdumps/x200/codec#0 new file mode 100644 index 0000000..2b9d6f3 --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/codec#0 @@ -0,0 +1,208 @@ +Codec: Conexant CX20561 (Hermosa) +Address: 0 +AFG Function Id: 0x1 (unsol 1) +MFG Function Id: 0x2 (unsol 1) +Vendor Id: 0x14f15051 +Subsystem Id: 0x17aa20ff +Revision Id: 0x100000 +Modem Function Group: 0x2 +Default PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM +Default Amp-In caps: N/A +Default Amp-Out caps: N/A +State of AFG node 0x01: + Power states: D0 D1 D2 D3 CLKSTOP + Power: setting=D0, actual=D0 +GPIO: io=4, o=0, i=0, unsolicited=1, wake=0 + IO[0]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[1]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[2]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[3]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 +Node 0x10 [Audio Output] wcaps 0xc1d: Stereo Amp-Out R/L + Control: name="Speaker Playback Volume", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Control: name="Speaker Playback Switch", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Device: name="CX20561 Analog", type="Audio", device=0 + Amp-Out caps: ofs=0x4a, nsteps=0x4a, stepsize=0x03, mute=0 + Amp-Out vals: [0x4a 0x4a] + Converter: stream=8, channel=0 + PCM: + rates [0x560]: 44100 48000 96000 192000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x11 [Audio Output] wcaps 0xc1d: Stereo Amp-Out R/L + Control: name="Headphone Playback Volume", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Control: name="Headphone Playback Switch", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Amp-Out caps: ofs=0x4a, nsteps=0x4a, stepsize=0x03, mute=0 + Amp-Out vals: [0x4a 0x4a] + Converter: stream=8, channel=0 + PCM: + rates [0x560]: 44100 48000 96000 192000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x12 [Audio Output] wcaps 0x211: Stereo Digital + Control: name="IEC958 Playback Con Mask", index=0, device=0 + Control: name="IEC958 Playback Pro Mask", index=0, device=0 + Control: name="IEC958 Playback Default", index=0, device=0 + Control: name="IEC958 Playback Switch", index=0, device=0 + Control: name="IEC958 Default PCM Playback Switch", index=0, device=0 + Device: name="CX20561 Digital", type="SPDIF", device=1 + Converter: stream=8, channel=0 + Digital: + Digital category: 0x0 + IEC Coding Type: 0x0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x5]: PCM AC3 +Node 0x13 [Beep Generator Widget] wcaps 0x70000c: Mono Amp-Out + Control: name="Beep Playback Volume", index=0, device=0 + ControlAmp: chs=1, dir=Out, idx=0, ofs=0 + Control: name="Beep Playback Switch", index=0, device=0 + ControlAmp: chs=1, dir=Out, idx=0, ofs=0 + Amp-Out caps: ofs=0x03, nsteps=0x03, stepsize=0x17, mute=0 + Amp-Out vals: [0x00] +Node 0x14 [Audio Input] wcaps 0x100d1b: Stereo Amp-In R/L + Device: name="CX20561 Analog", type="Audio", device=0 + Amp-In caps: ofs=0x4a, nsteps=0x50, stepsize=0x03, mute=0 + Amp-In vals: [0x50 0x50] [0x50 0x50] + Converter: stream=4, channel=0 + SDI-Select: 0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x1d* 0x17 +Node 0x15 [Audio Input] wcaps 0x100d1b: Stereo Amp-In R/L + Control: name="Capture Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=1, ofs=0 + Amp-In caps: ofs=0x4a, nsteps=0x50, stepsize=0x03, mute=0 + Amp-In vals: [0x50 0x50] + Converter: stream=0, channel=0 + SDI-Select: 0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 1 + 0x18 +Node 0x16 [Pin Complex] wcaps 0x400581: Stereo + Control: name="Headphone Jack", index=0, device=0 + Pincap 0x0000001c: OUT HP Detect + Pin Default 0x042140f0: [Jack] HP Out at Ext Right + Conn = 1/8, Color = Green + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0xc0: OUT HP + Unsolicited: tag=02, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10 0x11* +Node 0x17 [Pin Complex] wcaps 0x40048b: Stereo Amp-In + Control: name="Dock Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Dock Mic Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x27, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00001224: IN Detect + Vref caps: 50 80 + Pin Default 0x61a190f0: [N/A] Mic at Sep Rear + Conn = 1/8, Color = Pink + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x24: IN VREF_80 + Unsolicited: tag=03, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x18 [Pin Complex] wcaps 0x40048b: Stereo Amp-In + Control: name="Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Mic Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x27, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00001224: IN Detect + Vref caps: 50 80 + Pin Default 0x04a190f0: [Jack] Mic at Ext Right + Conn = 1/8, Color = Pink + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x24: IN VREF_80 + Unsolicited: tag=04, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x19 [Pin Complex] wcaps 0x400581: Stereo + Control: name="Dock Headphone Jack", index=0, device=0 + Pincap 0x00000014: OUT Detect + Pin Default 0x612140f0: [N/A] HP Out at Sep Rear + Conn = 1/8, Color = Green + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x40: OUT + Unsolicited: tag=01, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10 0x11* +Node 0x1a [Pin Complex] wcaps 0x400501: Stereo + Control: name="Speaker Phantom Jack", index=0, device=0 + Pincap 0x00010010: OUT EAPD + EAPD 0x2: EAPD + Pin Default 0x901701f0: [Fixed] Speaker at Int N/A + Conn = Analog, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10* 0x11 +Node 0x1b [Pin Complex] wcaps 0x400500: Mono + Pincap 0x00010010: OUT EAPD + EAPD 0x2: EAPD + Pin Default 0x40f001f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10* 0x11 +Node 0x1c [Pin Complex] wcaps 0x400701: Stereo Digital + Control: name="SPDIF Phantom Jack", index=0, device=0 + Pincap 0x00000010: OUT + Pin Default 0x40f001f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 1 + 0x12 +Node 0x1d [Pin Complex] wcaps 0x40040b: Stereo Amp-In + Control: name="Internal Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Internal Mic Phantom Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x2f, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00000020: IN + Pin Default 0x90a601f0: [Fixed] Mic at Int N/A + Conn = Digital, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x20: IN + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x1e [Vendor Defined Widget] wcaps 0xf00000: Mono diff --git a/site/docs/hardware/hwdumps/x200/cpuinfo.err.log b/site/docs/hardware/hwdumps/x200/cpuinfo.err.log new file mode 100644 index 0000000..e69de29 diff --git a/site/docs/hardware/hwdumps/x200/cpuinfo.log b/site/docs/hardware/hwdumps/x200/cpuinfo.log new file mode 100644 index 0000000..8b01059 --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/cpuinfo.log @@ -0,0 +1,52 @@ +processor : 0 +vendor_id : GenuineIntel +cpu family : 6 +model : 23 +model name : Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz +stepping : 6 +microcode : 0x60c +cpu MHz : 800.000 +cache size : 3072 KB +physical id : 0 +siblings : 2 +core id : 0 +cpu cores : 2 +apicid : 0 +initial apicid : 0 +fpu : yes +fpu_exception : yes +cpuid level : 10 +wp : yes +flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts nopl aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 lahf_lm dtherm tpr_shadow vnmi flexpriority +bogomips : 4787.97 +clflush size : 64 +cache_alignment : 64 +address sizes : 36 bits physical, 48 bits virtual +power management: + +processor : 1 +vendor_id : GenuineIntel +cpu family : 6 +model : 23 +model name : Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz +stepping : 6 +microcode : 0x60c +cpu MHz : 1600.000 +cache size : 3072 KB +physical id : 0 +siblings : 2 +core id : 1 +cpu cores : 2 +apicid : 1 +initial apicid : 1 +fpu : yes +fpu_exception : yes +cpuid level : 10 +wp : yes +flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts nopl aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 lahf_lm dtherm tpr_shadow vnmi flexpriority +bogomips : 4787.97 +clflush size : 64 +cache_alignment : 64 +address sizes : 36 bits physical, 48 bits virtual +power management: + diff --git a/site/docs/hardware/hwdumps/x200/dmesg.err.log b/site/docs/hardware/hwdumps/x200/dmesg.err.log new file mode 100644 index 0000000..e69de29 diff --git a/site/docs/hardware/hwdumps/x200/dmesg.log b/site/docs/hardware/hwdumps/x200/dmesg.log new file mode 100644 index 0000000..64eb580 --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/dmesg.log @@ -0,0 +1,1066 @@ +[ 0.000000] Initializing cgroup subsys cpuset +[ 0.000000] Initializing cgroup subsys cpu +[ 0.000000] Initializing cgroup subsys cpuacct +[ 0.000000] Linux version 3.13.0-39-lowlatency (root@devel.trisquel.info) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #66+7.0trisquel2 SMP PREEMPT Wed Oct 29 17:10:10 UTC 2014 (Ubuntu 3.13.0-39.66+7.0trisquel2-lowlatency 3.13.11.8-gnu) +[ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-3.13.0-39-lowlatency root=UUID=097336a2-7389-4897-a7e8-1f43e91aae96 ro nomdmonddf nomdmonisw nomdmonddf nomdmonisw +[ 0.000000] KERNEL supported cpus: +[ 0.000000] Intel GenuineIntel +[ 0.000000] AMD AuthenticAMD +[ 0.000000] Centaur CentaurHauls +[ 0.000000] Disabled fast string operations +[ 0.000000] e820: BIOS-provided physical RAM map: +[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009ebff] usable +[ 0.000000] BIOS-e820: [mem 0x000000000009ec00-0x000000000009ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved +[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000796a0fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000796a1000-0x00000000796a6fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000796a7000-0x00000000797b6fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000797b7000-0x000000007980efff] reserved +[ 0.000000] BIOS-e820: [mem 0x000000007980f000-0x00000000798c6fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000798c7000-0x00000000798d1fff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000798d2000-0x00000000798d4fff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x00000000798d5000-0x00000000798d8fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000798d9000-0x00000000798dcfff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000798dd000-0x00000000798dffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000798e0000-0x0000000079906fff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x0000000079907000-0x0000000079907fff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x0000000079908000-0x0000000079b0efff] reserved +[ 0.000000] BIOS-e820: [mem 0x0000000079b0f000-0x0000000079b9efff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x0000000079b9f000-0x0000000079bfefff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x0000000079bff000-0x0000000079bfffff] usable +[ 0.000000] BIOS-e820: [mem 0x0000000079c00000-0x000000007bffffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec0ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed003ff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed10000-0x00000000fed13fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed18000-0x00000000fed19fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed8ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000ff800000-0x00000000ffffffff] reserved +[ 0.000000] NX (Execute Disable) protection: active +[ 0.000000] SMBIOS 2.4 present. +[ 0.000000] DMI: LENOVO 7459GW4/7459GW4, BIOS 6DET65WW (3.15 ) 08/24/2010 +[ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved +[ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable +[ 0.000000] No AGP bridge found +[ 0.000000] e820: last_pfn = 0x79c00 max_arch_pfn = 0x400000000 +[ 0.000000] MTRR default type: uncachable +[ 0.000000] MTRR fixed ranges enabled: +[ 0.000000] 00000-9FFFF write-back +[ 0.000000] A0000-BFFFF uncachable +[ 0.000000] C0000-D3FFF write-protect +[ 0.000000] D4000-DBFFF uncachable +[ 0.000000] DC000-FFFFF write-protect +[ 0.000000] MTRR variable ranges enabled: +[ 0.000000] 0 base 07D000000 mask FFF000000 uncachable +[ 0.000000] 1 base 07E000000 mask FFE000000 uncachable +[ 0.000000] 2 base 000000000 mask F80000000 write-back +[ 0.000000] 3 base 079E00000 mask FFFE00000 uncachable +[ 0.000000] 4 disabled +[ 0.000000] 5 disabled +[ 0.000000] 6 disabled +[ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 +[ 0.000000] original variable MTRRs +[ 0.000000] reg 0, base: 2000MB, range: 16MB, type UC +[ 0.000000] reg 1, base: 2016MB, range: 32MB, type UC +[ 0.000000] reg 2, base: 0GB, range: 2GB, type WB +[ 0.000000] reg 3, base: 1950MB, range: 2MB, type UC +[ 0.000000] total RAM covered: 1998M +[ 0.000000] gran_size: 64K chunk_size: 64K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 128K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 256K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 512K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 1M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 2M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 4M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 64K chunk_size: 8M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 64K chunk_size: 16M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 64K chunk_size: 32M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 64K chunk_size: 64M num_reg: 7 lose cover RAM: 0G +[ 0.000000] gran_size: 64K chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 128K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 256K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 512K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 1M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 2M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 4M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 128K chunk_size: 8M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 128K chunk_size: 16M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 128K chunk_size: 32M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 128K chunk_size: 64M num_reg: 7 lose cover RAM: 0G +[ 0.000000] gran_size: 128K chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 256K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 512K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 1M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 2M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 4M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 256K chunk_size: 8M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 256K chunk_size: 16M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 256K chunk_size: 32M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 256K chunk_size: 64M num_reg: 7 lose cover RAM: 0G +[ 0.000000] gran_size: 256K chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 512K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 1M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 2M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 4M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 512K chunk_size: 8M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 512K chunk_size: 16M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 512K chunk_size: 32M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 512K chunk_size: 64M num_reg: 7 lose cover RAM: 0G +[ 0.000000] gran_size: 512K chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 1M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 2M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 4M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 1M chunk_size: 8M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 1M chunk_size: 16M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 1M chunk_size: 32M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 1M chunk_size: 64M num_reg: 7 lose cover RAM: 0G +[ 0.000000] gran_size: 1M chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 2M chunk_size: 2M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 2M chunk_size: 4M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 2M chunk_size: 8M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 2M chunk_size: 16M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 2M chunk_size: 32M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 2M chunk_size: 64M num_reg: 7 lose cover RAM: 0G +[ 0.000000] gran_size: 2M chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 2M chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 2M chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 2M chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 2M chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 4M chunk_size: 4M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 4M chunk_size: 8M num_reg: 7 lose cover RAM: 18M +[ 0.000000] gran_size: 4M chunk_size: 16M num_reg: 7 lose cover RAM: 18M +[ 0.000000] gran_size: 4M chunk_size: 32M num_reg: 7 lose cover RAM: 18M +[ 0.000000] gran_size: 4M chunk_size: 64M num_reg: 7 lose cover RAM: 2M +[ 0.000000] gran_size: 4M chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 4M chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 4M chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 4M chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 4M chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 8M chunk_size: 8M num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 16M num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 32M num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 64M num_reg: 7 lose cover RAM: 6M +[ 0.000000] gran_size: 8M chunk_size: 128M num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 256M num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 512M num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 1G num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 2G num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 16M chunk_size: 16M num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 16M chunk_size: 32M num_reg: 7 lose cover RAM: 30M +[ 0.000000] gran_size: 16M chunk_size: 64M num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 16M chunk_size: 128M num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 16M chunk_size: 256M num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 16M chunk_size: 512M num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 16M chunk_size: 1G num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 16M chunk_size: 2G num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 32M chunk_size: 32M num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 32M chunk_size: 64M num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 32M chunk_size: 128M num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 32M chunk_size: 256M num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 32M chunk_size: 512M num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 32M chunk_size: 1G num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 32M chunk_size: 2G num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 64M chunk_size: 64M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 64M chunk_size: 128M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 64M chunk_size: 256M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 64M chunk_size: 512M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 64M chunk_size: 1G num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 64M chunk_size: 2G num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 128M chunk_size: 128M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 128M chunk_size: 256M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 128M chunk_size: 512M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 128M chunk_size: 1G num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 128M chunk_size: 2G num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 256M chunk_size: 256M num_reg: 3 lose cover RAM: 206M +[ 0.000000] gran_size: 256M chunk_size: 512M num_reg: 3 lose cover RAM: 206M +[ 0.000000] gran_size: 256M chunk_size: 1G num_reg: 3 lose cover RAM: 206M +[ 0.000000] gran_size: 256M chunk_size: 2G num_reg: 3 lose cover RAM: 206M +[ 0.000000] gran_size: 512M chunk_size: 512M num_reg: 2 lose cover RAM: 462M +[ 0.000000] gran_size: 512M chunk_size: 1G num_reg: 2 lose cover RAM: 462M +[ 0.000000] gran_size: 512M chunk_size: 2G num_reg: 2 lose cover RAM: 462M +[ 0.000000] gran_size: 1G chunk_size: 1G num_reg: 1 lose cover RAM: 974M +[ 0.000000] gran_size: 1G chunk_size: 2G num_reg: 1 lose cover RAM: 974M +[ 0.000000] gran_size: 2G chunk_size: 2G num_reg: 0 lose cover RAM: 1998M +[ 0.000000] mtrr_cleanup: can not find optimal value +[ 0.000000] please specify mtrr_gran_size/mtrr_chunk_size +[ 0.000000] e820: update [mem 0x79e00000-0x79ffffff] usable ==> reserved +[ 0.000000] found SMP MP-table at [mem 0x000f72d0-0x000f72df] mapped at [ffff8800000f72d0] +[ 0.000000] Scanning 1 areas for low memory corruption +[ 0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576 +[ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff] +[ 0.000000] [mem 0x00000000-0x000fffff] page 4k +[ 0.000000] BRK [0x01fd9000, 0x01fd9fff] PGTABLE +[ 0.000000] BRK [0x01fda000, 0x01fdafff] PGTABLE +[ 0.000000] BRK [0x01fdb000, 0x01fdbfff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0x79400000-0x795fffff] +[ 0.000000] [mem 0x79400000-0x795fffff] page 2M +[ 0.000000] BRK [0x01fdc000, 0x01fdcfff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0x78000000-0x793fffff] +[ 0.000000] [mem 0x78000000-0x793fffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x00100000-0x77ffffff] +[ 0.000000] [mem 0x00100000-0x001fffff] page 4k +[ 0.000000] [mem 0x00200000-0x77ffffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x79600000-0x796a0fff] +[ 0.000000] [mem 0x79600000-0x796a0fff] page 4k +[ 0.000000] BRK [0x01fdd000, 0x01fddfff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0x796a7000-0x797b6fff] +[ 0.000000] [mem 0x796a7000-0x797b6fff] page 4k +[ 0.000000] init_memory_mapping: [mem 0x7980f000-0x798c6fff] +[ 0.000000] [mem 0x7980f000-0x798c6fff] page 4k +[ 0.000000] BRK [0x01fde000, 0x01fdefff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0x79bff000-0x79bfffff] +[ 0.000000] [mem 0x79bff000-0x79bfffff] page 4k +[ 0.000000] RAMDISK: [mem 0x35314000-0x36981fff] +[ 0.000000] ACPI: RSDP 00000000000f7290 000024 (v02 LENOVO) +[ 0.000000] ACPI: XSDT 0000000079b5b8ab 00008C (v01 LENOVO TP-6D 00003150 LTP 00000000) +[ 0.000000] ACPI: FACP 0000000079b5ba00 0000F4 (v03 LENOVO TP-6D 00003150 LNVO 00000001) +[ 0.000000] ACPI: DSDT 0000000079b5bdf4 00DF28 (v01 LENOVO TP-6D 00003150 MSFT 03000000) +[ 0.000000] ACPI: FACS 0000000079b8e000 000040 +[ 0.000000] ACPI: SSDT 0000000079b5bbb4 000240 (v01 LENOVO TP-6D 00003150 MSFT 03000000) +[ 0.000000] ACPI: ECDT 0000000079b69d1c 000052 (v01 LENOVO TP-6D 00003150 LNVO 00000001) +[ 0.000000] ACPI: APIC 0000000079b69d6e 000078 (v01 LENOVO TP-6D 00003150 LNVO 00000001) +[ 0.000000] ACPI: MCFG 0000000079b69de6 00003C (v01 LENOVO TP-6D 00003150 LNVO 00000001) +[ 0.000000] ACPI: HPET 0000000079b69e22 000038 (v01 LENOVO TP-6D 00003150 LNVO 00000001) +[ 0.000000] ACPI: BOOT 0000000079b69f38 000028 (v01 LENOVO TP-6D 00003150 LTP 00000001) +[ 0.000000] ACPI: ASF! 0000000079b69f60 0000A0 (v16 LENOVO TP-6D 00003150 PTL 00000001) +[ 0.000000] ACPI: SSDT 0000000079b8d1ea 000578 (v01 LENOVO TP-6D 00003150 INTL 20050513) +[ 0.000000] ACPI: TCPA 0000000079907000 000032 (v00 00000000 00000000) +[ 0.000000] ACPI: SSDT 00000000798d4000 000655 (v01 PmRef CpuPm 00003000 INTL 20050624) +[ 0.000000] ACPI: SSDT 00000000798d3000 000274 (v01 PmRef Cpu0Tst 00003000 INTL 20050624) +[ 0.000000] ACPI: SSDT 00000000798d2000 000242 (v01 PmRef ApTst 00003000 INTL 20050624) +[ 0.000000] ACPI: Local APIC address 0xfee00000 +[ 0.000000] No NUMA configuration found +[ 0.000000] Faking a node at [mem 0x0000000000000000-0x0000000079bfffff] +[ 0.000000] Initmem setup node 0 [mem 0x00000000-0x79bfffff] +[ 0.000000] NODE_DATA [mem 0x798c1000-0x798c5fff] +[ 0.000000] [ffffea0000000000-ffffea0001ffffff] PMD -> [ffff880076e00000-ffff880078dfffff] on node 0 +[ 0.000000] Zone ranges: +[ 0.000000] DMA [mem 0x00001000-0x00ffffff] +[ 0.000000] DMA32 [mem 0x01000000-0xffffffff] +[ 0.000000] Normal empty +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x00001000-0x0009dfff] +[ 0.000000] node 0: [mem 0x00100000-0x796a0fff] +[ 0.000000] node 0: [mem 0x796a7000-0x797b6fff] +[ 0.000000] node 0: [mem 0x7980f000-0x798c6fff] +[ 0.000000] node 0: [mem 0x79bff000-0x79bfffff] +[ 0.000000] On node 0 totalpages: 497671 +[ 0.000000] DMA zone: 64 pages used for memmap +[ 0.000000] DMA zone: 21 pages reserved +[ 0.000000] DMA zone: 3997 pages, LIFO batch:0 +[ 0.000000] DMA32 zone: 7728 pages used for memmap +[ 0.000000] DMA32 zone: 493674 pages, LIFO batch:31 +[ 0.000000] ACPI: PM-Timer IO Port: 0x1008 +[ 0.000000] ACPI: Local APIC address 0xfee00000 +[ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] disabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x03] disabled) +[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1]) +[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) +[ 0.000000] ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0]) +[ 0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23 +[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) +[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) +[ 0.000000] ACPI: IRQ0 used by override. +[ 0.000000] ACPI: IRQ2 used by override. +[ 0.000000] ACPI: IRQ9 used by override. +[ 0.000000] Using ACPI (MADT) for SMP configuration information +[ 0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000 +[ 0.000000] smpboot: Allowing 4 CPUs, 2 hotplug CPUs +[ 0.000000] nr_irqs_gsi: 40 +[ 0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x0009efff] +[ 0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff] +[ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000dbfff] +[ 0.000000] PM: Registered nosave memory: [mem 0x000dc000-0x000fffff] +[ 0.000000] PM: Registered nosave memory: [mem 0x796a1000-0x796a6fff] +[ 0.000000] PM: Registered nosave memory: [mem 0x797b7000-0x7980efff] +[ 0.000000] PM: Registered nosave memory: [mem 0x798c7000-0x798d1fff] +[ 0.000000] PM: Registered nosave memory: [mem 0x798d2000-0x798d4fff] +[ 0.000000] PM: Registered nosave memory: [mem 0x798d5000-0x798d8fff] +[ 0.000000] PM: Registered nosave memory: [mem 0x798d9000-0x798dcfff] +[ 0.000000] PM: Registered nosave memory: [mem 0x798dd000-0x798dffff] +[ 0.000000] PM: Registered nosave memory: [mem 0x798e0000-0x79906fff] +[ 0.000000] PM: Registered nosave memory: [mem 0x79907000-0x79907fff] +[ 0.000000] PM: Registered nosave memory: [mem 0x79908000-0x79b0efff] +[ 0.000000] PM: Registered nosave memory: [mem 0x79b0f000-0x79b9efff] +[ 0.000000] PM: Registered nosave memory: [mem 0x79b9f000-0x79bfefff] +[ 0.000000] e820: [mem 0x7c000000-0xdfffffff] available for PCI devices +[ 0.000000] Booting paravirtualized kernel on bare hardware +[ 0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:4 nr_node_ids:1 +[ 0.000000] PERCPU: Embedded 29 pages/cpu @ffff880079400000 s86848 r8192 d23744 u524288 +[ 0.000000] pcpu-alloc: s86848 r8192 d23744 u524288 alloc=1*2097152 +[ 0.000000] pcpu-alloc: [0] 0 1 2 3 +[ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 489858 +[ 0.000000] Policy zone: DMA32 +[ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-3.13.0-39-lowlatency root=UUID=097336a2-7389-4897-a7e8-1f43e91aae96 ro nomdmonddf nomdmonisw nomdmonddf nomdmonisw +[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) +[ 0.000000] Checking aperture... +[ 0.000000] No AGP bridge found +[ 0.000000] Calgary: detecting Calgary via BIOS EBDA area +[ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing! +[ 0.000000] Memory: 1917872K/1990684K available (7418K kernel code, 1135K rwdata, 3420K rodata, 1324K init, 1444K bss, 72812K reserved) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 +[ 0.000000] Preemptible hierarchical RCU implementation. +[ 0.000000] RCU dyntick-idle grace-period acceleration is enabled. +[ 0.000000] Dump stacks of tasks blocking RCU-preempt GP. +[ 0.000000] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=4. +[ 0.000000] Offload RCU callbacks from all CPUs +[ 0.000000] Offload RCU callbacks from CPUs: 0-3. +[ 0.000000] NR_IRQS:16640 nr_irqs:712 16 +[ 0.000000] Console: colour VGA+ 80x25 +[ 0.000000] console [tty0] enabled +[ 0.000000] allocated 8388608 bytes of page_cgroup +[ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups +[ 0.000000] hpet clockevent registered +[ 0.000000] tsc: Fast TSC calibration using PIT +[ 0.000000] tsc: Detected 2393.987 MHz processor +[ 0.001004] Calibrating delay loop (skipped), value calculated using timer frequency.. 4787.97 BogoMIPS (lpj=2393987) +[ 0.001099] pid_max: default: 32768 minimum: 301 +[ 0.001179] Security Framework initialized +[ 0.001251] AppArmor: AppArmor initialized +[ 0.001296] Yama: becoming mindful. +[ 0.001557] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes) +[ 0.002848] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes) +[ 0.003415] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes) +[ 0.003468] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes) +[ 0.003789] Initializing cgroup subsys memory +[ 0.003844] Initializing cgroup subsys devices +[ 0.003891] Initializing cgroup subsys freezer +[ 0.003939] Initializing cgroup subsys blkio +[ 0.003986] Initializing cgroup subsys bfqio +[ 0.004005] Initializing cgroup subsys perf_event +[ 0.004053] Initializing cgroup subsys hugetlb +[ 0.004120] Disabled fast string operations +[ 0.004170] CPU: Physical Processor ID: 0 +[ 0.004216] CPU: Processor Core ID: 0 +[ 0.004262] mce: CPU supports 6 MCE banks +[ 0.004312] CPU0: Thermal monitoring enabled (TM2) +[ 0.004366] Last level iTLB entries: 4KB 128, 2MB 4, 4MB 4 +[ 0.004366] Last level dTLB entries: 4KB 256, 2MB 0, 4MB 32 +[ 0.004366] tlb_flushall_shift: -1 +[ 0.004516] Freeing SMP alternatives memory: 24K (ffffffff81e68000 - ffffffff81e6e000) +[ 0.006138] ACPI: Core revision 20131115 +[ 0.012497] ACPI: All ACPI Tables successfully acquired +[ 0.013011] ftrace: allocating 28647 entries in 112 pages +[ 0.022461] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 +[ 0.032521] smpboot: CPU0: Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz (fam: 06, model: 17, stepping: 06) +[ 0.033000] Performance Events: PEBS fmt0+, 4-deep LBR, Core2 events, Intel PMU driver. +[ 0.033000] ... version: 2 +[ 0.033000] ... bit width: 40 +[ 0.033000] ... generic registers: 2 +[ 0.033000] ... value mask: 000000ffffffffff +[ 0.033000] ... max period: 000000007fffffff +[ 0.033000] ... fixed-purpose events: 3 +[ 0.033000] ... event mask: 0000000700000003 +[ 0.041071] x86: Booting SMP configuration: +[ 0.039030] Disabled fast string operations +[ 0.053119] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter. +[ 0.041119] .... node #0, CPUs: #1 +[ 0.053279] x86: Booted up 1 node, 2 CPUs +[ 0.053366] smpboot: Total of 2 processors activated (9575.94 BogoMIPS) +[ 0.054131] devtmpfs: initialized +[ 0.057653] EVM: security.selinux +[ 0.057699] EVM: security.SMACK64 +[ 0.057744] EVM: security.ima +[ 0.057788] EVM: security.capability +[ 0.058036] PM: Registering ACPI NVS region [mem 0x798c7000-0x798d1fff] (45056 bytes) +[ 0.058098] PM: Registering ACPI NVS region [mem 0x798d9000-0x798dcfff] (16384 bytes) +[ 0.058098] PM: Registering ACPI NVS region [mem 0x798e0000-0x79906fff] (159744 bytes) +[ 0.058098] PM: Registering ACPI NVS region [mem 0x79b0f000-0x79b9efff] (589824 bytes) +[ 0.059097] pinctrl core: initialized pinctrl subsystem +[ 0.059220] regulator-dummy: no parameters +[ 0.059299] RTC time: 6:48:55, date: 08/30/15 +[ 0.059386] NET: Registered protocol family 16 +[ 0.059557] cpuidle: using governor ladder +[ 0.059604] cpuidle: using governor menu +[ 0.059697] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it +[ 0.059758] ACPI: bus type PCI registered +[ 0.059805] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 +[ 0.059912] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) +[ 0.059976] PCI: MMCONFIG at [mem 0xe0000000-0xe3ffffff] reserved in E820 +[ 0.067547] PCI: Using configuration type 1 for base access +[ 0.067698] mtrr: your CPUs had inconsistent variable MTRR settings +[ 0.067747] mtrr: probably your BIOS does not setup all CPUs. +[ 0.067795] mtrr: corrected configuration. +[ 0.069011] bio: create slab at 0 +[ 0.069081] ACPI: Added _OSI(Module Device) +[ 0.069129] ACPI: Added _OSI(Processor Device) +[ 0.069176] ACPI: Added _OSI(3.0 _SCP Extensions) +[ 0.069176] ACPI: Added _OSI(Processor Aggregator Device) +[ 0.071018] ACPI : EC: EC description table is found, configuring boot EC +[ 0.075408] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored +[ 0.082370] ACPI: SSDT 00000000798d7c20 0002C8 (v01 PmRef Cpu0Ist 00003000 INTL 20050624) +[ 0.083085] ACPI: Dynamic OEM Table Load: +[ 0.083193] ACPI: SSDT (null) 0002C8 (v01 PmRef Cpu0Ist 00003000 INTL 20050624) +[ 0.083433] ACPI: SSDT 00000000798d5020 00087A (v01 PmRef Cpu0Cst 00003001 INTL 20050624) +[ 0.083951] ACPI: Dynamic OEM Table Load: +[ 0.084045] ACPI: SSDT (null) 00087A (v01 PmRef Cpu0Cst 00003001 INTL 20050624) +[ 0.087198] ACPI: SSDT 00000000798d6ca0 0001CF (v01 PmRef ApIst 00003000 INTL 20050624) +[ 0.088064] ACPI: Dynamic OEM Table Load: +[ 0.088171] ACPI: SSDT (null) 0001CF (v01 PmRef ApIst 00003000 INTL 20050624) +[ 0.089066] ACPI: SSDT 00000000798d6f20 00008D (v01 PmRef ApCst 00003000 INTL 20050624) +[ 0.089562] ACPI: Dynamic OEM Table Load: +[ 0.090005] ACPI: SSDT (null) 00008D (v01 PmRef ApCst 00003000 INTL 20050624) +[ 0.092138] ACPI: Interpreter enabled +[ 0.092190] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20131115/hwxface-580) +[ 0.092315] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20131115/hwxface-580) +[ 0.092449] ACPI: (supports S0 S3 S4 S5) +[ 0.092496] ACPI: Using IOAPIC for interrupt routing +[ 0.092565] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug +[ 0.093465] ACPI: ACPI Dock Station Driver: 3 docks/bays found +[ 0.103102] ACPI: Power Resource [PUBS] (on) +[ 0.108348] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.108789] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.109225] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.109664] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.110091] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.110528] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.110966] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.111407] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.111809] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) +[ 0.111863] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] +[ 0.112338] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] +[ 0.112429] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge +[ 0.112651] PCI host bridge to bus 0000:00 +[ 0.112699] pci_bus 0000:00: root bus resource [bus 00-ff] +[ 0.112748] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7] +[ 0.112797] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff] +[ 0.112847] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] +[ 0.112897] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff] +[ 0.112947] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff] +[ 0.112997] pci_bus 0000:00: root bus resource [mem 0x7c000000-0xfebfffff] +[ 0.113013] pci 0000:00:00.0: [8086:2a40] type 00 class 0x060000 +[ 0.113033] DMAR: Forcing write-buffer flush capability +[ 0.113081] DMAR: Disabling IOMMU for graphics on this chipset +[ 0.113196] pci 0000:00:02.0: [8086:2a42] type 00 class 0x030000 +[ 0.113209] pci 0000:00:02.0: reg 0x10: [mem 0xf2000000-0xf23fffff 64bit] +[ 0.113216] pci 0000:00:02.0: reg 0x18: [mem 0xd0000000-0xdfffffff 64bit pref] +[ 0.113222] pci 0000:00:02.0: reg 0x20: [io 0x1800-0x1807] +[ 0.113301] pci 0000:00:02.1: [8086:2a43] type 00 class 0x038000 +[ 0.113311] pci 0000:00:02.1: reg 0x10: [mem 0xf2400000-0xf24fffff 64bit] +[ 0.113403] pci 0000:00:03.0: [8086:2a44] type 00 class 0x078000 +[ 0.113419] pci 0000:00:03.0: reg 0x10: [mem 0xf2826800-0xf282680f 64bit] +[ 0.113469] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold +[ 0.113534] pci 0000:00:03.3: [8086:2a47] type 00 class 0x070002 +[ 0.113548] pci 0000:00:03.3: reg 0x10: [io 0x1830-0x1837] +[ 0.113555] pci 0000:00:03.3: reg 0x14: [mem 0xf2624000-0xf2624fff] +[ 0.113704] pci 0000:00:19.0: [8086:10f5] type 00 class 0x020000 +[ 0.113729] pci 0000:00:19.0: reg 0x10: [mem 0xf2600000-0xf261ffff] +[ 0.113740] pci 0000:00:19.0: reg 0x14: [mem 0xf2625000-0xf2625fff] +[ 0.113751] pci 0000:00:19.0: reg 0x18: [io 0x1840-0x185f] +[ 0.113839] pci 0000:00:19.0: PME# supported from D0 D3hot D3cold +[ 0.113882] pci 0000:00:19.0: System wakeup disabled by ACPI +[ 0.114019] pci 0000:00:1a.0: [8086:2937] type 00 class 0x0c0300 +[ 0.114075] pci 0000:00:1a.0: reg 0x20: [io 0x1860-0x187f] +[ 0.114173] pci 0000:00:1a.0: System wakeup disabled by ACPI +[ 0.114259] pci 0000:00:1a.1: [8086:2938] type 00 class 0x0c0300 +[ 0.114315] pci 0000:00:1a.1: reg 0x20: [io 0x1880-0x189f] +[ 0.114427] pci 0000:00:1a.2: [8086:2939] type 00 class 0x0c0300 +[ 0.114483] pci 0000:00:1a.2: reg 0x20: [io 0x18a0-0x18bf] +[ 0.114579] pci 0000:00:1a.2: System wakeup disabled by ACPI +[ 0.114674] pci 0000:00:1a.7: [8086:293c] type 00 class 0x0c0320 +[ 0.114700] pci 0000:00:1a.7: reg 0x10: [mem 0xf2826c00-0xf2826fff] +[ 0.114810] pci 0000:00:1a.7: PME# supported from D0 D3hot D3cold +[ 0.114854] pci 0000:00:1a.7: System wakeup disabled by ACPI +[ 0.114944] pci 0000:00:1b.0: [8086:293e] type 00 class 0x040300 +[ 0.114964] pci 0000:00:1b.0: reg 0x10: [mem 0xf2620000-0xf2623fff 64bit] +[ 0.115066] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold +[ 0.115120] pci 0000:00:1b.0: System wakeup disabled by ACPI +[ 0.115204] pci 0000:00:1c.0: [8086:2940] type 01 class 0x060400 +[ 0.115305] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold +[ 0.115352] pci 0000:00:1c.0: System wakeup disabled by ACPI +[ 0.115436] pci 0000:00:1c.1: [8086:2942] type 01 class 0x060400 +[ 0.115536] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold +[ 0.115584] pci 0000:00:1c.1: System wakeup disabled by ACPI +[ 0.115669] pci 0000:00:1c.3: [8086:2946] type 01 class 0x060400 +[ 0.115769] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold +[ 0.115816] pci 0000:00:1c.3: System wakeup disabled by ACPI +[ 0.115906] pci 0000:00:1d.0: [8086:2934] type 00 class 0x0c0300 +[ 0.115962] pci 0000:00:1d.0: reg 0x20: [io 0x18c0-0x18df] +[ 0.116067] pci 0000:00:1d.0: System wakeup disabled by ACPI +[ 0.116153] pci 0000:00:1d.1: [8086:2935] type 00 class 0x0c0300 +[ 0.116209] pci 0000:00:1d.1: reg 0x20: [io 0x18e0-0x18ff] +[ 0.116320] pci 0000:00:1d.2: [8086:2936] type 00 class 0x0c0300 +[ 0.116376] pci 0000:00:1d.2: reg 0x20: [io 0x1c00-0x1c1f] +[ 0.116498] pci 0000:00:1d.7: [8086:293a] type 00 class 0x0c0320 +[ 0.116523] pci 0000:00:1d.7: reg 0x10: [mem 0xf2827000-0xf28273ff] +[ 0.116632] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold +[ 0.116678] pci 0000:00:1d.7: System wakeup disabled by ACPI +[ 0.116764] pci 0000:00:1e.0: [8086:2448] type 01 class 0x060401 +[ 0.116898] pci 0000:00:1f.0: [8086:2917] type 00 class 0x060100 +[ 0.117115] pci 0000:00:1f.2: [8086:2929] type 00 class 0x010601 +[ 0.117142] pci 0000:00:1f.2: reg 0x10: [io 0x1c48-0x1c4f] +[ 0.117153] pci 0000:00:1f.2: reg 0x14: [io 0x183c-0x183f] +[ 0.117164] pci 0000:00:1f.2: reg 0x18: [io 0x1c40-0x1c47] +[ 0.117175] pci 0000:00:1f.2: reg 0x1c: [io 0x1838-0x183b] +[ 0.117186] pci 0000:00:1f.2: reg 0x20: [io 0x1c20-0x1c3f] +[ 0.117197] pci 0000:00:1f.2: reg 0x24: [mem 0xf2826000-0xf28267ff] +[ 0.117265] pci 0000:00:1f.2: PME# supported from D3hot +[ 0.117338] pci 0000:00:1f.3: [8086:2930] type 00 class 0x0c0500 +[ 0.117359] pci 0000:00:1f.3: reg 0x10: [mem 0xf2827400-0xf28274ff 64bit] +[ 0.117388] pci 0000:00:1f.3: reg 0x20: [io 0x1c60-0x1c7f] +[ 0.117535] pci 0000:00:1c.0: PCI bridge to [bus 02] +[ 0.117690] pci 0000:03:00.0: [8086:4237] type 00 class 0x028000 +[ 0.117730] pci 0000:03:00.0: reg 0x10: [mem 0xf2500000-0xf2501fff 64bit] +[ 0.117924] pci 0000:03:00.0: PME# supported from D0 D3hot D3cold +[ 0.119021] pci 0000:00:1c.1: PCI bridge to [bus 03] +[ 0.119076] pci 0000:00:1c.1: bridge window [mem 0xf2500000-0xf25fffff] +[ 0.119155] pci 0000:00:1c.3: PCI bridge to [bus 05-0c] +[ 0.119207] pci 0000:00:1c.3: bridge window [io 0x2000-0x2fff] +[ 0.119211] pci 0000:00:1c.3: bridge window [mem 0xf0000000-0xf1ffffff] +[ 0.119219] pci 0000:00:1c.3: bridge window [mem 0xf2900000-0xf29fffff 64bit pref] +[ 0.119318] pci 0000:00:1e.0: PCI bridge to [bus 0d] (subtractive decode) +[ 0.119318] pci 0000:00:1e.0: bridge window [io 0x0000-0x0cf7] (subtractive decode) +[ 0.119318] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff] (subtractive decode) +[ 0.119318] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode) +[ 0.119318] pci 0000:00:1e.0: bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode) +[ 0.119318] pci 0000:00:1e.0: bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode) +[ 0.119318] pci 0000:00:1e.0: bridge window [mem 0x7c000000-0xfebfffff] (subtractive decode) +[ 0.119318] acpi PNP0A08:00: Disabling ASPM (FADT indicates it is unsupported) +[ 0.121307] ACPI: Enabled 3 GPEs in block 00 to 3F +[ 0.121425] ACPI: \_SB_.PCI0: notify handler is installed +[ 0.121469] Found 1 acpi root devices +[ 0.121543] ACPI : EC: GPE = 0x11, I/O: command/status = 0x66, data = 0x62 +[ 0.121671] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none +[ 0.121671] vgaarb: loaded +[ 0.121671] vgaarb: bridge control possible 0000:00:02.0 +[ 0.122188] SCSI subsystem initialized +[ 0.122251] libata version 3.00 loaded. +[ 0.122251] ACPI: bus type USB registered +[ 0.122251] usbcore: registered new interface driver usbfs +[ 0.122251] usbcore: registered new interface driver hub +[ 0.122251] usbcore: registered new device driver usb +[ 0.123053] PCI: Using ACPI for IRQ routing +[ 0.125422] PCI: pci_cache_line_size set to 64 bytes +[ 0.125494] e820: reserve RAM buffer [mem 0x0009ec00-0x0009ffff] +[ 0.125496] e820: reserve RAM buffer [mem 0x796a1000-0x7bffffff] +[ 0.125498] e820: reserve RAM buffer [mem 0x797b7000-0x7bffffff] +[ 0.125500] e820: reserve RAM buffer [mem 0x798c7000-0x7bffffff] +[ 0.125503] e820: reserve RAM buffer [mem 0x79c00000-0x7bffffff] +[ 0.125588] NetLabel: Initializing +[ 0.125634] NetLabel: domain hash size = 128 +[ 0.125680] NetLabel: protocols = UNLABELED CIPSOv4 +[ 0.125737] NetLabel: unlabeled traffic allowed by default +[ 0.125795] HPET: 4 timers in total, 0 timers will be used for per-cpu timer +[ 0.125795] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0 +[ 0.126107] hpet0: 4 comparators, 64-bit 14.318180 MHz counter +[ 0.128030] Switched to clocksource hpet +[ 0.134288] AppArmor: AppArmor Filesystem Enabled +[ 0.134388] pnp: PnP ACPI init +[ 0.134450] ACPI: bus type PNP registered +[ 0.154864] system 00:00: [mem 0x00000000-0x0009ffff] could not be reserved +[ 0.154916] system 00:00: [mem 0x000c0000-0x000c3fff] could not be reserved +[ 0.154967] system 00:00: [mem 0x000c4000-0x000c7fff] could not be reserved +[ 0.155029] system 00:00: [mem 0x000c8000-0x000cbfff] has been reserved +[ 0.155080] system 00:00: [mem 0x000cc000-0x000cffff] has been reserved +[ 0.155130] system 00:00: [mem 0x000d0000-0x000d3fff] could not be reserved +[ 0.155181] system 00:00: [mem 0x000dc000-0x000dffff] could not be reserved +[ 0.155231] system 00:00: [mem 0x000e0000-0x000e3fff] could not be reserved +[ 0.155282] system 00:00: [mem 0x000e4000-0x000e7fff] could not be reserved +[ 0.155332] system 00:00: [mem 0x000e8000-0x000ebfff] could not be reserved +[ 0.155383] system 00:00: [mem 0x000ec000-0x000effff] could not be reserved +[ 0.155433] system 00:00: [mem 0x000f0000-0x000fffff] could not be reserved +[ 0.155484] system 00:00: [mem 0x00100000-0x7bffffff] could not be reserved +[ 0.155535] system 00:00: [mem 0xfec00000-0xfed3ffff] could not be reserved +[ 0.155585] system 00:00: [mem 0xfed4c000-0xffffffff] could not be reserved +[ 0.155638] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active) +[ 0.175625] system 00:01: [io 0x1000-0x107f] could not be reserved +[ 0.175676] system 00:01: [io 0x1180-0x11ff] has been reserved +[ 0.175726] system 00:01: [io 0x0800-0x080f] has been reserved +[ 0.175775] system 00:01: [io 0x15e0-0x15ef] has been reserved +[ 0.175825] system 00:01: [io 0x1600-0x167f] has been reserved +[ 0.175874] system 00:01: [io 0x1680-0x169f] has been reserved +[ 0.175923] system 00:01: [mem 0xe0000000-0xefffffff] has been reserved +[ 0.175974] system 00:01: [mem 0xfed1c000-0xfed1ffff] has been reserved +[ 0.176035] system 00:01: [mem 0xfed10000-0xfed13fff] has been reserved +[ 0.176086] system 00:01: [mem 0xfed18000-0xfed18fff] has been reserved +[ 0.176136] system 00:01: [mem 0xfed19000-0xfed19fff] has been reserved +[ 0.176187] system 00:01: [mem 0xfed45000-0xfed4bfff] has been reserved +[ 0.176238] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active) +[ 0.176291] pnp 00:02: Plug and Play ACPI device, IDs PNP0103 (active) +[ 0.176300] pnp 00:03: [dma 4] +[ 0.176318] pnp 00:03: Plug and Play ACPI device, IDs PNP0200 (active) +[ 0.176344] pnp 00:04: Plug and Play ACPI device, IDs PNP0800 (active) +[ 0.176381] pnp 00:05: Plug and Play ACPI device, IDs PNP0c04 (active) +[ 0.176413] pnp 00:06: Plug and Play ACPI device, IDs PNP0b00 (active) +[ 0.176441] pnp 00:07: Plug and Play ACPI device, IDs PNP0303 (active) +[ 0.176472] pnp 00:08: Plug and Play ACPI device, IDs IBM3780 PNP0f13 (active) +[ 0.196442] pnp 00:09: Plug and Play ACPI device, IDs PNP0c31 (active) +[ 0.196872] pnp: PnP ACPI: found 10 devices +[ 0.196919] ACPI: bus type PNP unregistered +[ 0.203744] pci 0000:00:1c.0: bridge window [io 0x1000-0x0fff] to [bus 02] add_size 1000 +[ 0.203748] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 02] add_size 200000 +[ 0.203751] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff] to [bus 02] add_size 200000 +[ 0.203761] pci 0000:00:1c.1: bridge window [io 0x1000-0x0fff] to [bus 03] add_size 1000 +[ 0.203764] pci 0000:00:1c.1: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 03] add_size 200000 +[ 0.203790] pci 0000:00:1c.0: res[14]=[mem 0x00100000-0x000fffff] get_res_add_size add_size 200000 +[ 0.203792] pci 0000:00:1c.0: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000 +[ 0.203794] pci 0000:00:1c.1: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000 +[ 0.203797] pci 0000:00:1c.0: res[13]=[io 0x1000-0x0fff] get_res_add_size add_size 1000 +[ 0.203799] pci 0000:00:1c.1: res[13]=[io 0x1000-0x0fff] get_res_add_size add_size 1000 +[ 0.203803] pci 0000:00:1c.0: BAR 14: assigned [mem 0x7c000000-0x7c1fffff] +[ 0.203855] pci 0000:00:1c.0: BAR 15: assigned [mem 0x7c200000-0x7c3fffff 64bit pref] +[ 0.203917] pci 0000:00:1c.1: BAR 15: assigned [mem 0x7c400000-0x7c5fffff 64bit pref] +[ 0.203979] pci 0000:00:1c.0: BAR 13: assigned [io 0x3000-0x3fff] +[ 0.204040] pci 0000:00:1c.1: BAR 13: assigned [io 0x4000-0x4fff] +[ 0.204091] pci 0000:00:1c.0: PCI bridge to [bus 02] +[ 0.204141] pci 0000:00:1c.0: bridge window [io 0x3000-0x3fff] +[ 0.204194] pci 0000:00:1c.0: bridge window [mem 0x7c000000-0x7c1fffff] +[ 0.204247] pci 0000:00:1c.0: bridge window [mem 0x7c200000-0x7c3fffff 64bit pref] +[ 0.204313] pci 0000:00:1c.1: PCI bridge to [bus 03] +[ 0.204362] pci 0000:00:1c.1: bridge window [io 0x4000-0x4fff] +[ 0.204415] pci 0000:00:1c.1: bridge window [mem 0xf2500000-0xf25fffff] +[ 0.204468] pci 0000:00:1c.1: bridge window [mem 0x7c400000-0x7c5fffff 64bit pref] +[ 0.204534] pci 0000:00:1c.3: PCI bridge to [bus 05-0c] +[ 0.204583] pci 0000:00:1c.3: bridge window [io 0x2000-0x2fff] +[ 0.204636] pci 0000:00:1c.3: bridge window [mem 0xf0000000-0xf1ffffff] +[ 0.204689] pci 0000:00:1c.3: bridge window [mem 0xf2900000-0xf29fffff 64bit pref] +[ 0.204755] pci 0000:00:1e.0: PCI bridge to [bus 0d] +[ 0.204815] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7] +[ 0.204817] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff] +[ 0.204819] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff] +[ 0.204821] pci_bus 0000:00: resource 7 [mem 0x000d4000-0x000d7fff] +[ 0.204823] pci_bus 0000:00: resource 8 [mem 0x000d8000-0x000dbfff] +[ 0.204824] pci_bus 0000:00: resource 9 [mem 0x7c000000-0xfebfffff] +[ 0.204827] pci_bus 0000:02: resource 0 [io 0x3000-0x3fff] +[ 0.204828] pci_bus 0000:02: resource 1 [mem 0x7c000000-0x7c1fffff] +[ 0.204830] pci_bus 0000:02: resource 2 [mem 0x7c200000-0x7c3fffff 64bit pref] +[ 0.204832] pci_bus 0000:03: resource 0 [io 0x4000-0x4fff] +[ 0.204834] pci_bus 0000:03: resource 1 [mem 0xf2500000-0xf25fffff] +[ 0.204836] pci_bus 0000:03: resource 2 [mem 0x7c400000-0x7c5fffff 64bit pref] +[ 0.204838] pci_bus 0000:05: resource 0 [io 0x2000-0x2fff] +[ 0.204840] pci_bus 0000:05: resource 1 [mem 0xf0000000-0xf1ffffff] +[ 0.204842] pci_bus 0000:05: resource 2 [mem 0xf2900000-0xf29fffff 64bit pref] +[ 0.204844] pci_bus 0000:0d: resource 4 [io 0x0000-0x0cf7] +[ 0.204846] pci_bus 0000:0d: resource 5 [io 0x0d00-0xffff] +[ 0.204848] pci_bus 0000:0d: resource 6 [mem 0x000a0000-0x000bffff] +[ 0.204850] pci_bus 0000:0d: resource 7 [mem 0x000d4000-0x000d7fff] +[ 0.204852] pci_bus 0000:0d: resource 8 [mem 0x000d8000-0x000dbfff] +[ 0.204853] pci_bus 0000:0d: resource 9 [mem 0x7c000000-0xfebfffff] +[ 0.204887] NET: Registered protocol family 2 +[ 0.205147] TCP established hash table entries: 16384 (order: 5, 131072 bytes) +[ 0.205279] TCP bind hash table entries: 16384 (order: 6, 262144 bytes) +[ 0.205428] TCP: Hash tables configured (established 16384 bind 16384) +[ 0.205529] TCP: reno registered +[ 0.205578] UDP hash table entries: 1024 (order: 3, 32768 bytes) +[ 0.205641] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes) +[ 0.205757] NET: Registered protocol family 1 +[ 0.205816] pci 0000:00:02.0: Boot video device +[ 0.206766] PCI: CLS 64 bytes, default 64 +[ 0.206828] Trying to unpack rootfs image as initramfs... +[ 0.654139] Freeing initrd memory: 22968K (ffff880035314000 - ffff880036982000) +[ 0.654271] Simple Boot Flag at 0x35 set to 0x1 +[ 0.654472] microcode: CPU0 sig=0x10676, pf=0x80, revision=0x60c +[ 0.654527] microcode: CPU1 sig=0x10676, pf=0x80, revision=0x60c +[ 0.654675] microcode: Microcode Update Driver: v2.00 , Peter Oruba +[ 0.654738] Scanning for low memory corruption every 60 seconds +[ 0.655070] Initialise system trusted keyring +[ 0.655166] audit: initializing netlink socket (disabled) +[ 0.655228] type=2000 audit(1440917335.654:1): initialized +[ 0.677686] HugeTLB registered 2 MB page size, pre-allocated 0 pages +[ 0.678936] zbud: loaded +[ 0.679129] VFS: Disk quotas dquot_6.5.2 +[ 0.679222] Dquot-cache hash table entries: 512 (order 0, 4096 bytes) +[ 0.679760] fuse init (API version 7.22) +[ 0.679888] msgmni has been set to 3790 +[ 0.679992] Key type big_key registered +[ 0.680581] Key type asymmetric registered +[ 0.680630] Asymmetric key parser 'x509' registered +[ 0.680708] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252) +[ 0.680805] io scheduler noop registered +[ 0.680854] io scheduler deadline registered +[ 0.680926] io scheduler cfq registered +[ 0.680975] io scheduler bfq registered (default) +[ 0.681033] BFQ I/O-scheduler version: v7r5 +[ 0.681277] pcieport 0000:00:1c.0: irq 40 for MSI/MSI-X +[ 0.681485] pcieport 0000:00:1c.1: irq 41 for MSI/MSI-X +[ 0.681648] pcieport 0000:00:1c.3: irq 42 for MSI/MSI-X +[ 0.681801] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt +[ 0.681856] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded +[ 0.681914] pcieport 0000:00:1c.1: Signaling PME through PCIe PME interrupt +[ 0.681967] pci 0000:03:00.0: Signaling PME through PCIe PME interrupt +[ 0.682032] pcie_pme 0000:00:1c.1:pcie01: service driver pcie_pme loaded +[ 0.682086] pcieport 0000:00:1c.3: Signaling PME through PCIe PME interrupt +[ 0.682140] pcie_pme 0000:00:1c.3:pcie01: service driver pcie_pme loaded +[ 0.682156] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 +[ 0.682263] pciehp 0000:00:1c.0:pcie04: HPC vendor_id 8086 device_id 2940 ss_vid 17aa ss_did 20f3 +[ 0.682387] pciehp 0000:00:1c.0:pcie04: service driver pciehp loaded +[ 0.682402] pciehp 0000:00:1c.1:pcie04: HPC vendor_id 8086 device_id 2942 ss_vid 17aa ss_did 20f3 +[ 0.682519] pciehp 0000:00:1c.1:pcie04: service driver pciehp loaded +[ 0.682533] pciehp 0000:00:1c.3:pcie04: HPC vendor_id 8086 device_id 2946 ss_vid 17aa ss_did 20f3 +[ 0.682653] pciehp 0000:00:1c.3:pcie04: service driver pciehp loaded +[ 0.682659] pciehp: PCI Express Hot Plug Controller Driver version: 0.4 +[ 0.682755] intel_idle: does not run on family 6 model 23 +[ 0.682764] ipmi message handler version 39.2 +[ 0.682977] ACPI: Deprecated procfs I/F for AC is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +[ 0.683222] ACPI: AC Adapter [AC] (on-line) +[ 0.683362] input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0C0D:00/input/input0 +[ 0.683702] ACPI: Lid Switch [LID] +[ 0.683781] input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input1 +[ 0.683844] ACPI: Sleep Button [SLPB] +[ 0.683929] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 +[ 0.683991] ACPI: Power Button [PWRF] +[ 0.685432] Monitor-Mwait will be used to enter C-1 state +[ 0.685438] Monitor-Mwait will be used to enter C-2 state +[ 0.685441] Monitor-Mwait will be used to enter C-3 state +[ 0.685444] tsc: Marking TSC unstable due to TSC halts in idle +[ 0.685502] ACPI: acpi_idle registered with cpuidle +[ 0.687967] thermal LNXTHERM:00: registered as thermal_zone0 +[ 0.688045] ACPI: Thermal Zone [THM0] (56 C) +[ 0.689472] thermal LNXTHERM:01: registered as thermal_zone1 +[ 0.689527] ACPI: Thermal Zone [THM1] (55 C) +[ 0.689603] GHES: HEST is not enabled! +[ 0.689793] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +[ 0.689861] ACPI: Battery Slot [BAT0] (battery absent) +[ 0.689943] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled +[ 0.712208] 0000:00:03.3: ttyS4 at I/O 0x1830 (irq = 17, base_baud = 115200) is a 16550A +[ 0.712544] Linux agpgart interface v0.103 +[ 0.712661] agpgart-intel 0000:00:00.0: Intel GM45 Chipset +[ 0.712794] agpgart-intel 0000:00:00.0: detected gtt size: 2097152K total, 262144K mappable +[ 0.713914] agpgart-intel 0000:00:00.0: detected 32768K stolen memory +[ 0.714136] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000 +[ 0.720051] tpm_tis 00:09: 1.2 TPM (device-id 0x1020, rev-id 6) +[ 0.720104] tpm_tis 00:09: Intel iTPM workaround enabled +[ 0.792118] tpm_tis 00:09: TPM is disabled/deactivated (0x6) +[ 0.793802] brd: module loaded +[ 0.794673] loop: module loaded +[ 0.795114] libphy: Fixed MDIO Bus: probed +[ 0.795245] tun: Universal TUN/TAP device driver, 1.6 +[ 0.795292] tun: (C) 1999-2004 Max Krasnyansky +[ 0.795389] PPP generic driver version 2.4.2 +[ 0.795505] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver +[ 0.795557] ehci-pci: EHCI PCI platform driver +[ 0.795729] ehci-pci 0000:00:1a.7: EHCI Host Controller +[ 0.795781] ehci-pci 0000:00:1a.7: new USB bus registered, assigned bus number 1 +[ 0.795855] ehci-pci 0000:00:1a.7: debug port 1 +[ 0.799819] ehci-pci 0000:00:1a.7: cache line size of 64 is not supported +[ 0.799914] ehci-pci 0000:00:1a.7: irq 23, io mem 0xf2826c00 +[ 0.806055] ehci-pci 0000:00:1a.7: USB 2.0 started, EHCI 1.00 +[ 0.806198] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 +[ 0.806249] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.806309] usb usb1: Product: EHCI Host Controller +[ 0.806356] usb usb1: Manufacturer: Linux 3.13.0-39-lowlatency ehci_hcd +[ 0.806406] usb usb1: SerialNumber: 0000:00:1a.7 +[ 0.806572] hub 1-0:1.0: USB hub found +[ 0.806625] hub 1-0:1.0: 6 ports detected +[ 0.806964] ehci-pci 0000:00:1d.7: EHCI Host Controller +[ 0.807027] ehci-pci 0000:00:1d.7: new USB bus registered, assigned bus number 2 +[ 0.807102] ehci-pci 0000:00:1d.7: debug port 1 +[ 0.811047] ehci-pci 0000:00:1d.7: cache line size of 64 is not supported +[ 0.811128] ehci-pci 0000:00:1d.7: irq 19, io mem 0xf2827000 +[ 0.817124] ehci-pci 0000:00:1d.7: USB 2.0 started, EHCI 1.00 +[ 0.817761] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002 +[ 0.817811] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.817871] usb usb2: Product: EHCI Host Controller +[ 0.817919] usb usb2: Manufacturer: Linux 3.13.0-39-lowlatency ehci_hcd +[ 0.817968] usb usb2: SerialNumber: 0000:00:1d.7 +[ 0.818141] hub 2-0:1.0: USB hub found +[ 0.818192] hub 2-0:1.0: 6 ports detected +[ 0.818460] ehci-platform: EHCI generic platform driver +[ 0.818515] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver +[ 0.818986] ohci-pci: OHCI PCI platform driver +[ 0.819056] ohci-platform: OHCI generic platform driver +[ 0.819118] uhci_hcd: USB Universal Host Controller Interface driver +[ 0.819235] uhci_hcd 0000:00:1a.0: UHCI Host Controller +[ 0.819286] uhci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 3 +[ 0.819442] uhci_hcd 0000:00:1a.0: irq 20, io base 0x00001860 +[ 0.819539] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.819590] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.819651] usb usb3: Product: UHCI Host Controller +[ 0.819698] usb usb3: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.819748] usb usb3: SerialNumber: 0000:00:1a.0 +[ 0.819903] hub 3-0:1.0: USB hub found +[ 0.819962] hub 3-0:1.0: 2 ports detected +[ 0.820186] uhci_hcd 0000:00:1a.1: UHCI Host Controller +[ 0.820237] uhci_hcd 0000:00:1a.1: new USB bus registered, assigned bus number 4 +[ 0.820407] uhci_hcd 0000:00:1a.1: irq 21, io base 0x00001880 +[ 0.820506] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.820557] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.820617] usb usb4: Product: UHCI Host Controller +[ 0.820665] usb usb4: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.820714] usb usb4: SerialNumber: 0000:00:1a.1 +[ 0.820868] hub 4-0:1.0: USB hub found +[ 0.820930] hub 4-0:1.0: 2 ports detected +[ 0.821160] uhci_hcd 0000:00:1a.2: UHCI Host Controller +[ 0.821212] uhci_hcd 0000:00:1a.2: new USB bus registered, assigned bus number 5 +[ 0.821367] uhci_hcd 0000:00:1a.2: irq 22, io base 0x000018a0 +[ 0.821465] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.821516] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.821577] usb usb5: Product: UHCI Host Controller +[ 0.821624] usb usb5: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.821674] usb usb5: SerialNumber: 0000:00:1a.2 +[ 0.821836] hub 5-0:1.0: USB hub found +[ 0.821893] hub 5-0:1.0: 2 ports detected +[ 0.822114] uhci_hcd 0000:00:1d.0: UHCI Host Controller +[ 0.822166] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 6 +[ 0.822323] uhci_hcd 0000:00:1d.0: irq 16, io base 0x000018c0 +[ 0.822435] usb usb6: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.822486] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.822552] usb usb6: Product: UHCI Host Controller +[ 0.822599] usb usb6: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.822649] usb usb6: SerialNumber: 0000:00:1d.0 +[ 0.822816] hub 6-0:1.0: USB hub found +[ 0.822867] hub 6-0:1.0: 2 ports detected +[ 0.823088] uhci_hcd 0000:00:1d.1: UHCI Host Controller +[ 0.823139] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 7 +[ 0.823297] uhci_hcd 0000:00:1d.1: irq 17, io base 0x000018e0 +[ 0.823398] usb usb7: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.823449] usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.823509] usb usb7: Product: UHCI Host Controller +[ 0.823557] usb usb7: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.823607] usb usb7: SerialNumber: 0000:00:1d.1 +[ 0.823765] hub 7-0:1.0: USB hub found +[ 0.823816] hub 7-0:1.0: 2 ports detected +[ 0.824045] uhci_hcd 0000:00:1d.2: UHCI Host Controller +[ 0.824097] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 8 +[ 0.824267] uhci_hcd 0000:00:1d.2: irq 18, io base 0x00001c00 +[ 0.824365] usb usb8: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.824415] usb usb8: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.824476] usb usb8: Product: UHCI Host Controller +[ 0.824524] usb usb8: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.824573] usb usb8: SerialNumber: 0000:00:1d.2 +[ 0.824732] hub 8-0:1.0: USB hub found +[ 0.824784] hub 8-0:1.0: 2 ports detected +[ 0.824974] i8042: PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12 +[ 0.835273] serio: i8042 KBD port at 0x60,0x64 irq 1 +[ 0.835347] serio: i8042 AUX port at 0x60,0x64 irq 12 +[ 0.835524] mousedev: PS/2 mouse device common for all mice +[ 0.835806] rtc_cmos 00:06: RTC can wake from S4 +[ 0.835996] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0 +[ 0.836163] rtc_cmos 00:06: alarms up to one month, y3k, 114 bytes nvram, hpet irqs +[ 0.836291] device-mapper: uevent: version 1.0.3 +[ 0.836409] device-mapper: ioctl: 4.27.0-ioctl (2013-10-30) initialised: dm-devel@redhat.com +[ 0.836476] ledtrig-cpu: registered to indicate activity on CPUs +[ 0.836624] TCP: cubic registered +[ 0.836776] NET: Registered protocol family 10 +[ 0.837000] NET: Registered protocol family 17 +[ 0.837068] Key type dns_resolver registered +[ 0.837424] Loading compiled-in X.509 certificates +[ 0.838592] Loaded X.509 cert 'Magrathea: Glacier signing key: a7171335f18ca6131c1947ca87d46fb662317fa6' +[ 0.838684] registered taskstats version 1 +[ 0.841129] Key type trusted registered +[ 0.843261] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 +[ 0.843344] Key type encrypted registered +[ 0.845402] AppArmor: AppArmor sha1 policy hashing enabled +[ 0.863122] tpm_tis 00:09: A TPM error (6) occurred attempting to read a pcr value +[ 0.863186] IMA: No TPM chip found, activating TPM-bypass! +[ 0.863533] regulator-dummy: disabling +[ 0.863620] Magic number: 11:688:823 +[ 0.863809] rtc_cmos 00:06: setting system clock to 2015-08-30 06:48:56 UTC (1440917336) +[ 0.866119] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found +[ 0.866172] EDD information not available. +[ 0.866304] PM: Hibernation image not present or could not be loaded. +[ 0.868348] Freeing unused kernel memory: 1324K (ffffffff81d1d000 - ffffffff81e68000) +[ 0.868413] Write protecting the kernel read-only data: 12288k +[ 0.872016] Freeing unused kernel memory: 764K (ffff880001741000 - ffff880001800000) +[ 0.875110] Freeing unused kernel memory: 676K (ffff880001b57000 - ffff880001c00000) +[ 0.894972] systemd-udevd[126]: starting version 204 +[ 0.928980] pps_core: LinuxPPS API ver. 1 registered +[ 0.930015] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti +[ 0.934247] PTP clock support registered +[ 0.940925] [drm] Initialized drm 1.1.0 20060810 +[ 0.948317] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k +[ 0.948333] wmi: Mapper loaded +[ 0.949020] e1000e: Copyright(c) 1999 - 2013 Intel Corporation. +[ 0.949310] e1000e 0000:00:19.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode +[ 0.949407] e1000e 0000:00:19.0: irq 43 for MSI/MSI-X +[ 1.143351] e1000e 0000:00:19.0 eth0: (PCI Express:2.5GT/s:Width x1) 00:1f:16:0b:4d:8c +[ 1.143422] e1000e 0000:00:19.0 eth0: Intel(R) PRO/1000 Network Connection +[ 1.143503] e1000e 0000:00:19.0 eth0: MAC: 7, PHY: 8, PBA No: 1008FF-0FF +[ 1.143581] ahci 0000:00:1f.2: version 3.0 +[ 1.143759] ahci 0000:00:1f.2: irq 44 for MSI/MSI-X +[ 1.143807] ahci 0000:00:1f.2: SSS flag set, parallel bus scan disabled +[ 1.143886] ahci 0000:00:1f.2: AHCI 0001.0200 32 slots 4 ports 3 Gbps 0x3 impl SATA mode +[ 1.143952] ahci 0000:00:1f.2: flags: 64bit ncq sntf stag pm led clo pio slum part ccc sxs +[ 1.144931] scsi0 : ahci +[ 1.145135] scsi1 : ahci +[ 1.145511] scsi2 : ahci +[ 1.145741] scsi3 : ahci +[ 1.145851] ata1: SATA max UDMA/133 abar m2048@0xf2826000 port 0xf2826100 irq 44 +[ 1.145924] ata2: SATA max UDMA/133 abar m2048@0xf2826000 port 0xf2826180 irq 44 +[ 1.145987] ata3: DUMMY +[ 1.146051] ata4: DUMMY +[ 1.146776] [drm] Memory usable by graphics device = 2048M +[ 1.211100] i915 0000:00:02.0: irq 45 for MSI/MSI-X +[ 1.211112] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). +[ 1.211164] [drm] Driver supports precise vblank timestamp query. +[ 1.211360] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem +[ 1.356901] fbcon: inteldrmfb (fb0) is primary device +[ 1.429783] psmouse serio1: alps: Unknown ALPS touchpad: E7=10 00 64, EC=10 00 64 +[ 1.451120] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300) +[ 1.452184] ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.452187] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out +[ 1.452301] ata1.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.452303] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out +[ 1.464094] usb 4-2: new full-speed USB device number 2 using uhci_hcd +[ 1.498665] ata1.00: ATA-8: WDC WD1600BEVS-08VAT2, 14.01A14, max UDMA/133 +[ 1.498667] ata1.00: 312581808 sectors, multi 16: LBA48 NCQ (depth 31/32), AA +[ 1.500316] ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.500319] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out +[ 1.500465] ata1.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.500467] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out +[ 1.502270] ata1.00: configured for UDMA/133 +[ 1.502467] scsi 0:0:0:0: Direct-Access ATA WDC WD1600BEVS-0 14.0 PQ: 0 ANSI: 5 +[ 1.502651] sd 0:0:0:0: [sda] 312581808 512-byte logical blocks: (160 GB/149 GiB) +[ 1.502695] sd 0:0:0:0: Attached scsi generic sg0 type 0 +[ 1.502732] sd 0:0:0:0: [sda] Write Protect is off +[ 1.502734] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 +[ 1.502774] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA +[ 1.537914] sda: sda1 sda2 < sda5 sda6 > +[ 1.538544] sd 0:0:0:0: [sda] Attached SCSI disk +[ 1.618541] usb 4-2: New USB device found, idVendor=0a5c, idProduct=2145 +[ 1.618544] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 +[ 1.618546] usb 4-2: Product: ThinkPad Bluetooth with Enhanced Data Rate II +[ 1.618547] usb 4-2: Manufacturer: Lenovo Computer Corp +[ 1.796484] psmouse serio1: trackpoint: IBM TrackPoint firmware: 0x0e, buttons: 3/3 +[ 1.807121] ata2: SATA link down (SStatus 0 SControl 300) +[ 1.814662] input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/input/input5 +[ 1.894282] Console: switching to colour frame buffer device 160x50 +[ 1.901135] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device +[ 1.902865] i915 0000:00:02.0: registered panic notifier +[ 1.907397] ACPI: Video Device [VID] (multi-head: yes rom: no post: no) +[ 1.916101] acpi device:02: registered as cooling_device2 +[ 1.917970] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input6 +[ 1.919867] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0 +[ 2.603154] md: linear personality registered for level -1 +[ 2.607184] md: multipath personality registered for level -4 +[ 2.611208] md: raid0 personality registered for level 0 +[ 2.615754] md: raid1 personality registered for level 1 +[ 2.637037] raid6: sse2x1 2871 MB/s +[ 2.654032] raid6: sse2x2 3125 MB/s +[ 2.671029] raid6: sse2x4 4628 MB/s +[ 2.671057] raid6: using algorithm sse2x4 (4628 MB/s) +[ 2.671090] raid6: using ssse3x2 recovery algorithm +[ 2.673224] xor: measuring software checksum speed +[ 2.683030] prefetch64-sse: 6432.000 MB/sec +[ 2.693030] generic_sse: 5720.000 MB/sec +[ 2.693061] xor: using function: prefetch64-sse (6432.000 MB/sec) +[ 2.695037] async_tx: api initialized (async) +[ 2.706535] md: raid6 personality registered for level 6 +[ 2.706574] md: raid5 personality registered for level 5 +[ 2.706609] md: raid4 personality registered for level 4 +[ 2.715477] md: raid10 personality registered for level 10 +[ 2.777351] random: nonblocking pool is initialized +[ 2.912964] bio: create slab at 1 +[ 2.914076] Btrfs loaded +[ 3.142639] EXT4-fs (sda1): mounted filesystem with ordered data mode. Opts: (null) +[ 13.257389] Adding 4230140k swap on /dev/sda5. Priority:-1 extents:1 across:4230140k FS +[ 13.348717] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 13.512598] systemd-udevd[410]: starting version 204 +[ 13.698475] lp: driver loaded but no devices found +[ 13.718842] ppdev: user-space parallel port driver +[ 13.888756] Bluetooth: Core ver 2.17 +[ 13.888782] NET: Registered protocol family 31 +[ 13.888785] Bluetooth: HCI device and connection manager initialized +[ 13.888797] Bluetooth: HCI socket layer initialized +[ 13.888801] Bluetooth: L2CAP socket layer initialized +[ 13.888807] Bluetooth: SCO socket layer initialized +[ 13.902331] usbcore: registered new interface driver btusb +[ 13.909756] ACPI Warning: 0x0000000000001028-0x000000000000102f SystemIO conflicts with Region \_SB_.PCI0.LPC_.PMIO 1 (20131115/utaddress-251) +[ 13.909766] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 13.909772] ACPI Warning: 0x00000000000011b0-0x00000000000011bf SystemIO conflicts with Region \_SB_.PCI0.LPC_.LPIO 1 (20131115/utaddress-251) +[ 13.909777] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 13.909779] ACPI Warning: 0x0000000000001180-0x00000000000011af SystemIO conflicts with Region \_SB_.PCI0.LPC_.LPIO 1 (20131115/utaddress-251) +[ 13.909783] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 13.909785] lpc_ich: Resource conflict(s) found affecting gpio_ich +[ 13.924585] EXT4-fs (sda1): re-mounted. Opts: errors=remount-ro +[ 13.962851] Non-volatile memory driver v1.3 +[ 14.000898] thinkpad_acpi: ThinkPad ACPI Extras v0.25 +[ 14.000903] thinkpad_acpi: http://ibm-acpi.sf.net/ +[ 14.000905] thinkpad_acpi: ThinkPad BIOS 6DET65WW (3.15 ), EC 7XHT24WW-1.06 +[ 14.000907] thinkpad_acpi: Lenovo ThinkPad X200, model 7459GW4 +[ 14.023348] thinkpad_acpi: detected a 16-level brightness capable ThinkPad +[ 14.023562] thinkpad_acpi: radio switch found; radios are enabled +[ 14.023579] thinkpad_acpi: This ThinkPad has standard ACPI backlight brightness control, supported by the ACPI video driver +[ 14.023581] thinkpad_acpi: Disabling thinkpad-acpi brightness events by default... +[ 14.027716] thinkpad_acpi: rfkill switch tpacpi_bluetooth_sw: radio is unblocked +[ 14.033143] thinkpad_acpi: Standard ACPI backlight interface available, not loading native one +[ 14.033423] thinkpad_acpi: Console audio control enabled, mode: monitor (read only) +[ 14.037967] input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input7 +[ 14.094334] snd_hda_intel 0000:00:1b.0: irq 46 for MSI/MSI-X +[ 14.117123] hda_codec: CX20561 (Hermosa): BIOS auto-probing. +[ 14.117573] autoconfig: line_outs=1 (0x1a/0x0/0x0/0x0/0x0) type:speaker +[ 14.117576] speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) +[ 14.117578] hp_outs=2 (0x19/0x16/0x0/0x0/0x0) +[ 14.117580] mono: mono_out=0x0 +[ 14.117582] dig-out=0x1c/0x0 +[ 14.117583] inputs: +[ 14.117585] Mic=0x18 +[ 14.117587] Internal Mic=0x1d +[ 14.117589] Dock Mic=0x17 +[ 14.118587] hda_codec: Enable sync_write for stable communication +[ 14.121304] input: HDA Intel Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input11 +[ 14.121403] input: HDA Intel Dock Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input10 +[ 14.121491] input: HDA Intel Dock Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9 +[ 14.121572] input: HDA Intel Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input8 +[ 14.141178] device-mapper: multipath: version 1.6.0 loaded +[ 14.154949] kvm: disabled by bios +[ 14.165173] kvm: disabled by bios +[ 14.310307] mei_me 0000:00:03.0: irq 47 for MSI/MSI-X +[ 14.401058] cfg80211: Calling CRDA to update world regulatory domain +[ 14.440429] Intel(R) Wireless WiFi driver for Linux, in-tree: +[ 14.440433] Copyright(c) 2003-2013 Intel Corporation +[ 14.440762] iwlwifi 0000:03:00.0: can't disable ASPM; OS doesn't have ASPM control +[ 14.440834] iwlwifi 0000:03:00.0: irq 48 for MSI/MSI-X +[ 14.441053] 0000:03:00.0: Missing Free firmware +[ 14.441095] iwlwifi 0000:03:00.0: Couldn't request the fw +[ 14.442753] iwlwifi: probe of 0000:03:00.0 failed with error -22 +[ 14.514047] pci 0000:03:00.0: Direct firmware load failed with error -2 +[ 14.514052] pci 0000:03:00.0: Falling back to user helper +[ 14.519440] type=1400 audit(1440917350.154:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/sbin/dhclient" pid=569 comm="apparmor_parser" +[ 14.519450] type=1400 audit(1440917350.154:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=569 comm="apparmor_parser" +[ 14.519457] type=1400 audit(1440917350.154:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=569 comm="apparmor_parser" +[ 14.520174] systemd-udevd[425]: renamed network interface eth0 to eth4 +[ 14.520232] type=1400 audit(1440917350.155:5): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=569 comm="apparmor_parser" +[ 14.520241] type=1400 audit(1440917350.155:6): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=569 comm="apparmor_parser" +[ 14.520582] type=1400 audit(1440917350.155:7): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=569 comm="apparmor_parser" +[ 15.055767] SGI XFS with ACLs, security attributes, realtime, large block/inode numbers, no debug enabled +[ 15.119824] XFS (sda6): Mounting Filesystem +[ 15.569603] XFS (sda6): Ending clean mount +[ 15.844338] init: failsafe main process (725) killed by TERM signal +[ 16.170233] type=1400 audit(1440917351.805:8): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/sbin/dhclient" pid=831 comm="apparmor_parser" +[ 16.170245] type=1400 audit(1440917351.805:9): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=831 comm="apparmor_parser" +[ 16.170252] type=1400 audit(1440917351.805:10): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=831 comm="apparmor_parser" +[ 16.170906] type=1400 audit(1440917351.805:11): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=831 comm="apparmor_parser" +[ 16.548278] Bluetooth: RFCOMM TTY layer initialized +[ 16.548295] Bluetooth: RFCOMM socket layer initialized +[ 16.548303] Bluetooth: RFCOMM ver 1.11 +[ 16.702630] init: cups main process (887) killed by HUP signal +[ 16.702645] init: cups main process ended, respawning +[ 16.717535] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 +[ 16.717540] Bluetooth: BNEP filters: protocol multicast +[ 16.717552] Bluetooth: BNEP socket layer initialized +[ 18.798586] init: plymouth-upstart-bridge main process ended, respawning +[ 19.246364] e1000e 0000:00:19.0: irq 43 for MSI/MSI-X +[ 19.347188] e1000e 0000:00:19.0: irq 43 for MSI/MSI-X +[ 19.347386] IPv6: ADDRCONF(NETDEV_UP): eth4: link is not ready +[ 19.347784] IPv6: ADDRCONF(NETDEV_UP): eth4: link is not ready +[ 22.755913] e1000e: eth4 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx +[ 22.756058] IPv6: ADDRCONF(NETDEV_CHANGE): eth4: link becomes ready +[ 46.558282] audit_printk_skb: 96 callbacks suppressed +[ 46.558287] type=1400 audit(1440913378.392:44): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/cups/backend/cups-pdf" pid=2159 comm="apparmor_parser" +[ 46.558298] type=1400 audit(1440913378.392:45): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=2159 comm="apparmor_parser" +[ 46.558959] type=1400 audit(1440913378.392:46): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=2159 comm="apparmor_parser" diff --git a/site/docs/hardware/hwdumps/x200/dmidecode.err.log b/site/docs/hardware/hwdumps/x200/dmidecode.err.log new file mode 100644 index 0000000..e69de29 diff --git a/site/docs/hardware/hwdumps/x200/dmidecode.log b/site/docs/hardware/hwdumps/x200/dmidecode.log new file mode 100644 index 0000000..a5a1961 --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/dmidecode.log @@ -0,0 +1,587 @@ +# dmidecode 2.12 +SMBIOS 2.4 present. +68 structures occupying 2464 bytes. +Table at 0x000E0010. + +Handle 0x0000, DMI type 0, 24 bytes +BIOS Information + Vendor: LENOVO + Version: 6DET65WW (3.15 ) + Release Date: 08/24/2010 + Address: 0xE0000 + Runtime Size: 128 kB + ROM Size: 8192 kB + Characteristics: + PCI is supported + PC Card (PCMCIA) is supported + PNP is supported + BIOS is upgradeable + BIOS shadowing is allowed + ESCD support is available + Boot from CD is supported + Selectable boot is supported + BIOS ROM is socketed + EDD is supported + ACPI is supported + USB legacy is supported + BIOS boot specification is supported + Targeted content distribution is supported + BIOS Revision: 3.21 + Firmware Revision: 1.6 + +Handle 0x0001, DMI type 1, 27 bytes +System Information + Manufacturer: LENOVO + Product Name: 7459GW4 + Version: ThinkPad X200 + Serial Number: L3AAR0B + UUID: 93861E01-4A15-11CB-8F2C-D4BC407E0839 + Wake-up Type: Power Switch + SKU Number: Not Specified + Family: ThinkPad X200 + +Handle 0x0002, DMI type 2, 8 bytes +Base Board Information + Manufacturer: LENOVO + Product Name: 7459GW4 + Version: Not Available + Serial Number: 1ZFDS89N4DD + +Handle 0x0003, DMI type 3, 13 bytes +Chassis Information + Manufacturer: LENOVO + Type: Notebook + Lock: Not Present + Version: Not Available + Serial Number: Not Available + Asset Tag: 1S7459GW4L3AAR0B + Boot-up State: Unknown + Power Supply State: Unknown + Thermal State: Unknown + Security Status: Unknown + +Handle 0x0004, DMI type 126, 13 bytes +Inactive + +Handle 0x0005, DMI type 126, 13 bytes +Inactive + +Handle 0x0006, DMI type 4, 35 bytes +Processor Information + Socket Designation: None + Type: Central Processor + Family: Other + Manufacturer: GenuineIntel + ID: 76 06 01 00 FF FB EB BF + Signature: Type 0, Family 6, Model 23, Stepping 6 + Flags: + FPU (Floating-point unit on-chip) + VME (Virtual mode extension) + DE (Debugging extension) + PSE (Page size extension) + TSC (Time stamp counter) + MSR (Model specific registers) + PAE (Physical address extension) + MCE (Machine check exception) + CX8 (CMPXCHG8 instruction supported) + APIC (On-chip APIC hardware supported) + SEP (Fast system call) + MTRR (Memory type range registers) + PGE (Page global enable) + MCA (Machine check architecture) + CMOV (Conditional move instruction supported) + PAT (Page attribute table) + PSE-36 (36-bit page size extension) + CLFSH (CLFLUSH instruction supported) + DS (Debug store) + ACPI (ACPI supported) + MMX (MMX technology supported) + FXSR (FXSAVE and FXSTOR instructions supported) + SSE (Streaming SIMD extensions) + SSE2 (Streaming SIMD extensions 2) + SS (Self-snoop) + HTT (Multi-threading) + TM (Thermal monitor supported) + PBE (Pending break enabled) + Version: Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz + Voltage: 1.2 V + External Clock: 266 MHz + Max Speed: 2400 MHz + Current Speed: 2400 MHz + Status: Populated, Enabled + Upgrade: None + L1 Cache Handle: 0x000A + L2 Cache Handle: 0x000C + L3 Cache Handle: Not Provided + Serial Number: Not Specified + Asset Tag: Not Specified + Part Number: Not Specified + +Handle 0x0007, DMI type 5, 20 bytes +Memory Controller Information + Error Detecting Method: None + Error Correcting Capabilities: + None + Supported Interleave: One-way Interleave + Current Interleave: One-way Interleave + Maximum Memory Module Size: 4096 MB + Maximum Total Memory Size: 8192 MB + Supported Speeds: + Other + Supported Memory Types: + DIMM + SDRAM + Memory Module Voltage: 2.9 V + Associated Memory Slots: 2 + 0x0008 + 0x0009 + Enabled Error Correcting Capabilities: + Unknown + +Handle 0x0008, DMI type 6, 12 bytes +Memory Module Information + Socket Designation: DIMM Slot 1 + Bank Connections: 0 1 + Current Speed: 42 ns + Type: DIMM SDRAM + Installed Size: 2048 MB (Double-bank Connection) + Enabled Size: 2048 MB (Double-bank Connection) + Error Status: OK + +Handle 0x0009, DMI type 6, 12 bytes +Memory Module Information + Socket Designation: DIMM Slot 2 + Bank Connections: 2 3 + Current Speed: 42 ns + Type: DIMM SDRAM + Installed Size: Not Installed + Enabled Size: Not Installed + Error Status: OK + +Handle 0x000A, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L1 Cache + Configuration: Enabled, Socketed, Level 1 + Operational Mode: Write Back + Location: Internal + Installed Size: 64 kB + Maximum Size: 64 kB + Supported SRAM Types: + Synchronous + Installed SRAM Type: Synchronous + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Instruction + Associativity: 8-way Set-associative + +Handle 0x000B, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L1 Cache + Configuration: Enabled, Socketed, Level 1 + Operational Mode: Write Back + Location: Internal + Installed Size: 64 kB + Maximum Size: 64 kB + Supported SRAM Types: + Synchronous + Installed SRAM Type: Synchronous + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Data + Associativity: 8-way Set-associative + +Handle 0x000C, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L2 Cache + Configuration: Enabled, Socketed, Level 2 + Operational Mode: Write Back + Location: Internal + Installed Size: 3072 kB + Maximum Size: 3072 kB + Supported SRAM Types: + Burst + Installed SRAM Type: Burst + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Unified + Associativity: 8-way Set-associative + +Handle 0x000D, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: External Monitor + External Connector Type: DB-15 female + Port Type: Video Port + +Handle 0x000E, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Microphone Jack + External Connector Type: Mini Jack (headphones) + Port Type: Audio Port + +Handle 0x000F, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Headphone Jack + External Connector Type: Mini Jack (headphones) + Port Type: Audio Port + +Handle 0x0010, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Modem + External Connector Type: RJ-11 + Port Type: Modem Port + +Handle 0x0011, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Ethernet + External Connector Type: RJ-45 + Port Type: Network Port + +Handle 0x0012, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 1 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0013, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 2 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0014, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 3 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0015, DMI type 126, 9 bytes +Inactive + +Handle 0x0016, DMI type 126, 9 bytes +Inactive + +Handle 0x0017, DMI type 126, 9 bytes +Inactive + +Handle 0x0018, DMI type 126, 9 bytes +Inactive + +Handle 0x0019, DMI type 126, 9 bytes +Inactive + +Handle 0x001A, DMI type 126, 9 bytes +Inactive + +Handle 0x001B, DMI type 126, 13 bytes +Inactive + +Handle 0x001C, DMI type 10, 6 bytes +On Board Device Information + Type: Other + Status: Disabled + Description: IBM Embedded Security hardware + +Handle 0x001D, DMI type 11, 5 bytes +OEM Strings + String 1: IBM ThinkPad Embedded Controller -[7XHT24WW-1.06 ]- + +Handle 0x001E, DMI type 13, 22 bytes +BIOS Language Information + Language Description Format: Abbreviated + Installable Languages: 1 + enUS + Currently Installed Language: enUS + +Handle 0x001F, DMI type 15, 25 bytes +System Event Log + Area Length: 0 bytes + Header Start Offset: 0x0000 + Header Length: 16 bytes + Data Start Offset: 0x0010 + Access Method: General-purpose non-volatile data functions + Access Address: 0x0000 + Status: Valid, Not Full + Change Token: 0x000000FC + Header Format: Type 1 + Supported Log Type Descriptors: 1 + Descriptor 1: POST error + Data Format 1: POST results bitmap + +Handle 0x0020, DMI type 16, 15 bytes +Physical Memory Array + Location: System Board Or Motherboard + Use: System Memory + Error Correction Type: None + Maximum Capacity: 4 GB + Error Information Handle: Not Provided + Number Of Devices: 2 + +Handle 0x0021, DMI type 17, 27 bytes +Memory Device + Array Handle: 0x0020 + Error Information Handle: No Error + Total Width: 64 bits + Data Width: 64 bits + Size: 2048 MB + Form Factor: SODIMM + Set: None + Locator: DIMM 1 + Bank Locator: Bank 0/1 + Type: DDR3 + Type Detail: Synchronous + Speed: 1066 MHz + Manufacturer: 02FE + Serial Number: F4BB7CA2 + Asset Tag: 0839 + Part Number: EBJ21UE8BASA-AE-E + +Handle 0x0022, DMI type 17, 27 bytes +Memory Device + Array Handle: 0x0020 + Error Information Handle: No Error + Total Width: Unknown + Data Width: Unknown + Size: No Module Installed + Form Factor: SODIMM + Set: None + Locator: DIMM 2 + Bank Locator: Bank 2/3 + Type: DDR2 + Type Detail: Synchronous + Speed: 1066 MHz + Manufacturer: + Serial Number: + Asset Tag: + Part Number: + +Handle 0x0023, DMI type 18, 23 bytes +32-bit Memory Error Information + Type: OK + Granularity: Unknown + Operation: Unknown + Vendor Syndrome: Unknown + Memory Array Address: Unknown + Device Address: Unknown + Resolution: Unknown + +Handle 0x0024, DMI type 19, 15 bytes +Memory Array Mapped Address + Starting Address: 0x00000000000 + Ending Address: 0x0007FFFFFFF + Range Size: 2 GB + Physical Array Handle: 0x0020 + Partition Width: 2 + +Handle 0x0025, DMI type 20, 19 bytes +Memory Device Mapped Address + Starting Address: 0x00000000000 + Ending Address: 0x0007FFFFFFF + Range Size: 2 GB + Physical Device Handle: 0x0021 + Memory Array Mapped Address Handle: 0x0024 + Partition Row Position: 1 + +Handle 0x0026, DMI type 20, 19 bytes +Memory Device Mapped Address + Starting Address: 0x0007FFFFC00 + Ending Address: 0x0007FFFFFFF + Range Size: 1 kB + Physical Device Handle: 0x0022 + Memory Array Mapped Address Handle: 0x0024 + Partition Row Position: 1 + +Handle 0x0027, DMI type 21, 7 bytes +Built-in Pointing Device + Type: Track Point + Interface: PS/2 + Buttons: 3 + +Handle 0x0028, DMI type 126, 26 bytes +Inactive + +Handle 0x0029, DMI type 126, 26 bytes +Inactive + +Handle 0x002A, DMI type 24, 5 bytes +Hardware Security + Power-On Password Status: Disabled + Keyboard Password Status: Disabled + Administrator Password Status: Disabled + Front Panel Reset Status: Unknown + +Handle 0x002B, DMI type 32, 11 bytes +System Boot Information + Status: No errors detected + +Handle 0x002C, DMI type 131, 17 bytes +OEM-specific Type + Header and Data: + 83 11 2C 00 01 02 03 FF FF 1F 00 00 00 00 00 02 + 00 + Strings: + BOOTINF 20h + BOOTDEV 21h + KEYPTRS 23h + +Handle 0x002D, DMI type 131, 22 bytes +OEM-specific Type + Header and Data: + 83 16 2D 00 01 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 01 + Strings: + TVT-Enablement + +Handle 0x002E, DMI type 132, 7 bytes +OEM-specific Type + Header and Data: + 84 07 2E 00 02 D8 36 + +Handle 0x002F, DMI type 133, 5 bytes +OEM-specific Type + Header and Data: + 85 05 2F 00 01 + Strings: + KHOIHGIUCCHHII + +Handle 0x0030, DMI type 134, 13 bytes +OEM-specific Type + Header and Data: + 86 0D 30 00 30 10 08 20 00 00 00 00 00 + +Handle 0x0031, DMI type 134, 16 bytes +OEM-specific Type + Header and Data: + 86 10 31 00 00 49 4E 54 43 01 01 00 00 02 01 02 + Strings: + TPM INFO + System Reserved + +Handle 0x0032, DMI type 135, 13 bytes +OEM-specific Type + Header and Data: + 87 0D 32 00 54 50 07 00 01 00 00 00 00 + +Handle 0x0033, DMI type 135, 18 bytes +OEM-specific Type + Header and Data: + 87 12 33 00 54 50 07 01 01 B9 05 00 00 00 00 00 + 00 00 + +Handle 0x0034, DMI type 135, 35 bytes +OEM-specific Type + Header and Data: + 87 23 34 00 54 50 07 02 42 41 59 20 49 2F 4F 20 + 01 00 02 00 00 0B 00 48 1C 3E 18 02 00 0B 00 40 + 1C 3A 18 + +Handle 0x0035, DMI type 135, 34 bytes +OEM-specific Type + Header and Data: + 87 22 35 00 54 50 07 04 01 06 01 01 02 00 02 01 + 02 00 03 01 02 00 04 01 02 00 05 01 02 00 06 01 + 02 00 + +Handle 0x0036, DMI type 135, 10 bytes +OEM-specific Type + Header and Data: + 87 0A 36 00 54 50 07 03 01 0A + +Handle 0x0037, DMI type 136, 6 bytes +OEM-specific Type + Header and Data: + 88 06 37 00 5A 5A + +Handle 0x0038, DMI type 126, 28 bytes +Inactive + +Handle 0x0039, DMI type 138, 40 bytes +OEM-specific Type + Header and Data: + 8A 28 39 00 14 01 02 01 40 02 01 40 02 01 40 02 + 01 40 01 40 42 49 4F 53 20 50 61 73 73 77 6F 72 + 64 20 46 6F 72 6D 61 74 + +Handle 0x003A, DMI type 139, 37 bytes +OEM-specific Type + Header and Data: + 8B 25 3A 00 11 01 0A 00 00 00 00 00 00 00 00 00 + 00 50 57 4D 53 20 4B 65 79 20 49 6E 66 6F 72 6D + 61 74 69 6F 6E + +Handle 0x003B, DMI type 140, 67 bytes +OEM-specific Type + Header and Data: + 8C 43 3B 00 4C 45 4E 4F 56 4F 0B 00 01 9A 13 CD + C4 7A 2A 8E 76 C3 C4 4E B9 B1 DD 4E 7C 01 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 + +Handle 0x003C, DMI type 140, 47 bytes +OEM-specific Type + Header and Data: + 8C 2F 3C 00 4C 45 4E 4F 56 4F 0B 01 01 08 00 BF + DA 3C 04 5C 72 D9 7D 0D 79 DE 46 98 23 10 B1 00 + 00 00 00 10 00 10 00 10 01 D0 00 20 01 00 01 + +Handle 0x003D, DMI type 140, 63 bytes +OEM-specific Type + Header and Data: + 8C 3F 3D 00 4C 45 4E 4F 56 4F 0B 02 01 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +Handle 0x003E, DMI type 140, 17 bytes +OEM-specific Type + Header and Data: + 8C 11 3E 00 4C 45 4E 4F 56 4F 0B 03 01 00 00 00 + 00 + +Handle 0x003F, DMI type 140, 19 bytes +OEM-specific Type + Header and Data: + 8C 13 3F 00 4C 45 4E 4F 56 4F 0B 04 01 B2 00 53 + 4D 20 00 + +Handle 0x0040, DMI type 129, 8 bytes +OEM-specific Type + Header and Data: + 81 08 40 00 01 01 02 01 + Strings: + Intel_ASF + Intel_ASF_001 + +Handle 0x0041, DMI type 130, 20 bytes +OEM-specific Type + Header and Data: + 82 14 41 00 24 41 4D 54 01 01 01 01 01 A5 0B 04 + 00 00 00 00 + +Handle 0x0042, DMI type 131, 64 bytes +OEM-specific Type + Header and Data: + 83 40 42 00 14 00 00 00 00 00 40 2A 00 00 00 00 + F8 00 17 29 00 00 00 00 2D 00 00 00 00 00 04 00 + 64 04 03 00 01 00 01 15 C8 00 F5 10 00 00 00 00 + 00 00 00 00 07 00 00 00 76 50 72 6F 00 00 00 00 + +Handle 0x0043, DMI type 127, 4 bytes +End Of Table + diff --git a/site/docs/hardware/hwdumps/x200/ectool.err.log b/site/docs/hardware/hwdumps/x200/ectool.err.log new file mode 100644 index 0000000..452503e --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/ectool.err.log @@ -0,0 +1 @@ +bash: ectool: command not found diff --git a/site/docs/hardware/hwdumps/x200/ectool.log b/site/docs/hardware/hwdumps/x200/ectool.log new file mode 100644 index 0000000..e69de29 diff --git a/site/docs/hardware/hwdumps/x200/flashrom_info.err.log b/site/docs/hardware/hwdumps/x200/flashrom_info.err.log new file mode 100644 index 0000000..933ac57 --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/flashrom_info.err.log @@ -0,0 +1,14 @@ +======================================================================== +WARNING! You seem to be running flashrom on an unsupported laptop. +Laptops, notebooks and netbooks are difficult to support and we +recommend to use the vendor flashing utility. The embedded controller +(EC) in these machines often interacts badly with flashing. +See http://www.flashrom.org/Laptops for details. + +If flash is shared with the EC, erase is guaranteed to brick your laptop +and write may brick your laptop. +Read and probe may irritate your EC and cause fan failure, backlight +failure and sudden poweroff. +You have been warned. +======================================================================== +Proceeding anyway because user forced us to. diff --git a/site/docs/hardware/hwdumps/x200/flashrom_info.log b/site/docs/hardware/hwdumps/x200/flashrom_info.log new file mode 100644 index 0000000..d9a82f8 --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/flashrom_info.log @@ -0,0 +1,289 @@ +flashrom v0.9.6.1-r1563 on Linux 3.13.0-39-lowlatency (x86_64) +flashrom is free software, get the source code at http://www.flashrom.org + +flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian +Command line (3 args): flashrom -V -p internal:laptop=force_I_want_a_brick +Calibrating delay loop... OS timer resolution is 1 usecs, 1578M loops per second, 10 myus = 11 us, 100 myus = 114 us, 1000 myus = 1002 us, 10000 myus = 10004 us, 4 myus = 5 us, OK. +Initializing internal programmer +No coreboot table found. +DMI string system-manufacturer: "LENOVO" +DMI string system-product-name: "7459GW4" +DMI string system-version: "ThinkPad X200" +DMI string baseboard-manufacturer: "LENOVO" +DMI string baseboard-product-name: "7459GW4" +DMI string baseboard-version: "Not Available" +DMI string chassis-type: "Notebook" +Laptop detected via DMI. +Found chipset "Intel ICH9M-E" with PCI ID 8086:2917. Enabling flash write... +0xfff80000/0xffb80000 FWH IDSEL: 0x0 +0xfff00000/0xffb00000 FWH IDSEL: 0x0 +0xffe80000/0xffa80000 FWH IDSEL: 0x0 +0xffe00000/0xffa00000 FWH IDSEL: 0x0 +0xffd80000/0xff980000 FWH IDSEL: 0x0 +0xffd00000/0xff900000 FWH IDSEL: 0x0 +0xffc80000/0xff880000 FWH IDSEL: 0x0 +0xffc00000/0xff800000 FWH IDSEL: 0x0 +0xff700000/0xff300000 FWH IDSEL: 0x4 +0xff600000/0xff200000 FWH IDSEL: 0x5 +0xff500000/0xff100000 FWH IDSEL: 0x6 +0xff400000/0xff000000 FWH IDSEL: 0x7 +0xfff80000/0xffb80000 FWH decode enabled +0xfff00000/0xffb00000 FWH decode enabled +0xffe80000/0xffa80000 FWH decode enabled +0xffe00000/0xffa00000 FWH decode enabled +0xffd80000/0xff980000 FWH decode enabled +0xffd00000/0xff900000 FWH decode enabled +0xffc80000/0xff880000 FWH decode enabled +0xffc00000/0xff800000 FWH decode enabled +0xff700000/0xff300000 FWH decode disabled +0xff600000/0xff200000 FWH decode disabled +0xff500000/0xff100000 FWH decode disabled +0xff400000/0xff000000 FWH decode disabled +Maximum FWH chip size: 0x400000 bytes +BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 +Root Complex Register Block address = 0xfed1c000 +GCS = 0x7b0461: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x1 (SPI) +Top Swap : not enabled +SPIBAR = 0xfed1c000 + 0x3800 +0x04: 0xe008 (HSFS) +HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 +WARNING: SPI Configuration Lockdown activated. +Reading OPCODES... done +0x06: 0x3f04 (HSFC) +HSFC: FGO=0, FCYCLE=2, FDBC=63, SME=0 +0x08: 0x00001000 (FADDR) +0x50: 0x00001a1b (FRAP) +BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b +0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. +0x58: 0x07ff0600 FREG1: BIOS region (0x00600000-0x007fffff) is read-write. +0x5C: 0x05f50001 FREG2: WARNING: Management Engine region (0x00001000-0x005f5fff) is locked. +0x60: 0x05f705f6 FREG3: Gigabit Ethernet region (0x005f6000-0x005f7fff) is read-write. +0x64: 0x05ff05f8 FREG4: Platform Data region (0x005f8000-0x005fffff) is read-write. +0x74: 0x9fff07e0 PR0: WARNING: 0x007e0000-0x01ffffff is read-only. +0x84: 0x85ff85f8 PR4: WARNING: 0x005f8000-0x005fffff is locked. +Please send a verbose log to flashrom@flashrom.org if this board is not listed on +http://flashrom.org/Supported_hardware#Supported_mainboards yet. +Writes have been disabled. You can enforce write support with the +ich_spi_force programmer option, but it will most likely harm your hardware! +If you force flashrom you will get no support if something breaks. +0x90: 0x04 (SSFS) +SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 +0x91: 0x000000 (SSFC) +SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 +0x94: 0x5006 (PREOP) +0x96: 0x143b (OPTYPE) +0x98: 0x05200302 (OPMENU) +0x9C: 0x0601209f (OPMENU+4) +0xA0: 0x00000000 (BBAR) +0xC4: 0x00002005 (LVSCC) +LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 +0xC8: 0x00002005 (UVSCC) +UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 +0xD0: 0x00000000 (FPB) + +SPI Read Configuration: prefetching disabled, caching enabled, OK. +The following protocols are supported: FWH, SPI. +Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Chip status register is 00 +Chip status register: Status Register Write Disable (SRWD) is not set +Chip status register: Bit 6 is not set +Chip status register: Block Protect 3 (BP3) is not set +Chip status register: Block Protect 2 (BP2) is not set +Chip status register: Block Protect 1 (BP1) is not set +Chip status register: Block Protect 0 (BP0) is not set +Chip status register: Write Enable Latch (WEL) is not set +Chip status register: Write In Progress (WIP/BUSY) is not set +Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000. +Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. +Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. +Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. +Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. +Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. +Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. +Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. +Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. +Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. +Receiving SFDP signature failed. +Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. +Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x0a, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Found Macronix flash chip "MX25L6405" (8192 kB, SPI). +No operations were specified. +Restoring MMIO space at 0x7f9c951da8a0 +Restoring PCI config space for 00:1f:0 reg 0xdc diff --git a/site/docs/hardware/hwdumps/x200/flashrom_read.err.log b/site/docs/hardware/hwdumps/x200/flashrom_read.err.log new file mode 100644 index 0000000..0a7925d --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/flashrom_read.err.log @@ -0,0 +1,16 @@ +======================================================================== +WARNING! You seem to be running flashrom on an unsupported laptop. +Laptops, notebooks and netbooks are difficult to support and we +recommend to use the vendor flashing utility. The embedded controller +(EC) in these machines often interacts badly with flashing. +See http://www.flashrom.org/Laptops for details. + +If flash is shared with the EC, erase is guaranteed to brick your laptop +and write may brick your laptop. +Read and probe may irritate your EC and cause fan failure, backlight +failure and sudden poweroff. +You have been warned. +======================================================================== +Proceeding anyway because user forced us to. +Transaction error! +Read operation failed! diff --git a/site/docs/hardware/hwdumps/x200/flashrom_read.log b/site/docs/hardware/hwdumps/x200/flashrom_read.log new file mode 100644 index 0000000..0c78c81 --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/flashrom_read.log @@ -0,0 +1,292 @@ +flashrom v0.9.6.1-r1563 on Linux 3.13.0-39-lowlatency (x86_64) +flashrom is free software, get the source code at http://www.flashrom.org + +flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian +Command line (5 args): flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin +Calibrating delay loop... OS timer resolution is 2 usecs, 1579M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1004 us, 10000 myus = 10014 us, 8 myus = 9 us, OK. +Initializing internal programmer +No coreboot table found. +DMI string system-manufacturer: "LENOVO" +DMI string system-product-name: "7459GW4" +DMI string system-version: "ThinkPad X200" +DMI string baseboard-manufacturer: "LENOVO" +DMI string baseboard-product-name: "7459GW4" +DMI string baseboard-version: "Not Available" +DMI string chassis-type: "Notebook" +Laptop detected via DMI. +Found chipset "Intel ICH9M-E" with PCI ID 8086:2917. Enabling flash write... +0xfff80000/0xffb80000 FWH IDSEL: 0x0 +0xfff00000/0xffb00000 FWH IDSEL: 0x0 +0xffe80000/0xffa80000 FWH IDSEL: 0x0 +0xffe00000/0xffa00000 FWH IDSEL: 0x0 +0xffd80000/0xff980000 FWH IDSEL: 0x0 +0xffd00000/0xff900000 FWH IDSEL: 0x0 +0xffc80000/0xff880000 FWH IDSEL: 0x0 +0xffc00000/0xff800000 FWH IDSEL: 0x0 +0xff700000/0xff300000 FWH IDSEL: 0x4 +0xff600000/0xff200000 FWH IDSEL: 0x5 +0xff500000/0xff100000 FWH IDSEL: 0x6 +0xff400000/0xff000000 FWH IDSEL: 0x7 +0xfff80000/0xffb80000 FWH decode enabled +0xfff00000/0xffb00000 FWH decode enabled +0xffe80000/0xffa80000 FWH decode enabled +0xffe00000/0xffa00000 FWH decode enabled +0xffd80000/0xff980000 FWH decode enabled +0xffd00000/0xff900000 FWH decode enabled +0xffc80000/0xff880000 FWH decode enabled +0xffc00000/0xff800000 FWH decode enabled +0xff700000/0xff300000 FWH decode disabled +0xff600000/0xff200000 FWH decode disabled +0xff500000/0xff100000 FWH decode disabled +0xff400000/0xff000000 FWH decode disabled +Maximum FWH chip size: 0x400000 bytes +BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 +Root Complex Register Block address = 0xfed1c000 +GCS = 0x7b0461: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x1 (SPI) +Top Swap : not enabled +SPIBAR = 0xfed1c000 + 0x3800 +0x04: 0xe008 (HSFS) +HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 +WARNING: SPI Configuration Lockdown activated. +Reading OPCODES... done +0x06: 0x3f04 (HSFC) +HSFC: FGO=0, FCYCLE=2, FDBC=63, SME=0 +0x08: 0x00000000 (FADDR) +0x50: 0x00001a1b (FRAP) +BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b +0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. +0x58: 0x07ff0600 FREG1: BIOS region (0x00600000-0x007fffff) is read-write. +0x5C: 0x05f50001 FREG2: WARNING: Management Engine region (0x00001000-0x005f5fff) is locked. +0x60: 0x05f705f6 FREG3: Gigabit Ethernet region (0x005f6000-0x005f7fff) is read-write. +0x64: 0x05ff05f8 FREG4: Platform Data region (0x005f8000-0x005fffff) is read-write. +0x74: 0x9fff07e0 PR0: WARNING: 0x007e0000-0x01ffffff is read-only. +0x84: 0x85ff85f8 PR4: WARNING: 0x005f8000-0x005fffff is locked. +Please send a verbose log to flashrom@flashrom.org if this board is not listed on +http://flashrom.org/Supported_hardware#Supported_mainboards yet. +Writes have been disabled. You can enforce write support with the +ich_spi_force programmer option, but it will most likely harm your hardware! +If you force flashrom you will get no support if something breaks. +0x90: 0x04 (SSFS) +SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 +0x91: 0x004240 (SSFC) +SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=2, SME=0, SCF=0 +0x94: 0x5006 (PREOP) +0x96: 0x143b (OPTYPE) +0x98: 0x05200302 (OPMENU) +0x9C: 0x0601209f (OPMENU+4) +0xA0: 0x00000000 (BBAR) +0xC4: 0x00002005 (LVSCC) +LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 +0xC8: 0x00002005 (UVSCC) +UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 +0xD0: 0x00000000 (FPB) + +SPI Read Configuration: prefetching disabled, caching enabled, OK. +The following protocols are supported: FWH, SPI. +Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Chip status register is 00 +Chip status register: Status Register Write Disable (SRWD) is not set +Chip status register: Bit 6 is not set +Chip status register: Block Protect 3 (BP3) is not set +Chip status register: Block Protect 2 (BP2) is not set +Chip status register: Block Protect 1 (BP1) is not set +Chip status register: Block Protect 0 (BP0) is not set +Chip status register: Write Enable Latch (WEL) is not set +Chip status register: Write In Progress (WIP/BUSY) is not set +Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000. +Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. +Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. +Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. +Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. +Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. +Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. +Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. +Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. +Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. +Receiving SFDP signature failed. +Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. +Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x0a, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Found Macronix flash chip "MX25L6405" (8192 kB, SPI). +Reading flash... SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 +SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 +Running OPCODE 0x03 failed at address 0x001000 (payload length was 64). +FAILED. +Restoring MMIO space at 0x7f53b721c8a0 +Restoring PCI config space for 00:1f:0 reg 0xdc diff --git a/site/docs/hardware/hwdumps/x200/input_bustypes.log b/site/docs/hardware/hwdumps/x200/input_bustypes.log new file mode 100644 index 0000000..ebce5d5 --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/input_bustypes.log @@ -0,0 +1,11 @@ +0019 +0000 +0000 +0019 +0019 +0011 +0011 +0019 +0019 +0000 +0000 diff --git a/site/docs/hardware/hwdumps/x200/inteltool.err.log b/site/docs/hardware/hwdumps/x200/inteltool.err.log new file mode 100644 index 0000000..b192da9 --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/inteltool.err.log @@ -0,0 +1 @@ +bash: inteltool: command not found diff --git a/site/docs/hardware/hwdumps/x200/inteltool.log b/site/docs/hardware/hwdumps/x200/inteltool.log new file mode 100644 index 0000000..e69de29 diff --git a/site/docs/hardware/hwdumps/x200/ioports.err.log b/site/docs/hardware/hwdumps/x200/ioports.err.log new file mode 100644 index 0000000..e69de29 diff --git a/site/docs/hardware/hwdumps/x200/ioports.log b/site/docs/hardware/hwdumps/x200/ioports.log new file mode 100644 index 0000000..54e3a06 --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/ioports.log @@ -0,0 +1,60 @@ +0000-0cf7 : PCI Bus 0000:00 + 0000-001f : dma1 + 0020-0021 : pic1 + 0040-0043 : timer0 + 0050-0053 : timer1 + 0060-0060 : keyboard + 0062-0062 : EC data + 0064-0064 : keyboard + 0066-0066 : EC cmd + 0070-0071 : rtc0 + 0080-008f : dma page reg + 00a0-00a1 : pic2 + 00c0-00df : dma2 + 00f0-00ff : fpu + 03c0-03df : vga+ + 0800-080f : pnp 00:01 +0cf8-0cff : PCI conf1 +0d00-ffff : PCI Bus 0000:00 + 1000-1003 : ACPI PM1a_EVT_BLK + 1004-1005 : ACPI PM1a_CNT_BLK + 1008-100b : ACPI PM_TMR + 1010-1015 : ACPI CPU throttle + 1020-102f : ACPI GPE0_BLK + 1030-1033 : iTCO_wdt + 1050-1050 : ACPI PM2_CNT_BLK + 1060-107f : iTCO_wdt + 1180-11ff : pnp 00:01 + 15e0-15ef : pnp 00:01 + 1600-167f : pnp 00:01 + 1680-169f : pnp 00:01 + 1800-1807 : 0000:00:02.0 + 1830-1837 : 0000:00:03.3 + 1830-1837 : serial + 1838-183b : 0000:00:1f.2 + 1838-183b : ahci + 183c-183f : 0000:00:1f.2 + 183c-183f : ahci + 1840-185f : 0000:00:19.0 + 1860-187f : 0000:00:1a.0 + 1860-187f : uhci_hcd + 1880-189f : 0000:00:1a.1 + 1880-189f : uhci_hcd + 18a0-18bf : 0000:00:1a.2 + 18a0-18bf : uhci_hcd + 18c0-18df : 0000:00:1d.0 + 18c0-18df : uhci_hcd + 18e0-18ff : 0000:00:1d.1 + 18e0-18ff : uhci_hcd + 1c00-1c1f : 0000:00:1d.2 + 1c00-1c1f : uhci_hcd + 1c20-1c3f : 0000:00:1f.2 + 1c20-1c3f : ahci + 1c40-1c47 : 0000:00:1f.2 + 1c40-1c47 : ahci + 1c48-1c4f : 0000:00:1f.2 + 1c48-1c4f : ahci + 1c60-1c7f : 0000:00:1f.3 + 2000-2fff : PCI Bus 0000:05 + 3000-3fff : PCI Bus 0000:02 + 4000-4fff : PCI Bus 0000:03 diff --git a/site/docs/hardware/hwdumps/x200/lspci.err.log b/site/docs/hardware/hwdumps/x200/lspci.err.log new file mode 100644 index 0000000..e69de29 diff --git a/site/docs/hardware/hwdumps/x200/lspci.log b/site/docs/hardware/hwdumps/x200/lspci.log new file mode 100644 index 0000000..df6b6cc --- /dev/null +++ b/site/docs/hardware/hwdumps/x200/lspci.log @@ -0,0 +1,2287 @@ +00:00.0 Host bridge [0600]: Intel Corporation Mobile 4 Series Chipset Memory Controller Hub [8086:2a40] (rev 07) + Subsystem: Lenovo Device [17aa:20e0] + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- + Kernel driver in use: agpgart-intel +00: 86 80 40 2a 06 01 90 20 07 00 00 06 00 00 00 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 e0 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 90 d1 fe 00 00 00 00 01 00 d1 fe 00 00 00 00 +50: 00 00 50 03 59 02 00 00 00 00 00 00 00 00 00 00 +60: 01 00 00 e0 00 00 00 00 01 80 d1 fe 00 00 00 00 +70: 01 00 60 7c 00 00 00 00 01 10 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 10 11 11 01 30 11 11 00 ff 03 00 00 00 1a 3b 00 +a0: 10 00 f0 07 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 7c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 91 02 00 00 +e0: 09 00 0a 11 88 64 00 1c 01 00 00 00 00 00 00 00 +f0: 01 00 00 00 00 00 00 00 a0 0f 07 00 00 00 00 00 +100: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +1a0: 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:02.0 VGA compatible controller [0300]: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a42] (rev 07) (prog-if 00 [VGA controller]) + Subsystem: Lenovo Device [17aa:20e4] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- [disabled] + Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 4152 + Capabilities: [d0] Power Management version 3 + Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Kernel driver in use: i915 +00: 86 80 42 2a 07 04 90 00 07 00 00 03 00 00 80 00 +10: 04 00 00 f2 00 00 00 00 0c 00 00 d0 00 00 00 00 +20: 01 18 00 00 00 00 00 00 00 00 00 00 aa 17 e4 20 +30: 00 00 00 00 90 00 00 00 00 00 00 00 0b 01 00 00 +40: 00 00 00 00 48 00 00 00 09 00 0a 11 88 64 00 1c +50: 01 00 50 03 19 00 00 00 00 00 00 00 00 00 00 7a +60: 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 05 d0 01 00 0c 30 e0 fe 52 41 00 00 00 00 00 00 +a0: 00 00 00 00 09 00 06 20 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 40 01 00 00 +d0: 01 00 23 00 00 00 00 00 00 00 00 00 34 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 80 00 1a 41 20 00 00 +f0: 0d 1c 34 07 eb 00 00 00 a0 0f 07 00 ea b0 b6 79 + +00:02.1 Display controller [0380]: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a43] (rev 07) + Subsystem: Lenovo Device [17aa:20e4] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #0, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41c1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=01 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 40 29 07 05 10 00 03 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 02 02 00 30 30 00 00 +20: 00 7c 10 7c 21 7c 31 7c 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 04 00 +40: 10 80 41 01 00 80 00 00 00 00 10 00 11 4c 11 01 +50: 00 00 01 10 e0 a0 00 00 38 00 00 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 +f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1c.1 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 2 [8086:2942] (rev 03) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <256ns, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #1, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- + Changed: MRL- PresDet- LinkState+ + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41d1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=02 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 42 29 07 05 10 00 03 00 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00 00 00 00 00 00 00 00 00 00 +f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1c.3 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 4 [8086:2946] (rev 03) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #3, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41e1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=04 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 46 29 07 05 10 00 03 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 05 0c 00 20 20 00 00 +20: 00 f0 f0 f1 91 f2 91 f2 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 04 00 +40: 10 80 41 01 00 80 00 00 00 00 10 00 11 4c 11 04 +50: 03 00 01 10 e0 a0 18 00 38 00 00 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe e1 41 00 00 00 00 00 00 +90: 0d a0 00 00 aa 17 f3 20 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 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00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1d.0 USB controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934] (rev 03) (prog-if 00 [UHCI]) + Subsystem: Lenovo Device [17aa:20f0] + Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [50] Subsystem: Lenovo Device [17aa:20f4] +00: 86 80 48 24 07 01 10 00 93 01 04 06 00 00 01 00 +10: 00 00 00 00 00 00 00 00 00 0d 0d 00 f0 00 80 22 +20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 04 00 +40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00 +50: 0d 00 00 00 aa 17 f4 20 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 03 00 00 00 00 00 + +00:1f.0 ISA bridge [0601]: Intel Corporation ICH9M-E LPC Interface Controller [8086:2917] (rev 03) + Subsystem: Lenovo Device [17aa:20f5] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- + Kernel driver in use: lpc_ich +00: 86 80 17 29 07 00 10 02 03 00 01 06 00 00 80 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 f5 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 10 00 00 80 00 00 00 81 11 00 00 10 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 8b 8b 8b 8b 90 00 00 00 8b 8b 8b 8b f8 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 10 00 0f 3f 01 16 7c 00 e1 15 0c 00 81 16 1c 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 24 0a 00 00 39 00 80 00 2b 1c 0a 00 00 03 00 c0 +b0: 00 00 f0 00 00 00 00 00 08 00 02 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 67 45 00 00 00 ff 00 00 00 00 00 00 +e0: 09 00 0c 10 00 02 c4 03 04 00 00 00 00 00 00 00 +f0: 01 c0 d1 fe 00 00 00 00 86 0f 03 00 00 00 00 00 + +00:1f.2 SATA controller [0106]: Intel Corporation 82801IBM/IEM (ICH9M/ICH9M-E) 4 port SATA Controller [AHCI mode] [8086:2929] (rev 03) (prog-if 01 [AHCI 1.0]) + Subsystem: Lenovo Device [17aa:20f8] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- +
+![iMac5,2]() +
+ +| ***Specifications*** | | +|----------------------------|------------------------------------------------| +| **Manufacturer** | Apple | +| **Name** | iMac 17-inch "Core 2 Duo" 1.83 | +| **Released** | 2006 | +| **Chipset** | Intel Calistoga 945GM | +| **CPU** | Intel Core 2 Duo T5600 | +| **Graphics** | Intel GMA 950 | +| **Display** | 1440x900 TFT | +| **Memory** | 512MB, 1GB (upgradable to 2GB) | +| **Architecture** | x86_64 | +| **EC** | Proprietary | +| **Original boot firmware** | Apple EFI | +| **Intel ME/AMD PSP** | Not present. | +| **Flash chip** | SOIC-8 2MiB (Probably upgradable to 16MiB) | + +``` +W+: Works without blobs; +N: Doesn't work; +W*: Works with blobs; +U: Untested; +P+: Partially works; +P*: Partially works with blobs +``` + +| ***Features*** | | +|----------------|---------------------------------------| +| **Internal flashing with original boot firmware** | U | +| **Display** | U | +| **Audio** | U | +| **RAM Init** | U | +| **External output** | U | +| **Display brightness** | U | + +| ***Payloads supported*** | | +|---------------------------|-----------| +| **GRUB** | Works | +| **SeaBIOS** | Works | +| **SeaBIOS with GRUB** | Works | + +Information to be written soon, but this board is merged in libreboot. + +This board is very similar to the [MacBook2,1](./macbook21.md). + +Just refer back to the [hardware section](./) and [install guides](../install/) diff --git a/site/docs/hardware/index.md b/site/docs/hardware/index.md new file mode 100644 index 0000000..8c807e5 --- /dev/null +++ b/site/docs/hardware/index.md @@ -0,0 +1,115 @@ +--- +title: Hardware compatibility list +x-toc-enable: true +... + +This sections relates to known hardware compatibility in libreboot. + +For installation instructions, refer to [../install/](../install/). + +NOTE: For T60/R60 thinkpads, make sure that it has an Intel GPU, not an ATI GPU +because coreboot lacks native video initialization for the ATI GPUs on these +machines. + +(for later machines like T500, T400, ATI GPU doesn't matter, because it also +has an Intel GPU, and libreboot uses the Intel one) + +Supported hardware +================== + +libreboot currently supports the following systems in this release: + +### Servers (AMD, Intel, x86) + +- [ASUS KGPE-D16 motherboard](kgpe-d16.md) +- [ASUS KFSN4-DRE motherboard](kfsn4-dre.md) + +### Desktops (AMD, Intel, x86) + +- [ASUS KCMA-D8 motherboard](kcma-d8.md) +- [Gigabyte GA-G41M-ES2L motherboard](ga-g41m-es2l.md) +- [Acer G43T-AM3](acer_g43t-am3.md) +- [Intel D510MO and D410PT motherboards](d510mo.md) +- [Apple iMac 5,2](imac52.md) + +### Laptops (Intel, x86) + +- **[Dell Latitute E6400, E6400 XFR and E6400 ATG, all with Nvidia or Intel + GPU](e6400.md) (easy to flash, no disassembly, similar + hardware to X200/T400)** +- ThinkPad X60 / X60S / X60 Tablet +- ThinkPad T60 (with Intel GPU) +- [Lenovo ThinkPad X200 / X200S / X200 Tablet](x200.md) +- Lenovo ThinkPad X301 +- [Lenovo ThinkPad R400](r400.md) +- [Lenovo ThinkPad T400 / T400S](t400.md) +- [Lenovo ThinkPad T500](t500.md) +- [Lenovo ThinkPad W500](t500.md) +- [Lenovo ThinkPad R500](r500.md) +- [Apple MacBook1,1 and MacBook2,1](macbook21.md) + +### Laptops (ARM, with U-Boot payload) + +- [ASUS Chromebook Flip C101 (gru-bob)](../install/chromebooks.md) +- [Samsung Chromebook Plus (v1) (gru-kevin)](../install/chromebooks.md) + +### Emulation + +- [Qemu x86](../misc/emulation.md) +- [Qemu arm64](../misc/emulation.md) + +## Removed boards + +These boards were in Libreboot, but have been removed with the intention of +re-adding them at a later date. They were removed due to issues. List: + +- [ASUS Chromebook C201PA (veyron-speedy)](../install/c201.md) +- [Intel D945GCLF](d945gclf.md) (removed from lbmk, TODO: re-add support) + +TODO: More hardware is supported. See `resources/coreboot/` in lbmk. Update +the above list! + +'Supported' means that the build scripts know how to build ROM images +for these systems, and that the systems have been tested (confirmed +working). There may be exceptions; in other words, this is a list of +'officially' supported systems. + +EC update on i945 (X60, T60) and GM45 (X200, X301, T400, T500, R400, W500, R500) +============================================================== + +It is recommended that you update to the latest EC firmware version. The +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from +libreboot, so we don't actually provide that, but if you still have +Lenovo BIOS then you can just run the Lenovo BIOS update utility, which +will update both the BIOS and EC version. See: + +- [../install/#flashrom](../install/#flashrom) +- + +NOTE: this can only be done when you are using Lenovo BIOS. How to +update the EC firmware while running libreboot is unknown. libreboot +only replaces the BIOS firmware, not EC. + +Updated EC firmware has several advantages e.g. better battery +handling. + +How to find what EC version you have (i945/GM45) +------------------------------------------------ + +In Linux, you can try this: + + grep 'at EC' /proc/asound/cards + +Sample output: + + ThinkPad Console Audio Control at EC reg 0x30, fw 7WHT19WW-3.6 + +7WHT19WW is the version in different notation, use search engine to find +out regular version - in this case it's a 1.06 for x200 tablet + +Alternatively, if `dmidecode` is available, run the following command (as `root`) to +find the currently flashed BIOS version: + + dmidecode -s bios-version + +On a T400 running the latest BIOS this would give `7UET94WW (3.24 )` as result. diff --git a/site/docs/hardware/kcma-d8.md b/site/docs/hardware/kcma-d8.md new file mode 100644 index 0000000..b3065d7 --- /dev/null +++ b/site/docs/hardware/kcma-d8.md @@ -0,0 +1,199 @@ +--- +title: ASUS KCMA-D8 desktop/workstation board +x-toc-enable: true +... + +Introduction +============ + +Specifications available here: + + +Quite a nice board; can have up to 16 Opteron 4200/4300 CPU cores, with up to +64GiB of RAM. It holds its own against more modern machines, especially when +compiling large source trees (for compilers, what you want is high RAM and more +CPU cores). + +This is a desktop board using AMD hardware (Fam10h *and Fam15h* CPUs +available). It can also be used for building a high-powered workstation. +libreboot also supports it. The coreboot port was done by Timothy Pearson of +Raptor Engineering Inc. and, working with them, merged into libreboot many +years ago. + +Note that not all boards are compatible. See [board status](#boardstatus) +below to determine compatibility with your board. + +Flashing instructions can be found at +[../install/](../install/) - note that external +flashing is required (e.g. RPi), if the proprietary (ASUS) firmware is +currently installed. If you already have Libreboot or coreboot, by default +it is possible to re-flash using software running in Linux on the kcma-d8, +without using external hardware. + +If you currently have the ASUS firmware, please ignore the above link and +instead refer to the section below: + +Flashing +======== + +The default ASUS firmware write-protects the flash, so you have to remove the +chip and re-flash it using external hardware. + +It has a 25XX NOR flash (SPI protocol) in a P-DIP 8 socket, which looks like +this: + +![](https://av.libreboot.org/dip8/dip8.jpg) + +The default chip is a 2MiB one, but we recommend upgrading it to a 16MiB chip. + +NOTE: If you're already running libreboot, you probably don't +need to re-flash externally. Refer instead to the generic instructions on +this page: [../install/](../install/) + +Refer to the following guide:\ +[Externally rewrite 25xx NOR flash via SPI protocol](../install/spi.md) + +PCI option ROMs +=============== + +Unlike Libreboot 20160907, Libreboot in newer releases now supports finding and +loading PCI option ROMs automatically, both in GRUB and SeaBIOS on this machine. +This was inherited by libreboot, when the Libreboot project was forked. + +So for example, if you wish to use an add-on graphics card, you can! It's no +problem, and should work just fine. + +CPU coolers +=========== + +With some creativity, standard AM3+ coolers will work fine. + +2 x Socket C32 (LGA1207) available, so you can use 2 CPUs. (up to 32GiB per CPU) + +CPU compatibility +================= + +- Opteron 4100 series: Incompatible +- Opteron 4200 series: Compatible +- Opteron 4300 series: Compatible + +Board status (compatibility) {#boardstatus} +============================ + +There are two ways to identify a supported KCMA-D8 board: + +1. Serial number (sticker attached to the 24-pin ATX power connector) +2. BIOS version (sticker next to CPU slot 1, last four digits) + +Supported boards begin with a serial number of **B9S2xxxxxxxx** or above where +the first character refers to the year of manufacture (A = 2010, B = 2011, etc.) +and the following character the month in hexadecimal (1...9, A, B, C). Thus, any +board produced September 2011 *or later* are compatible with libreboot. Boards +originally shipped with BIOS version **2001** or higher are also compatible. + +For help locating these identifying markers, see [ASUS documentation for determining Opteron 4200 series compatibility](https://web.archive.org/web/20200710022605/https://dlcdnets.asus.com/pub/ASUS/mb/SocketC%281027%29/KCMA-D8/Manual&QVL/How_to_identify_MB_supporting_Opteron_4200_CPU.pdf) + +For more detailed information regarding the coreboot port, see + + +Form factor {#formfactor} +=========== + +This board is ATX form factor. While the [ATX standard, version 2.2](https://web.archive.org/web/20120725150314/http://www.formfactors.org/developer/specs/atx2_2.pdf) +specifies board dimensions 305mm x 244mm, this board measures 305mm x 253mm; +please ensure that your case supports this extra ~cm in width. + +IPMI iKVM module add-on {#ipmi} +======================= + +Don't use it. It uses proprietary firmware and adds a backdoor (remote +out-of-band management chip, similar to the [Intel Management +Engine](../../faq.md#intelme). Fortunately, the firmware is +unsigned (possible to replace) and physically separate from the +mainboard since it's on the add-on module, which you don't have to +install. + +Flash chips {#flashchips} +=========== + +2MiB flash chips are included by default, on these boards. It's on a +P-DIP 8 slot (SPI chip). The flash chip can be upgraded to higher sizes: +4MiB, 8MiB or 16MiB. With at least 8MiB, you could feasibly fit a +compressed linux+initramfs image (BusyBox+Linux system) into CBFS and +boot that, loading it into memory (and nowadays there is LinuxBoot, for which +we would recommend a 16MiB boot flash) + +*DO NOT hot-swap the chip with your bare hands. Use a P-DIP 8 chip +extractor. These can be found online. See +* + +Ideally, you should not hot-swap. Only remove the IC when the system is +powered down and disconnected from mains. + +Native graphics initialization {#graphics} +============================== + +Only text-mode is known to work, but linux(kernel) can initialize the +framebuffer display (if it has KMS - kernel mode setting). + +NOTE: This section relates to the onboard ASpeed GPU. You *can* use an add-on +PCI-E GPU in one of the available slots on the mainboard. Nvidia GTX 780 cards +are what libreboot recommends; it has excellent support in Nouveau (free Linux +kernel / mesa driver for Nvidia cards) and generally works well; however, the +performance won't be as high in Nouveau, compared to the non-free Nvidia driver +because the Nouveau driver can't increase the GPU clock (it doesn't know how, +as of 18 March 2021). + +Current issues {#issues} +============== + +- Opteron 4100 series CPUs are currently incompatible +- LRDIMM memory modules are currently incompatible + (use UDIMMs please) +- Memory initialization is still problematic for some modules. We + recommend avoiding Kingston and Super Talent modules for this reason. + +The coreboot wiki has some information about RAM compatibility. The wiki is +deprecated but the info on it is still correct for this board. Some other +considerations: + +- Booting from USB mass storage devices is currently broken under GRUB. + Consequently, the textmode ROM with SeaBIOS is recommended otherwise + in order to install an operating system you will need a hard disk with + a pre-installed OS or will have to plug in another HDD or CD/DVD + reader in order to boot OS installation media. +- SeaBIOS lacked serial console support out-of-the-box in release 20160907 + and as such a workaround using SGABIOS is necessary. You can find + instructions on how to do this on the + [Notabug issue tracker](http://web.archive.org/web/20210416011941/https://notabug.org/libreboot/libreboot/issues/736) + TODO: test whether this is still the case in libreboot, which uses a newer + version of coreboot nowadays) +- SAS (via PIKE 2008 module) requires non-free option ROM (and + SeaBIOS) to boot from it (theoretically possible to replace, but you + can put a kernel in CBFS or on SATA and boot from that, which + can be on a SAS drive. The linux kernel can use those SAS drives + (via PIKE module) without an option ROM). + NOTE: SeaBIOS can load PCI-E option ROMs, and by default it will do so in + libreboot, so you could use it. However, you could *also* simply + install 16MiB NOR flash with linuxboot payload in it, and use linuxboot + which has the Linux kernel, which can use SAS drives without needing that + option ROM; then it can kexec another linux kernel, which in turn also can + can use those drives. Or just put a standard linux kernel and initramfs + in cbfs and chainload that from GRUB, with the right parameters. +- IPMI iKVM module (optional add-on card) uses proprietary firmware. + Since it's for remote out-of-band management, it's theoretically a + backdoor similar to the Intel Management Engine. Fortunately, unlike + the ME, this firmware is unsigned which means that a free + replacement is theoretically possible. For now, the libreboot + project recommends not installing the module. [This + project](https://github.com/facebook/openbmc) might be interesting + to derive from, for those who want to work on a free replacement. In + practise, out-of-band management isn't very useful anyway (or at + the very least, it's not a major inconvenience to not have it). +- Graphics: only text-mode works. See [\#graphics](#graphics) + +Hardware specifications {#specifications} +----------------------- + +Check the ASUS website. + diff --git a/site/docs/hardware/kfsn4-dre.md b/site/docs/hardware/kfsn4-dre.md new file mode 100644 index 0000000..bb2053f --- /dev/null +++ b/site/docs/hardware/kfsn4-dre.md @@ -0,0 +1,152 @@ +--- +title: ASUS KFSN4-DRE server/workstation board +x-toc-enable: true +... + +
+
+![ASUS KFSN4-DRE]() +
+ +| ***Specifications*** | | +|----------------------------|------------------------------------------------| +| **Manufacturer** | ASUS | +| **Name** | KFSN4-DRE | +| **Released** | ? | +| **Chipset** | nVIDIA nForce Professional 2200 | +| **CPU** | AMD Opteron 2000 series (Barcelona Family) | +| **Graphics** | XGI Z9s VGA Controller | +| **Display** | None. | +| **Memory** | 512MB, 1GB, 2GB, 4GB | +| **Architecture** | x86_64 | +| **Original boot firmware** | AMIBIOS | +| **Intel ME/AMD PSP** | Not present. | +| **Flash chip** | PLCC 1MiB (Upgradable to 2MiB) | + +``` +W+: Works without blobs; +N: Doesn't work; +W*: Works with blobs; +U: Untested; +P+: Partially works; +P*: Partially works with blobs +``` + +| ***Features*** | | +|----------------|---------------------------------------| +| **Internal flashing with original boot firmware** | W+ | +| **Display** | - | +| **Audio** | W+ | +| **RAM Init** | W+ | +| **External output** | W+ | +| **Display brightness** | - | + +| ***Payloads supported*** | | +|---------------------------|-----------------| +| **GRUB** | Partially works | +| **SeaBIOS** | Partially works | +| **SeaBIOS with GRUB** | Partially works | +
+ +This is a server board using AMD hardware (Fam10h). It can also be used +for building a high-powered workstation. Powered by libreboot. + +Flashing instructions can be found at +[../install/\#flashrom](../install/) + +Form factor {#formfactor} +=========== + +These boards use the SSI EEB 3.61 form factor; make sure that your case +supports this. This form factor is similar to E-ATX in that the size is +identical, but the position of the screws are different. + +Flash chips {#flashchips} +=========== + +These boards use LPC flash (not SPI), in a PLCC socket. The default +flash size 1MiB (8Mbits), and can be upgraded to 2MiB (16Mbits). +SST49LF080A is the default that the board uses. SST49LF016C is an +example of a 2MiB (16Mbits) chip, which might work. It is believed that +2MiB (16Mbits) is the maximum size available for the flash chip. + +*DO NOT hot-swap the chip with your bare hands. Use a PLCC chip +extractor. These can be found online. See +* + +Native graphics initialization {#graphics} +============================== + +Native graphics initialization exists (XGI Z9s) for this board. +Framebuffer- and text-mode both work. A serial port is also available. + +Memory +====== + +DDR2 533/667 Registered ECC. 16 slots. Total capacity up to 64GiB. + +Hex-core CPUs {#hexcore} +============= + +PCB revision 1.05G is the latest version of this board and the best one +(the revision number is be printed on the board), if you want to use +dual hex-core CPUs (Opteron 2400/8400 series), though only two board +configurations are believed to support them. Other revisions are +believed to only support dual quad-core CPUs. + +To be sure your board supports a CPU check the official ASUS website here: +. Note: not all CPUs are listed. + +If you are running a Hex-Core CPU on any board version, please contact us. + +Board configurations {#configurations} +============== +There are 7 different configurations of this board: "standard", 2S, iKVM, +iKVM/IST, SAS, SAS/iKVM and SAS/iKVM/IST. + +The 2S boards have two PCI-E slots with the numbers of lanes shared, +making each slot have 8 lanes. + +The iKVM boards are so called because they offer a remote real-time access +to the machine through a removable PCI management card, their hardware is +the same as the non-iKVM ones. + +The SAS versions have a 4-port SAS controller and a four 7-pin SAS connectors +instead of the PCI-E 8x slot which is present in all the other board configurations. +Note: the SAS functionality is **not supported** by libreboot. + +The IST versions with PCB revision 1.05G are the ones who are believed to +support the six core Opteron Istanbul processors (2400 and 8400 series). + +Current issues {#issues} +============== + +- There seems to be a 30 second bootblock delay (observed by + tpearson); the system otherwise boots and works as expected. See + [text/kfsn4-dre/bootlog.txt](text/kfsn4-dre/bootlog.txt) - this uses + the 'simple' bootblock, while tpearson uses the 'normal' + bootblock, which tpearson suspects may be a possible cause. This + person says that they will look into it. [This + config](http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asus/kfsn4-dre/4.0-10101-g039edeb/2015-06-27T03:59:16Z/config.txt;h=4742905c185a93fbda8eb14322dd82c70641aef0;hb=055f5df4e000a97453dfad6c91c2d06ea22b8545) + doesn't have the issue. + +- Text-mode is jittery and it may not be usable, so it's recommended + to flash the BIOS with the coreboot frame-buffer image (kfsn4-dre_corebootfb.rom). + The jitter disappears if using KMS once the kernel starts, but it will + remain, if booting the kernel in text-mode. + +- Booting from USB mass storage devices is not possible; neither GRUB + nor SeaBIOS detect USB drives when present. USB keyboards function + under both GRUB and SeaBIOS, albeit slowly under GRUB (several seconds per + character typed). + +- To install an operating system you will need a hard disk + with a pre-installed OS otherwise you have to plug in another hard disk or + a CD/DVD reader in order to boot a copy of the installer of your OS, since + the USB booting doesn't work. + +Other information +================= + +[specifications](https://web.archive.org/web/20181212180051/http://ftp.tekwind.co.jp/pub/asustw/mb/Socket%20F/KFSN4-DRE/Manual/e3335_kfsn4-dre.pdf) + diff --git a/site/docs/hardware/kgpe-d16.md b/site/docs/hardware/kgpe-d16.md new file mode 100644 index 0000000..8898aff --- /dev/null +++ b/site/docs/hardware/kgpe-d16.md @@ -0,0 +1,212 @@ +--- +title: ASUS KGPE-D16 server/workstation board +x-toc-enable: true +... + +Introduction +============ + +This is a server board using AMD hardware (Fam10h *and Fam15h* CPUs +available). It can also be used for building a high-powered workstation. +Powered by libreboot. The coreboot port was done by Timothy Pearson of +Raptor Engineering Inc. and, working with them (and sponsoring the +work), merged into libreboot. + +*Memory initialization is still problematic, for some modules. We +recommend avoiding Kingston modules.* +*For working configurations see .* + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) - note that external +flashing is required, if the proprietary (ASUS) firmware is +currently installed. If you already have libreboot, by default it is +possible to re-flash using software running in Linux on the +KGPE-D16, without using external hardware. + +CPU compatibility +================= + +Opteron 62xx and 63xx CPUs work just fine. + +Board status (compatibility) {#boardstatus} +============================ + +See . + +Form factor {#formfactor} +=========== + +These boards use the SSI EEB 3.61 form factor; make sure that your case +supports this. This form factor is similar to E-ATX in that the size is +identical, but the position of the screws are different. + +IPMI iKVM module add-on {#ipmi} +======================= + +Don't use it. It uses proprietary firmware and adds a backdoor (remote +out-of-band management chip, similar to the [Intel Management +Engine](../../faq.md#intelme). Fortunately, the firmware is +unsigned (possibly to replace) and physically separate from the +mainboard since it's on the add-on module, which you don't have to +install. + +Flash chips {#flashchips} +=========== + +2MiB flash chips are included by default, on these boards. It's on a +P-DIP 8 slot (SPI chip). The flash chip can be upgraded to higher sizes: +4MiB, 8MiB or 16MiB. With at least 8MiB, you could feasibly fit a +compressed linux+initramfs image (BusyBox+Linux system) into CBFS and +boot that, loading it into memory. + +libreboot has configs for 2, 4, 8 and 16 MiB flash chip sizes (default +flash chip is 2MiB). + +*DO NOT hot-swap the chip with your bare hands. Use a P-DIP 8 chip +extractor. These can be found online. See +* + +This guide shows how to flash the chip:\ +[25xx NOR flashing guide](../install/spi.md) + +Native graphics initialization {#graphics} +============================== + +Only text-mode is known to work, but linux(kernel) can initialize the +framebuffer display (if it has KMS - kernel mode setting). + +Current issues {#issues} +============== + +- LRDIMM memory modules are currently incompatible +- SAS (via PIKE 2008 module) requires non-free option ROM (and + SeaBIOS) to boot from it (theoretically possible to replace, but you + can put a kernel in CBFS or on SATA and boot from that, which + can be on a SAS drive. The linux kernel can use those SAS drives + (via PIKE module) without an option ROM). +- SeaBIOS lacked serial console support out-of-the-box in release 20160907 + and as such a workaround using SGABIOS is necessary. You can find + instructions on how to do this on the + [Notabug issue tracker](http://web.archive.org/web/20210416011941/https://notabug.org/libreboot/libreboot/issues/736) +- IPMI iKVM module (optional add-on card) uses proprietary firmware. + Since it's for remote out-of-band management, it's theoretically a + backdoor similar to the Intel Management Engine. Fortunately, unlike + the ME, this firmware is unsigned which means that a free + replacement is theoretically possible. For now, the libreboot + project recommends not installing the module. [This + project](https://github.com/facebook/openbmc) might be interesting + to derive from, for those who want to work on a free replacement. In + practise, out-of-band management isn't very useful anyway (or at + the very least, it's not a major inconvenience to not have it). +- Graphics: only text-mode works. See [\#graphics](#graphics) + +Hardware specifications {#specifications} +----------------------- + +The information here is adapted, from the ASUS website. + +### Processor / system bus + +- 2 CPU sockets (G34 compatible) +- HyperTransport™ Technology 3.0 +- CPUs supported: + - AMD Opteron 6100 series (Fam10h. No IOMMU support. *Not* + recommended - old. View errata datasheet here: + ) + - AMD Opteron 6200 series (Fam15h, with full IOMMU support in + libreboot. + - AMD Opteron 6300 series (Fam15h, with full IOMMU support in + libreboot. +- 6.4 GT/s per link (triple link) + +### Core logic + +- AMD SR5690 +- AMD SP5100 + +### Memory compatibility (with libreboot) + +- *Total Slots:* 16 (4-channel per CPU, 8 DIMM per CPU), ECC +- *Capacity:* Maximum up to 256GB RDIMM (Tested max 128GB) +- *Memory Type that is compatible:* + - DDR3 1600/1333/1066/800 UDIMM\* + - DDR3 1600/1333/1066/800 RDIMM\* +- *Compatible sizes per memory module:* + - 16GB, 8GB, 4GB, 3GB, 2GB, 1GB RDIMM + - 8GB, 4GB, 2GB, 1GB UDIMM + +### Expansion slots + +- *Total slot:* 6 +- *Slot Location 1:* PCI 32bit/33MHz +- *Slot Location 2:* PCI-E x16 (Gen2 X8 Link) +- *Slot Location 3:* PCI-E x16 (Gen2 X16 Link), Auto switch to x8 + link if slot 2 is occupied +- *Slot Location 4:* PCI-E x8 (Gen2 X4 Link) +- *Slot Location 5:* PCI-E x16 (Gen2 X16 Link) +- *Slot Location 6:* PCI-E x16 (Gen2 X16 Link), Auto turn off if + slot 5 is occupied, For 1U FH/FL Card, MIO supported +- *Additional Slot 1:* PIKE slot (for SAS drives. See notes above) +- Follow SSI Location\# + +### Form factor {#form-factor} + +- SSI EEB 3.61 (12"x13") + +### ASUS features + +- Fan Speed Control +- Rack Ready (Rack and Pedestal dual use) + +### Storage + +- *SATA controller:* + - AMD SP5100 + - 6 x SATA2 300MB/s +- *SAS/SATA Controller:* + - ASUS PIKE2008 3Gbps 8-port SAS card included + +### Networking + +- 2 x Intel® 82574L + 1 x Mgmt LAN + +### Graphics + +- Aspeed AST2050 with 8MB VRAM + +### On board I/O + +- 1 x PSU Power Connector (24-pin SSI power connector + 8-pin SSI + 12V + 8-pin SSI 12V power connector) +- 1 x Management Connector , Onboard socket for management card +- 3 x USB pin header , Up to 6 Devices +- 1 x Internal A Type USB Port +- 8 x Fan Header , 4pin (3pin/4pin fan dual support) +- 2 x SMBus +- 1 x Serial Port Header +- 1 x TPM header +- 1 x PS/2 KB/MS port + +### Back I/O ports + +- 1 x External Serial Port +- 2 x External USB Port +- 1 x VGA Port +- 2 x RJ-45 +- 1 x PS/2 KB/Mouse + +### Environment + +- *Operation temperature:* 10C \~ 35C +- *Non operation temperature:* -40C \~ 70C +- *Non operation humidity:* 20% \~ 90% ( Non condensing) + +### Monitoring + +- CPU temperatures +- Fan speed (RPM) + +### Note: + +- \* DDR3 1600 can only be supported with AMD Opteron 6300/6200 series + processor diff --git a/site/docs/hardware/mac_address.md b/site/docs/hardware/mac_address.md new file mode 100644 index 0000000..bc9f24d --- /dev/null +++ b/site/docs/hardware/mac_address.md @@ -0,0 +1,108 @@ +--- +title: Changing the MAC address +x-toc-enable: true +... + +Introduction (GM45+e1000) +========================= + +This section is applicable to all libreboot-supported laptops with the +mobile 4 series chipset (as shown in `$ lspci`) +that use the e1000 ethernet controller (e.g. T400, X200). +The R500 is an exception to this as it does not use the built-in e1000. + +On all these laptops, the +[MAC address](https://en.wikipedia.org/wiki/MAC_address) +for the built-in gigabit ethernet controller is stored inside the flash chip, +along with libreboot and other configuration data. Therefore, installing +libreboot will overwrite it. + +Thus, for these laptops, prebuilt libreboot already contains a generic +MAC address in the configuration section. This address is `00:f5:f0:40:71:fe +in builds before 2018-01-16 and `00:4c:69:62:72:65` (see the ascii character +set) afterwards. +Unless you change it, your computer will boot and use it. This can lead +to network problems if you have more than one libreboot computer on +the same layer2 network (e.g. on the same network switch). The switch +(postman) will simply not know who to deliver to as the MAC (house) addresses +will be the same. + +To prevent these address clashes, you can either modify prebuilt libreboot +to use an address of your own choosing or you can change the address in your +operating system's boot scripts. + +In either case, it is a good idea to write down the address that your +computer originally had. + +Obtaining the existing MAC address +================================== + +The existing MAC address may be obtained by the following methods: + +1. Run `ip link` or `ifconfig` in a terminal/console/shell; + find your ethernet device (e.g., **enpXXX** or **ethXXX**), + and look for a set of 12 colon-delimited + [hexadecimal digits](https://en.wikipedia.org/wiki/Hexadecimal). + For example: `00:f3:f0:45:91:fe`. + + * `$ ip link + + ... link/ether ??:??:??:??:??:?? brd ... + + * Alternatively: + + ifconfig + + ... ether ??:??:??:??:??:?? txqueuelen ... + + +2. Otherwise you can read the white label that is often found on the + motherboard under the memory sticks: + ![](https://av.libreboot.org/t400/macaddress1.jpg) + +3. The MAC address is usually listed on the laptop chassis as well. This one + will be incorrect if the motherboard was changed and the stickers were not + updated. + +Changing the MAC address in the operating system +================================================ + +There are three portable ways of doing so: + +1. Using the new iproute2 package: + + ip link set down + + ip link set dev address 00:4c:69:62:72:65 + + ip link set up + + +2. Using the old `ifconfig` command: + + ifconfig hw ether 00:4c:69:62:72:65 + + +3. Using the macchanger package. + +You can use use of these three methods in your operating system's +init scripts or you can use your operating system's own networking +configuration. Refer to your operating system's documentation for +how to do this. + +Changing the MAC address on X200/T400/T500/W500 +=============================================== + +On GM45 laptops with ICH9M southbridge and Intel PHY module, the MAC address +is hardcoded in boot flash, which means it can be changed if you re-flash. + +See [ich9utils documentation](../install/ich9utils.md) + +If *all* you want to do is change the MAC address, you might try `nvmutil` +instead. See notes below: + +Also see [nvmutil documentation](../install/nvmutil.md) + +The nvmutil utility is yet another utility provided by Libreboot, for +changing your MAC address. It is a standalone utility, that operates +only on pre-assembled GbE files. diff --git a/site/docs/hardware/macbook21.md b/site/docs/hardware/macbook21.md new file mode 100644 index 0000000..97f12d1 --- /dev/null +++ b/site/docs/hardware/macbook21.md @@ -0,0 +1,343 @@ +--- +title: MacBook2,1 and MacBook1,1 +x-toc-enable: true +... + +
+
+![MacBook2,1]() +
+ +| ***Specifications*** | | +|----------------------------|------------------------------------------------| +| **Manufacturer** | Apple | +| **Name** | Late 2006/Mid 2007 MacBook "Core 2 Duo" / Early + 2006 MacBook "Core Duo" | +| **Released** | 2006/2007 | +| **Chipset** | Intel Calistoga 945GM | +| **CPU** | Intel Core 2 Duo or Intel Core Duo on + original MacBooks | +| **Graphics** | Intel GMA 950 | +| **Display** | 1280x800 TFT | +| **Memory** | 512MB, 1GB (upgradable to 4GB with 3GB usable) | +| **Architecture** | x86_64 | +| **EC** | Proprietary | +| **Original boot firmware** | Apple EFI | +| **Intel ME/AMD PSP** | Not present. | +| **Flash chip** | SOIC-8 2MiB (Upgradable to 16MiB) | + +``` +W+: Works without blobs; +N: Doesn't work; +W*: Works with blobs; +U: Untested; +P+: Partially works; +P*: Partially works with blobs +``` + +| ***Features*** | | +|----------------|---------------------------------------| +| **Internal flashing with original boot firmware** | W+ | +| **Display** | W+ | +| **Audio** | W+ | +| **RAM Init** | W+ | +| **External output** | W+ | +| **Display brightness** | P+ | + +| ***Payloads supported*** | | +|---------------------------|-----------| +| **GRUB** | Works | +| **SeaBIOS** | Works | +| **SeaBIOS with GRUB** | Works | +
+The MacBook1,1 and MacBook2,1 are very similar to the +ThinkPad X60. It shares some hardware with the X60 such as the chipset. + +You do not need to use external flashing equipment when flashing the MacBook2,1 +but the MacBook1,1 requires external flashing equipment while running Apple EFI +firmware. + +MacBook2,1 laptops come with Core 2 Duo processors +which support 64-bit operating systems (and 32-bit). The MacBook1,1 +uses Core Duo processors (supports 32-bit OS but not 64-bit), and it is +believed that this is the only difference. + +Compatibility +============= + +The following pages list many models of MacBook1,1 and MacBook2,1: + +* +* + +Models +------ + +Specifically (Order No. / Model No. / CPU) for the MacBook1,1: + +* MA255LL/A / A1181 (EMC 2092) / Core Duo T2500 *(tested - working)* +* MA254LL/A / A1181 (EMC 2092) / Core Duo T2400 *(tested - working)* +* MA472LL/A / A1181 (EMC 2092) / Core Duo T2500 (untested) + +For the MacBook2,1: + +* MA699LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T5600 *(tested - + working)* +* MA701LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T7200 *(tested - + working)* +* MB061LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7200 (untested) +* MA700LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T7200 *(tested - + working)* +* MB063LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7400 *(tested - working)* +* MB062LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7400 *(tested - + working)* + +It's believed that all MacBook2,1 and MacBook1,1 models work fine with +Libreboot. If there's a model not in the list or not confirmed working +here and you happen to have that model and that model works with Libreboot +then don't forget to [send a patch](../../git.md), confirming that it +actually works! + +Internal flashing +================= + +MacBook2,1 can always be flashed internally, even if running Apple firmware: + + sudo flashrom -p internal:laptop=force_I_want_a_brick,boardmismatch=force -w your.rom + +The MacBook1,1 can't be flashed internally if running the Apple EFI firmware. +You must flash externally. + +External flashing +================= + +MacBook1,1 requires external flashing, if running the default Apple firmware. +MacBook2,1 can be flashed internally, regardless. +If running coreboot or libreboot you can already internally re-flash. + +[This page shows disassembly +guides](https://www.ifixit.com/Device/MacBook_Core_2_Duo) + +Locate the flash. It'll be a SOIC8, which looks like this: + +![](https://av.libreboot.org/chip/soic8.jpg) + +The chip is located under the motherboard. [How to remove the +motherboard](https://www.ifixit.com/Guide/MacBook+Core+2+Duo+PRAM+Battery+Replacement/529). + +Refer to the following guide:\ +[Externally rewrite 25xx NOR flash via SPI protocol](../install/spi.md) + +OSes using Linux on Apple EFI firmware +====================================== + +You have 2 choices for booting up OSes using Linux as their kernel +on the MacBook: + +* Boot via USB ; + +* Boot via a CD or DVD. + +Boot via a CD or DVD +-------------------- + +The Apple EFI firmware contains a PC BIOS emulation layer for booting +Microsoft Windows on CDs and DVDs. That emulation layer **only** works +if booting from a CD/DVD or from the hard drive. The MacBook will **not** +boot MBR bootloaders from USB, which is why booting from a CD or DVD is +easier than booting from a USB. + +* First, burn your ISO to a CD or DVD ; + +* Reboot and while rebooting, hold down the Alt/Control key, a boot menu +should pop up, requesting you to choose which device to boot from ; + +* Select the CD/DVD icon with 'Windows' as the label (the Apple EFI firmware +elways recognises CDs/DVDs using MBR as 'Windows', because the emulation +layer was made specifically for booting Microsoft Windows as part of +BootCamp, a tool which allowed dual-booting Windows and OS X) ; + +* Install it like you normally would (If there's an OS X installation then +it's highly recommended to save all your data and wipe it. Libreboot isn't +able and will never be able to boot OS X) ; + +* While rebooting, hold Alt/Control once again, and select the hard disk +icon with the 'Windows' label, after each subsequent boot, the Apple EFI +should boot up properly automatically. + +*If you installed your OS alongside OS X then you won't be able to boot +to it using GRUB, despite the fact that it does sometimes show up. You +also won't be able to boot it up when using Libreboot.* + +Boot via USB +------------ + +This method is harder than booting from a CD/DVD and may soft-brick your +MacBook but it's the only way to boot up successfully from a USB. + +The PC BIOS emulation layer found in the Apple EFI firmware doesn't work +when booting up from a USB stick. Despite the fact that the +MacBook2,1 does use a 64-Bit processor, the firmware only supports booting +32-Bit EFI devices, meaning you're stuck with 32-Bit OSes and rare +64-Bit OSes which have ISOs that still support booting from 32-Bit EFI. +Meanwhile, GRUB fully supports booting up 64-Bit OSes on 32-Bit EFI. + +* First, search for an ISO that supports 32-Bit EFI while being 64-Bit or +a normal 32-Bit ISO and put it in your USB stick ; + +* Reboot and while rebooting, hold down the Alt/Control key, a boot menu +should pop up, requesting you to choose which device to boot from ; + +* Select the USB icon ; + +* Install it like you normally would (If there's an OS X installation then +it's highly recommended to save all your data and wipe it. Libreboot isn't +able and will never be able to boot OS X) ; + +* Reboot. It should boot up to your newly-installed system if you wiped OS X, +else, hold Alt/Control and select the correct boot device ; + +* Flash Libreboot. DO NOT REBOOT AGAIN BEFORE FLASHING. Sometimes the +firmware can get confused, because Apple never intended to boot other +EFI OSes other than OS X, as such there's a chance that your MacBook can +become [soft-bricked](https://apple.stackexchange.com/questions/408104/late-2006-macbook-doesnt-turn-on-fan-spinning-but-no-chime/409754). +If that is the case then dissassemble it and remove +the CMOS/PRAM battery, wait a few minutes, and put it back in. + +*If you want to install Libreboot with the SeaBIOS payload then be sure +to reconfigure GRUB2 correctly, else your system won't boot.* + +Coreboot wiki page +================== + +The following page has some information: + +* + +Issues and solutions/workarounds +================================ + +There is one mouse button only, however multiple finger tapping +works. The Apple logo on the +back is a hole, exposing the backlight, which means that it glows. You +should [cover it up](http://cweiske.de/tagebuch/tuxbook.htm). + +*The MacBook2,1 comes with a webcam which does not work with free +software. Webcams are a privacy and security risk; cover it up! Or +remove it.* + +Make it overheat less +--------------------- + +NOTE: on newer libreboot revisions, this section is less relevant, because C3 +states are supported now. However, this section may still be useful, so it will +be retained. + +The MacBook2,1 overheats a lot with libreboot, we still don't know why but a simple workaround is to install macfanctld. + +Macfanctld is available on the default repos of many distributions. + +For example, to install macfanctld on an Arch-based distro, you would run as root + + pacman -S macfanctld + +and don't forget to enable it by using `systemctl` or by a script that will run macfanctld if using runit. + +Then, you want to install powertop and tlp. +And then, run the following on battery + + sudo tlp start && sudo powertop --calibrate + +Then, after quitting powertop, run : + + sudo powertop --auto-tune + +Now, configure tlp, edit the `/etc/tlp.conf` and uncomment/add/modify the following: + +``` +CPU_BOOST_ON_AC=1 +CPU_BOOST_ON_BAT=0 + +SCHED_POWERSAVE_ON_AC=0 +SCHED_POWERSAVE_ON_BAT=1 + +PLATFORM_PROFILE_ON_AC=performance +PLATFORM_PROFILE_ON_BAT=low-power +``` + +The MacBook will still overheat, just less. + +Enable AltGr +------------ + +The keyboard has a keypad enter instead of an AltGr. The first key on +the right side of the spacebar is the Apple "command" key. On its +right is the keypad enter. We can make it act as an AltGr. + +If your operating system is Debian or other dpkg-based distribution, +there is an easy solution. Under root (or sudo) run + + dpkg-reconfigure keyboard-configuration + +and select the option "apple laptop", leave other settings as their +defaults until you are given the option "Use Keypad Enter as +AltGr". Select this. The keypad enter key will then act as an AltGr +everywhere. + + +For Arch-based distributions you can enable AltGr manually. Simply add the +line: + + KEYMAP_TOGGLE=lv3:enter_switch + +to the file /etc/vconsole.conf and then restart the computer. + +Make touchpad more responsive +----------------------------- + +Linux kernels of version 3.15 or lower might make the touchpad +extremely sluggish. A user reported that they could get better +response from the touchpad with the following in their xorg.conf: + +``` + Section "InputClass" + Identifier "Synaptics Touchpad" + Driver "synaptics" + MatchIsTouchpad "on" + MatchDevicePath "/dev/input/event*" + Driver "synaptics" + The next two values determine how much pressure one needs + for tapping, moving the cursor and other events. + Option "FingerLow" "10" + Option "FingerHigh" "15" + Do not emulate mouse buttons in the touchpad corners. + Option "RTCornerButton" "0" + Option "RBCornerButton" "0" + Option "LTCornerButton" "0" + Option "LBCornerButton" "0" + One finger tap = left-click + Option "TapButton1" "1" + Two fingers tap = right-click + Option "TapButton2" "3" + Three fingers tap = middle-mouse + Option "TapButton3" "2" + Try to not count the palm of the hand landing on the touchpad + as a tap. Not sure if helps. + Option "PalmDetect" "1" + The following modifies how long and how fast scrolling continues + after lifting the finger when scrolling + Option "CoastingSpeed" "20" + Option "CoastingFriction" "200" + Smaller number means that the finger has to travel less distance + for it to count as cursor movement. Larger number prevents cursor + shaking. + Option "HorizHysteresis" "10" + Option "VertHysteresis" "10" + Prevent two-finger scrolling. Very jerky movement + Option "HorizTwoFingerScroll" "0" + Option "VertTwoFingerScroll" "0" + Use edge scrolling + Option "HorizEdgeScroll" "1" + Option "VertEdgeScroll" "1" + EndSection +``` diff --git a/site/docs/hardware/r400.md b/site/docs/hardware/r400.md new file mode 100644 index 0000000..61492ff --- /dev/null +++ b/site/docs/hardware/r400.md @@ -0,0 +1,105 @@ +--- +title: ThinkPad R400 +x-toc-enable: true +... + +
+
+![ThinkPad R400]() +
+ +| ***Specifications*** | | +|----------------------------|------------------------------------------------| +| **Manufacturer** | Lenovo | +| **Name** | ThinkPad R400 | +| **Released** | 2009 | +| **Chipset** | Intel Cantiga GM45 | +| **CPU** | Intel Core 2 Duo (Penryn/Merom family) or + Celeron M (Merom L family) | +| **Graphics** | Intel GMA 4500MHD (and ATI Mobility Radeon HD + 3470 or nVIDIA + GeForce 9300M on some models) | +| **Display** | 1280x800/1440x900 TFT | +| **Memory** | Up to 8GB | +| **Architecture** | x86_64 | +| **EC** | Proprietary | +| **Original boot firmware** | LenovoBIOS | +| **Intel ME/AMD PSP** | Present. Can be completly disabled. | +| **Flash chip** | SOIC-8/SOIC-16 4MiB/8MiB (Upgradable to 16MiB) | + +``` +W+: Works without blobs; +N: Doesn't work; +W*: Works with blobs; +U: Untested; +P+: Partially works; +P*: Partially works with blobs +``` + +| ***Features*** | | +|----------------|---------------------------------------| +| **Internal flashing with original boot firmware** | N | +| **Display** | W+ | +| **Audio** | W+ | +| **RAM Init** | W+ | +| **External output** | W+ | +| **Display brightness** | P+ | + +| ***Payloads supported*** | | +|---------------------------|-----------| +| **GRUB** | Works | +| **SeaBIOS** | Works | +| **SeaBIOS with GRUB** | Works | +
+Dell Latitude E6400 +=================== + +**If you haven't bought an R400 yet: the [Dell Latitude +E6400](../../news/e6400.md) is much easier to flash; no disassembly required, +it can be flashed entirely in software from Dell BIOS to Libreboot. It is the +same hardware generation (GM45), with same CPUs, video processor, etc.** + +Introduction +============ + +It is believed that all or most R400 laptops are compatible. See notes +about [CPU +compatibility](../install/r400_external.html#cpu_compatibility) for +potential incompatibilities. + +There are two possible flash chip sizes for the R400: 4MiB (32Mbit) or +8MiB (64Mbit). This can be identified by the type of flash chip below +the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. + +*The R400 laptops come with the ME (and sometimes AMT in addition) +before flashing libreboot. libreboot disables and removes it by using a +modified descriptor: see [../install/ich9utils.md](../install/ich9utils.md)* +(contains notes, plus instructions) + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +EC update {#ecupdate} +========= + +It is recommended that you update to the latest EC firmware version. The +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from +libreboot, so we don't actually provide that, but if you still have +Lenovo BIOS then you can just run the Lenovo BIOS update utility, which +will update both the BIOS and EC version. See: + +- [../install/#flashrom](../install/#flashrom) +- + +NOTE: this can only be done when you are using Lenovo BIOS. How to +update the EC firmware while running libreboot is unknown. libreboot +only replaces the BIOS firmware, not EC. + +Updated EC firmware has several advantages e.g. bettery battery +handling. + +The R400 is almost identical to the X200, code-wise. See +[x200.md](x200.md). + +TODO: put hardware register logs here like on the [X200](x200.md) and +[T400](t400.md) page. diff --git a/site/docs/hardware/r500.md b/site/docs/hardware/r500.md new file mode 100644 index 0000000..3454432 --- /dev/null +++ b/site/docs/hardware/r500.md @@ -0,0 +1,81 @@ +--- +title: ThinkPad R500 +x-toc-enable: true +... + +
+
+![ThinkPad R500]() +
+ +| ***Specifications*** | | +|----------------------------|------------------------------------------------| +| **Manufacturer** | Lenovo | +| **Name** | ThinkPad R500 | +| **Released** | 2009 | +| **Chipset** | Intel Cantiga GM45 | +| **CPU** | Intel Core 2 Duo (Penryn/Merom family) or + Celeron M (Merom L family) | +| **Graphics** | Intel GMA 4500MHD (or ATI Mobility Radeon HD + 3470 on some models) | +| **Display** | 1280x800/1680x1050 TFT | +| **Memory** | 512MB, 2GB or 4GB (Upgradable to 8GB) | +| **Architecture** | x86_64 | +| **EC** | Proprietary | +| **Original boot firmware** | LenovoBIOS | +| **Intel ME/AMD PSP** | Present. Can be completly disabled. | +| **Flash chip** | SOIC-8/SOIC-16/WSON-8 4MiB/8MiB (Upgradable + to 16MiB) | +``` +W+: Works without blobs; +N: Doesn't work; +W*: Works with blobs; +U: Untested; +P+: Partially works; +P*: Partially works with blobs +``` + +| ***Features*** | | +|----------------|---------------------------------------| +| **Internal flashing with original boot firmware** | N | +| **Display** | W+ | +| **Audio** | W+ | +| **RAM Init** | W+ | +| **External output** | W+ | +| **Display brightness** | P+ | + +| ***Payloads supported*** | | +|---------------------------|-----------| +| **GRUB** | Works | +| **SeaBIOS** | Works | +| **SeaBIOS with GRUB** | Works | +
+Dell Latitude E6400 +=================== + +**If you haven't bought an R500 yet: the [Dell Latitude +E6400](../../news/e6400.md) is much easier to flash; no disassembly required, +it can be flashed entirely in software from Dell BIOS to Libreboot. It is the +same hardware generation (GM45), with same CPUs, video processor, etc.** + +Introduction +============ + +This board as basically identical to the T500, and has very similar disassembly. +You must take it apart and flash the chip externally. + +The chip is 4MiB NOR flash (SPI protocol) is SOIC8 form factory. + +Refer to the following guide:\ +[Externally rewrite 25xx NOR flash via SPI protocol](../install/spi.md) + +Unlike other GM45+ICH9M thinkpads in libreboot, the R500 doesn't have an Intel +PHY (for Gigabit Ethernet). However, libreboot still includes an Intel flash +descriptor, but with just the descriptor and BIOS region. The `ich9gen` program +supports this fully. + +Therefore, you do not have to worry about the MAC address. The onboard NIC for +ethernet is made by Broadcom (and works in linux-libre). + +Refer to T500 disassembly guide. The R500 disassembly procedure is almost +identical. diff --git a/site/docs/hardware/t400.md b/site/docs/hardware/t400.md new file mode 100644 index 0000000..e385311 --- /dev/null +++ b/site/docs/hardware/t400.md @@ -0,0 +1,101 @@ +--- +title: ThinkPad T400 +x-toc-enable: true +... + +
+
+ThinkPad T400 +
+ +| ***Specifications*** | | +|----------------------------|------------------------------------------------| +| **Manufacturer** | Lenovo | +| **Name** | ThinkPad T400 | +| **Released** | 2009 | +| **Chipset** | Intel Cantiga GM45 | +| **CPU** | Intel Core 2 Duo (Penryn family). A Quad-core + mod exists, replacing the Core 2 Duo with a Core Quad | +| **Graphics** | Intel GMA 4500MHD (and ATI Mobility Radeon HD + 3650 on some models) | +| **Display** | 1280x800/1440x900 TFT | +| **Memory** | 2 or 4GB (Upgradable to 8GB) | +| **Architecture** | x86_64 | +| **EC** | Proprietary | +| **Original boot firmware** | LenovoBIOS | +| **Intel ME/AMD PSP** | Present. Can be completly disabled. | +| **Flash chip** | SOIC-8/SOIC-16/WSON-8 4MiB/8MiB (Upgradable + to 16MiB) | +``` +W+: Works without blobs; +N: Doesn't work; +W*: Works with blobs; +U: Untested; +P+: Partially works; +P*: Partially works with blobs +``` + +| ***Features*** | | +|----------------|---------------------------------------| +| **Internal flashing with original boot firmware** | N | +| **Display** | W+ | +| **Audio** | W+ | +| **RAM Init** | W+ | +| **External output** | W+ | +| **Display brightness** | P+ | + +| ***Payloads supported*** | | +|---------------------------|-----------| +| **GRUB** | Works | +| **SeaBIOS** | Works | +| **SeaBIOS with GRUB** | Works | +
+Dell Latitude E6400 +=================== + +**If you haven't bought an T400 yet: the [Dell Latitude +E6400](../../news/e6400.md) is much easier to flash; no disassembly required, +it can be flashed entirely in software from Dell BIOS to Libreboot. It is the +same hardware generation (GM45), with same CPUs, video processor, etc.** + +Introduction +============ + +It is believed that all or most laptops of the model T400 are compatible. See notes +about [CPU +compatibility](../install/t400_external.html#cpu_compatibility) for +potential incompatibilities. + +There are two possible flash chip sizes for the T400: 4MiB (32Mbit) or +8MiB (64Mbit). This can be identified by the type of flash chip below +the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. + +*The T400 laptops come with the ME (and sometimes AMT in addition) +before flashing libreboot. libreboot disables and removes it by using a +modified descriptor: see [../install/ich9utils.md](../install/ich9utils.md)* +(contains notes, plus instructions) + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +EC update {#ecupdate} +========= + +It is recommended that you update to the latest EC firmware version. The +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from +libreboot, so we don't actually provide that, but if you still have +Lenovo BIOS then you can just run the Lenovo BIOS update utility, which +will update both the BIOS and EC version. See: + +- [../install/#flashrom](../install/#flashrom) +- + +NOTE: this can only be done when you are using Lenovo BIOS. How to +update the EC firmware while running libreboot is unknown. libreboot +only replaces the BIOS firmware, not EC. + +Updated EC firmware has several advantages e.g. bettery battery +handling. + +The T400 is almost identical to the X200, code-wise. See +[x200.md](x200.md). diff --git a/site/docs/hardware/t500.md b/site/docs/hardware/t500.md new file mode 100644 index 0000000..5e16608 --- /dev/null +++ b/site/docs/hardware/t500.md @@ -0,0 +1,103 @@ +--- +title: ThinkPad T500 +x-toc-enable: true +... + +
+
+ThinkPad T500 +
+ +| ***Specifications*** | | +|----------------------------|------------------------------------------------| +| **Manufacturer** | Lenovo | +| **Name** | ThinkPad T500 | +| **Released** | 2009 | +| **Chipset** | Intel Cantiga GM45 | +| **CPU** | Intel Core 2 Duo (Penryn family). A Quad-core + mod exists, replacing the Core 2 Duo with a Core Quad | +| **Graphics** | Intel GMA 4500MHD (and ATI Mobility Radeon HD + 3650 on some models) | +| **Display** | 1280x800/1680x1050/1920x1200 TFT | +| **Memory** | 2 or 4GB (Upgradable to 8GB) | +| **Architecture** | x86_64 | +| **EC** | Proprietary | +| **Original boot firmware** | LenovoBIOS | +| **Intel ME/AMD PSP** | Present. Can be completly disabled. | +| **Flash chip** | SOIC-8/SOIC-16/WSON-8 4MiB/8MiB (Upgradable + to 16MiB) | +``` +W+: Works without blobs; +N: Doesn't work; +W*: Works with blobs; +U: Untested; +P+: Partially works; +P*: Partially works with blobs +``` + +| ***Features*** | | +|----------------|---------------------------------------| +| **Internal flashing with original boot firmware** | N | +| **Display** | W+ | +| **Audio** | W+ | +| **RAM Init** | W+ | +| **External output** | W+ | +| **Display brightness** | P+ | + +| ***Payloads supported*** | | +|---------------------------|-----------| +| **GRUB** | Works | +| **SeaBIOS** | Works | +| **SeaBIOS with GRUB** | Works | +
+Dell Latitude E6400 +=================== + +**If you haven't bought an T500 yet: the [Dell Latitude +E6400](../../news/e6400.md) is much easier to flash; no disassembly required, +it can be flashed entirely in software from Dell BIOS to Libreboot. It is the +same hardware generation (GM45), with same CPUs, video processor, etc.** + +Introduction +============ + +It is believed that all or most T500 laptops are compatible. See notes +about [CPU +compatibility](../install/t500_external.html#cpu_compatibility) for +potential incompatibilities. + +W500 is also compatible, and mostly the same design as T500. + +There are two possible flash chip sizes for the T500: 4MiB (32Mbit) or +8MiB (64Mbit). This can be identified by the type of flash chip below +the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. + +*The T500 laptops come with the ME (and sometimes AMT in addition) +before flashing libreboot. libreboot disables and removes it by using a +modified descriptor: see [../install/ich9utils.md](../install/ich9utils.md)* +(contains notes, plus instructions) + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +EC update {#ecupdate} +========= + +It is recommended that you update to the latest EC firmware version. The +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from +libreboot, so we don't actually provide that, but if you still have +Lenovo BIOS then you can just run the Lenovo BIOS update utility, which +will update both the BIOS and EC version. See: + +- [../install/#flashrom](../install/#flashrom) +- + +NOTE: this can only be done when you are using Lenovo BIOS. How to +update the EC firmware while running libreboot is unknown. libreboot +only replaces the BIOS firmware, not EC. + +Updated EC firmware has several advantages e.g. bettery battery +handling. + +The T500 is almost identical to the X200, code-wise. See +[x200.md](x200.md). diff --git a/site/docs/hardware/text/kfsn4-dre/bootlog.txt b/site/docs/hardware/text/kfsn4-dre/bootlog.txt new file mode 100644 index 0000000..ea6722d --- /dev/null +++ b/site/docs/hardware/text/kfsn4-dre/bootlog.txt @@ -0,0 +1,3871 @@ +*****TEXT MODE ROM IMAGE***** + + + +coreboot-4.0 Fri Jun 26 20:19:07 UTC 2015 romstage starting... +BSP Family_Model: 00100f21 +*sysinfo range: [000c4000,000c6899] +bsp_apicid = 00 +cpu_init_detectedx = 00000000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: 'cpu_microcode_blob.bin' not found. +[microcode] microcode file not found. Skipping updates. +cpuSetAMDMSR done +Enter amd_ht_init() +AMD_CB_EventNotify() + event class: 05 + event: 1004 + data: 04 00 00 01 +AMD_CB_EventNotify() + event class: 05 + event: 2006 + data: 04 00 01 00 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Exit amd_ht_init() +cpuSetAMDPCI 00 done +cpuSetAMDPCI 01 done +Prep FID/VID Node:00 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f23 + F3xD8: 03001c14 + F3xDC: 00005428 +Prep FID/VID Node:01 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f23 + F3xD8: 03001c14 + F3xDC: 00005428 +setup_remote_node: 01 done +Start node 01 done. +core0 started: 01 + +Begin FIDVID MSR 0xc0010071 0x20a600e4 0x38045044 +FIDVID on BSP, APIC_id: 00 +BSP fid = 10400 +Wait for AP stage 1: ap_apicid = 1 +init_fidvid_bsp_stage1: timed out reading from ap 01 +Wait for AP stage 1: ap_apicid = 2 +init_fidvid_bsp_stage1: timed out reading from ap 02 +Wait for AP stage 1: ap_apicid = 3 +init_fidvid_bsp_stage1: timed out reading from ap 03 +Wait for AP stage 1: ap_apicid = 4 + readback = 4010401 + common_fid(packed) = 10400 +Wait for AP stage 1: ap_apicid = 5 +init_fidvid_bsp_stage1: timed out reading from ap 05 +Wait for AP stage 1: ap_apicid = 6 +init_fidvid_bsp_stage1: timed out reading from ap 06 +Wait for AP stage 1: ap_apicid = 7 +init_fidvid_bsp_stage1: timed out reading from ap 07 +common_fid = 10400 +FID Change Node:00, F3xD4: c3310f24 +FID Change Node:01, F3xD4: c3310f24 +End FIDVIDMSR 0xc0010071 0x20a600e4 0x38005044 +start_other_cores() +init node: 00 cores: 03 +Start other core - nodeid: 00 cores: 03 +init node: 01 cores: 03 +Start other core - nodeid: 01 cores: 03 +started ap apicid: * AP 01started +* AP 02started +* AP 03started +* AP 05started +* AP 06started +* AP 07started + +set_ck804_base_unit_id() +...WARM RESET... + + + + +coreboot-4.0 Fri Jun 26 20:19:07 UTC 2015 romstage starting... +BSP Family_Model: 00100f21 +*sysinfo range: [000c4000,000c6899] +bsp_apicid = 00 +cpu_init_detectedx = 00000000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: 'cpu_microcode_blob.bin' not found. +[microcode] microcode file not found. Skipping updates. +cpuSetAMDMSR done +Enter amd_ht_init() +AMD_CB_EventNotify() + event class: 05 + event: 1004 + data: 04 00 00 01 +AMD_CB_EventNotify() + event class: 05 + event: 2006 + data: 04 00 01 00 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Exit amd_ht_init() +cpuSetAMDPCI 00 done +cpuSetAMDPCI 01 done +Prep FID/VID Node:00 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f24 + F3xD8: 03001c14 + F3xDC: 00005428 +Prep FID/VID Node:01 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f24 + F3xD8: 03001c14 + F3xDC: 00005428 +setup_remote_node: 01 done +Start node 01 done. +core0 started: 01 + +Begin FIDVID MSR 0xc0010071 0x20a600e4 0x38005044 +End FIDVIDMSR 0xc0010071 0x20a600e4 0x38003803 +start_other_cores() +init node: 00 cores: 03 +Start other core - nodeid: 00 cores: 03 +init node: 01 cores: 03 +Start other core - nodeid: 01 cores: 03 +started ap apicid: * AP 01started +* AP 02started +* AP 03started +* AP 05started +* AP 06started +* AP 07started + +set_ck804_base_unit_id() +fill_mem_ctrl() +enable_smbus() +SMBus controller enabled +raminit_amdmct() +raminit_amdmct begin: +activate_spd_rom() for node 00 +enable_spd_node0() +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +activate_spd_rom() for node 01 +enable_spd_node1() +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 + Node: 00 base: 00 limit: ffffff BottomIO: c00000 + Node: 01 base: 1400000 limit: 17fffff BottomIO: c00000 + Copy dram map from Node 0 to Node 01 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +raminit_amdmct end: +CBMEM: +IMD: root @ bffff000 254 entries. +IMD: root @ bfffec00 62 entries. +amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +disable_spd() +enable_msi_mapping() +Prepare CAR migration and stack regions... Fill [003fd000-003fffff] ... Done +Copying data from cache to RAM... Copy [000c4000-000c693f] to [003fd6c0 - 003fffff] ... Done +Switching to use RAM as stack... Top about 003fd6ac ... Done +Disabling cache as ram now +Prepare ramstage memory region... Fill [00000000-003fcfff] ... Done +CBFS provider active. +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/ramstage' +CBFS: Found @ offset 15440 size 147e1 +'fallback/ramstage' located at offset: 15478 size: 147e1 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Capability: type 0x0a @ 0x44 + + +coreboot-4.0 Fri Jun 26 20:19:07 UTC 2015 ramstage starting... +Moving GDT to bfffe980...ok +BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 0 +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0 +Enumerating buses... +Show all devs... Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:18.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:01.0: enabled 1 +PNP: 002e.0: enabled 1 +PNP: 002e.1: enabled 0 +PNP: 002e.2: enabled 1 +PNP: 002e.3: enabled 1 +PNP: 002e.5: enabled 1 +PNP: 002e.7: enabled 0 +PNP: 002e.8: enabled 0 +PNP: 002e.9: enabled 1 +PNP: 002e.a: enabled 0 +PNP: 002e.b: enabled 1 +PCI: 00:01.1: enabled 1 +I2C: 00:50: enabled 1 +I2C: 00:51: enabled 1 +I2C: 00:52: enabled 1 +I2C: 00:53: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:2f: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:04.0: enabled 0 +PCI: 00:04.1: enabled 0 +PCI: 00:06.0: enabled 1 +PCI: 00:07.0: enabled 1 +PCI: 00:08.0: enabled 1 +PCI: 00:09.0: enabled 1 +PCI: 00:04.0: enabled 1 +PCI: 00:0a.0: enabled 0 +PCI: 00:0b.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:0c.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:0d.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:0e.0: enabled 1 +PCI: 00:0f.0: enabled 0 +PCI: 00:18.1: enabled 1 +PCI: 00:18.2: enabled 1 +PCI: 00:18.3: enabled 1 +PCI: 00:18.4: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:19.1: enabled 1 +PCI: 00:19.2: enabled 1 +PCI: 00:19.3: enabled 1 +PCI: 00:19.4: enabled 1 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + DOMAIN: 0000: enabled 1 + PCI: 00:18.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:01.0: enabled 1 + PNP: 002e.0: enabled 1 + PNP: 002e.1: enabled 0 + PNP: 002e.2: enabled 1 + PNP: 002e.3: enabled 1 + PNP: 002e.5: enabled 1 + PNP: 002e.7: enabled 0 + PNP: 002e.8: enabled 0 + PNP: 002e.9: enabled 1 + PNP: 002e.a: enabled 0 + PNP: 002e.b: enabled 1 + PCI: 00:01.1: enabled 1 + I2C: 00:50: enabled 1 + I2C: 00:51: enabled 1 + I2C: 00:52: enabled 1 + I2C: 00:53: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:2f: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:04.0: enabled 0 + PCI: 00:04.1: enabled 0 + PCI: 00:06.0: enabled 1 + PCI: 00:07.0: enabled 1 + PCI: 00:08.0: enabled 1 + PCI: 00:09.0: enabled 1 + PCI: 00:04.0: enabled 1 + PCI: 00:0a.0: enabled 0 + PCI: 00:0b.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:0c.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:0d.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:0e.0: enabled 1 + PCI: 00:0f.0: enabled 0 + PCI: 00:18.1: enabled 1 + PCI: 00:18.2: enabled 1 + PCI: 00:18.3: enabled 1 + PCI: 00:18.4: enabled 1 + PCI: 00:19.0: enabled 1 + PCI: 00:19.1: enabled 1 + PCI: 00:19.2: enabled 1 + PCI: 00:19.3: enabled 1 + PCI: 00:19.4: enabled 1 +Root Device scanning... +root_dev_scan_bus for Root Device +setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 +setup_bsp_ramtop, TOP MEM2: msr.lo = 0x80000000, msr.hi = 0x00000001 +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +CPU_CLUSTER: 0 scanning... +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 + PCI: 00:18.3 siblings=3 +CPU: APIC: 00 enabled +CPU: APIC: 01 enabled +CPU: APIC: 02 enabled +CPU: APIC: 03 enabled + PCI: 00:19.3 siblings=3 +CPU: APIC: 04 enabled +CPU: APIC: 05 enabled +CPU: APIC: 06 enabled +CPU: APIC: 07 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:18.0 [1022/1200] bus ops +PCI: 00:18.0 [1022/1200] enabled +PCI: 00:18.1 [1022/1201] enabled +PCI: 00:18.2 [1022/1202] enabled +PCI: 00:18.3 [1022/1203] ops +PCI: 00:18.3 [1022/1203] enabled +PCI: 00:18.4 [1022/1204] enabled +PCI: 00:19.0 [1022/1200] bus ops +PCI: 00:19.0 [1022/1200] enabled +PCI: 00:19.1 [1022/1201] enabled +PCI: 00:19.2 [1022/1202] enabled +PCI: 00:19.3 [1022/1203] ops +PCI: 00:19.3 [1022/1203] enabled +PCI: 00:19.4 [1022/1204] enabled +PCI: 00:18.0 scanning... +PCI: 00:00.0 [10de/005e] ops +PCI: 00:00.0 [10de/005e] enabled +Capability: type 0x08 @ 0x44 +flags: 0x01e0 +PCI: 00:00.0 count: 000f static_count: 0010 +PCI: 00:00.0 [10de/005e] enabled next_unitid: 0010 +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [10de/005e] enabled +PCI: 00:01.0 [10de/0051] bus ops +PCI: 00:01.0 [10de/0051] enabled +PCI: 00:01.1 [10de/0052] bus ops +PCI: 00:01.1 [10de/0052] enabled +PCI: 00:02.0 [10de/005a] ops +PCI: 00:02.0 [10de/005a] enabled +PCI: 00:02.1 [10de/005b] ops +PCI: 00:02.1 [10de/005b] enabled +PCI: 00:04.0 [10de/0059] ops +PCI: 00:04.0 [10de/0059] disabled +PCI: 00:04.1 [10de/0058] ops +PCI: 00:04.1 [10de/0058] disabled +PCI: 00:06.0 [10de/0053] ops +PCI: 00:06.0 [10de/0053] enabled +PCI: 00:07.0 [10de/0054] ops +PCI: 00:07.0 [10de/0054] enabled +PCI: 00:08.0 [10de/0055] ops +PCI: 00:08.0 [10de/0055] enabled +PCI: 00:09.0 [10de/005c] bus ops +PCI: 00:09.0 [10de/005c] enabled +PCI: 00:0b.0 [10de/005d] bus ops +PCI: 00:0b.0 [10de/005d] enabled +PCI: 00:0c.0 [10de/005d] bus ops +PCI: 00:0c.0 [10de/005d] enabled +PCI: 00:0d.0 [10de/005d] bus ops +PCI: 00:0d.0 [10de/005d] enabled +PCI: 00:0e.0 [10de/005d] bus ops +PCI: 00:0e.0 [10de/005d] enabled +PCI: 00:01.0 scanning... +scan_lpc_bus for PCI: 00:01.0 +PNP: 002e.0 enabled +PNP: 002e.1 disabled +PNP: 002e.2 enabled +PNP: 002e.3 enabled +PNP: 002e.5 enabled +PNP: 002e.7 disabled +PNP: 002e.8 disabled +PNP: 002e.9 enabled +PNP: 002e.a disabled +PNP: 002e.b enabled +scan_lpc_bus for PCI: 00:01.0 done +PCI: 00:01.1 scanning... +scan_smbus for PCI: 00:01.1 +smbus: PCI: 00:01.1[0]->I2C: 01:50 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:51 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:52 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:53 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:54 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:55 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:56 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:57 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:2f enabled +scan_smbus for PCI: 00:01.1 done +PCI: 00:09.0 scanning... +do_pci_scan_bridge for PCI: 00:09.0 +PCI: pci_scan_bus for bus 01 +PCI: 01:04.0 [18ca/0020] ops +PCI: 01:04.0 [18ca/0020] enabled +PCI: 00:0b.0 scanning... +do_pci_scan_bridge for PCI: 00:0b.0 +PCI: pci_scan_bus for bus 02 +PCI: 02:00.0 [14e4/1659] enabled +PCI: 00:0c.0 scanning... +do_pci_scan_bridge for PCI: 00:0c.0 +PCI: pci_scan_bus for bus 03 +PCI: 03:00.0 [14e4/1659] enabled +PCI: 00:0d.0 scanning... +do_pci_scan_bridge for PCI: 00:0d.0 +PCI: pci_scan_bus for bus 04 +PCI: Static device PCI: 04:00.0 not found, disabling it. +PCI: 00:0e.0 scanning... +do_pci_scan_bridge for PCI: 00:0e.0 +PCI: pci_scan_bus for bus 05 +PCI: 00:19.0 scanning... +DOMAIN: 0000 passpw: enabled +DOMAIN: 0000 passpw: enabled +root_dev_scan_bus for Root Device done +done +BS: BS_DEV_ENUMERATE times (us): entry 0 run 598152 exit 0 +found VGA at PCI: 01:04.0 +Setting up VGA for PCI: 01:04.0 +Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:09.0 +Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +APIC: 01 missing read_resources +APIC: 02 missing read_resources +APIC: 03 missing read_resources +APIC: 04 missing read_resources +APIC: 05 missing read_resources +APIC: 06 missing read_resources +APIC: 07 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +PCI: 00:18.0 read_resources bus 0 link: 1 +PCI: 00:01.0 read_resources bus 0 link: 0 +PCI: 00:01.0 read_resources bus 0 link: 0 done +PCI: 00:01.1 read_resources bus 1 link: 0 +I2C: 01:50 missing read_resources +I2C: 01:51 missing read_resources +I2C: 01:52 missing read_resources +I2C: 01:53 missing read_resources +I2C: 01:54 missing read_resources +I2C: 01:55 missing read_resources +I2C: 01:56 missing read_resources +I2C: 01:57 missing read_resources +PCI: 00:01.1 read_resources bus 1 link: 0 done +PCI: 00:01.1 read_resources bus 2 link: 1 +PCI: 00:01.1 read_resources bus 2 link: 1 done +PCI: 00:09.0 read_resources bus 1 link: 0 +PCI: 00:09.0 read_resources bus 1 link: 0 done +PCI: 00:0b.0 read_resources bus 2 link: 0 +PCI: 00:0b.0 read_resources bus 2 link: 0 done +PCI: 00:0c.0 read_resources bus 3 link: 0 +PCI: 00:0c.0 read_resources bus 3 link: 0 done +PCI: 00:0d.0 read_resources bus 4 link: 0 +PCI: 00:0d.0 read_resources bus 4 link: 0 done +PCI: 00:0e.0 read_resources bus 5 link: 0 +PCI: 00:0e.0 read_resources bus 5 link: 0 done +PCI: 00:18.0 read_resources bus 0 link: 1 done +PCI: 00:18.0 read_resources bus 0 link: 0 +PCI: 00:18.0 read_resources bus 0 link: 0 done +PCI: 00:18.0 read_resources bus 0 link: 2 +PCI: 00:18.0 read_resources bus 0 link: 2 done +PCI: 00:18.0 read_resources bus 0 link: 3 +PCI: 00:18.0 read_resources bus 0 link: 3 done +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +PCI: 00:18.4 read_resources bus 0 link: 0 +PCI: 00:18.4 read_resources bus 0 link: 0 done +PCI: 00:18.4 read_resources bus 0 link: 1 +PCI: 00:18.4 read_resources bus 0 link: 1 done +PCI: 00:18.4 read_resources bus 0 link: 2 +PCI: 00:18.4 read_resources bus 0 link: 2 done +PCI: 00:18.4 read_resources bus 0 link: 3 +PCI: 00:18.4 read_resources bus 0 link: 3 done +PCI: 00:19.0 read_resources bus 0 link: 0 +PCI: 00:19.0 read_resources bus 0 link: 0 done +PCI: 00:19.0 read_resources bus 0 link: 1 +PCI: 00:19.0 read_resources bus 0 link: 1 done +PCI: 00:19.0 read_resources bus 0 link: 2 +PCI: 00:19.0 read_resources bus 0 link: 2 done +PCI: 00:19.0 read_resources bus 0 link: 3 +PCI: 00:19.0 read_resources bus 0 link: 3 done +PCI: 00:19.4 read_resources bus 0 link: 0 +PCI: 00:19.4 read_resources bus 0 link: 0 done +PCI: 00:19.4 read_resources bus 0 link: 1 +PCI: 00:19.4 read_resources bus 0 link: 1 done +PCI: 00:19.4 read_resources bus 0 link: 2 +PCI: 00:19.4 read_resources bus 0 link: 2 done +PCI: 00:19.4 read_resources bus 0 link: 3 +PCI: 00:19.4 read_resources bus 0 link: 3 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: 01 + APIC: 02 + APIC: 03 + APIC: 04 + APIC: 05 + APIC: 06 + APIC: 07 + DOMAIN: 0000 child on link 0 PCI: 00:18.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 + DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 + PCI: 00:18.0 child on link 0 PCI: 00:00.0 + PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8 + PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b8 + PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b0 + PCI: 00:00.0 + PCI: 00:01.0 child on link 0 PNP: 002e.0 + PCI: 00:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10 + PCI: 00:01.0 resource base fec00000 size 1000 align 12 gran 12 limit ffffffff flags c0000200 index 14 + PCI: 00:01.0 resource base fed00000 size 1000 align 12 gran 12 limit ffffffff flags c0000200 index 44 + PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60 + PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 64 + PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 68 + PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PNP: 002e.0 + PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.3 + PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000500 index f1 + PNP: 002e.5 + PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 + PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 + PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 + PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.7 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 + PNP: 002e.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.8 + PNP: 002e.9 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 30 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f1 + PNP: 002e.a + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.b + PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60 + PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PCI: 00:01.1 child on link 0 I2C: 01:50 + PCI: 00:01.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 10 + PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 + PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24 + I2C: 01:50 + I2C: 01:51 + I2C: 01:52 + I2C: 01:53 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:2f + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:04.0 + PCI: 00:04.1 + PCI: 00:06.0 + PCI: 00:06.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:07.0 + PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:07.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:07.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 00:08.0 + PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 00:09.0 child on link 0 PCI: 01:04.0 + PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 + PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:04.0 + PCI: 01:04.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 + PCI: 01:04.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 14 + PCI: 01:04.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18 + PCI: 00:0a.0 + PCI: 00:0b.0 child on link 0 PCI: 02:00.0 + PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:0c.0 child on link 0 PCI: 03:00.0 + PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 03:00.0 + PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:0d.0 child on link 0 PCI: 04:00.0 + PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 04:00.0 + PCI: 00:0e.0 + PCI: 00:0e.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:0f.0 + PCI: 00:18.1 + PCI: 00:18.2 + PCI: 00:18.3 + PCI: 00:18.4 + PCI: 00:19.0 + PCI: 00:19.1 + PCI: 00:19.2 + PCI: 00:19.3 + PCI: 00:19.4 +DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:04.0 18 * [0x0 - 0x7f] io +PCI: 00:09.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:0e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:09.0 1c * [0x0 - 0xfff] io +PCI: 00:01.0 60 * [0x1000 - 0x10ff] io +PCI: 00:01.0 64 * [0x1400 - 0x14ff] io +PCI: 00:01.0 68 * [0x1800 - 0x18ff] io +PCI: 00:01.0 10 * [0x1c00 - 0x1c7f] io +PCI: 00:01.1 20 * [0x1c80 - 0x1cbf] io +PCI: 00:01.1 24 * [0x1cc0 - 0x1cff] io +PCI: 00:01.1 10 * [0x2000 - 0x201f] io +PCI: 00:06.0 20 * [0x2020 - 0x202f] io +PCI: 00:07.0 20 * [0x2030 - 0x203f] io +PCI: 00:08.0 20 * [0x2040 - 0x204f] io +PCI: 00:07.0 10 * [0x2050 - 0x2057] io +PCI: 00:07.0 18 * [0x2058 - 0x205f] io +PCI: 00:08.0 10 * [0x2060 - 0x2067] io +PCI: 00:08.0 18 * [0x2068 - 0x206f] io +PCI: 00:07.0 14 * [0x2070 - 0x2073] io +PCI: 00:07.0 1c * [0x2074 - 0x2077] io +PCI: 00:08.0 14 * [0x2078 - 0x207b] io +PCI: 00:08.0 1c * [0x207c - 0x207f] io +PCI: 00:18.0 io: base: 2080 size: 3000 align: 12 gran: 12 limit: ffff done +PCI: 00:18.0 110d8 * [0x0 - 0x2fff] io +DOMAIN: 0000 io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff +PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:04.0 10 * [0x0 - 0x3ffffff] prefmem +PCI: 00:09.0 prefmem: base: 4000000 size: 4000000 align: 26 gran: 20 limit: ffffffff done +PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:0e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:09.0 24 * [0x0 - 0x3ffffff] prefmem +PCI: 00:18.0 prefmem: base: 4000000 size: 4000000 align: 26 gran: 20 limit: ffffffff done +PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff +PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:04.0 14 * [0x0 - 0x3ffff] mem +PCI: 00:09.0 mem: base: 40000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:0b.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 03:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:0c.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:0e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:09.0 20 * [0x0 - 0xfffff] mem +PCI: 00:0b.0 20 * [0x100000 - 0x1fffff] mem +PCI: 00:0c.0 20 * [0x200000 - 0x2fffff] mem +PCI: 00:02.0 10 * [0x300000 - 0x300fff] mem +PCI: 00:07.0 24 * [0x301000 - 0x301fff] mem +PCI: 00:08.0 24 * [0x302000 - 0x302fff] mem +PCI: 00:02.1 10 * [0x303000 - 0x3030ff] mem +PCI: 00:18.0 mem: base: 303100 size: 400000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:18.0 110b8 * [0x0 - 0x3ffffff] prefmem +PCI: 00:18.0 110b0 * [0x4000000 - 0x43fffff] mem +DOMAIN: 0000 mem: base: 4400000 size: 4400000 align: 26 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed) +constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed) +constrain_resources: PCI: 00:01.0 14 base fec00000 limit fec00fff mem (fixed) +constrain_resources: PCI: 00:01.0 10000000 base 00000000 limit 00000fff io (fixed) +avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 base f8000000 limit febfffff +Setting resources... +DOMAIN: 0000 io: base:1000 size:3000 align:12 gran:0 limit:ffff +PCI: 00:18.0 110d8 * [0x1000 - 0x3fff] io +DOMAIN: 0000 io: next_base: 4000 size: 3000 align: 12 gran: 0 done +PCI: 00:18.0 io: base:1000 size:3000 align:12 gran:12 limit:3fff +PCI: 00:09.0 1c * [0x1000 - 0x1fff] io +PCI: 00:01.0 60 * [0x2000 - 0x20ff] io +PCI: 00:01.0 64 * [0x2400 - 0x24ff] io +PCI: 00:01.0 68 * [0x2800 - 0x28ff] io +PCI: 00:01.0 10 * [0x2c00 - 0x2c7f] io +PCI: 00:01.1 20 * [0x2c80 - 0x2cbf] io +PCI: 00:01.1 24 * [0x2cc0 - 0x2cff] io +PCI: 00:01.1 10 * [0x3000 - 0x301f] io +PCI: 00:06.0 20 * [0x3020 - 0x302f] io +PCI: 00:07.0 20 * [0x3030 - 0x303f] io +PCI: 00:08.0 20 * [0x3040 - 0x304f] io +PCI: 00:07.0 10 * [0x3050 - 0x3057] io +PCI: 00:07.0 18 * [0x3058 - 0x305f] io +PCI: 00:08.0 10 * [0x3060 - 0x3067] io +PCI: 00:08.0 18 * [0x3068 - 0x306f] io +PCI: 00:07.0 14 * [0x3070 - 0x3073] io +PCI: 00:07.0 1c * [0x3074 - 0x3077] io +PCI: 00:08.0 14 * [0x3078 - 0x307b] io +PCI: 00:08.0 1c * [0x307c - 0x307f] io +PCI: 00:18.0 io: next_base: 3080 size: 3000 align: 12 gran: 12 done +PCI: 00:09.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff +PCI: 01:04.0 18 * [0x1000 - 0x107f] io +PCI: 00:09.0 io: next_base: 1080 size: 1000 align: 12 gran: 12 done +PCI: 00:0b.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0b.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +PCI: 00:0c.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0c.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +PCI: 00:0d.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0d.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +PCI: 00:0e.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0e.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +DOMAIN: 0000 mem: base:f8000000 size:4400000 align:26 gran:0 limit:febfffff +PCI: 00:18.0 110b8 * [0xf8000000 - 0xfbffffff] prefmem +PCI: 00:18.0 110b0 * [0xfc000000 - 0xfc3fffff] mem +DOMAIN: 0000 mem: next_base: fc400000 size: 4400000 align: 26 gran: 0 done +PCI: 00:18.0 prefmem: base:f8000000 size:4000000 align:26 gran:20 limit:fbffffff +PCI: 00:09.0 24 * [0xf8000000 - 0xfbffffff] prefmem +PCI: 00:18.0 prefmem: next_base: fc000000 size: 4000000 align: 26 gran: 20 done +PCI: 00:09.0 prefmem: base:f8000000 size:4000000 align:26 gran:20 limit:fbffffff +PCI: 01:04.0 10 * [0xf8000000 - 0xfbffffff] prefmem +PCI: 00:09.0 prefmem: next_base: fc000000 size: 4000000 align: 26 gran: 20 done +PCI: 00:0b.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0b.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:0c.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0c.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:0d.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0d.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:0e.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0e.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:18.0 mem: base:fc000000 size:400000 align:20 gran:20 limit:fc3fffff +PCI: 00:09.0 20 * [0xfc000000 - 0xfc0fffff] mem +PCI: 00:0b.0 20 * [0xfc100000 - 0xfc1fffff] mem +PCI: 00:0c.0 20 * [0xfc200000 - 0xfc2fffff] mem +PCI: 00:02.0 10 * [0xfc300000 - 0xfc300fff] mem +PCI: 00:07.0 24 * [0xfc301000 - 0xfc301fff] mem +PCI: 00:08.0 24 * [0xfc302000 - 0xfc302fff] mem +PCI: 00:02.1 10 * [0xfc303000 - 0xfc3030ff] mem +PCI: 00:18.0 mem: next_base: fc303100 size: 400000 align: 20 gran: 20 done +PCI: 00:09.0 mem: base:fc000000 size:100000 align:20 gran:20 limit:fc0fffff +PCI: 01:04.0 14 * [0xfc000000 - 0xfc03ffff] mem +PCI: 00:09.0 mem: next_base: fc040000 size: 100000 align: 20 gran: 20 done +PCI: 00:0b.0 mem: base:fc100000 size:100000 align:20 gran:20 limit:fc1fffff +PCI: 02:00.0 10 * [0xfc100000 - 0xfc10ffff] mem +PCI: 00:0b.0 mem: next_base: fc110000 size: 100000 align: 20 gran: 20 done +PCI: 00:0c.0 mem: base:fc200000 size:100000 align:20 gran:20 limit:fc2fffff +PCI: 03:00.0 10 * [0xfc200000 - 0xfc20ffff] mem +PCI: 00:0c.0 mem: next_base: fc210000 size: 100000 align: 20 gran: 20 done +PCI: 00:0d.0 mem: base:fc3fffff size:0 align:20 gran:20 limit:fc3fffff +PCI: 00:0d.0 mem: next_base: fc3fffff size: 0 align: 20 gran: 20 done +PCI: 00:0e.0 mem: base:fc3fffff size:0 align:20 gran:20 limit:fc3fffff +PCI: 00:0e.0 mem: next_base: fc3fffff size: 0 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +0: mmio_basek=00300000, basek=00400000, limitk=00500000 +1: mmio_basek=00300000, basek=00500000, limitk=00600000 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device +PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io +PCI: 00:18.0 110b8 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x14 prefmem +PCI: 00:18.0 110b0 <- [0x00fc000000 - 0x00fc3fffff] size 0x00400000 gran 0x14 mem +PCI: 00:18.0 assign_resources, bus 0 link: 1 +PCI: 00:01.0 10 <- [0x0000002c00 - 0x0000002c7f] size 0x00000080 gran 0x07 io +PCI: 00:01.0 60 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io +PCI: 00:01.0 64 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io +PCI: 00:01.0 68 <- [0x0000002800 - 0x00000028ff] size 0x00000100 gran 0x08 io +PCI: 00:01.0 assign_resources, bus 0 link: 0 +PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io +PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq +PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq +PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io +PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq +PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io +PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq +PNP: 002e.3 f1 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 io +PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io +PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io +PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq +PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq +ERROR: PNP: 002e.5 f0 irq size: 0x0000000001 not assigned +ERROR: PNP: 002e.9 30 irq size: 0x0000000001 not assigned +ERROR: PNP: 002e.9 f0 irq size: 0x0000000001 not assigned +ERROR: PNP: 002e.9 f1 irq size: 0x0000000001 not assigned +PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io +PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq +PCI: 00:01.0 assign_resources, bus 0 link: 0 +PCI: 00:01.0 14 <- [0x00fec00000 - 0x00fec00fff] size 0x00001000 gran 0x0c mem +PCI: 00:01.0 44 <- [0x00fed00000 - 0x00fed00fff] size 0x00001000 gran 0x0c mem +PCI: 00:01.1 10 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io +PCI: 00:01.1 20 <- [0x0000002c80 - 0x0000002cbf] size 0x00000040 gran 0x06 io +PCI: 00:01.1 24 <- [0x0000002cc0 - 0x0000002cff] size 0x00000040 gran 0x06 io +PCI: 00:01.1 assign_resources, bus 1 link: 0 +PCI: 00:01.1 assign_resources, bus 1 link: 0 +PCI: 00:02.0 10 <- [0x00fc300000 - 0x00fc300fff] size 0x00001000 gran 0x0c mem +PCI: 00:02.1 10 <- [0x00fc303000 - 0x00fc3030ff] size 0x00000100 gran 0x08 mem +PCI: 00:06.0 20 <- [0x0000003020 - 0x000000302f] size 0x00000010 gran 0x04 io +PCI: 00:07.0 10 <- [0x0000003050 - 0x0000003057] size 0x00000008 gran 0x03 io +PCI: 00:07.0 14 <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io +PCI: 00:07.0 18 <- [0x0000003058 - 0x000000305f] size 0x00000008 gran 0x03 io +PCI: 00:07.0 1c <- [0x0000003074 - 0x0000003077] size 0x00000004 gran 0x02 io +PCI: 00:07.0 20 <- [0x0000003030 - 0x000000303f] size 0x00000010 gran 0x04 io +PCI: 00:07.0 24 <- [0x00fc301000 - 0x00fc301fff] size 0x00001000 gran 0x0c mem +PCI: 00:08.0 10 <- [0x0000003060 - 0x0000003067] size 0x00000008 gran 0x03 io +PCI: 00:08.0 14 <- [0x0000003078 - 0x000000307b] size 0x00000004 gran 0x02 io +PCI: 00:08.0 18 <- [0x0000003068 - 0x000000306f] size 0x00000008 gran 0x03 io +PCI: 00:08.0 1c <- [0x000000307c - 0x000000307f] size 0x00000004 gran 0x02 io +PCI: 00:08.0 20 <- [0x0000003040 - 0x000000304f] size 0x00000010 gran 0x04 io +PCI: 00:08.0 24 <- [0x00fc302000 - 0x00fc302fff] size 0x00001000 gran 0x0c mem +PCI: 00:09.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:09.0 24 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x14 bus 01 prefmem +PCI: 00:09.0 20 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 bus 01 mem +PCI: 00:09.0 assign_resources, bus 1 link: 0 +PCI: 01:04.0 10 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a prefmem +PCI: 01:04.0 14 <- [0x00fc000000 - 0x00fc03ffff] size 0x00040000 gran 0x12 mem +PCI: 01:04.0 18 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io +PCI: 00:09.0 assign_resources, bus 1 link: 0 +PCI: 00:0b.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:0b.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:0b.0 20 <- [0x00fc100000 - 0x00fc1fffff] size 0x00100000 gran 0x14 bus 02 mem +PCI: 00:0b.0 assign_resources, bus 2 link: 0 +PCI: 02:00.0 10 <- [0x00fc100000 - 0x00fc10ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:0b.0 assign_resources, bus 2 link: 0 +PCI: 00:0c.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:0c.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:0c.0 20 <- [0x00fc200000 - 0x00fc2fffff] size 0x00100000 gran 0x14 bus 03 mem +PCI: 00:0c.0 assign_resources, bus 3 link: 0 +PCI: 03:00.0 10 <- [0x00fc200000 - 0x00fc20ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:0c.0 assign_resources, bus 3 link: 0 +PCI: 00:0d.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:0d.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:0d.0 20 <- [0x00fc3fffff - 0x00fc3ffffe] size 0x00000000 gran 0x14 bus 04 mem +PCI: 00:0d.0 assign_resources, bus 4 link: 0 +PCI: 00:0d.0 assign_resources, bus 4 link: 0 +PCI: 00:0e.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 05 io +PCI: 00:0e.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 05 prefmem +PCI: 00:0e.0 20 <- [0x00fc3fffff - 0x00fc3ffffe] size 0x00000000 gran 0x14 bus 05 mem +PCI: 00:18.0 assign_resources, bus 0 link: 1 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: 01 + APIC: 02 + APIC: 03 + APIC: 04 + APIC: 05 + APIC: 06 + APIC: 07 + DOMAIN: 0000 child on link 0 PCI: 00:18.0 + DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base f8000000 size 4400000 align 26 gran 0 limit febfffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 + DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 + DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 + DOMAIN: 0000 resource base 100000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 30 + DOMAIN: 0000 resource base 140000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 41 + PCI: 00:18.0 child on link 0 PCI: 00:00.0 + PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit 3fff flags 60080100 index 110d8 + PCI: 00:18.0 resource base f8000000 size 4000000 align 26 gran 20 limit fbffffff flags 60081200 index 110b8 + PCI: 00:18.0 resource base fc000000 size 400000 align 20 gran 20 limit fc3fffff flags 60080200 index 110b0 + PCI: 00:00.0 + PCI: 00:01.0 child on link 0 PNP: 002e.0 + PCI: 00:01.0 resource base 2c00 size 80 align 7 gran 7 limit 2c7f flags 60000100 index 10 + PCI: 00:01.0 resource base fec00000 size 1000 align 12 gran 12 limit ffffffff flags e0000200 index 14 + PCI: 00:01.0 resource base fed00000 size 1000 align 12 gran 12 limit ffffffff flags e0000200 index 44 + PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 60 + PCI: 00:01.0 resource base 2400 size 100 align 8 gran 8 limit 24ff flags 60000100 index 64 + PCI: 00:01.0 resource base 2800 size 100 align 8 gran 8 limit 28ff flags 60000100 index 68 + PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PNP: 002e.0 + PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.3 + PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000500 index f1 + PNP: 002e.5 + PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 + PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 + PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 + PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.7 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 + PNP: 002e.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.8 + PNP: 002e.9 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 30 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f1 + PNP: 002e.a + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.b + PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags e0000100 index 60 + PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PCI: 00:01.1 child on link 0 I2C: 01:50 + PCI: 00:01.1 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 10 + PCI: 00:01.1 resource base 2c80 size 40 align 6 gran 6 limit 2cbf flags 60000100 index 20 + PCI: 00:01.1 resource base 2cc0 size 40 align 6 gran 6 limit 2cff flags 60000100 index 24 + I2C: 01:50 + I2C: 01:51 + I2C: 01:52 + I2C: 01:53 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:2f + PCI: 00:02.0 + PCI: 00:02.0 resource base fc300000 size 1000 align 12 gran 12 limit fc300fff flags 60000200 index 10 + PCI: 00:02.1 + PCI: 00:02.1 resource base fc303000 size 100 align 8 gran 8 limit fc3030ff flags 60000200 index 10 + PCI: 00:04.0 + PCI: 00:04.1 + PCI: 00:06.0 + PCI: 00:06.0 resource base 3020 size 10 align 4 gran 4 limit 302f flags 60000100 index 20 + PCI: 00:07.0 + PCI: 00:07.0 resource base 3050 size 8 align 3 gran 3 limit 3057 flags 60000100 index 10 + PCI: 00:07.0 resource base 3070 size 4 align 2 gran 2 limit 3073 flags 60000100 index 14 + PCI: 00:07.0 resource base 3058 size 8 align 3 gran 3 limit 305f flags 60000100 index 18 + PCI: 00:07.0 resource base 3074 size 4 align 2 gran 2 limit 3077 flags 60000100 index 1c + PCI: 00:07.0 resource base 3030 size 10 align 4 gran 4 limit 303f flags 60000100 index 20 + PCI: 00:07.0 resource base fc301000 size 1000 align 12 gran 12 limit fc301fff flags 60000200 index 24 + PCI: 00:08.0 + PCI: 00:08.0 resource base 3060 size 8 align 3 gran 3 limit 3067 flags 60000100 index 10 + PCI: 00:08.0 resource base 3078 size 4 align 2 gran 2 limit 307b flags 60000100 index 14 + PCI: 00:08.0 resource base 3068 size 8 align 3 gran 3 limit 306f flags 60000100 index 18 + PCI: 00:08.0 resource base 307c size 4 align 2 gran 2 limit 307f flags 60000100 index 1c + PCI: 00:08.0 resource base 3040 size 10 align 4 gran 4 limit 304f flags 60000100 index 20 + PCI: 00:08.0 resource base fc302000 size 1000 align 12 gran 12 limit fc302fff flags 60000200 index 24 + PCI: 00:09.0 child on link 0 PCI: 01:04.0 + PCI: 00:09.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c + PCI: 00:09.0 resource base f8000000 size 4000000 align 26 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:09.0 resource base fc000000 size 100000 align 20 gran 20 limit fc0fffff flags 60080202 index 20 + PCI: 01:04.0 + PCI: 01:04.0 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60001200 index 10 + PCI: 01:04.0 resource base fc000000 size 40000 align 18 gran 18 limit fc03ffff flags 60000200 index 14 + PCI: 01:04.0 resource base 1000 size 80 align 7 gran 7 limit 107f flags 60000100 index 18 + PCI: 01:04.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3 + PCI: 00:0a.0 + PCI: 00:0b.0 child on link 0 PCI: 02:00.0 + PCI: 00:0b.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0b.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0b.0 resource base fc100000 size 100000 align 20 gran 20 limit fc1fffff flags 60080202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base fc100000 size 10000 align 16 gran 16 limit fc10ffff flags 60000201 index 10 + PCI: 00:0c.0 child on link 0 PCI: 03:00.0 + PCI: 00:0c.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0c.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0c.0 resource base fc200000 size 100000 align 20 gran 20 limit fc2fffff flags 60080202 index 20 + PCI: 03:00.0 + PCI: 03:00.0 resource base fc200000 size 10000 align 16 gran 16 limit fc20ffff flags 60000201 index 10 + PCI: 00:0d.0 child on link 0 PCI: 04:00.0 + PCI: 00:0d.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0d.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0d.0 resource base fc3fffff size 0 align 20 gran 20 limit fc3fffff flags 60080202 index 20 + PCI: 04:00.0 + PCI: 00:0e.0 + PCI: 00:0e.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0e.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0e.0 resource base fc3fffff size 0 align 20 gran 20 limit fc3fffff flags 60080202 index 20 + PCI: 00:0f.0 + PCI: 00:18.1 + PCI: 00:18.2 + PCI: 00:18.3 + PCI: 00:18.4 + PCI: 00:19.0 + PCI: 00:19.1 + PCI: 00:19.2 + PCI: 00:19.3 + PCI: 00:19.4 +Done allocating resources. +BS: BS_DEV_RESOURCES times (us): entry 0 run 3267943 exit 0 +Enabling resources... +PCI: 00:18.0 cmd <- 00 +PCI: 00:18.1 subsystem <- 1043/8162 +PCI: 00:18.1 cmd <- 00 +PCI: 00:18.2 subsystem <- 1043/8162 +PCI: 00:18.2 cmd <- 00 +PCI: 00:18.3 cmd <- 00 +PCI: 00:18.4 subsystem <- 1043/8162 +PCI: 00:18.4 cmd <- 00 +PCI: 00:19.0 cmd <- 00 +PCI: 00:19.1 subsystem <- 1043/8162 +PCI: 00:19.1 cmd <- 00 +PCI: 00:19.2 subsystem <- 1043/8162 +PCI: 00:19.2 cmd <- 00 +PCI: 00:19.3 cmd <- 00 +PCI: 00:19.4 subsystem <- 1043/8162 +PCI: 00:19.4 cmd <- 00 +PCI: 00:00.0 subsystem <- 1043/8162 +PCI: 00:00.0 cmd <- 06 +PCI: 00:01.0 subsystem <- 1043/8162 +PCI: 00:01.0 cmd <- 0f +ck804 lpc decode:PNP: 002e.0, base=0x000003f0, end=0x000003f7 +ck804 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff +ck804 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff +ck804 lpc decode:PNP: 002e.3, base=0x00000004, end=0x00000004 +ck804 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 +ck804 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 +ck804 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000297 +PCI: 00:01.1 subsystem <- 1043/8162 +PCI: 00:01.1 cmd <- 01 +PCI: 00:02.0 subsystem <- 1043/8162 +PCI: 00:02.0 cmd <- 02 +PCI: 00:02.1 subsystem <- 1043/8162 +PCI: 00:02.1 cmd <- 02 +PCI: 00:06.0 subsystem <- 1043/8162 +PCI: 00:06.0 cmd <- 01 +PCI: 00:07.0 subsystem <- 1043/8162 +PCI: 00:07.0 cmd <- 03 +PCI: 00:08.0 subsystem <- 1043/8162 +PCI: 00:08.0 cmd <- 03 +PCI: 00:09.0 bridge ctrl <- 000b +PCI: 00:09.0 cmd <- 07 +PCI: 00:0b.0 bridge ctrl <- 0003 +PCI: 00:0b.0 cmd <- 06 +PCI: 00:0c.0 bridge ctrl <- 0003 +PCI: 00:0c.0 cmd <- 06 +PCI: 00:0d.0 bridge ctrl <- 0003 +PCI: 00:0d.0 cmd <- 00 +PCI: 00:0e.0 bridge ctrl <- 0003 +PCI: 00:0e.0 cmd <- 00 +PCI: 01:04.0 cmd <- 03 +PCI: 02:00.0 subsystem <- 1043/8162 +PCI: 02:00.0 cmd <- 02 +PCI: 03:00.0 subsystem <- 1043/8162 +PCI: 03:00.0 cmd <- 02 +done. +BS: BS_DEV_ENABLE times (us): entry 0 run 162779 exit 0 +Initializing devices... +Root Device init ... +Root Device init finished in 1931 usecs +CPU_CLUSTER: 0 init ... +start_eip=0x00001000, code_size=0x00000031 +CPU1: stack_base 00138000, stack_end 00138ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Initializing CPU #1 +Startup point 1. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +Sending STARTUP #2 to 1. +After apic_write. +CPU: family 10, model 02, stepping 01 +Startup point 1. +Waiting for send to finish... ++nodeid = 00, coreid = 01 +After Startup. +CPU2: stack_base 00137000, stack_end 00137ff8 +Enabling cache +Asserting INIT. +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Waiting for send to finish... ++MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6 +0x00000000c0000000 - 0x00000000f8000000 size 0x38000000 type 0 +0x00000000f8000000 - 0x00000000fc000000 size 0x04000000 type 1 +0x00000000fc000000 - 0x0000000100000000 size 0x04000000 type 0 +0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6 +Deasserting INIT. +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +Waiting for send to finish... ++MTRR: default type WB/UC MTRR counts: 5/3. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 +MTRR: 2 base 0x00000000f8000000 mask 0x0000fffffc000000 type 1 +#startup loops: 2. +Sending STARTUP #1 to 2. +After apic_write. + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Startup point 1. +Waiting for send to finish... ++Setting up local apic...Sending STARTUP #2 to 2. +After apic_write. + apic_id: 0x01 done. +Startup point 1. +Waiting for send to finish... ++CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +Initializing CPU #2 +After Startup. +siblings = 03, CPU3: stack_base 00136000, stack_end 00136ff8 +CPU #1 initialized +Asserting INIT. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +Deasserting INIT. +Waiting for send to finish... ++CPU: family 10, model 02, stepping 01 +#startup loops: 2. +Sending STARTUP #1 to 3. +After apic_write. +nodeid = 00, coreid = 02 +Startup point 1. +Waiting for send to finish... ++Initializing CPU #3 +Sending STARTUP #2 to 3. +After apic_write. +Enabling cache +Startup point 1. +Waiting for send to finish... ++CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +After Startup. +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU4: stack_base 00135000, stack_end 00135ff8 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Asserting INIT. +Setting up local apic...Waiting for send to finish... ++ apic_id: 0x02 done. +Deasserting INIT. +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +Waiting for send to finish... ++siblings = 03, #startup loops: 2. +Sending STARTUP #1 to 4. +After apic_write. +CPU #2 initialized +Startup point 1. +Waiting for send to finish... ++Initializing CPU #4 +Sending STARTUP #2 to 4. +After apic_write. +CPU: vendor AMD device 100f21 +Startup point 1. +Waiting for send to finish... ++CPU: family 10, model 02, stepping 01 +After Startup. +CPU5: stack_base 00134000, stack_end 00134ff8 +nodeid = 00, coreid = 03 +Asserting INIT. +Waiting for send to finish... ++Enabling cache +Deasserting INIT. +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Waiting for send to finish... ++MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +#startup loops: 2. +Sending STARTUP #1 to 5. +After apic_write. + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Startup point 1. +Waiting for send to finish... ++Setting up local apic...Sending STARTUP #2 to 5. +After apic_write. + apic_id: 0x03 done. +Startup point 1. +Waiting for send to finish... ++CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +After Startup. +siblings = 03, CPU6: stack_base 00133000, stack_end 00133ff8 +CPU #3 initialized +Asserting INIT. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +Deasserting INIT. +Waiting for send to finish... ++Initializing CPU #5 +#startup loops: 2. +Sending STARTUP #1 to 6. +After apic_write. +CPU: family 10, model 02, stepping 01 +Startup point 1. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +Sending STARTUP #2 to 6. +After apic_write. +Initializing CPU #6 +Startup point 1. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +After Startup. +CPU7: stack_base 00132000, stack_end 00132ff8 +nodeid = 01, coreid = 00 +Asserting INIT. +Waiting for send to finish... ++CPU: family 10, model 02, stepping 01 +Deasserting INIT. +Waiting for send to finish... ++nodeid = 01, coreid = 01 +#startup loops: 2. +Sending STARTUP #1 to 7. +After apic_write. +CPU: family 10, model 02, stepping 01 +Startup point 1. +Waiting for send to finish... ++Enabling cache +Sending STARTUP #2 to 7. +After apic_write. +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Startup point 1. +Waiting for send to finish... ++MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +After Startup. +Initializing CPU #0 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +CPU: vendor AMD device 100f21 +CPU: family 10, model 02, stepping 01 +Setting up local apic...nodeid = 00, coreid = 00 + apic_id: 0x05 done. +Enabling cache +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +siblings = 03, MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU #5 initialized + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Enabling cache +Setting up local apic...CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB + apic_id: 0x00 done. +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +siblings = 03, Setting up local apic...CPU #0 initialized + apic_id: 0x04 done. +Waiting for 3 CPUS to stop +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +siblings = 03, nodeid = 01, coreid = 02 +CPU #4 initialized +Enabling cache +Waiting for 2 CPUS to stop +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Initializing CPU #7 +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU: vendor AMD device 100f21 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +CPU: family 10, model 02, stepping 01 +Setting up local apic...nodeid = 01, coreid = 03 + apic_id: 0x06 done. +Enabling cache +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +siblings = 03, MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU #6 initialized + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Waiting for 1 CPUS to stop +Setting up local apic... apic_id: 0x07 done. +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +siblings = 03, CPU #7 initialized +All AP CPUs stopped (14884 loops) +CPU1: stack: 00138000 - 00139000, lowest used address 00138c8c, stack used: 884 bytes +CPU2: stack: 00137000 - 00138000, lowest used address 00137cd4, stack used: 812 bytes +CPU3: stack: 00136000 - 00137000, lowest used address 00136cd4, stack used: 812 bytes +CPU4: stack: 00135000 - 00136000, lowest used address 00135cd4, stack used: 812 bytes +CPU5: stack: 00134000 - 00135000, lowest used address 00134cd4, stack used: 812 bytes +CPU6: stack: 00133000 - 00134000, lowest used address 00133cd4, stack used: 812 bytes +CPU7: stack: 00132000 - 00133000, lowest used address 00132cd4, stack used: 812 bytes +CPU_CLUSTER: 0 init finished in 995136 usecs +PCI: 00:18.0 init ... +PCI: 00:18.0 init finished in 2030 usecs +PCI: 00:18.1 init ... +PCI: 00:18.1 init finished in 2027 usecs +PCI: 00:18.2 init ... +PCI: 00:18.2 init finished in 2018 usecs +PCI: 00:18.3 init ... +NB: Function 3 Misc Control.. done. +PCI: 00:18.3 init finished in 5293 usecs +PCI: 00:18.4 init ... +PCI: 00:18.4 init finished in 2018 usecs +PCI: 00:19.0 init ... +PCI: 00:19.0 init finished in 2019 usecs +PCI: 00:19.1 init ... +PCI: 00:19.1 init finished in 2018 usecs +PCI: 00:19.2 init ... +PCI: 00:19.2 init finished in 2017 usecs +PCI: 00:19.3 init ... +NB: Function 3 Misc Control.. done. +PCI: 00:19.3 init finished in 5268 usecs +PCI: 00:19.4 init ... +PCI: 00:19.4 init finished in 2017 usecs +PCI: 00:00.0 init ... +PCI: 00:00.0 init finished in 2028 usecs +PCI: 00:01.0 init ... +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: Dumping registers + reg 0x0000: 0x00000000 + reg 0x0001: 0x00170011 + reg 0x0002: 0x00000000 +IOAPIC: 24 interrupts +IOAPIC: Enabling interrupts on FSB +IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 +IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 +IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 +lpc_init: pm_base = 2000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +set power on after power fail +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +RTC Init +PCI: 00:01.0 init finished in 164685 usecs +PCI: 00:02.0 init ... +PCI: 00:02.0 init finished in 2026 usecs +PCI: 00:02.1 init ... +PCI: 00:02.1 init finished in 2018 usecs +PCI: 00:06.0 init ... +IDE1 IDE0 +PCI: 00:06.0 init finished in 3105 usecs +PCI: 00:07.0 init ... +SATA S SATA P +PCI: 00:07.0 init finished in 3534 usecs +PCI: 00:08.0 init ... +SATA S SATA P +PCI: 00:08.0 init finished in 3517 usecs +PCI: 00:09.0 init ... +PCI DOMAIN mem base = 0x00f8000000 +[0x50] <-- 0xf8000000 +PCI: 00:09.0 init finished in 7192 usecs +PCI: 00:0b.0 init ... +PCI: 00:0b.0 init finished in 2017 usecs +PCI: 00:0c.0 init ... +PCI: 00:0c.0 init finished in 2019 usecs +PCI: 00:0d.0 init ... +PCI: 00:0d.0 init finished in 2019 usecs +PCI: 00:0e.0 init ... +PCI: 00:0e.0 init finished in 2018 usecs +PNP: 002e.0 init ... +PNP: 002e.0 init finished in 1939 usecs +PNP: 002e.2 init ... +PNP: 002e.2 init finished in 1930 usecs +PNP: 002e.3 init ... +PNP: 002e.3 init finished in 1931 usecs +PNP: 002e.5 init ... +Keyboard init... +PNP: 002e.5 init finished in 352042 usecs +PNP: 002e.9 init ... +PNP: 002e.9 init finished in 1928 usecs +PNP: 002e.b init ... +PNP: 002e.b init finished in 1929 usecs +smbus: PCI: 00:01.1[0]->I2C: 01:2f init ... +ID: 5ca3 +I2C: 01:2f init finished in 101140 usecs +PCI: 01:04.0 init ... +XGI Z9s: initializing video device +XGI VGA: Relocate IO address: 1000 [00001030] +XGI VGA: chipid = 31 +XGI VGA: Framebuffer at 0xf8000000, mapped to 0xf8000000, size 16384k +XGI VGA: MMIO at 0xfc000000, mapped to 0xfc000000, size 256k +XGI VGA: No or unknown bridge type detected +XGI VGA: Default mode is 800x600x16 (60Hz) +XGI VGA: Set new mode: 800x600x16-60 +PCI: 01:04.0 init finished in 42544 usecs +PCI: 02:00.0 init ... +PCI: 02:00.0 init finished in 2018 usecs +PCI: 03:00.0 init ... +PCI: 03:00.0 init finished in 2018 usecs +Devices initialized +Show all devs... After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:18.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:01.0: enabled 1 +PNP: 002e.0: enabled 1 +PNP: 002e.1: enabled 0 +PNP: 002e.2: enabled 1 +PNP: 002e.3: enabled 1 +PNP: 002e.5: enabled 1 +PNP: 002e.7: enabled 0 +PNP: 002e.8: enabled 0 +PNP: 002e.9: enabled 1 +PNP: 002e.a: enabled 0 +PNP: 002e.b: enabled 1 +PCI: 00:01.1: enabled 1 +I2C: 01:50: enabled 1 +I2C: 01:51: enabled 1 +I2C: 01:52: enabled 1 +I2C: 01:53: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:2f: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:04.0: enabled 0 +PCI: 00:04.1: enabled 0 +PCI: 00:06.0: enabled 1 +PCI: 00:07.0: enabled 1 +PCI: 00:08.0: enabled 1 +PCI: 00:09.0: enabled 1 +PCI: 01:04.0: enabled 1 +PCI: 00:0a.0: enabled 0 +PCI: 00:0b.0: enabled 1 +PCI: 02:00.0: enabled 1 +PCI: 00:0c.0: enabled 1 +PCI: 03:00.0: enabled 1 +PCI: 00:0d.0: enabled 1 +PCI: 04:00.0: enabled 0 +PCI: 00:0e.0: enabled 1 +PCI: 00:0f.0: enabled 0 +PCI: 00:18.1: enabled 1 +PCI: 00:18.2: enabled 1 +PCI: 00:18.3: enabled 1 +PCI: 00:18.4: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:19.1: enabled 1 +PCI: 00:19.2: enabled 1 +PCI: 00:19.3: enabled 1 +PCI: 00:19.4: enabled 1 +APIC: 01: enabled 1 +APIC: 02: enabled 1 +APIC: 03: enabled 1 +APIC: 04: enabled 1 +APIC: 05: enabled 1 +APIC: 06: enabled 1 +APIC: 07: enabled 1 +BS: BS_DEV_INIT times (us): entry 0 run 1990325 exit 0 +Finalize devices... +Devices finalized +BS: BS_POST_DEVICE times (us): entry 0 run 3526 exit 0 +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CONFIG_LOGICAL_CPUS==1: apicid_base: 00000001 +Writing IRQ routing tables to 0xf0000...done. +Writing IRQ routing tables to 0xbffd8000...done. +PIRQ table: 224 bytes. +Wrote the mp table end at: 000f0410 - 000f05cc +Wrote the mp table end at: bffd7010 - bffd71cc +MP table: 460 bytes. +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/dsdt.aml' +CBFS: Found @ offset c00 size 2644 +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/slic' +CBFS: 'fallback/slic' not found. +ACPI: Writing ACPI tables at bffb3000. +ACPI: * FACS +ACPI: * DSDT +ACPI: * FADT +pm_base: 0x2000 +ACPI: added table 1/32, length now 40 +ACPI: * SSDT +processor_brand=Quad-Core AMD Opteron(tm) Processor 8347 +Pstates algorithm ... +Pstate_freq[0] = 1900MHz Pstate_power[0] = 23040mw +Pstate_latency[0] = 5us +Pstate_freq[1] = 1700MHz Pstate_power[1] = 21385mw +Pstate_latency[1] = 5us +Pstate_freq[2] = 1400MHz Pstate_power[2] = 18787mw +Pstate_latency[2] = 5us +Pstate_freq[3] = 1200MHz Pstate_power[3] = 16770mw +Pstate_latency[3] = 5us +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +ACPI: added table 2/32, length now 44 +ACPI: * MCFG +ACPI: * TCPA +TCPA log created at bffa3000 +ACPI: added table 3/32, length now 48 +ACPI: * MADT +ACPI: added table 4/32, length now 52 +current = bffb6910 +ACPI: * SRAT at bffb6910 +SRAT: lapic cpu_index=00, node_id=00, apic_id=00 +SRAT: lapic cpu_index=01, node_id=00, apic_id=01 +SRAT: lapic cpu_index=02, node_id=00, apic_id=02 +SRAT: lapic cpu_index=03, node_id=00, apic_id=03 +SRAT: lapic cpu_index=04, node_id=01, apic_id=04 +SRAT: lapic cpu_index=05, node_id=01, apic_id=05 +SRAT: lapic cpu_index=06, node_id=01, apic_id=06 +SRAT: lapic cpu_index=07, node_id=01, apic_id=07 +set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 +set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 +set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 +set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00100000 +set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=00500000, sizek=00100000 +ACPI: added table 5/32, length now 56 +ACPI: * SLIT at bffb6a88 +ACPI: added table 6/32, length now 60 +ACPI: * HPET +ACPI: added table 7/32, length now 64 +ACPI: * SRAT at bffb6b00 +SRAT: lapic cpu_index=00, node_id=00, apic_id=00 +SRAT: lapic cpu_index=01, node_id=00, apic_id=01 +SRAT: lapic cpu_index=02, node_id=00, apic_id=02 +SRAT: lapic cpu_index=03, node_id=00, apic_id=03 +SRAT: lapic cpu_index=04, node_id=01, apic_id=04 +SRAT: lapic cpu_index=05, node_id=01, apic_id=05 +SRAT: lapic cpu_index=06, node_id=01, apic_id=06 +SRAT: lapic cpu_index=07, node_id=01, apic_id=07 +set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 +set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 +set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 +set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00100000 +set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=00500000, sizek=00100000 +ACPI: added table 8/32, length now 68 +ACPI: * SLIT at bffb6c78 +ACPI: added table 9/32, length now 72 +ACPI: done. +ACPI tables: 15536 bytes. +smbios_write_tables: bffa2000 +Root Device (ASUS KFSN4-DRE) +CPU_CLUSTER: 0 (AMD FAM10 Root Complex) +APIC: 00 (unknown) +DOMAIN: 0000 (AMD FAM10 Root Complex) +PCI: 00:18.0 (AMD FAM10 Northbridge) +PCI: 00:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:01.0 (NVIDIA CK804 Southbridge) +PNP: 002e.0 (Winbond W83627THG Super I/O) +PNP: 002e.1 (Winbond W83627THG Super I/O) +PNP: 002e.2 (Winbond W83627THG Super I/O) +PNP: 002e.3 (Winbond W83627THG Super I/O) +PNP: 002e.5 (Winbond W83627THG Super I/O) +PNP: 002e.7 (Winbond W83627THG Super I/O) +PNP: 002e.8 (Winbond W83627THG Super I/O) +PNP: 002e.9 (Winbond W83627THG Super I/O) +PNP: 002e.a (Winbond W83627THG Super I/O) +PNP: 002e.b (Winbond W83627THG Super I/O) +PCI: 00:01.1 (NVIDIA CK804 Southbridge) +I2C: 01:50 (unknown) +I2C: 01:51 (unknown) +I2C: 01:52 (unknown) +I2C: 01:53 (unknown) +I2C: 01:54 (unknown) +I2C: 01:55 (unknown) +I2C: 01:56 (unknown) +I2C: 01:57 (unknown) +I2C: 01:2f (Nuvoton W83793 Hardware Monitor) +PCI: 00:02.0 (NVIDIA CK804 Southbridge) +PCI: 00:02.1 (NVIDIA CK804 Southbridge) +PCI: 00:04.0 (NVIDIA CK804 Southbridge) +PCI: 00:04.1 (NVIDIA CK804 Southbridge) +PCI: 00:06.0 (NVIDIA CK804 Southbridge) +PCI: 00:07.0 (NVIDIA CK804 Southbridge) +PCI: 00:08.0 (NVIDIA CK804 Southbridge) +PCI: 00:09.0 (NVIDIA CK804 Southbridge) +PCI: 01:04.0 (NVIDIA CK804 Southbridge) +PCI: 00:0a.0 (NVIDIA CK804 Southbridge) +PCI: 00:0b.0 (NVIDIA CK804 Southbridge) +PCI: 02:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:0c.0 (NVIDIA CK804 Southbridge) +PCI: 03:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:0d.0 (NVIDIA CK804 Southbridge) +PCI: 04:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:0e.0 (NVIDIA CK804 Southbridge) +PCI: 00:0f.0 (NVIDIA CK804 Southbridge) +PCI: 00:18.1 (AMD FAM10 Northbridge) +PCI: 00:18.2 (AMD FAM10 Northbridge) +PCI: 00:18.3 (AMD FAM10 Northbridge) +PCI: 00:18.4 (AMD FAM10 Northbridge) +PCI: 00:19.0 (AMD FAM10 Northbridge) +PCI: 00:19.1 (AMD FAM10 Northbridge) +PCI: 00:19.2 (AMD FAM10 Northbridge) +PCI: 00:19.3 (AMD FAM10 Northbridge) +PCI: 00:19.4 (AMD FAM10 Northbridge) +APIC: 01 (unknown) +APIC: 02 (unknown) +APIC: 03 (unknown) +APIC: 04 (unknown) +APIC: 05 (unknown) +APIC: 06 (unknown) +APIC: 07 (unknown) +SMBIOS tables: 553 bytes. +Writing table forward entry at 0x00000500 +Wrote coreboot table at: 00000500, 0x10 bytes, checksum 9fe4 +Table forward entry ends at 0x00000528. +... aligned to 0x00001000 +Writing coreboot table at 0xbff9a000 +rom_table_end = 0xbff9a000 +... aligned to 0xbffa0000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 + 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES + 1. 0000000000001000-000000000009ffff: RAM + 2. 00000000000a0000-00000000000bffff: RESERVED + 3. 00000000000c0000-00000000bff99fff: RAM + 4. 00000000bff9a000-00000000bfffffff: CONFIGURATION TABLES + 5. 00000000c0000000-00000000cfffffff: RESERVED + 6. 0000000100000000-000000017fffffff: RAM +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Wrote coreboot table at: bff9a000, 0xc08 bytes, checksum 440a +coreboot table: 3104 bytes. +IMD ROOT 0. bffff000 00001000 +IMD SMALL 1. bfffe000 00001000 +CAR GLOBALS 2. bfffb000 0000291c +CONSOLE 3. bffdb000 00020000 +AMDMEM INFO 4. bffd9000 0000172c +IRQ TABLE 5. bffd8000 00001000 +SMP TABLE 6. bffd7000 00001000 +ACPI 7. bffb3000 00024000 +54435041 8. bffa3000 00010000 +SMBIOS 9. bffa2000 00000800 +COREBOOT 10. bff9a000 00008000 +IMD small region: + IMD ROOT 0. bfffec00 00000400 + USBDEBUG 1. bfffeba0 00000058 + ROMSTAGE 2. bfffeb80 00000004 + GDT 3. bfffe980 00000200 +BS: BS_WRITE_TABLES times (us): entry 0 run 759226 exit 0 +CBFS provider active. +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/payload' +CBFS: Found @ offset 29c80 size 92b41 +'fallback/payload' located at offset: 29cb8 size: 92b41 +Loading segment from rom address 0xfff29cb8 + code (compression=1) + New segment dstaddr 0x8200 memsize 0x17420 srcaddr 0xfff29d0c filesize 0x8215 +Loading segment from rom address 0xfff29cd4 + code (compression=1) + New segment dstaddr 0x100000 memsize 0x23f9f0 srcaddr 0xfff31f21 filesize 0x8a8d8 +Loading segment from rom address 0xfff29cf0 + Entry Point 0x00008200 +Bounce Buffer at bfc5b000, 3401660 bytes +Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017420 filesz: 0x0000000000008215 +lb: [0x0000000000100000, 0x00000000001fedcc) +Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017420 filesz: 0x0000000000008215 +using LZMA +[ 0x00008200, 00017ce3, 0x0001f620) <- fff29d0c +Clearing Segment: addr: 0x0000000000017ce3 memsz: 0x000000000000793d +dest 00008200, end 0001f620, bouncebuffer bfc5b000 +Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000023f9f0 filesz: 0x000000000008a8d8 +lb: [0x0000000000100000, 0x00000000001fedcc) +segment: [0x0000000000100000, 0x000000000018a8d8, 0x000000000033f9f0) + bounce: [0x00000000bfc5b000, 0x00000000bfce58d8, 0x00000000bfe9a9f0) +Post relocation: addr: 0x00000000bfc5b000 memsz: 0x000000000023f9f0 filesz: 0x000000000008a8d8 +using LZMA +[ 0xbfc5b000, bfe9a9f0, 0xbfe9a9f0) <- fff31f21 +dest bfc5b000, end bfe9a9f0, bouncebuffer bfc5b000 +move suffix around: from bfd59dcc, to 1fedcc, amount: 140c24 +Loaded segments +BS: BS_PAYLOAD_LOAD times (us): entry 0 run 781450 exit 0 +Jumping to boot code at 00008200(bff9a000) +CPU0: stack: 00139000 - 0013a000, lowest used address 00139ae0, stack used: 1312 bytes +entry = 0x00008200 +lb_start = 0x00100000 +lb_size = 0x000fedcc +buffer = 0xbfc5b000 +[?25lFREE AS IN FREEDOM + + ++----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. + + Press enter to boot the selected OS, `e' to edit the commands + + before booting or `c' for a command-line.  *Load Operating System  Parse ISOLINUX menu (ahci0)  Parse ISOLINUX menu (USB)  Parse ISOLINUX menu (CD/DVD)  Switch to grubtest.cfg  Search for GRUB configuration (grub.cfg) outside of CBFS  Load MemTest86+        The highlighted entry will be executed automatically in 1s.  The highlighted entry will be executed automatically in 0s. [?25h Booting `Load Operating System' + + + + Failed to boot both default and fallback entries. + + +Press any key to continue... + +[?25lFREE AS IN FREEDOM + + ++----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. + + Press enter to boot the selected OS, `e' to edit the commands + + before booting or `c' for a command-line.  *Load Operating System  Parse ISOLINUX menu (ahci0)  Parse ISOLINUX menu (USB)  Parse ISOLINUX menu (CD/DVD)  Switch to grubtest.cfg  Search for GRUB configuration (grub.cfg) outside of CBFS  Load MemTest86+          Load Operating System *Parse ISOLINUX menu (ahci0)  Parse ISOLINUX menu (ahci0) *Parse ISOLINUX menu (USB)  Parse ISOLINUX menu (USB) *Parse ISOLINUX menu (CD/DVD)  Parse ISOLINUX menu (CD/DVD) *Switch to grubtest.cfg  ��ޒ���������� + +*****GRAPHICAL FRAMEBUFFER ROM IMAGE***** + + + +coreboot-4.0 Fri Jun 26 20:19:42 UTC 2015 romstage starting... +BSP Family_Model: 00100f21 +*sysinfo range: [000c4000,000c6899] +bsp_apicid = 00 +cpu_init_detectedx = 00000000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: 'cpu_microcode_blob.bin' not found. +[microcode] microcode file not found. Skipping updates. +cpuSetAMDMSR done +Enter amd_ht_init() +AMD_CB_EventNotify() + event class: 05 + event: 1004 + data: 04 00 00 01 +AMD_CB_EventNotify() + event class: 05 + event: 2006 + data: 04 00 01 00 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Exit amd_ht_init() +cpuSetAMDPCI 00 done +cpuSetAMDPCI 01 done +Prep FID/VID Node:00 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f23 + F3xD8: 03001c14 + F3xDC: 00005428 +Prep FID/VID Node:01 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f23 + F3xD8: 03001c14 + F3xDC: 00005428 +setup_remote_node: 01 done +Start node 01 done. +core0 started: 01 + +Begin FIDVID MSR 0xc0010071 0x20a600e4 0x38045044 +FIDVID on BSP, APIC_id: 00 +BSP fid = 10400 +Wait for AP stage 1: ap_apicid = 1 +init_fidvid_bsp_stage1: timed out reading from ap 01 +Wait for AP stage 1: ap_apicid = 2 +init_fidvid_bsp_stage1: timed out reading from ap 02 +Wait for AP stage 1: ap_apicid = 3 +init_fidvid_bsp_stage1: timed out reading from ap 03 +Wait for AP stage 1: ap_apicid = 4 + readback = 4010401 + common_fid(packed) = 10400 +Wait for AP stage 1: ap_apicid = 5 +init_fidvid_bsp_stage1: timed out reading from ap 05 +Wait for AP stage 1: ap_apicid = 6 +init_fidvid_bsp_stage1: timed out reading from ap 06 +Wait for AP stage 1: ap_apicid = 7 +init_fidvid_bsp_stage1: timed out reading from ap 07 +common_fid = 10400 +FID Change Node:00, F3xD4: c3310f24 +FID Change Node:01, F3xD4: c3310f24 +End FIDVIDMSR 0xc0010071 0x20a600e4 0x38005044 +start_other_cores() +init node: 00 cores: 03 +Start other core - nodeid: 00 cores: 03 +init node: 01 cores: 03 +Start other core - nodeid: 01 cores: 03 +started ap apicid: 01start + +coreboot-4.0 Fri Jun 26 20:19:42 UTC 2015 romstage starting... +BSP Family_Model: 00100f21 +*sysinfo range: [000c4000,000c6899] +bsp_apicid = 00 +cpu_init_detectedx = 00000000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: 'cpu_microcode_blob.bin' not found. +[microcode] microcode file not found. Skipping updates. +cpuSetAMDMSR done +Enter amd_ht_init() +AMD_CB_EventNotify() + event class: 05 + event: 1004 + data: 04 00 00 01 +AMD_CB_EventNotify() + event class: 05 + event: 2006 + data: 04 00 01 00 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Exit amd_ht_init() +cpuSetAMDPCI 00 done +cpuSetAMDPCI 01 done +Prep FID/VID Node:00 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f24 + F3xD8: 03001c14 + F3xDC: 00005428 +Prep FID/VID Node:01 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f24 + F3xD8: 03001c14 + F3xDC: 00005428 +setup_remote_node: 01 done +Start node 01 done. +core0 started: 01 + +Begin FIDVID MSR 0xc0010071 0x20a600e4 0x38005044 +End FIDVIDMSR 0xc0010071 0x20a600e4 0x38003803 +start_other_cores() +init node: 00 cores: 03 +Start other core - nodeid: 00 cores: 03 +init node: 01 cores: 03 +Start other core - nodeid: 01 cores: 03 +started ap apicid: * AP 01started +* AP 02started +* AP 03started +* AP 05started +* AP 06started +* AP 07started + +set_ck804_base_unit_id() +fill_mem_ctrl() +enable_smbus() +SMBus controller enabled +raminit_amdmct() +raminit_amdmct begin: +activate_spd_rom() for node 00 +enable_spd_node0() +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +activate_spd_rom() for node 01 +enable_spd_node1() +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 + Node: 00 base: 00 limit: ffffff BottomIO: c00000 + Node: 01 base: 1400000 limit: 17fffff BottomIO: c00000 + Copy dram map from Node 0 to Node 01 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +raminit_amdmct end: +CBMEM: +IMD: root @ bffff000 254 entries. +IMD: root @ bfffec00 62 entries. +amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +disable_spd() +enable_msi_mapping() +Prepare CAR migration and stack regions... Fill [003fd000-003fffff] ... Done +Copying data from cache to RAM... Copy [000c4000-000c693f] to [003fd6c0 - 003fffff] ... Done +Switching to use RAM as stack... Top about 003fd6ac ... Done +Disabling cache as ram now +Prepare ramstage memory region... Fill [00000000-003fcfff] ... Done +CBFS provider active. +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/ramstage' +CBFS: Found @ offset 15440 size 147e1 +'fallback/ramstage' located at offset: 15478 size: 147e1 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Capability: type 0x0a @ 0x44 + +coreboot-4.0 Fri Jun 26 20:19:42 UTC 2015 ramstage starting... +Moving GDT to bfffe980...ok +BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 0 +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0 +Enumerating buses... +Show all devs... Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:18.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:01.0: enabled 1 +PNP: 002e.0: enabled 1 +PNP: 002e.1: enabled 0 +PNP: 002e.2: enabled 1 +PNP: 002e.3: enabled 1 +PNP: 002e.5: enabled 1 +PNP: 002e.7: enabled 0 +PNP: 002e.8: enabled 0 +PNP: 002e.9: enabled 1 +PNP: 002e.a: enabled 0 +PNP: 002e.b: enabled 1 +PCI: 00:01.1: enabled 1 +I2C: 00:50: enabled 1 +I2C: 00:51: enabled 1 +I2C: 00:52: enabled 1 +I2C: 00:53: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:2f: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:04.0: enabled 0 +PCI: 00:04.1: enabled 0 +PCI: 00:06.0: enabled 1 +PCI: 00:07.0: enabled 1 +PCI: 00:08.0: enabled 1 +PCI: 00:09.0: enabled 1 +PCI: 00:04.0: enabled 1 +PCI: 00:0a.0: enabled 0 +PCI: 00:0b.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:0c.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:0d.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:0e.0: enabled 1 +PCI: 00:0f.0: enabled 0 +PCI: 00:18.1: enabled 1 +PCI: 00:18.2: enabled 1 +PCI: 00:18.3: enabled 1 +PCI: 00:18.4: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:19.1: enabled 1 +PCI: 00:19.2: enabled 1 +PCI: 00:19.3: enabled 1 +PCI: 00:19.4: enabled 1 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + DOMAIN: 0000: enabled 1 + PCI: 00:18.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:01.0: enabled 1 + PNP: 002e.0: enabled 1 + PNP: 002e.1: enabled 0 + PNP: 002e.2: enabled 1 + PNP: 002e.3: enabled 1 + PNP: 002e.5: enabled 1 + PNP: 002e.7: enabled 0 + PNP: 002e.8: enabled 0 + PNP: 002e.9: enabled 1 + PNP: 002e.a: enabled 0 + PNP: 002e.b: enabled 1 + PCI: 00:01.1: enabled 1 + I2C: 00:50: enabled 1 + I2C: 00:51: enabled 1 + I2C: 00:52: enabled 1 + I2C: 00:53: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:2f: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:04.0: enabled 0 + PCI: 00:04.1: enabled 0 + PCI: 00:06.0: enabled 1 + PCI: 00:07.0: enabled 1 + PCI: 00:08.0: enabled 1 + PCI: 00:09.0: enabled 1 + PCI: 00:04.0: enabled 1 + PCI: 00:0a.0: enabled 0 + PCI: 00:0b.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:0c.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:0d.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:0e.0: enabled 1 + PCI: 00:0f.0: enabled 0 + PCI: 00:18.1: enabled 1 + PCI: 00:18.2: enabled 1 + PCI: 00:18.3: enabled 1 + PCI: 00:18.4: enabled 1 + PCI: 00:19.0: enabled 1 + PCI: 00:19.1: enabled 1 + PCI: 00:19.2: enabled 1 + PCI: 00:19.3: enabled 1 + PCI: 00:19.4: enabled 1 +Root Device scanning... +root_dev_scan_bus for Root Device +setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 +setup_bsp_ramtop, TOP MEM2: msr.lo = 0x80000000, msr.hi = 0x00000001 +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +CPU_CLUSTER: 0 scanning... +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 + PCI: 00:18.3 siblings=3 +CPU: APIC: 00 enabled +CPU: APIC: 01 enabled +CPU: APIC: 02 enabled +CPU: APIC: 03 enabled + PCI: 00:19.3 siblings=3 +CPU: APIC: 04 enabled +CPU: APIC: 05 enabled +CPU: APIC: 06 enabled +CPU: APIC: 07 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:18.0 [1022/1200] bus ops +PCI: 00:18.0 [1022/1200] enabled +PCI: 00:18.1 [1022/1201] enabled +PCI: 00:18.2 [1022/1202] enabled +PCI: 00:18.3 [1022/1203] ops +PCI: 00:18.3 [1022/1203] enabled +PCI: 00:18.4 [1022/1204] enabled +PCI: 00:19.0 [1022/1200] bus ops +PCI: 00:19.0 [1022/1200] enabled +PCI: 00:19.1 [1022/1201] enabled +PCI: 00:19.2 [1022/1202] enabled +PCI: 00:19.3 [1022/1203] ops +PCI: 00:19.3 [1022/1203] enabled +PCI: 00:19.4 [1022/1204] enabled +PCI: 00:18.0 scanning... +PCI: 00:00.0 [10de/005e] ops +PCI: 00:00.0 [10de/005e] enabled +Capability: type 0x08 @ 0x44 +flags: 0x01e0 +PCI: 00:00.0 count: 000f static_count: 0010 +PCI: 00:00.0 [10de/005e] enabled next_unitid: 0010 +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [10de/005e] enabled +PCI: 00:01.0 [10de/0051] bus ops +PCI: 00:01.0 [10de/0051] enabled +PCI: 00:01.1 [10de/0052] bus ops +PCI: 00:01.1 [10de/0052] enabled +PCI: 00:02.0 [10de/005a] ops +PCI: 00:02.0 [10de/005a] enabled +PCI: 00:02.1 [10de/005b] ops +PCI: 00:02.1 [10de/005b] enabled +PCI: 00:04.0 [10de/0059] ops +PCI: 00:04.0 [10de/0059] disabled +PCI: 00:04.1 [10de/0058] ops +PCI: 00:04.1 [10de/0058] disabled +PCI: 00:06.0 [10de/0053] ops +PCI: 00:06.0 [10de/0053] enabled +PCI: 00:07.0 [10de/0054] ops +PCI: 00:07.0 [10de/0054] enabled +PCI: 00:08.0 [10de/0055] ops +PCI: 00:08.0 [10de/0055] enabled +PCI: 00:09.0 [10de/005c] bus ops +PCI: 00:09.0 [10de/005c] enabled +PCI: 00:0b.0 [10de/005d] bus ops +PCI: 00:0b.0 [10de/005d] enabled +PCI: 00:0c.0 [10de/005d] bus ops +PCI: 00:0c.0 [10de/005d] enabled +PCI: 00:0d.0 [10de/005d] bus ops +PCI: 00:0d.0 [10de/005d] enabled +PCI: 00:0e.0 [10de/005d] bus ops +PCI: 00:0e.0 [10de/005d] enabled +PCI: 00:01.0 scanning... +scan_lpc_bus for PCI: 00:01.0 +PNP: 002e.0 enabled +PNP: 002e.1 disabled +PNP: 002e.2 enabled +PNP: 002e.3 enabled +PNP: 002e.5 enabled +PNP: 002e.7 disabled +PNP: 002e.8 disabled +PNP: 002e.9 enabled +PNP: 002e.a disabled +PNP: 002e.b enabled +scan_lpc_bus for PCI: 00:01.0 done +PCI: 00:01.1 scanning... +scan_smbus for PCI: 00:01.1 +smbus: PCI: 00:01.1[0]->I2C: 01:50 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:51 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:52 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:53 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:54 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:55 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:56 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:57 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:2f enabled +scan_smbus for PCI: 00:01.1 done +PCI: 00:09.0 scanning... +do_pci_scan_bridge for PCI: 00:09.0 +PCI: pci_scan_bus for bus 01 +PCI: 01:04.0 [18ca/0020] ops +PCI: 01:04.0 [18ca/0020] enabled +PCI: 00:0b.0 scanning... +do_pci_scan_bridge for PCI: 00:0b.0 +PCI: pci_scan_bus for bus 02 +PCI: 02:00.0 [14e4/1659] enabled +PCI: 00:0c.0 scanning... +do_pci_scan_bridge for PCI: 00:0c.0 +PCI: pci_scan_bus for bus 03 +PCI: 03:00.0 [14e4/1659] enabled +PCI: 00:0d.0 scanning... +do_pci_scan_bridge for PCI: 00:0d.0 +PCI: pci_scan_bus for bus 04 +PCI: Static device PCI: 04:00.0 not found, disabling it. +PCI: 00:0e.0 scanning... +do_pci_scan_bridge for PCI: 00:0e.0 +PCI: pci_scan_bus for bus 05 +PCI: 00:19.0 scanning... +DOMAIN: 0000 passpw: enabled +DOMAIN: 0000 passpw: enabled +root_dev_scan_bus for Root Device done +done +BS: BS_DEV_ENUMERATE times (us): entry 0 run 598144 exit 0 +found VGA at PCI: 01:04.0 +Setting up VGA for PCI: 01:04.0 +Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:09.0 +Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +APIC: 01 missing read_resources +APIC: 02 missing read_resources +APIC: 03 missing read_resources +APIC: 04 missing read_resources +APIC: 05 missing read_resources +APIC: 06 missing read_resources +APIC: 07 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +PCI: 00:18.0 read_resources bus 0 link: 1 +PCI: 00:01.0 read_resources bus 0 link: 0 +PCI: 00:01.0 read_resources bus 0 link: 0 done +PCI: 00:01.1 read_resources bus 1 link: 0 +I2C: 01:50 missing read_resources +I2C: 01:51 missing read_resources +I2C: 01:52 missing read_resources +I2C: 01:53 missing read_resources +I2C: 01:54 missing read_resources +I2C: 01:55 missing read_resources +I2C: 01:56 missing read_resources +I2C: 01:57 missing read_resources +PCI: 00:01.1 read_resources bus 1 link: 0 done +PCI: 00:01.1 read_resources bus 2 link: 1 +PCI: 00:01.1 read_resources bus 2 link: 1 done +PCI: 00:09.0 read_resources bus 1 link: 0 +PCI: 00:09.0 read_resources bus 1 link: 0 done +PCI: 00:0b.0 read_resources bus 2 link: 0 +PCI: 00:0b.0 read_resources bus 2 link: 0 done +PCI: 00:0c.0 read_resources bus 3 link: 0 +PCI: 00:0c.0 read_resources bus 3 link: 0 done +PCI: 00:0d.0 read_resources bus 4 link: 0 +PCI: 00:0d.0 read_resources bus 4 link: 0 done +PCI: 00:0e.0 read_resources bus 5 link: 0 +PCI: 00:0e.0 read_resources bus 5 link: 0 done +PCI: 00:18.0 read_resources bus 0 link: 1 done +PCI: 00:18.0 read_resources bus 0 link: 0 +PCI: 00:18.0 read_resources bus 0 link: 0 done +PCI: 00:18.0 read_resources bus 0 link: 2 +PCI: 00:18.0 read_resources bus 0 link: 2 done +PCI: 00:18.0 read_resources bus 0 link: 3 +PCI: 00:18.0 read_resources bus 0 link: 3 done +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +PCI: 00:18.4 read_resources bus 0 link: 0 +PCI: 00:18.4 read_resources bus 0 link: 0 done +PCI: 00:18.4 read_resources bus 0 link: 1 +PCI: 00:18.4 read_resources bus 0 link: 1 done +PCI: 00:18.4 read_resources bus 0 link: 2 +PCI: 00:18.4 read_resources bus 0 link: 2 done +PCI: 00:18.4 read_resources bus 0 link: 3 +PCI: 00:18.4 read_resources bus 0 link: 3 done +PCI: 00:19.0 read_resources bus 0 link: 0 +PCI: 00:19.0 read_resources bus 0 link: 0 done +PCI: 00:19.0 read_resources bus 0 link: 1 +PCI: 00:19.0 read_resources bus 0 link: 1 done +PCI: 00:19.0 read_resources bus 0 link: 2 +PCI: 00:19.0 read_resources bus 0 link: 2 done +PCI: 00:19.0 read_resources bus 0 link: 3 +PCI: 00:19.0 read_resources bus 0 link: 3 done +PCI: 00:19.4 read_resources bus 0 link: 0 +PCI: 00:19.4 read_resources bus 0 link: 0 done +PCI: 00:19.4 read_resources bus 0 link: 1 +PCI: 00:19.4 read_resources bus 0 link: 1 done +PCI: 00:19.4 read_resources bus 0 link: 2 +PCI: 00:19.4 read_resources bus 0 link: 2 done +PCI: 00:19.4 read_resources bus 0 link: 3 +PCI: 00:19.4 read_resources bus 0 link: 3 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: 01 + APIC: 02 + APIC: 03 + APIC: 04 + APIC: 05 + APIC: 06 + APIC: 07 + DOMAIN: 0000 child on link 0 PCI: 00:18.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 + DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 + PCI: 00:18.0 child on link 0 PCI: 00:00.0 + PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8 + PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b8 + PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b0 + PCI: 00:00.0 + PCI: 00:01.0 child on link 0 PNP: 002e.0 + PCI: 00:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10 + PCI: 00:01.0 resource base fec00000 size 1000 align 12 gran 12 limit ffffffff flags c0000200 index 14 + PCI: 00:01.0 resource base fed00000 size 1000 align 12 gran 12 limit ffffffff flags c0000200 index 44 + PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60 + PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 64 + PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 68 + PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PNP: 002e.0 + PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.3 + PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000500 index f1 + PNP: 002e.5 + PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 + PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 + PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 + PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.7 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 + PNP: 002e.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.8 + PNP: 002e.9 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 30 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f1 + PNP: 002e.a + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.b + PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60 + PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PCI: 00:01.1 child on link 0 I2C: 01:50 + PCI: 00:01.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 10 + PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 + PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24 + I2C: 01:50 + I2C: 01:51 + I2C: 01:52 + I2C: 01:53 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:2f + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:04.0 + PCI: 00:04.1 + PCI: 00:06.0 + PCI: 00:06.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:07.0 + PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:07.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:07.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 00:08.0 + PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 00:09.0 child on link 0 PCI: 01:04.0 + PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 + PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:04.0 + PCI: 01:04.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 + PCI: 01:04.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 14 + PCI: 01:04.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18 + PCI: 00:0a.0 + PCI: 00:0b.0 child on link 0 PCI: 02:00.0 + PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:0c.0 child on link 0 PCI: 03:00.0 + PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 03:00.0 + PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:0d.0 child on link 0 PCI: 04:00.0 + PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 04:00.0 + PCI: 00:0e.0 + PCI: 00:0e.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:0f.0 + PCI: 00:18.1 + PCI: 00:18.2 + PCI: 00:18.3 + PCI: 00:18.4 + PCI: 00:19.0 + PCI: 00:19.1 + PCI: 00:19.2 + PCI: 00:19.3 + PCI: 00:19.4 +DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:04.0 18 * [0x0 - 0x7f] io +PCI: 00:09.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:0e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:09.0 1c * [0x0 - 0xfff] io +PCI: 00:01.0 60 * [0x1000 - 0x10ff] io +PCI: 00:01.0 64 * [0x1400 - 0x14ff] io +PCI: 00:01.0 68 * [0x1800 - 0x18ff] io +PCI: 00:01.0 10 * [0x1c00 - 0x1c7f] io +PCI: 00:01.1 20 * [0x1c80 - 0x1cbf] io +PCI: 00:01.1 24 * [0x1cc0 - 0x1cff] io +PCI: 00:01.1 10 * [0x2000 - 0x201f] io +PCI: 00:06.0 20 * [0x2020 - 0x202f] io +PCI: 00:07.0 20 * [0x2030 - 0x203f] io +PCI: 00:08.0 20 * [0x2040 - 0x204f] io +PCI: 00:07.0 10 * [0x2050 - 0x2057] io +PCI: 00:07.0 18 * [0x2058 - 0x205f] io +PCI: 00:08.0 10 * [0x2060 - 0x2067] io +PCI: 00:08.0 18 * [0x2068 - 0x206f] io +PCI: 00:07.0 14 * [0x2070 - 0x2073] io +PCI: 00:07.0 1c * [0x2074 - 0x2077] io +PCI: 00:08.0 14 * [0x2078 - 0x207b] io +PCI: 00:08.0 1c * [0x207c - 0x207f] io +PCI: 00:18.0 io: base: 2080 size: 3000 align: 12 gran: 12 limit: ffff done +PCI: 00:18.0 110d8 * [0x0 - 0x2fff] io +DOMAIN: 0000 io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff +PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:04.0 10 * [0x0 - 0x3ffffff] prefmem +PCI: 00:09.0 prefmem: base: 4000000 size: 4000000 align: 26 gran: 20 limit: ffffffff done +PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:0e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:09.0 24 * [0x0 - 0x3ffffff] prefmem +PCI: 00:18.0 prefmem: base: 4000000 size: 4000000 align: 26 gran: 20 limit: ffffffff done +PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff +PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:04.0 14 * [0x0 - 0x3ffff] mem +PCI: 00:09.0 mem: base: 40000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:0b.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 03:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:0c.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:0e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:09.0 20 * [0x0 - 0xfffff] mem +PCI: 00:0b.0 20 * [0x100000 - 0x1fffff] mem +PCI: 00:0c.0 20 * [0x200000 - 0x2fffff] mem +PCI: 00:02.0 10 * [0x300000 - 0x300fff] mem +PCI: 00:07.0 24 * [0x301000 - 0x301fff] mem +PCI: 00:08.0 24 * [0x302000 - 0x302fff] mem +PCI: 00:02.1 10 * [0x303000 - 0x3030ff] mem +PCI: 00:18.0 mem: base: 303100 size: 400000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:18.0 110b8 * [0x0 - 0x3ffffff] prefmem +PCI: 00:18.0 110b0 * [0x4000000 - 0x43fffff] mem +DOMAIN: 0000 mem: base: 4400000 size: 4400000 align: 26 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed) +constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed) +constrain_resources: PCI: 00:01.0 14 base fec00000 limit fec00fff mem (fixed) +constrain_resources: PCI: 00:01.0 10000000 base 00000000 limit 00000fff io (fixed) +avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 base f8000000 limit febfffff +Setting resources... +DOMAIN: 0000 io: base:1000 size:3000 align:12 gran:0 limit:ffff +PCI: 00:18.0 110d8 * [0x1000 - 0x3fff] io +DOMAIN: 0000 io: next_base: 4000 size: 3000 align: 12 gran: 0 done +PCI: 00:18.0 io: base:1000 size:3000 align:12 gran:12 limit:3fff +PCI: 00:09.0 1c * [0x1000 - 0x1fff] io +PCI: 00:01.0 60 * [0x2000 - 0x20ff] io +PCI: 00:01.0 64 * [0x2400 - 0x24ff] io +PCI: 00:01.0 68 * [0x2800 - 0x28ff] io +PCI: 00:01.0 10 * [0x2c00 - 0x2c7f] io +PCI: 00:01.1 20 * [0x2c80 - 0x2cbf] io +PCI: 00:01.1 24 * [0x2cc0 - 0x2cff] io +PCI: 00:01.1 10 * [0x3000 - 0x301f] io +PCI: 00:06.0 20 * [0x3020 - 0x302f] io +PCI: 00:07.0 20 * [0x3030 - 0x303f] io +PCI: 00:08.0 20 * [0x3040 - 0x304f] io +PCI: 00:07.0 10 * [0x3050 - 0x3057] io +PCI: 00:07.0 18 * [0x3058 - 0x305f] io +PCI: 00:08.0 10 * [0x3060 - 0x3067] io +PCI: 00:08.0 18 * [0x3068 - 0x306f] io +PCI: 00:07.0 14 * [0x3070 - 0x3073] io +PCI: 00:07.0 1c * [0x3074 - 0x3077] io +PCI: 00:08.0 14 * [0x3078 - 0x307b] io +PCI: 00:08.0 1c * [0x307c - 0x307f] io +PCI: 00:18.0 io: next_base: 3080 size: 3000 align: 12 gran: 12 done +PCI: 00:09.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff +PCI: 01:04.0 18 * [0x1000 - 0x107f] io +PCI: 00:09.0 io: next_base: 1080 size: 1000 align: 12 gran: 12 done +PCI: 00:0b.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0b.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +PCI: 00:0c.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0c.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +PCI: 00:0d.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0d.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +PCI: 00:0e.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0e.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +DOMAIN: 0000 mem: base:f8000000 size:4400000 align:26 gran:0 limit:febfffff +PCI: 00:18.0 110b8 * [0xf8000000 - 0xfbffffff] prefmem +PCI: 00:18.0 110b0 * [0xfc000000 - 0xfc3fffff] mem +DOMAIN: 0000 mem: next_base: fc400000 size: 4400000 align: 26 gran: 0 done +PCI: 00:18.0 prefmem: base:f8000000 size:4000000 align:26 gran:20 limit:fbffffff +PCI: 00:09.0 24 * [0xf8000000 - 0xfbffffff] prefmem +PCI: 00:18.0 prefmem: next_base: fc000000 size: 4000000 align: 26 gran: 20 done +PCI: 00:09.0 prefmem: base:f8000000 size:4000000 align:26 gran:20 limit:fbffffff +PCI: 01:04.0 10 * [0xf8000000 - 0xfbffffff] prefmem +PCI: 00:09.0 prefmem: next_base: fc000000 size: 4000000 align: 26 gran: 20 done +PCI: 00:0b.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0b.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:0c.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0c.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:0d.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0d.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:0e.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0e.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:18.0 mem: base:fc000000 size:400000 align:20 gran:20 limit:fc3fffff +PCI: 00:09.0 20 * [0xfc000000 - 0xfc0fffff] mem +PCI: 00:0b.0 20 * [0xfc100000 - 0xfc1fffff] mem +PCI: 00:0c.0 20 * [0xfc200000 - 0xfc2fffff] mem +PCI: 00:02.0 10 * [0xfc300000 - 0xfc300fff] mem +PCI: 00:07.0 24 * [0xfc301000 - 0xfc301fff] mem +PCI: 00:08.0 24 * [0xfc302000 - 0xfc302fff] mem +PCI: 00:02.1 10 * [0xfc303000 - 0xfc3030ff] mem +PCI: 00:18.0 mem: next_base: fc303100 size: 400000 align: 20 gran: 20 done +PCI: 00:09.0 mem: base:fc000000 size:100000 align:20 gran:20 limit:fc0fffff +PCI: 01:04.0 14 * [0xfc000000 - 0xfc03ffff] mem +PCI: 00:09.0 mem: next_base: fc040000 size: 100000 align: 20 gran: 20 done +PCI: 00:0b.0 mem: base:fc100000 size:100000 align:20 gran:20 limit:fc1fffff +PCI: 02:00.0 10 * [0xfc100000 - 0xfc10ffff] mem +PCI: 00:0b.0 mem: next_base: fc110000 size: 100000 align: 20 gran: 20 done +PCI: 00:0c.0 mem: base:fc200000 size:100000 align:20 gran:20 limit:fc2fffff +PCI: 03:00.0 10 * [0xfc200000 - 0xfc20ffff] mem +PCI: 00:0c.0 mem: next_base: fc210000 size: 100000 align: 20 gran: 20 done +PCI: 00:0d.0 mem: base:fc3fffff size:0 align:20 gran:20 limit:fc3fffff +PCI: 00:0d.0 mem: next_base: fc3fffff size: 0 align: 20 gran: 20 done +PCI: 00:0e.0 mem: base:fc3fffff size:0 align:20 gran:20 limit:fc3fffff +PCI: 00:0e.0 mem: next_base: fc3fffff size: 0 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +0: mmio_basek=00300000, basek=00400000, limitk=00500000 +1: mmio_basek=00300000, basek=00500000, limitk=00600000 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device +PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io +PCI: 00:18.0 110b8 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x14 prefmem +PCI: 00:18.0 110b0 <- [0x00fc000000 - 0x00fc3fffff] size 0x00400000 gran 0x14 mem +PCI: 00:18.0 assign_resources, bus 0 link: 1 +PCI: 00:01.0 10 <- [0x0000002c00 - 0x0000002c7f] size 0x00000080 gran 0x07 io +PCI: 00:01.0 60 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io +PCI: 00:01.0 64 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io +PCI: 00:01.0 68 <- [0x0000002800 - 0x00000028ff] size 0x00000100 gran 0x08 io +PCI: 00:01.0 assign_resources, bus 0 link: 0 +PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io +PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq +PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq +PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io +PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq +PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io +PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq +PNP: 002e.3 f1 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 io +PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io +PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io +PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq +PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq +ERROR: PNP: 002e.5 f0 irq size: 0x0000000001 not assigned +ERROR: PNP: 002e.9 30 irq size: 0x0000000001 not assigned +ERROR: PNP: 002e.9 f0 irq size: 0x0000000001 not assigned +ERROR: PNP: 002e.9 f1 irq size: 0x0000000001 not assigned +PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io +PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq +PCI: 00:01.0 assign_resources, bus 0 link: 0 +PCI: 00:01.0 14 <- [0x00fec00000 - 0x00fec00fff] size 0x00001000 gran 0x0c mem +PCI: 00:01.0 44 <- [0x00fed00000 - 0x00fed00fff] size 0x00001000 gran 0x0c mem +PCI: 00:01.1 10 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io +PCI: 00:01.1 20 <- [0x0000002c80 - 0x0000002cbf] size 0x00000040 gran 0x06 io +PCI: 00:01.1 24 <- [0x0000002cc0 - 0x0000002cff] size 0x00000040 gran 0x06 io +PCI: 00:01.1 assign_resources, bus 1 link: 0 +PCI: 00:01.1 assign_resources, bus 1 link: 0 +PCI: 00:02.0 10 <- [0x00fc300000 - 0x00fc300fff] size 0x00001000 gran 0x0c mem +PCI: 00:02.1 10 <- [0x00fc303000 - 0x00fc3030ff] size 0x00000100 gran 0x08 mem +PCI: 00:06.0 20 <- [0x0000003020 - 0x000000302f] size 0x00000010 gran 0x04 io +PCI: 00:07.0 10 <- [0x0000003050 - 0x0000003057] size 0x00000008 gran 0x03 io +PCI: 00:07.0 14 <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io +PCI: 00:07.0 18 <- [0x0000003058 - 0x000000305f] size 0x00000008 gran 0x03 io +PCI: 00:07.0 1c <- [0x0000003074 - 0x0000003077] size 0x00000004 gran 0x02 io +PCI: 00:07.0 20 <- [0x0000003030 - 0x000000303f] size 0x00000010 gran 0x04 io +PCI: 00:07.0 24 <- [0x00fc301000 - 0x00fc301fff] size 0x00001000 gran 0x0c mem +PCI: 00:08.0 10 <- [0x0000003060 - 0x0000003067] size 0x00000008 gran 0x03 io +PCI: 00:08.0 14 <- [0x0000003078 - 0x000000307b] size 0x00000004 gran 0x02 io +PCI: 00:08.0 18 <- [0x0000003068 - 0x000000306f] size 0x00000008 gran 0x03 io +PCI: 00:08.0 1c <- [0x000000307c - 0x000000307f] size 0x00000004 gran 0x02 io +PCI: 00:08.0 20 <- [0x0000003040 - 0x000000304f] size 0x00000010 gran 0x04 io +PCI: 00:08.0 24 <- [0x00fc302000 - 0x00fc302fff] size 0x00001000 gran 0x0c mem +PCI: 00:09.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:09.0 24 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x14 bus 01 prefmem +PCI: 00:09.0 20 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 bus 01 mem +PCI: 00:09.0 assign_resources, bus 1 link: 0 +PCI: 01:04.0 10 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a prefmem +PCI: 01:04.0 14 <- [0x00fc000000 - 0x00fc03ffff] size 0x00040000 gran 0x12 mem +PCI: 01:04.0 18 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io +PCI: 00:09.0 assign_resources, bus 1 link: 0 +PCI: 00:0b.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:0b.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:0b.0 20 <- [0x00fc100000 - 0x00fc1fffff] size 0x00100000 gran 0x14 bus 02 mem +PCI: 00:0b.0 assign_resources, bus 2 link: 0 +PCI: 02:00.0 10 <- [0x00fc100000 - 0x00fc10ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:0b.0 assign_resources, bus 2 link: 0 +PCI: 00:0c.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:0c.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:0c.0 20 <- [0x00fc200000 - 0x00fc2fffff] size 0x00100000 gran 0x14 bus 03 mem +PCI: 00:0c.0 assign_resources, bus 3 link: 0 +PCI: 03:00.0 10 <- [0x00fc200000 - 0x00fc20ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:0c.0 assign_resources, bus 3 link: 0 +PCI: 00:0d.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:0d.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:0d.0 20 <- [0x00fc3fffff - 0x00fc3ffffe] size 0x00000000 gran 0x14 bus 04 mem +PCI: 00:0d.0 assign_resources, bus 4 link: 0 +PCI: 00:0d.0 assign_resources, bus 4 link: 0 +PCI: 00:0e.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 05 io +PCI: 00:0e.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 05 prefmem +PCI: 00:0e.0 20 <- [0x00fc3fffff - 0x00fc3ffffe] size 0x00000000 gran 0x14 bus 05 mem +PCI: 00:18.0 assign_resources, bus 0 link: 1 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: 01 + APIC: 02 + APIC: 03 + APIC: 04 + APIC: 05 + APIC: 06 + APIC: 07 + DOMAIN: 0000 child on link 0 PCI: 00:18.0 + DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base f8000000 size 4400000 align 26 gran 0 limit febfffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 + DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 + DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 + DOMAIN: 0000 resource base 100000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 30 + DOMAIN: 0000 resource base 140000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 41 + PCI: 00:18.0 child on link 0 PCI: 00:00.0 + PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit 3fff flags 60080100 index 110d8 + PCI: 00:18.0 resource base f8000000 size 4000000 align 26 gran 20 limit fbffffff flags 60081200 index 110b8 + PCI: 00:18.0 resource base fc000000 size 400000 align 20 gran 20 limit fc3fffff flags 60080200 index 110b0 + PCI: 00:00.0 + PCI: 00:01.0 child on link 0 PNP: 002e.0 + PCI: 00:01.0 resource base 2c00 size 80 align 7 gran 7 limit 2c7f flags 60000100 index 10 + PCI: 00:01.0 resource base fec00000 size 1000 align 12 gran 12 limit ffffffff flags e0000200 index 14 + PCI: 00:01.0 resource base fed00000 size 1000 align 12 gran 12 limit ffffffff flags e0000200 index 44 + PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 60 + PCI: 00:01.0 resource base 2400 size 100 align 8 gran 8 limit 24ff flags 60000100 index 64 + PCI: 00:01.0 resource base 2800 size 100 align 8 gran 8 limit 28ff flags 60000100 index 68 + PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PNP: 002e.0 + PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.3 + PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000500 index f1 + PNP: 002e.5 + PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 + PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 + PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 + PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.7 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 + PNP: 002e.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.8 + PNP: 002e.9 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 30 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f1 + PNP: 002e.a + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.b + PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags e0000100 index 60 + PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PCI: 00:01.1 child on link 0 I2C: 01:50 + PCI: 00:01.1 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 10 + PCI: 00:01.1 resource base 2c80 size 40 align 6 gran 6 limit 2cbf flags 60000100 index 20 + PCI: 00:01.1 resource base 2cc0 size 40 align 6 gran 6 limit 2cff flags 60000100 index 24 + I2C: 01:50 + I2C: 01:51 + I2C: 01:52 + I2C: 01:53 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:2f + PCI: 00:02.0 + PCI: 00:02.0 resource base fc300000 size 1000 align 12 gran 12 limit fc300fff flags 60000200 index 10 + PCI: 00:02.1 + PCI: 00:02.1 resource base fc303000 size 100 align 8 gran 8 limit fc3030ff flags 60000200 index 10 + PCI: 00:04.0 + PCI: 00:04.1 + PCI: 00:06.0 + PCI: 00:06.0 resource base 3020 size 10 align 4 gran 4 limit 302f flags 60000100 index 20 + PCI: 00:07.0 + PCI: 00:07.0 resource base 3050 size 8 align 3 gran 3 limit 3057 flags 60000100 index 10 + PCI: 00:07.0 resource base 3070 size 4 align 2 gran 2 limit 3073 flags 60000100 index 14 + PCI: 00:07.0 resource base 3058 size 8 align 3 gran 3 limit 305f flags 60000100 index 18 + PCI: 00:07.0 resource base 3074 size 4 align 2 gran 2 limit 3077 flags 60000100 index 1c + PCI: 00:07.0 resource base 3030 size 10 align 4 gran 4 limit 303f flags 60000100 index 20 + PCI: 00:07.0 resource base fc301000 size 1000 align 12 gran 12 limit fc301fff flags 60000200 index 24 + PCI: 00:08.0 + PCI: 00:08.0 resource base 3060 size 8 align 3 gran 3 limit 3067 flags 60000100 index 10 + PCI: 00:08.0 resource base 3078 size 4 align 2 gran 2 limit 307b flags 60000100 index 14 + PCI: 00:08.0 resource base 3068 size 8 align 3 gran 3 limit 306f flags 60000100 index 18 + PCI: 00:08.0 resource base 307c size 4 align 2 gran 2 limit 307f flags 60000100 index 1c + PCI: 00:08.0 resource base 3040 size 10 align 4 gran 4 limit 304f flags 60000100 index 20 + PCI: 00:08.0 resource base fc302000 size 1000 align 12 gran 12 limit fc302fff flags 60000200 index 24 + PCI: 00:09.0 child on link 0 PCI: 01:04.0 + PCI: 00:09.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c + PCI: 00:09.0 resource base f8000000 size 4000000 align 26 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:09.0 resource base fc000000 size 100000 align 20 gran 20 limit fc0fffff flags 60080202 index 20 + PCI: 01:04.0 + PCI: 01:04.0 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60001200 index 10 + PCI: 01:04.0 resource base fc000000 size 40000 align 18 gran 18 limit fc03ffff flags 60000200 index 14 + PCI: 01:04.0 resource base 1000 size 80 align 7 gran 7 limit 107f flags 60000100 index 18 + PCI: 01:04.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3 + PCI: 00:0a.0 + PCI: 00:0b.0 child on link 0 PCI: 02:00.0 + PCI: 00:0b.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0b.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0b.0 resource base fc100000 size 100000 align 20 gran 20 limit fc1fffff flags 60080202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base fc100000 size 10000 align 16 gran 16 limit fc10ffff flags 60000201 index 10 + PCI: 00:0c.0 child on link 0 PCI: 03:00.0 + PCI: 00:0c.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0c.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0c.0 resource base fc200000 size 100000 align 20 gran 20 limit fc2fffff flags 60080202 index 20 + PCI: 03:00.0 + PCI: 03:00.0 resource base fc200000 size 10000 align 16 gran 16 limit fc20ffff flags 60000201 index 10 + PCI: 00:0d.0 child on link 0 PCI: 04:00.0 + PCI: 00:0d.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0d.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0d.0 resource base fc3fffff size 0 align 20 gran 20 limit fc3fffff flags 60080202 index 20 + PCI: 04:00.0 + PCI: 00:0e.0 + PCI: 00:0e.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0e.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0e.0 resource base fc3fffff size 0 align 20 gran 20 limit fc3fffff flags 60080202 index 20 + PCI: 00:0f.0 + PCI: 00:18.1 + PCI: 00:18.2 + PCI: 00:18.3 + PCI: 00:18.4 + PCI: 00:19.0 + PCI: 00:19.1 + PCI: 00:19.2 + PCI: 00:19.3 + PCI: 00:19.4 +Done allocating resources. +BS: BS_DEV_RESOURCES times (us): entry 0 run 3268064 exit 0 +Enabling resources... +PCI: 00:18.0 cmd <- 00 +PCI: 00:18.1 subsystem <- 1043/8162 +PCI: 00:18.1 cmd <- 00 +PCI: 00:18.2 subsystem <- 1043/8162 +PCI: 00:18.2 cmd <- 00 +PCI: 00:18.3 cmd <- 00 +PCI: 00:18.4 subsystem <- 1043/8162 +PCI: 00:18.4 cmd <- 00 +PCI: 00:19.0 cmd <- 00 +PCI: 00:19.1 subsystem <- 1043/8162 +PCI: 00:19.1 cmd <- 00 +PCI: 00:19.2 subsystem <- 1043/8162 +PCI: 00:19.2 cmd <- 00 +PCI: 00:19.3 cmd <- 00 +PCI: 00:19.4 subsystem <- 1043/8162 +PCI: 00:19.4 cmd <- 00 +PCI: 00:00.0 subsystem <- 1043/8162 +PCI: 00:00.0 cmd <- 06 +PCI: 00:01.0 subsystem <- 1043/8162 +PCI: 00:01.0 cmd <- 0f +ck804 lpc decode:PNP: 002e.0, base=0x000003f0, end=0x000003f7 +ck804 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff +ck804 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff +ck804 lpc decode:PNP: 002e.3, base=0x00000004, end=0x00000004 +ck804 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 +ck804 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 +ck804 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000297 +PCI: 00:01.1 subsystem <- 1043/8162 +PCI: 00:01.1 cmd <- 01 +PCI: 00:02.0 subsystem <- 1043/8162 +PCI: 00:02.0 cmd <- 02 +PCI: 00:02.1 subsystem <- 1043/8162 +PCI: 00:02.1 cmd <- 02 +PCI: 00:06.0 subsystem <- 1043/8162 +PCI: 00:06.0 cmd <- 01 +PCI: 00:07.0 subsystem <- 1043/8162 +PCI: 00:07.0 cmd <- 03 +PCI: 00:08.0 subsystem <- 1043/8162 +PCI: 00:08.0 cmd <- 03 +PCI: 00:09.0 bridge ctrl <- 000b +PCI: 00:09.0 cmd <- 07 +PCI: 00:0b.0 bridge ctrl <- 0003 +PCI: 00:0b.0 cmd <- 06 +PCI: 00:0c.0 bridge ctrl <- 0003 +PCI: 00:0c.0 cmd <- 06 +PCI: 00:0d.0 bridge ctrl <- 0003 +PCI: 00:0d.0 cmd <- 00 +PCI: 00:0e.0 bridge ctrl <- 0003 +PCI: 00:0e.0 cmd <- 00 +PCI: 01:04.0 cmd <- 03 +PCI: 02:00.0 subsystem <- 1043/8162 +PCI: 02:00.0 cmd <- 02 +PCI: 03:00.0 subsystem <- 1043/8162 +PCI: 03:00.0 cmd <- 02 +done. +BS: BS_DEV_ENABLE times (us): entry 0 run 162780 exit 0 +Initializing devices... +Root Device init ... +Root Device init finished in 1931 usecs +CPU_CLUSTER: 0 init ... +start_eip=0x00001000, code_size=0x00000031 +CPU1: stack_base 00138000, stack_end 00138ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Initializing CPU #1 +Startup point 1. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +Sending STARTUP #2 to 1. +After apic_write. +CPU: family 10, model 02, stepping 01 +Startup point 1. +Waiting for send to finish... ++nodeid = 00, coreid = 01 +After Startup. +CPU2: stack_base 00137000, stack_end 00137ff8 +Enabling cache +Asserting INIT. +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Waiting for send to finish... ++MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6 +0x00000000c0000000 - 0x00000000f8000000 size 0x38000000 type 0 +0x00000000f8000000 - 0x00000000fc000000 size 0x04000000 type 1 +0x00000000fc000000 - 0x0000000100000000 size 0x04000000 type 0 +0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6 +Deasserting INIT. +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +Waiting for send to finish... ++MTRR: default type WB/UC MTRR counts: 5/3. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 +MTRR: 2 base 0x00000000f8000000 mask 0x0000fffffc000000 type 1 +#startup loops: 2. +Sending STARTUP #1 to 2. +After apic_write. + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Startup point 1. +Waiting for send to finish... ++Setting up local apic...Sending STARTUP #2 to 2. +After apic_write. + apic_id: 0x01 done. +Startup point 1. +Waiting for send to finish... ++CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +After Startup. +siblings = 03, CPU3: stack_base 00136000, stack_end 00136ff8 +CPU #1 initialized +Asserting INIT. +Waiting for send to finish... ++Initializing CPU #2 +Deasserting INIT. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +#startup loops: 2. +Sending STARTUP #1 to 3. +After apic_write. +CPU: family 10, model 02, stepping 01 +Startup point 1. +Waiting for send to finish... ++nodeid = 00, coreid = 02 +Sending STARTUP #2 to 3. +After apic_write. +Enabling cache +Startup point 1. +Waiting for send to finish... ++CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +After Startup. +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU4: stack_base 00135000, stack_end 00135ff8 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Asserting INIT. +Setting up local apic...Waiting for send to finish... ++ apic_id: 0x02 done. +Deasserting INIT. +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +Waiting for send to finish... ++siblings = 03, #startup loops: 2. +Sending STARTUP #1 to 4. +After apic_write. +CPU #2 initialized +Startup point 1. +Waiting for send to finish... ++Initializing CPU #3 +Sending STARTUP #2 to 4. +After apic_write. +CPU: vendor AMD device 100f21 +Startup point 1. +Waiting for send to finish... ++Initializing CPU #4 +After Startup. +CPU5: stack_base 00134000, stack_end 00134ff8 +CPU: vendor AMD device 100f21 +Asserting INIT. +Waiting for send to finish... ++CPU: family 10, model 02, stepping 01 +Deasserting INIT. +Waiting for send to finish... ++nodeid = 01, coreid = 00 +#startup loops: 2. +Sending STARTUP #1 to 5. +After apic_write. +CPU: family 10, model 02, stepping 01 +Startup point 1. +Waiting for send to finish... ++Enabling cache +Sending STARTUP #2 to 5. +After apic_write. +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Startup point 1. +Waiting for send to finish... ++MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +After Startup. +CPU6: stack_base 00133000, stack_end 00133ff8 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Asserting INIT. +Setting up local apic...Waiting for send to finish... ++ apic_id: 0x04 done. +Deasserting INIT. +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +Waiting for send to finish... ++siblings = 03, #startup loops: 2. +Sending STARTUP #1 to 6. +After apic_write. +CPU #4 initialized +Startup point 1. +Waiting for send to finish... ++nodeid = 00, coreid = 03 +Sending STARTUP #2 to 6. +After apic_write. +Initializing CPU #6 +Startup point 1. +Waiting for send to finish... ++Enabling cache +After Startup. +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +CPU7: stack_base 00132000, stack_end 00132ff8 +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +Asserting INIT. +Waiting for send to finish... ++ +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Deasserting INIT. +Setting up local apic...Waiting for send to finish... ++ apic_id: 0x03 done. +#startup loops: 2. +Sending STARTUP #1 to 7. +After apic_write. +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +Startup point 1. +Waiting for send to finish... ++siblings = 03, Sending STARTUP #2 to 7. +After apic_write. +CPU #3 initialized +Startup point 1. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +After Startup. +Initializing CPU #0 +Initializing CPU #5 +CPU: vendor AMD device 100f21 +CPU: family 10, model 02, stepping 01 +nodeid = 00, coreid = 00 +Enabling cache +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Initializing CPU #7 +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU: vendor AMD device 100f21 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +CPU: family 10, model 02, stepping 01 +Setting up local apic...nodeid = 01, coreid = 02 + apic_id: 0x00 done. +CPU: family 10, model 02, stepping 01 +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +siblings = 03, CPU: vendor AMD device 100f21 +CPU #0 initialized +Waiting for 3 CPUS to stop +Enabling cache +CPU: family 10, model 02, stepping 01 +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +nodeid = 01, coreid = 01 +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +Enabling cache +nodeid = 01, coreid = 03 +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +Setting up local apic... +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + + apic_id: 0x06 done. +Setting up local apic...CPU model: Quad-Core AMD Opteron(tm) Processor 8347 + apic_id: 0x05 done. +siblings = 03, Enabling cache +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +CPU #6 initialized +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +siblings = 03, MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU #5 initialized + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Waiting for 2 CPUS to stop +Setting up local apic...Waiting for 1 CPUS to stop + apic_id: 0x07 done. +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +siblings = 03, CPU #7 initialized +All AP CPUs stopped (15172 loops) +CPU1: stack: 00138000 - 00139000, lowest used address 00138c8c, stack used: 884 bytes +CPU2: stack: 00137000 - 00138000, lowest used address 00137cd4, stack used: 812 bytes +CPU3: stack: 00136000 - 00137000, lowest used address 00136cd4, stack used: 812 bytes +CPU4: stack: 00135000 - 00136000, lowest used address 00135cd4, stack used: 812 bytes +CPU5: stack: 00134000 - 00135000, lowest used address 00134cd4, stack used: 812 bytes +CPU6: stack: 00133000 - 00134000, lowest used address 00133cd4, stack used: 812 bytes +CPU7: stack: 00132000 - 00133000, lowest used address 00132cd4, stack used: 812 bytes +CPU_CLUSTER: 0 init finished in 995136 usecs +PCI: 00:18.0 init ... +PCI: 00:18.0 init finished in 2028 usecs +PCI: 00:18.1 init ... +PCI: 00:18.1 init finished in 2027 usecs +PCI: 00:18.2 init ... +PCI: 00:18.2 init finished in 2018 usecs +PCI: 00:18.3 init ... +NB: Function 3 Misc Control.. done. +PCI: 00:18.3 init finished in 5294 usecs +PCI: 00:18.4 init ... +PCI: 00:18.4 init finished in 2018 usecs +PCI: 00:19.0 init ... +PCI: 00:19.0 init finished in 2018 usecs +PCI: 00:19.1 init ... +PCI: 00:19.1 init finished in 2018 usecs +PCI: 00:19.2 init ... +PCI: 00:19.2 init finished in 2019 usecs +PCI: 00:19.3 init ... +NB: Function 3 Misc Control.. done. +PCI: 00:19.3 init finished in 5277 usecs +PCI: 00:19.4 init ... +PCI: 00:19.4 init finished in 2017 usecs +PCI: 00:00.0 init ... +PCI: 00:00.0 init finished in 2028 usecs +PCI: 00:01.0 init ... +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: Dumping registers + reg 0x0000: 0x00000000 + reg 0x0001: 0x00170011 + reg 0x0002: 0x00000000 +IOAPIC: 24 interrupts +IOAPIC: Enabling interrupts on FSB +IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 +IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 +IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 +lpc_init: pm_base = 2000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +set power on after power fail +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +RTC Init +PCI: 00:01.0 init finished in 164771 usecs +PCI: 00:02.0 init ... +PCI: 00:02.0 init finished in 2026 usecs +PCI: 00:02.1 init ... +PCI: 00:02.1 init finished in 2018 usecs +PCI: 00:06.0 init ... +IDE1 IDE0 +PCI: 00:06.0 init finished in 3096 usecs +PCI: 00:07.0 init ... +SATA S SATA P +PCI: 00:07.0 init finished in 3535 usecs +PCI: 00:08.0 init ... +SATA S SATA P +PCI: 00:08.0 init finished in 3526 usecs +PCI: 00:09.0 init ... +PCI DOMAIN mem base = 0x00f8000000 +[0x50] <-- 0xf8000000 +PCI: 00:09.0 init finished in 7192 usecs +PCI: 00:0b.0 init ... +PCI: 00:0b.0 init finished in 2018 usecs +PCI: 00:0c.0 init ... +PCI: 00:0c.0 init finished in 2019 usecs +PCI: 00:0d.0 init ... +PCI: 00:0d.0 init finished in 2019 usecs +PCI: 00:0e.0 init ... +PCI: 00:0e.0 init finished in 2019 usecs +PNP: 002e.0 init ... +PNP: 002e.0 init finished in 1939 usecs +PNP: 002e.2 init ... +PNP: 002e.2 init finished in 1929 usecs +PNP: 002e.3 init ... +PNP: 002e.3 init finished in 1930 usecs +PNP: 002e.5 init ... +Keyboard init... +PNP: 002e.5 init finished in 351037 usecs +PNP: 002e.9 init ... +PNP: 002e.9 init finished in 1928 usecs +PNP: 002e.b init ... +PNP: 002e.b init finished in 1930 usecs +smbus: PCI: 00:01.1[0]->I2C: 01:2f init ... +ID: 5ca3 +I2C: 01:2f init finished in 101155 usecs +PCI: 01:04.0 init ... +XGI Z9s: initializing video device +XGI VGA: Relocate IO address: 1000 [00001030] +XGI VGA: chipid = 31 +XGI VGA: Framebuffer at 0xf8000000, mapped to 0xf8000000, size 16384k +XGI VGA: MMIO at 0xfc000000, mapped to 0xfc000000, size 256k +XGI VGA: No or unknown bridge type detected +XGI VGA: Default mode is 800x600x16 (60Hz) +XGI VGA: Set new mode: 800x600x16-60 +PCI: 01:04.0 init finished in 42560 usecs +PCI: 02:00.0 init ... +PCI: 02:00.0 init finished in 2017 usecs +PCI: 03:00.0 init ... +PCI: 03:00.0 init finished in 2018 usecs +Devices initialized +Show all devs... After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:18.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:01.0: enabled 1 +PNP: 002e.0: enabled 1 +PNP: 002e.1: enabled 0 +PNP: 002e.2: enabled 1 +PNP: 002e.3: enabled 1 +PNP: 002e.5: enabled 1 +PNP: 002e.7: enabled 0 +PNP: 002e.8: enabled 0 +PNP: 002e.9: enabled 1 +PNP: 002e.a: enabled 0 +PNP: 002e.b: enabled 1 +PCI: 00:01.1: enabled 1 +I2C: 01:50: enabled 1 +I2C: 01:51: enabled 1 +I2C: 01:52: enabled 1 +I2C: 01:53: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:2f: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:04.0: enabled 0 +PCI: 00:04.1: enabled 0 +PCI: 00:06.0: enabled 1 +PCI: 00:07.0: enabled 1 +PCI: 00:08.0: enabled 1 +PCI: 00:09.0: enabled 1 +PCI: 01:04.0: enabled 1 +PCI: 00:0a.0: enabled 0 +PCI: 00:0b.0: enabled 1 +PCI: 02:00.0: enabled 1 +PCI: 00:0c.0: enabled 1 +PCI: 03:00.0: enabled 1 +PCI: 00:0d.0: enabled 1 +PCI: 04:00.0: enabled 0 +PCI: 00:0e.0: enabled 1 +PCI: 00:0f.0: enabled 0 +PCI: 00:18.1: enabled 1 +PCI: 00:18.2: enabled 1 +PCI: 00:18.3: enabled 1 +PCI: 00:18.4: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:19.1: enabled 1 +PCI: 00:19.2: enabled 1 +PCI: 00:19.3: enabled 1 +PCI: 00:19.4: enabled 1 +APIC: 01: enabled 1 +APIC: 02: enabled 1 +APIC: 03: enabled 1 +APIC: 04: enabled 1 +APIC: 05: enabled 1 +APIC: 06: enabled 1 +APIC: 07: enabled 1 +BS: BS_DEV_INIT times (us): entry 0 run 1989467 exit 0 +Finalize devices... +Devices finalized +BS: BS_POST_DEVICE times (us): entry 0 run 3526 exit 0 +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CONFIG_LOGICAL_CPUS==1: apicid_base: 00000001 +Writing IRQ routing tables to 0xf0000...done. +Writing IRQ routing tables to 0xbffd8000...done. +PIRQ table: 224 bytes. +Wrote the mp table end at: 000f0410 - 000f05cc +Wrote the mp table end at: bffd7010 - bffd71cc +MP table: 460 bytes. +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/dsdt.aml' +CBFS: Found @ offset c00 size 2644 +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/slic' +CBFS: 'fallback/slic' not found. +ACPI: Writing ACPI tables at bffb3000. +ACPI: * FACS +ACPI: * DSDT +ACPI: * FADT +pm_base: 0x2000 +ACPI: added table 1/32, length now 40 +ACPI: * SSDT +processor_brand=Quad-Core AMD Opteron(tm) Processor 8347 +Pstates algorithm ... +Pstate_freq[0] = 1900MHz Pstate_power[0] = 23040mw +Pstate_latency[0] = 5us +Pstate_freq[1] = 1700MHz Pstate_power[1] = 21385mw +Pstate_latency[1] = 5us +Pstate_freq[2] = 1400MHz Pstate_power[2] = 18787mw +Pstate_latency[2] = 5us +Pstate_freq[3] = 1200MHz Pstate_power[3] = 16770mw +Pstate_latency[3] = 5us +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +l 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +ACPI: added table 2/32, length now 44 +ACPI: * MCFG +ACPI: * TCPA +TCPA log created at bffa3000 +ACPI: added table 3/32, length now 48 +ACPI: * MADT +ACPI: added table 4/32, length now 52 +current = bffb6910 +ACPI: * SRAT at bffb6910 +SRAT: lapic cpu_index=00, node_id=00, apic_id=00 +SRAT: lapic cpu_index=01, node_id=00, apic_id=01 +SRAT: lapic cpu_index=02, node_id=00, apic_id=02 +SRAT: lapic cpu_index=03, node_id=00, apic_id=03 +SRAT: lapic cpu_index=04, node_id=01, apic_id=04 +SRAT: lapic cpu_index=05, node_id=01, apic_id=05 +SRAT: lapic cpu_index=06, node_id=01, apic_id=06 +SRAT: lapic cpu_index=07, node_id=01, apic_id=07 +set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 +set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 +set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 +set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00100000 +set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=00500000, sizek=00100000 +ACPI: added table 5/32, length now 56 +ACPI: * SLIT at bffb6a88 +ACPI: added table 6/32, length now 60 +ACPI: * HPET +ACPI: added table 7/32, length now 64 +ACPI: * SRAT at bffb6b00 +SRAT: lapic cpu_index=00, node_id=00, apic_id=00 +SRAT: lapic cpu_index=01, node_id=00, apic_id=01 +SRAT: lapic cpu_index=02, node_id=00, apic_id=02 +SRAT: lapic cpu_index=03, node_id=00, apic_id=03 +SRAT: lapic cpu_index=04, node_id=01, apic_id=04 +SRAT: lapic cpu_index=05, node_id=01, apic_id=05 +SRAT: lapic cpu_index=06, node_id=01, apic_id=06 +SRAT: lapic cpu_index=07, node_id=01, apic_id=07 +set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 +set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 +set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 +set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00100000 +set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=00500000, sizek=00100000 +ACPI: added table 8/32, length now 68 +ACPI: * SLIT at bffb6c78 +ACPI: added table 9/32, length now 72 +ACPI: done. +ACPI tables: 15536 bytes. +smbios_write_tables: bffa2000 +Root Device (ASUS KFSN4-DRE) +CPU_CLUSTER: 0 (AMD FAM10 Root Complex) +APIC: 00 (unknown) +DOMAIN: 0000 (AMD FAM10 Root Complex) +PCI: 00:18.0 (AMD FAM10 Northbridge) +PCI: 00:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:01.0 (NVIDIA CK804 Southbridge) +PNP: 002e.0 (Winbond W83627THG Super I/O) +PNP: 002e.1 (Winbond W83627THG Super I/O) +PNP: 002e.2 (Winbond W83627THG Super I/O) +PNP: 002e.3 (Winbond W83627THG Super I/O) +PNP: 002e.5 (Winbond W83627THG Super I/O) +PNP: 002e.7 (Winbond W83627THG Super I/O) +PNP: 002e.8 (Winbond W83627THG Super I/O) +PNP: 002e.9 (Winbond W83627THG Super I/O) +PNP: 002e.a (Winbond W83627THG Super I/O) +PNP: 002e.b (Winbond W83627THG Super I/O) +PCI: 00:01.1 (NVIDIA CK804 Southbridge) +I2C: 01:50 (unknown) +I2C: 01:51 (unknown) +I2C: 01:52 (unknown) +I2C: 01:53 (unknown) +I2C: 01:54 (unknown) +I2C: 01:55 (unknown) +I2C: 01:56 (unknown) +I2C: 01:57 (unknown) +I2C: 01:2f (Nuvoton W83793 Hardware Monitor) +PCI: 00:02.0 (NVIDIA CK804 Southbridge) +PCI: 00:02.1 (NVIDIA CK804 Southbridge) +PCI: 00:04.0 (NVIDIA CK804 Southbridge) +PCI: 00:04.1 (NVIDIA CK804 Southbridge) +PCI: 00:06.0 (NVIDIA CK804 Southbridge) +PCI: 00:07.0 (NVIDIA CK804 Southbridge) +PCI: 00:08.0 (NVIDIA CK804 Southbridge) +PCI: 00:09.0 (NVIDIA CK804 Southbridge) +PCI: 01:04.0 (NVIDIA CK804 Southbridge) +PCI: 00:0a.0 (NVIDIA CK804 Southbridge) +PCI: 00:0b.0 (NVIDIA CK804 Southbridge) +PCI: 02:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:0c.0 (NVIDIA CK804 Southbridge) +PCI: 03:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:0d.0 (NVIDIA CK804 Southbridge) +PCI: 04:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:0e.0 (NVIDIA CK804 Southbridge) +PCI: 00:0f.0 (NVIDIA CK804 Southbridge) +PCI: 00:18.1 (AMD FAM10 Northbridge) +PCI: 00:18.2 (AMD FAM10 Northbridge) +PCI: 00:18.3 (AMD FAM10 Northbridge) +PCI: 00:18.4 (AMD FAM10 Northbridge) +PCI: 00:19.0 (AMD FAM10 Northbridge) +PCI: 00:19.1 (AMD FAM10 Northbridge) +PCI: 00:19.2 (AMD FAM10 Northbridge) +PCI: 00:19.3 (AMD FAM10 Northbridge) +PCI: 00:19.4 (AMD FAM10 Northbridge) +APIC: 01 (unknown) +APIC: 02 (unknown) +APIC: 03 (unknown) +APIC: 04 (unknown) +APIC: 05 (unknown) +APIC: 06 (unknown) +APIC: 07 (unknown) +SMBIOS tables: 553 bytes. +Writing table forward entry at 0x00000500 +Wrote coreboot table at: 00000500, 0x10 bytes, checksum 9fe4 +Table forward entry ends at 0x00000528. +... aligned to 0x00001000 +Writing coreboot table at 0xbff9a000 +rom_table_end = 0xbff9a000 +... aligned to 0xbffa0000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 + 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES + 1. 0000000000001000-000000000009ffff: RAM + 2. 00000000000a0000-00000000000bffff: RESERVED + 3. 00000000000c0000-00000000bff99fff: RAM + 4. 00000000bff9a000-00000000bfffffff: CONFIGURATION TABLES + 5. 00000000c0000000-00000000cfffffff: RESERVED + 6. 0000000100000000-000000017fffffff: RAM +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Wrote coreboot table at: bff9a000, 0xc08 bytes, checksum 44e8 +coreboot table: 3104 bytes. +IMD ROOT 0. bffff000 00001000 +IMD SMALL 1. bfffe000 00001000 +CAR GLOBALS 2. bfffb000 0000291c +CONSOLE 3. bffdb000 00020000 +AMDMEM INFO 4. bffd9000 0000172c +IRQ TABLE 5. bffd8000 00001000 +SMP TABLE 6. bffd7000 00001000 +ACPI 7. bffb3000 00024000 +54435041 8. bffa3000 00010000 +SMBIOS 9. bffa2000 00000800 +COREBOOT 10. bff9a000 00008000 +IMD small region: + IMD ROOT 0. bfffec00 00000400 + USBDEBUG 1. bfffeba0 00000058 + ROMSTAGE 2. bfffeb80 00000004 + GDT 3. bfffe980 00000200 +BS: BS_WRITE_TABLES times (us): entry 0 run 760427 exit 0 +CBFS provider active. +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/payload' +CBFS: Found @ offset 29c80 size 8f395 +'fallback/payload' located at offset: 29cb8 size: 8f395 +Loading segment from rom address 0xfff29cb8 + code (compression=1) + New segment dstaddr 0x8200 memsize 0x17420 srcaddr 0xfff29d0c filesize 0x8215 +Loading segment from rom address 0xfff29cd4 + code (compression=1) + New segment dstaddr 0x100000 memsize 0x2213f0 srcaddr 0xfff31f21 filesize 0x8712c +Loading segment from rom address 0xfff29cf0 + Entry Point 0x00008200 +Bounce Buffer at bfc79000, 3277244 bytes +Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017420 filesz: 0x0000000000008215 +lb: [0x0000000000100000, 0x00000000001fedcc) +Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017420 filesz: 0x0000000000008215 +using LZMA +[ 0x00008200, 00017ce3, 0x0001f620) <- fff29d0c +Clearing Segment: addr: 0x0000000000017ce3 memsz: 0x000000000000793d +dest 00008200, end 0001f620, bouncebuffer bfc79000 +Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000002213f0 filesz: 0x000000000008712c +lb: [0x0000000000100000, 0x00000000001fedcc) +segment: [0x0000000000100000, 0x000000000018712c, 0x00000000003213f0) + bounce: [0x00000000bfc79000, 0x00000000bfd0012c, 0x00000000bfe9a3f0) +Post relocation: addr: 0x00000000bfc79000 memsz: 0x00000000002213f0 filesz: 0x000000000008712c +using LZMA +[ 0xbfc79000, bfe9a3f0, 0xbfe9a3f0) <- fff31f21 +dest bfc79000, end bfe9a3f0, bouncebuffer bfc79000 +move suffix around: from bfd77dcc, to 1fedcc, amount: 122624 +Loaded segments +BS: BS_PAYLOAD_LOAD times (us): entry 0 run 819203 exit 0 +Jumping to boot code at 00008200(bff9a000) +CPU0: stack: 00139000 - 0013a000, lowest used address 00139ae0, stack used: 1312 bytes +entry = 0x00008200 +lb_start = 0x00100000 +lb_size = 0x000fedcc +buffer = 0xbfc79000 +[?25lFREE AS IN FREEDOM + + ++----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. + + Press enter to boot the selected OS, `e' to edit the commands + + before booting or `c' for a command-line.  *Load Operating System  Parse ISOLINUX menu (ahci0)  Parse ISOLINUX menu (USB)  Parse ISOLINUX menu (CD/DVD)  Switch to grubtest.cfg  Search for GRUB configuration (grub.cfg) outside of CBFS         The highlighted entry will be executed automatically in 1s.  The highlighted entry will be executed automatically in 0s. [?25h Booting `Load Operating System' + + + + Failed to boot both default and fallback entries. + + +Press any key to continue... + +[?25lFREE AS IN FREEDOM + + ++----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. + + Press enter to boot the selected OS, `e' to edit the commands + + before booting or `c' for a command-line.  *Load Operating System  Parse ISOLINUX menu (ahci0) diff --git a/site/docs/hardware/text/x200s/cblog00.txt b/site/docs/hardware/text/x200s/cblog00.txt new file mode 100644 index 0000000..331cb64 --- /dev/null +++ b/site/docs/hardware/text/x200s/cblog00.txt @@ -0,0 +1,196 @@ +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +WARNING: Ignoring S4-assertion-width violation. +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using low power mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 14 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 15 + Max clock: 533 MHz + CAS: 0x01c0 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +SFF platform unsupported in RCOMP initialization. +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +Interrupted RAM init, reset required. +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using low power mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 14 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 15 + Max clock: 533 MHz + CAS: 0x01c0 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +SFF platform unsupported in RCOMP initialization. +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +Interrupted RAM init, reset required. +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using low power mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 14 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 15 + Max clock: 533 MHz + CAS: 0x01c0 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +SFF platform unsupported in RCOMP initialization. diff --git a/site/docs/hardware/text/x200s/cblog01.txt b/site/docs/hardware/text/x200s/cblog01.txt new file mode 100644 index 0000000..afad2fe --- /dev/null +++ b/site/docs/hardware/text/x200s/cblog01.txt @@ -0,0 +1,1569 @@ +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +WARNING: Ignoring S4-assertion-width violation. +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using high performance mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Bank 1 populated: + Raw card type: F + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +DIMMs support 666 MHz, but chipset only runs at up to 533. Limiting... +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +Memory configured in dual-channel assymetric mode. +Memory map: +TOM = 512MB +TOLUD = 512MB +TOUUD = 512MB +REMAP: base = 65535MB + limit = 0MB +usedMEsize: 0MB +Performing Jedec initialization at address 0x00000000. +Performing Jedec initialization at address 0x08000000. +Performing Jedec initialization at address 0x10000000. +Performing Jedec initialization at address 0x18000000. +Final timings for group 0 on channel 0: 6.1.0.2.2 +Final timings for group 1 on channel 0: 6.0.2.6.1 +Final timings for group 2 on channel 0: 6.1.0.8.7 +Final timings for group 3 on channel 0: 6.1.0.7.1 +Final timings for group 0 on channel 1: 6.1.0.0.6 +Final timings for group 1 on channel 1: 6.0.2.3.4 +Final timings for group 2 on channel 1: 6.1.0.6.6 +Final timings for group 3 on channel 1: 6.1.0.3.6 +Lower bound for byte lane 0 on channel 0: 0.0 +Upper bound for byte lane 0 on channel 0: 10.1 +Final timings for byte lane 0 on channel 0: 5.0 +Lower bound for byte lane 1 on channel 0: 0.0 +Upper bound for byte lane 1 on channel 0: 11.1 +Final timings for byte lane 1 on channel 0: 5.4 +Lower bound for byte lane 2 on channel 0: 0.0 +Upper bound for byte lane 2 on channel 0: 11.3 +Final timings for byte lane 2 on channel 0: 5.5 +Lower bound for byte lane 3 on channel 0: 0.0 +Upper bound for byte lane 3 on channel 0: 10.2 +Final timings for byte lane 3 on channel 0: 5.1 +Lower bound for byte lane 4 on channel 0: 0.0 +Upper bound for byte lane 4 on channel 0: 10.2 +Final timings for byte lane 4 on channel 0: 5.1 +Lower bound for byte lane 5 on channel 0: 0.0 +Upper bound for byte lane 5 on channel 0: 8.6 +Final timings for byte lane 5 on channel 0: 4.3 +Lower bound for byte lane 6 on channel 0: 0.0 +Upper bound for byte lane 6 on channel 0: 11.2 +Final timings for byte lane 6 on channel 0: 5.5 +Lower bound for byte lane 7 on channel 0: 0.0 +Upper bound for byte lane 7 on channel 0: 9.3 +Final timings for byte lane 7 on channel 0: 4.5 +Lower bound for byte lane 0 on channel 1: 0.0 +Upper bound for byte lane 0 on channel 1: 10.0 +Final timings for byte lane 0 on channel 1: 5.0 +Lower bound for byte lane 1 on channel 1: 0.0 +Upper bound for byte lane 1 on channel 1: 11.2 +Final timings for byte lane 1 on channel 1: 5.5 +Lower bound for byte lane 2 on channel 1: 0.0 +Upper bound for byte lane 2 on channel 1: 10.3 +Final timings for byte lane 2 on channel 1: 5.1 +Lower bound for byte lane 3 on channel 1: 0.0 +Upper bound for byte lane 3 on channel 1: 9.6 +Final timings for byte lane 3 on channel 1: 4.7 +Lower bound for byte lane 4 on channel 1: 0.0 +Upper bound for byte lane 4 on channel 1: 11.3 +Final timings for byte lane 4 on channel 1: 5.5 +Lower bound for byte lane 5 on channel 1: 0.0 +Upper bound for byte lane 5 on channel 1: 8.4 +Final timings for byte lane 5 on channel 1: 4.2 +Lower bound for byte lane 6 on channel 1: 0.0 +Upper bound for byte lane 6 on channel 1: 11.2 +Final timings for byte lane 6 on channel 1: 5.5 +Lower bound for byte lane 7 on channel 1: 0.0 +Upper bound for byte lane 7 on channel 1: 9.4 +Final timings for byte lane 7 on channel 1: 4.6 +Lower bound for group 0 on channel 0: 1.6.3 +Upper bound for group 0 on channel 0: 2.2.7 +Final timings for group 0 on channel 0: 1.10.5 +Lower bound for group 1 on channel 0: 1.5.5 +Upper bound for group 1 on channel 0: 2.1.6 +Final timings for group 1 on channel 0: 1.9.5 +Lower bound for group 2 on channel 0: 2.0.0 +Upper bound for group 2 on channel 0: 2.8.7 +Final timings for group 2 on channel 0: 2.4.3 +Lower bound for group 3 on channel 0: 2.4.2 +Upper bound for group 3 on channel 0: 3.0.4 +Final timings for group 3 on channel 0: 2.8.3 +IGD decoded, subtracting 32M UMA and 4M GTT +Memory configured in dual-channel interleaved mode. +Memory map: +TOM = 8192MB +TOLUD = 3072MB +TOUUD = 9216MB +REMAP: base = 8192MB + limit = 9152MB +usedMEsize: 0MB +Enabling IGD. +Finally disabling PEG in favor of IGD. +PEG x1 disabled, SDVO disabled +ICH9 waits for VC1 negotiation... done. +ICH9 waits for port arbitration table update... done. +CBMEM: root @ bdbff000 254 entries. +exit main() +Trying CBFS ramstage loader. +CBFS: loading stage fallback/ramstage @ 0x100000 (290876 bytes), entry @ 0x100000 +EHCI debug port found in CBMEM. +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 booting... +BS: Entering BS_PRE_DEVICE state. +CBMEM: recovering 6/254 entries from root @ bdbff000 +Moving GDT to bdbda000...ok +BS: Exiting BS_PRE_DEVICE state. +BS: Entering BS_DEV_INIT_CHIPS state. +Initializing i82801ix southbridge... +BS: Exiting BS_DEV_INIT_CHIPS state. +BS: Entering BS_DEV_ENUMERATE state. +Enumerating buses... +Show all devs...Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +APIC: acac: enabled 0 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:03.0: enabled 1 +PCI: 00:03.1: enabled 0 +PCI: 00:03.2: enabled 0 +PCI: 00:03.3: enabled 0 +IOAPIC: 02: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:1a.0: enabled 1 +PCI: 00:1a.1: enabled 1 +PCI: 00:1a.2: enabled 1 +PCI: 00:1a.7: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1c.4: enabled 0 +PCI: 00:1c.5: enabled 0 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:5c: enabled 1 +I2C: 00:5d: enabled 1 +I2C: 00:5e: enabled 1 +I2C: 00:5f: enabled 1 +PCI: 00:1f.5: enabled 0 +PCI: 00:1f.6: enabled 0 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + APIC: acac: enabled 0 + DOMAIN: 0000: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:03.0: enabled 1 + PCI: 00:03.1: enabled 0 + PCI: 00:03.2: enabled 0 + PCI: 00:03.3: enabled 0 + IOAPIC: 02: enabled 1 + PCI: 00:19.0: enabled 1 + PCI: 00:1a.0: enabled 1 + PCI: 00:1a.1: enabled 1 + PCI: 00:1a.2: enabled 1 + PCI: 00:1a.7: enabled 1 + PCI: 00:1b.0: enabled 1 + PCI: 00:1c.0: enabled 1 + PCI: 00:1c.1: enabled 1 + PCI: 00:1c.2: enabled 1 + PCI: 00:1c.3: enabled 1 + PCI: 00:1c.4: enabled 0 + PCI: 00:1c.5: enabled 0 + PCI: 00:1d.0: enabled 1 + PCI: 00:1d.1: enabled 1 + PCI: 00:1d.2: enabled 1 + PCI: 00:1d.7: enabled 1 + PCI: 00:1e.0: enabled 1 + PCI: 00:1f.0: enabled 1 + PNP: 00ff.1: enabled 1 + PNP: 00ff.2: enabled 1 + PCI: 00:1f.2: enabled 1 + PCI: 00:1f.3: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:5c: enabled 1 + I2C: 00:5d: enabled 1 + I2C: 00:5e: enabled 1 + I2C: 00:5f: enabled 1 + PCI: 00:1f.5: enabled 0 + PCI: 00:1f.6: enabled 0 +scan_static_bus for Root Device +CPU_CLUSTER: 0 enabled +Normal boot. +DOMAIN: 0000 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/2a40] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:02.0 [8086/0000] ops +PCI: 00:02.0 [8086/2a42] enabled +PCI: 00:02.1 [8086/2a43] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: Static device PCI: 00:03.0 not found, disabling it. +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:19.0 [8086/10f5] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1a.0 [8086/2937] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1a.1 [8086/2938] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1a.2 [8086/2939] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:1a.7 [8086/0000] ops +PCI: 00:1a.7 [8086/293c] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1b.0 [8086/293e] ops +PCI: 00:1b.0 [8086/293e] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1c.0 [8086/0000] bus ops +PCI: 00:1c.0 [8086/2940] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1c.1 [8086/0000] bus ops +PCI: 00:1c.1 [8086/2942] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1c.2 [8086/0000] bus ops +PCI: 00:1c.2 [8086/2944] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1c.3 [8086/0000] bus ops +PCI: 00:1c.3 [8086/2946] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:1d.0 [8086/2934] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1d.1 [8086/2935] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1d.2 [8086/2936] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:1d.7 [8086/0000] ops +PCI: 00:1d.7 [8086/293a] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1e.0 [8086/0000] bus ops +PCI: 00:1e.0 [8086/2448] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1f.0 [8086/0000] bus ops +PCI: 00:1f.0 [8086/2917] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:1f.2 [8086/0000] ops +PCI: 00:1f.2 [8086/2928] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1f.3 [8086/0000] bus ops +PCI: 00:1f.3 [8086/2930] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: Left over static devices: +IOAPIC: 02 +PCI: Check your devicetree.cb. +do_pci_scan_bridge for PCI: 00:1c.0 +PCI: pci_scan_bus for bus 01 +PCI: pci_scan_bus returning with max=001 +do_pci_scan_bridge returns max 1 +do_pci_scan_bridge for PCI: 00:1c.1 +PCI: pci_scan_bus for bus 02 +PCI: pci_scan_bus returning with max=002 +do_pci_scan_bridge returns max 2 +do_pci_scan_bridge for PCI: 00:1c.2 +PCI: pci_scan_bus for bus 03 +PCI: pci_scan_bus returning with max=003 +do_pci_scan_bridge returns max 3 +do_pci_scan_bridge for PCI: 00:1c.3 +PCI: pci_scan_bus for bus 04 +PCI: pci_scan_bus returning with max=004 +do_pci_scan_bridge returns max 4 +do_pci_scan_bridge for PCI: 00:1e.0 +PCI: pci_scan_bus for bus 05 +PCI: pci_scan_bus returning with max=005 +do_pci_scan_bridge returns max 5 +scan_static_bus for PCI: 00:1f.0 +WARNING: No CMOS option 'touchpad'. +PNP: 00ff.1 enabled +recv_ec_data: 0x37 +recv_ec_data: 0x58 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x32 +recv_ec_data: 0x32 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x06 +recv_ec_data: 0x03 +recv_ec_data: 0x40 +recv_ec_data: 0x10 +EC Firmware ID 7XHT22WW-3.6, Version 4.01A +recv_ec_data: 0x00 +recv_ec_data: 0x10 +recv_ec_data: 0x20 +recv_ec_data: 0x30 +recv_ec_data: 0x00 +recv_ec_data: 0x00 +recv_ec_data: 0xa6 +recv_ec_data: 0x01 +recv_ec_data: 0x70 +dock is not connected +PNP: 00ff.2 enabled +scan_static_bus for PCI: 00:1f.0 done +scan_static_bus for PCI: 00:1f.3 +smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled +scan_static_bus for PCI: 00:1f.3 done +PCI: pci_scan_bus returning with max=005 +scan_static_bus for Root Device done +done +BS: Exiting BS_DEV_ENUMERATE state. +BS: Entering BS_DEV_RESOURCES state. +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +TOUUD 0x240000000 TOLUD 0xc0000000 TOM 0x200000000 +IGD decoded, subtracting 32M UMA and 4M GTT +Available memory below 4GB: 3036M +Available memory above 4GB: 5120M +Adding UMA memory area base=0xbdc00000 size=0x2400000 +Adding PCIe config bar base=0xf0000000 size=0x4000000 +DOMAIN: 0000 read_resources bus 0 link: 0 +More than one caller of pci_ehci_read_resources from PCI: 00:1a.7 +PCI: 00:1c.0 read_resources bus 1 link: 0 +PCI: 00:1c.0 read_resources bus 1 link: 0 done +PCI: 00:1c.1 read_resources bus 2 link: 0 +PCI: 00:1c.1 read_resources bus 2 link: 0 done +PCI: 00:1c.2 read_resources bus 3 link: 0 +PCI: 00:1c.2 read_resources bus 3 link: 0 done +PCI: 00:1c.3 read_resources bus 4 link: 0 +PCI: 00:1c.3 read_resources bus 4 link: 0 done +PCI: 00:1d.7 EHCI BAR hook registered +PCI: 00:1e.0 read_resources bus 5 link: 0 +PCI: 00:1e.0 read_resources bus 5 link: 0 done +PCI: 00:1f.0 read_resources bus 0 link: 0 +PNP: 00ff.1 missing read_resources +PNP: 00ff.2 missing read_resources +PCI: 00:1f.0 read_resources bus 0 link: 0 done +PCI: 00:1f.3 read_resources bus 1 link: 0 +PCI: 00:1f.3 read_resources bus 1 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: acac + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bdb40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base 100000000 size 140000000 align 0 gran 0 limit 0 flags e0004200 index 5 + DOMAIN: 0000 resource base bdc00000 size 2400000 align 0 gran 0 limit 0 flags f0000200 index 6 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 + PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 20 + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 10 + PCI: 00:03.0 + PCI: 00:03.1 + PCI: 00:03.2 + PCI: 00:03.3 + PCI: 00:19.0 + PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 + PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 + PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 + PCI: 00:1a.0 + PCI: 00:1a.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1a.1 + PCI: 00:1a.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1a.2 + PCI: 00:1a.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1a.7 + PCI: 00:1a.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.1 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.3Unknown device path type: 0 + child on link 0 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 +Unknown device path type: 0 + +Unknown device path type: 0 + resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10 +Unknown device path type: 0 + resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14 +Unknown device path type: 0 + resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18 + PCI: 00:1c.4 + PCI: 00:1c.5 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:54 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f + PCI: 00:1f.5 + PCI: 00:1f.6 +DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +Unknown device path type: 0 + 18 * [0x0 - 0xfff] io +PCI: 00:1c.3 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 1c * [0x0 - 0xfff] io +PCI: 00:19.0 18 * [0x1000 - 0x101f] io +PCI: 00:1a.0 20 * [0x1020 - 0x103f] io +PCI: 00:1a.1 20 * [0x1040 - 0x105f] io +PCI: 00:1a.2 20 * [0x1060 - 0x107f] io +PCI: 00:1d.0 20 * [0x1080 - 0x109f] io +PCI: 00:1d.1 20 * [0x10a0 - 0x10bf] io +PCI: 00:1d.2 20 * [0x10c0 - 0x10df] io +PCI: 00:1f.2 20 * [0x10e0 - 0x10ff] io +PCI: 00:02.0 20 * [0x1400 - 0x1407] io +PCI: 00:1f.2 10 * [0x1408 - 0x140f] io +PCI: 00:1f.2 18 * [0x1410 - 0x1417] io +PCI: 00:1f.2 14 * [0x1418 - 0x141b] io +PCI: 00:1f.2 1c * [0x141c - 0x141f] io +DOMAIN: 0000 compute_resources_io: base: 1420 size: 1420 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +Unknown device path type: 0 + 14 * [0x0 - 0x7fffff] prefmem +PCI: 00:1c.3 compute_resources_prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +Unknown device path type: 0 + 10 * [0x0 - 0x7fffff] mem +PCI: 00:1c.3 compute_resources_mem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:1c.3 24 * [0x10000000 - 0x107fffff] prefmem +PCI: 00:1c.3 20 * [0x10800000 - 0x10ffffff] mem +PCI: 00:02.0 10 * [0x11000000 - 0x113fffff] mem +PCI: 00:02.1 10 * [0x11400000 - 0x114fffff] mem +PCI: 00:19.0 10 * [0x11500000 - 0x1151ffff] mem +PCI: 00:1b.0 10 * [0x11520000 - 0x11523fff] mem +PCI: 00:19.0 14 * [0x11524000 - 0x11524fff] mem +PCI: 00:1f.2 24 * [0x11525000 - 0x115257ff] mem +PCI: 00:1a.7 10 * [0x11525800 - 0x11525bff] mem +PCI: 00:1d.7 10 * [0x11525c00 - 0x11525fff] mem +PCI: 00:1f.3 10 * [0x11526000 - 0x115260ff] mem +DOMAIN: 0000 compute_resources_mem: base: 11526100 size: 11526100 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:02.1 +constrain_resources: PCI: 00:19.0 +constrain_resources: PCI: 00:1a.0 +constrain_resources: PCI: 00:1a.1 +constrain_resources: PCI: 00:1a.2 +constrain_resources: PCI: 00:1a.7 +constrain_resources: PCI: 00:1b.0 +constrain_resources: PCI: 00:1c.0 +constrain_resources: PCI: 00:1c.1 +constrain_resources: PCI: 00:1c.2 +constrain_resources: PCI: 00:1c.3 +Unknown device path type: 0 +constrain_resources: +constrain_resources: PCI: 00:1d.0 +constrain_resources: PCI: 00:1d.1 +constrain_resources: PCI: 00:1d.2 +constrain_resources: PCI: 00:1d.7 +constrain_resources: PCI: 00:1e.0 +constrain_resources: PCI: 00:1f.0 +constrain_resources: PNP: 00ff.1 +constrain_resources: PNP: 00ff.2 +skipping PNP: 00ff.2@60 fixed resource, size=0! +skipping PNP: 00ff.2@62 fixed resource, size=0! +skipping PNP: 00ff.2@64 fixed resource, size=0! +skipping PNP: 00ff.2@66 fixed resource, size=0! +constrain_resources: PCI: 00:1f.2 +constrain_resources: PCI: 00:1f.3 +constrain_resources: I2C: 01:54 +constrain_resources: I2C: 01:55 +constrain_resources: I2C: 01:56 +constrain_resources: I2C: 01:57 +constrain_resources: I2C: 01:5c +constrain_resources: I2C: 01:5d +constrain_resources: I2C: 01:5e +constrain_resources: I2C: 01:5f +avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff + lim->base 000015f0 lim->limit 0000ffff +avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff + lim->base c0000000 lim->limit efffffff +Setting resources... +DOMAIN: 0000 allocate_resources_io: base:15f0 size:1420 align:12 gran:0 limit:ffff +Assigned: PCI: 00:1c.3 1c * [0x2000 - 0x2fff] io +Assigned: PCI: 00:19.0 18 * [0x3000 - 0x301f] io +Assigned: PCI: 00:1a.0 20 * [0x3020 - 0x303f] io +Assigned: PCI: 00:1a.1 20 * [0x3040 - 0x305f] io +Assigned: PCI: 00:1a.2 20 * [0x3060 - 0x307f] io +Assigned: PCI: 00:1d.0 20 * [0x3080 - 0x309f] io +Assigned: PCI: 00:1d.1 20 * [0x30a0 - 0x30bf] io +Assigned: PCI: 00:1d.2 20 * [0x30c0 - 0x30df] io +Assigned: PCI: 00:1f.2 20 * [0x30e0 - 0x30ff] io +Assigned: PCI: 00:02.0 20 * [0x3400 - 0x3407] io +Assigned: PCI: 00:1f.2 10 * [0x3408 - 0x340f] io +Assigned: PCI: 00:1f.2 18 * [0x3410 - 0x3417] io +Assigned: PCI: 00:1f.2 14 * [0x3418 - 0x341b] io +Assigned: PCI: 00:1f.2 1c * [0x341c - 0x341f] io +DOMAIN: 0000 allocate_resources_io: next_base: 3420 size: 1420 align: 12 gran: 0 done +PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ffff +Unknown device path type: 0 +Assigned: 18 * [0x2000 - 0x2fff] io +PCI: 00:1c.3 allocate_resources_io: next_base: 3000 size: 1000 align: 12 gran: 12 done +PCI: 00:1e.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1e.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:11526100 align:28 gran:0 limit:efffffff +Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem +Assigned: PCI: 00:1c.3 24 * [0xe0000000 - 0xe07fffff] prefmem +Assigned: PCI: 00:1c.3 20 * [0xe0800000 - 0xe0ffffff] mem +Assigned: PCI: 00:02.0 10 * [0xe1000000 - 0xe13fffff] mem +Assigned: PCI: 00:02.1 10 * [0xe1400000 - 0xe14fffff] mem +Assigned: PCI: 00:19.0 10 * [0xe1500000 - 0xe151ffff] mem +Assigned: PCI: 00:1b.0 10 * [0xe1520000 - 0xe1523fff] mem +Assigned: PCI: 00:19.0 14 * [0xe1524000 - 0xe1524fff] mem +Assigned: PCI: 00:1f.2 24 * [0xe1525000 - 0xe15257ff] mem +Assigned: PCI: 00:1a.7 10 * [0xe1525800 - 0xe1525bff] mem +Assigned: PCI: 00:1d.7 10 * [0xe1525c00 - 0xe1525fff] mem +Assigned: PCI: 00:1f.3 10 * [0xe1526000 - 0xe15260ff] mem +DOMAIN: 0000 allocate_resources_mem: next_base: e1526100 size: 11526100 align: 28 gran: 0 done +PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_prefmem: base:e0000000 size:800000 align:22 gran:20 limit:efffffff +Unknown device path type: 0 +Assigned: 14 * [0xe0000000 - 0xe07fffff] prefmem +PCI: 00:1c.3 allocate_resources_prefmem: next_base: e0800000 size: 800000 align: 22 gran: 20 done +PCI: 00:1c.3 allocate_resources_mem: base:e0800000 size:800000 align:22 gran:20 limit:efffffff +Unknown device path type: 0 +Assigned: 10 * [0xe0800000 - 0xe0ffffff] mem +PCI: 00:1c.3 allocate_resources_mem: next_base: e1000000 size: 800000 align: 22 gran: 20 done +PCI: 00:1e.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1e.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1e.0 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +DOMAIN: 0000 03 <- [0x0000000000 - 0x000009ffff] size 0x000a0000 gran 0x00 mem +DOMAIN: 0000 04 <- [0x00000c0000 - 0x00bdbfffff] size 0xbdb40000 gran 0x00 mem +DOMAIN: 0000 05 <- [0x0100000000 - 0x023fffffff] size 0x140000000 gran 0x00 mem +DOMAIN: 0000 06 <- [0x00bdc00000 - 0x00bfffffff] size 0x02400000 gran 0x00 mem +DOMAIN: 0000 07 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:02.0 10 <- [0x00e1000000 - 0x00e13fffff] size 0x00400000 gran 0x16 mem64 +PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 +PCI: 00:02.0 20 <- [0x0000003400 - 0x0000003407] size 0x00000008 gran 0x03 io +PCI: 00:02.1 10 <- [0x00e1400000 - 0x00e14fffff] size 0x00100000 gran 0x14 mem64 +PCI: 00:19.0 10 <- [0x00e1500000 - 0x00e151ffff] size 0x00020000 gran 0x11 mem +PCI: 00:19.0 14 <- [0x00e1524000 - 0x00e1524fff] size 0x00001000 gran 0x0c mem +PCI: 00:19.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io +PCI: 00:1a.0 20 <- [0x0000003020 - 0x000000303f] size 0x00000020 gran 0x05 io +PCI: 00:1a.1 20 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io +PCI: 00:1a.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io +PCI: 00:1a.7 10 <- [0x00e1525800 - 0x00e1525bff] size 0x00000400 gran 0x0a mem +PCI: 00:1b.0 10 <- [0x00e1520000 - 0x00e1523fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.1 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 mem +PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem +PCI: 00:1c.3 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io +PCI: 00:1c.3 24 <- [0x00e0000000 - 0x00e07fffff] size 0x00800000 gran 0x14 bus 04 prefmem +PCI: 00:1c.3 20 <- [0x00e0800000 - 0x00e0ffffff] size 0x00800000 gran 0x14 bus 04 mem +PCI: 00:1c.3 assign_resources, bus 4 link: 0 +Unknown device path type: 0 + missing set_resources +PCI: 00:1c.3 assign_resources, bus 4 link: 0 +PCI: 00:1d.0 20 <- [0x0000003080 - 0x000000309f] size 0x00000020 gran 0x05 io +PCI: 00:1d.1 20 <- [0x00000030a0 - 0x00000030bf] size 0x00000020 gran 0x05 io +PCI: 00:1d.2 20 <- [0x00000030c0 - 0x00000030df] size 0x00000020 gran 0x05 io +PCI: 00:1d.7 EHCI Debug Port hook triggered +PCI: 00:1d.7 10 <- [0x00e1525c00 - 0x00e1525fff] size 0x00000400 gran 0x0a mem +PCI: 00:1d.7 EHCI Debug Port relocated +PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io +PCI: 00:1e.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 05 prefmem +PCI: 00:1e.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 05 mem +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PNP: 00ff.1 missing set_resources +PNP: 00ff.2 missing set_resources +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PCI: 00:1f.2 10 <- [0x0000003408 - 0x000000340f] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x0000003418 - 0x000000341b] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x0000003410 - 0x0000003417] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x000000341c - 0x000000341f] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x00000030e0 - 0x00000030ff] size 0x00000020 gran 0x05 io +PCI: 00:1f.2 24 <- [0x00e1525000 - 0x00e15257ff] size 0x00000800 gran 0x0b mem +PCI: 00:1f.3 10 <- [0x00e1526000 - 0x00e15260ff] size 0x00000100 gran 0x08 mem64 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: acac + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 15f0 size 1420 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base d0000000 size 11526100 align 28 gran 0 limit efffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bdb40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base 100000000 size 140000000 align 0 gran 0 limit 0 flags e0004200 index 5 + DOMAIN: 0000 resource base bdc00000 size 2400000 align 0 gran 0 limit 0 flags f0000200 index 6 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:02.0 + PCI: 00:02.0 resource base e1000000 size 400000 align 22 gran 22 limit efffffff flags 60000201 index 10 + PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18 + PCI: 00:02.0 resource base 3400 size 8 align 3 gran 3 limit ffff flags 60000100 index 20 + PCI: 00:02.1 + PCI: 00:02.1 resource base e1400000 size 100000 align 20 gran 20 limit efffffff flags 60000201 index 10 + PCI: 00:03.0 + PCI: 00:03.1 + PCI: 00:03.2 + PCI: 00:03.3 + PCI: 00:19.0 + PCI: 00:19.0 resource base e1500000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10 + PCI: 00:19.0 resource base e1524000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 14 + PCI: 00:19.0 resource base 3000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 + PCI: 00:1a.0 + PCI: 00:1a.0 resource base 3020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1a.1 + PCI: 00:1a.1 resource base 3040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1a.2 + PCI: 00:1a.2 resource base 3060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1a.7 + PCI: 00:1a.7 resource base e1525800 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base e1520000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 + PCI: 00:1c.0 + PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.1 + PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.3Unknown device path type: 0 + child on link 0 + PCI: 00:1c.3 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.3 resource base e0000000 size 800000 align 22 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.3 resource base e0800000 size 800000 align 22 gran 20 limit efffffff flags 60080202 index 20 +Unknown device path type: 0 + +Unknown device path type: 0 + resource base e0800000 size 800000 align 22 gran 22 limit efffffff flags 40000200 index 10 +Unknown device path type: 0 + resource base e0000000 size 800000 align 22 gran 22 limit efffffff flags 40001200 index 14 +Unknown device path type: 0 + resource base 2000 size 1000 align 12 gran 12 limit ffff flags 40000100 index 18 + PCI: 00:1c.4 + PCI: 00:1c.5 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 3080 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 30a0 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 30c0 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base e1525c00 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1e.0 + PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 3408 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.2 resource base 3418 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.2 resource base 3410 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.2 resource base 341c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.2 resource base 30e0 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 resource base e1525000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:54 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + PCI: 00:1f.3 resource base e1526000 size 100 align 8 gran 8 limit efffffff flags 60000201 index 10 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f + PCI: 00:1f.5 + PCI: 00:1f.6 +Done allocating resources. +BS: Exiting BS_DEV_RESOURCES state. +BS: Entering BS_DEV_ENABLE state. +Enabling resources... +PCI: 00:00.0 subsystem <- 17aa/20e0 +PCI: 00:00.0 cmd <- 06 +PCI: 00:02.0 subsystem <- 17aa/20e4 +PCI: 00:02.0 cmd <- 03 +PCI: 00:02.1 subsystem <- 17aa/20e4 +PCI: 00:02.1 cmd <- 02 +PCI: 00:19.0 subsystem <- 0000/0000 +PCI: 00:19.0 cmd <- 103 +PCI: 00:1a.0 subsystem <- 17aa/20f0 +PCI: 00:1a.0 cmd <- 01 +PCI: 00:1a.1 subsystem <- 17aa/20f0 +PCI: 00:1a.1 cmd <- 01 +PCI: 00:1a.2 subsystem <- 17aa/20f0 +PCI: 00:1a.2 cmd <- 01 +PCI: 00:1a.7 subsystem <- 17aa/20f1 +PCI: 00:1a.7 cmd <- 102 +PCI: 00:1b.0 subsystem <- 17aa/20f2 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 17aa/20f3 +PCI: 00:1c.0 cmd <- 100 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 17aa/20f3 +PCI: 00:1c.1 cmd <- 100 +PCI: 00:1c.2 bridge ctrl <- 0003 +PCI: 00:1c.2 subsystem <- 17aa/20f3 +PCI: 00:1c.2 cmd <- 100 +PCI: 00:1c.3 bridge ctrl <- 0003 +PCI: 00:1c.3 subsystem <- 17aa/20f3 +PCI: 00:1c.3 cmd <- 107 +PCI: 00:1d.0 subsystem <- 17aa/20f0 +PCI: 00:1d.0 cmd <- 01 +PCI: 00:1d.1 subsystem <- 17aa/20f0 +PCI: 00:1d.1 cmd <- 01 +PCI: 00:1d.2 subsystem <- 17aa/20f0 +PCI: 00:1d.2 cmd <- 01 +PCI: 00:1d.7 subsystem <- 17aa/20f1 +PCI: 00:1d.7 cmd <- 102 +PCI: 00:1e.0 bridge ctrl <- 0003 +PCI: 00:1e.0 subsystem <- 17aa/20f4 +PCI: 00:1e.0 cmd <- 100 +PCI: 00:1f.0 subsystem <- 17aa/20f5 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.2 subsystem <- 17aa/20f8 +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 17aa/20f9 +PCI: 00:1f.3 cmd <- 103 +done. +BS: Exiting BS_DEV_ENABLE state. +BS: Entering BS_DEV_INIT state. +Initializing devices... +Root Device init +Keyboard init... +No PS/2 keyboard detected. +CPU_CLUSTER: 0 init +start_eip=0x00001000, code_size=0x00000031 +Initializing SMM handler... ... pmbase = 0x0600 + +SMI_STS: MCSMI +PM1_STS: +GPE0_STS: GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 +ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 +TCO_STS: + ... raise SMI# +Initializing CPU #0 +CPU: vendor Intel device 1067a +CPU: family 06, model 17, stepping 0a +Enabling cache +microcode: sig=0x1067a pf=0x80 revision=0x0 +microcode: updated to revision 0xa0b date=2010-09-28 +CPU: Intel(R) Core(TM)2 Duo CPU L9400 @ 1.86GHz. +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000bdc00000 size 0xbdb40000 type 6 +0x00000000bdc00000 - 0x00000000d0000000 size 0x12400000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +0x0000000100000000 - 0x0000000240000000 size 0x140000000 type 6 +MTRR addr 0x0-0x10 set to 6 type @ 0 +MTRR addr 0x10-0x20 set to 6 type @ 1 +MTRR addr 0x20-0x30 set to 6 type @ 2 +MTRR addr 0x30-0x40 set to 6 type @ 3 +MTRR addr 0x40-0x50 set to 6 type @ 4 +MTRR addr 0x50-0x60 set to 6 type @ 5 +MTRR addr 0x60-0x70 set to 6 type @ 6 +MTRR addr 0x70-0x80 set to 6 type @ 7 +MTRR addr 0x80-0x84 set to 6 type @ 8 +MTRR addr 0x84-0x88 set to 6 type @ 9 +MTRR addr 0x88-0x8c set to 6 type @ 10 +MTRR addr 0x8c-0x90 set to 6 type @ 11 +MTRR addr 0x90-0x94 set to 6 type @ 12 +MTRR addr 0x94-0x98 set to 6 type @ 13 +MTRR addr 0x98-0x9c set to 6 type @ 14 +MTRR addr 0x9c-0xa0 set to 6 type @ 15 +MTRR addr 0xa0-0xa4 set to 0 type @ 16 +MTRR addr 0xa4-0xa8 set to 0 type @ 17 +MTRR addr 0xa8-0xac set to 0 type @ 18 +MTRR addr 0xac-0xb0 set to 0 type @ 19 +MTRR addr 0xb0-0xb4 set to 0 type @ 20 +MTRR addr 0xb4-0xb8 set to 0 type @ 21 +MTRR addr 0xb8-0xbc set to 0 type @ 22 +MTRR addr 0xbc-0xc0 set to 0 type @ 23 +MTRR addr 0xc0-0xc1 set to 6 type @ 24 +MTRR addr 0xc1-0xc2 set to 6 type @ 25 +MTRR addr 0xc2-0xc3 set to 6 type @ 26 +MTRR addr 0xc3-0xc4 set to 6 type @ 27 +MTRR addr 0xc4-0xc5 set to 6 type @ 28 +MTRR addr 0xc5-0xc6 set to 6 type @ 29 +MTRR addr 0xc6-0xc7 set to 6 type @ 30 +MTRR addr 0xc7-0xc8 set to 6 type @ 31 +MTRR addr 0xc8-0xc9 set to 6 type @ 32 +MTRR addr 0xc9-0xca set to 6 type @ 33 +MTRR addr 0xca-0xcb set to 6 type @ 34 +MTRR addr 0xcb-0xcc set to 6 type @ 35 +MTRR addr 0xcc-0xcd set to 6 type @ 36 +MTRR addr 0xcd-0xce set to 6 type @ 37 +MTRR addr 0xce-0xcf set to 6 type @ 38 +MTRR addr 0xcf-0xd0 set to 6 type @ 39 +MTRR addr 0xd0-0xd1 set to 6 type @ 40 +MTRR addr 0xd1-0xd2 set to 6 type @ 41 +MTRR addr 0xd2-0xd3 set to 6 type @ 42 +MTRR addr 0xd3-0xd4 set to 6 type @ 43 +MTRR addr 0xd4-0xd5 set to 6 type @ 44 +MTRR addr 0xd5-0xd6 set to 6 type @ 45 +MTRR addr 0xd6-0xd7 set to 6 type @ 46 +MTRR addr 0xd7-0xd8 set to 6 type @ 47 +MTRR addr 0xd8-0xd9 set to 6 type @ 48 +MTRR addr 0xd9-0xda set to 6 type @ 49 +MTRR addr 0xda-0xdb set to 6 type @ 50 +MTRR addr 0xdb-0xdc set to 6 type @ 51 +MTRR addr 0xdc-0xdd set to 6 type @ 52 +MTRR addr 0xdd-0xde set to 6 type @ 53 +MTRR addr 0xde-0xdf set to 6 type @ 54 +MTRR addr 0xdf-0xe0 set to 6 type @ 55 +MTRR addr 0xe0-0xe1 set to 6 type @ 56 +MTRR addr 0xe1-0xe2 set to 6 type @ 57 +MTRR addr 0xe2-0xe3 set to 6 type @ 58 +MTRR addr 0xe3-0xe4 set to 6 type @ 59 +MTRR addr 0xe4-0xe5 set to 6 type @ 60 +MTRR addr 0xe5-0xe6 set to 6 type @ 61 +MTRR addr 0xe6-0xe7 set to 6 type @ 62 +MTRR addr 0xe7-0xe8 set to 6 type @ 63 +MTRR addr 0xe8-0xe9 set to 6 type @ 64 +MTRR addr 0xe9-0xea set to 6 type @ 65 +MTRR addr 0xea-0xeb set to 6 type @ 66 +MTRR addr 0xeb-0xec set to 6 type @ 67 +MTRR addr 0xec-0xed set to 6 type @ 68 +MTRR addr 0xed-0xee set to 6 type @ 69 +MTRR addr 0xee-0xef set to 6 type @ 70 +MTRR addr 0xef-0xf0 set to 6 type @ 71 +MTRR addr 0xf0-0xf1 set to 6 type @ 72 +MTRR addr 0xf1-0xf2 set to 6 type @ 73 +MTRR addr 0xf2-0xf3 set to 6 type @ 74 +MTRR addr 0xf3-0xf4 set to 6 type @ 75 +MTRR addr 0xf4-0xf5 set to 6 type @ 76 +MTRR addr 0xf5-0xf6 set to 6 type @ 77 +MTRR addr 0xf6-0xf7 set to 6 type @ 78 +MTRR addr 0xf7-0xf8 set to 6 type @ 79 +MTRR addr 0xf8-0xf9 set to 6 type @ 80 +MTRR addr 0xf9-0xfa set to 6 type @ 81 +MTRR addr 0xfa-0xfb set to 6 type @ 82 +MTRR addr 0xfb-0xfc set to 6 type @ 83 +MTRR addr 0xfc-0xfd set to 6 type @ 84 +MTRR addr 0xfd-0xfe set to 6 type @ 85 +MTRR addr 0xfe-0xff set to 6 type @ 86 +MTRR addr 0xff-0x100 set to 6 type @ 87 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 36 bits +MTRR: default type WB/UC MTRR counts: 5/7. +MTRR: WB selected as default type. +MTRR: 0 base 0x00000000bdc00000 mask 0x0000000fffc00000 type 0 +MTRR: 1 base 0x00000000be000000 mask 0x0000000ffe000000 type 0 +MTRR: 2 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 +MTRR: 4 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x00 done. +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 0: 0, 0, 7, 0x21, 35000; encoded: 0x0721 +WARNING: No CMOS option 'hyper_threading'. +CPU: 0 2 siblings +CPU: 0 has sibling 1 +CPU #0 initialized +CPU1: stack_base 00141000, stack_end 00141ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++Sending STARTUP #2 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #1 +Waiting for 1 CPUS to stop +CPU: vendor Intel device 1067a +CPU: family 06, model 17, stepping 0a +Enabling cache +microcode: sig=0x1067a pf=0x80 revision=0x0 +microcode: updated to revision 0xa0b date=2010-09-28 +CPU: Intel(R) Core(TM)2 Duo CPU L9400 @ 1.86GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 36 bits + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x01 done. +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 7, 0x21, 35000; encoded: 0x0721 +CPU: 1 2 siblings +CPU #1 initialized +All AP CPUs stopped (4540 loops) +CPU1: stack: 00141000 - 00142000, lowest used address 00141b6c, stack used: 1172 bytes +DOMAIN: 0000 init +PCI: 00:00.0 init +PCI: 00:02.0 init +Initializing VGA without OPROM. MMIO 0xe1000000 +EDID: +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +Extracted contents: +header: 00 00 00 00 00 00 00 00 +serial number: 00 00 00 00 00 00 00 00 00 00 +version: 00 00 +basic params: 00 00 00 00 00 +chroma info: 00 00 00 00 00 00 00 00 00 00 +established: 00 00 00 +standard: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +descriptor 1: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +descriptor 3: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +descriptor 4: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +extensions: 00 +checksum: 00 + +No header found +Couldn't find GFX clock divisors +PCI: 00:02.1 init +PCI: 00:19.0 init +PCI: 00:1a.0 init +PCI: 00:1a.1 init +PCI: 00:1a.2 init +PCI: 00:1a.7 init +EHCI: Setting up controller.. done. +PCI: 00:1b.0 init +Azalia: base = e1520000 +Azalia: No codec! +PCI: 00:1c.0 init +Initializing ICH9 PCIe root port. +PCI: 00:1c.1 init +Initializing ICH9 PCIe root port. +PCI: 00:1c.2 init +Initializing ICH9 PCIe root port. +PCI: 00:1c.3 init +Initializing ICH9 PCIe root port. +PCI: 00:1d.0 init +PCI: 00:1d.1 init +PCI: 00:1d.2 init +PCI: 00:1d.7 init +EHCI: Setting up controller.. done. +PCI: 00:1e.0 init +PCI: 00:1f.0 init +i82801ix: lpc_init +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +IOAPIC: Dumping registers + reg 0x0000: 0x02000000 + reg 0x0001: 0x00170020 + reg 0x0002: 0x00170020 +IOAPIC: 24 interrupts +IOAPIC: Enabling interrupts on FSB +IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 +IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 +IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 +WARNING: No CMOS option 'power_on_after_fail'. +Set power on after power failure. +WARNING: No CMOS option 'nmi'. +NMI sources disabled. +rtc_failed = 0x4 +RTC Init +RTC: Clear requested +Disabling ACPI via APMC: +done. +Locking SMM. +PCI: 00:1f.2 init +i82801ix_sata: initializing... +SATA controller in AHCI mode. +ABAR: E1525000 +PCI: 00:1f.3 init +smbus: PCI: 00:1f.3[0]->I2C: 01:54 init +smbus: PCI: 00:1f.3[0]->I2C: 01:55 init +smbus: PCI: 00:1f.3[0]->I2C: 01:56 init +smbus: PCI: 00:1f.3[0]->I2C: 01:57 init +smbus: PCI: 00:1f.3[0]->I2C: 01:5c init +Locking EEPROM RFID +init EEPROM done +smbus: PCI: 00:1f.3[0]->I2C: 01:5d init +smbus: PCI: 00:1f.3[0]->I2C: 01:5e init +smbus: PCI: 00:1f.3[0]->I2C: 01:5f init +Devices initialized +Show all devs...After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +APIC: acac: enabled 0 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:03.0: enabled 0 +PCI: 00:03.1: enabled 0 +PCI: 00:03.2: enabled 0 +PCI: 00:03.3: enabled 0 +IOAPIC: 02: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:1a.0: enabled 1 +PCI: 00:1a.1: enabled 1 +PCI: 00:1a.2: enabled 1 +PCI: 00:1a.7: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1c.4: enabled 0 +PCI: 00:1c.5: enabled 0 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:5c: enabled 1 +I2C: 01:5d: enabled 1 +I2C: 01:5e: enabled 1 +I2C: 01:5f: enabled 1 +PCI: 00:1f.5: enabled 0 +PCI: 00:1f.6: enabled 0 +Unknown device path type: 0 +: enabled 1 +APIC: 01: enabled 1 +BS: Exiting BS_DEV_INIT state. +BS: Entering BS_POST_DEVICE state. +Finalize devices... +Devices finalized +BS: Exiting BS_POST_DEVICE state. +BS: Entering BS_OS_RESUME_CHECK state. +BS: Exiting BS_OS_RESUME_CHECK state. +BS: Entering BS_WRITE_TABLES state. +Writing ISA IRQs +no IRQ found for PCI: 00:00.0 +fixed IRQ entry for: PCI: 00:02.0: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:02.1 +no IRQ found for PCI: 00:19.0 +fixed IRQ entry for: PCI: 00:1a.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1a.1: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1a.2: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1a.7: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1b.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1c.0: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:1c.1 +no IRQ found for PCI: 00:1c.2 +no IRQ found for PCI: 00:1c.3 +fixed IRQ entry for: PCI: 00:1d.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1d.1: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1d.2: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1d.7: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:1e.0 +no IRQ found for PCI: 00:1f.0 +fixed IRQ entry for: PCI: 00:1f.2: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1f.3: INTC# -> IOAPIC 2 PIN 18 +Wrote the mp table end at: 000f0010 - 000f0194 +MPTABLE len: 404 +Writing ISA IRQs +no IRQ found for PCI: 00:00.0 +fixed IRQ entry for: PCI: 00:02.0: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:02.1 +no IRQ found for PCI: 00:19.0 +fixed IRQ entry for: PCI: 00:1a.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1a.1: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1a.2: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1a.7: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1b.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1c.0: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:1c.1 +no IRQ found for PCI: 00:1c.2 +no IRQ found for PCI: 00:1c.3 +fixed IRQ entry for: PCI: 00:1d.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1d.1: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1d.2: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1d.7: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:1e.0 +no IRQ found for PCI: 00:1f.0 +fixed IRQ entry for: PCI: 00:1f.2: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1f.3: INTC# -> IOAPIC 2 PIN 18 +Wrote the mp table end at: bdad9010 - bdad9194 +MPTABLE len: 404 +MP table: 404 bytes. +ACPI: Writing ACPI tables at bdab5000. +ACPI: * FACS +ACPI: * DSDT +ACPI: * FADT +ACPI: added table 1/32, length now 40 +ACPI: * SSDT +Found 1 CPU(s) with 2 core(s) each. +clocks between 800 and 2133 MHz. +adding 4 P-States between busratio 6 and 8, incl. P0 +PSS: 1867MHz power 35000 control 0x829 status 0x829 +PSS: 1866MHz power 35000 control 0x721 status 0x721 +PSS: 1600MHz power 15000 control 0x617 status 0x617 +PSS: 800MHz power 12000 control 0x8611 status 0x8611 +clocks between 800 and 2133 MHz. +adding 4 P-States between busratio 6 and 8, incl. P0 +PSS: 1867MHz power 35000 control 0x829 status 0x829 +PSS: 1866MHz power 35000 control 0x721 status 0x721 +PSS: 1600MHz power 15000 control 0x617 status 0x617 +PSS: 800MHz power 12000 control 0x8611 status 0x8611 +ACPI: added table 2/32, length now 44 +ACPI: * MCFG +ACPI: added table 3/32, length now 48 +ACPI: * MADT +ACPI: added table 4/32, length now 52 +current = bdab8e40 +ACPI: * DMAR +ACPI: added table 5/32, length now 56 +current = bdab8ef0 +ACPI: * HPET +ACPI: added table 6/32, length now 60 +ACPI: done. +ACPI tables: 16176 bytes. +smbios_write_tables: bdab3000 +recv_ec_data: 0x37 +recv_ec_data: 0x58 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x32 +recv_ec_data: 0x32 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x06 +recv_ec_data: 0x03 +Root Device (LENOVO ThinkPad X200) +CPU_CLUSTER: 0 (Intel GM45 Northbridge) +APIC: 00 (Socket BGA956 CPU) +APIC: acac (Intel Penryn CPU) +DOMAIN: 0000 (Intel GM45 Northbridge) +PCI: 00:00.0 (Intel GM45 Northbridge) +PCI: 00:02.0 (Intel GM45 Northbridge) +PCI: 00:02.1 (Intel GM45 Northbridge) +PCI: 00:03.0 (Intel GM45 Northbridge) +PCI: 00:03.1 (Intel GM45 Northbridge) +PCI: 00:03.2 (Intel GM45 Northbridge) +PCI: 00:03.3 (Intel GM45 Northbridge) +IOAPIC: 02 (IOAPIC) +PCI: 00:19.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1a.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1a.1 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1a.2 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1a.7 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1b.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.1 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.2 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.3 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.4 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.5 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1d.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1d.1 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1d.2 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1d.7 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1e.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1f.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7) +PNP: 00ff.2 (Lenovo H8 EC) +PCI: 00:1f.2 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1f.3 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +I2C: 01:54 (AT24RF08C) +I2C: 01:55 (AT24RF08C) +I2C: 01:56 (AT24RF08C) +I2C: 01:57 (AT24RF08C) +I2C: 01:5c (AT24RF08C) +I2C: 01:5d (AT24RF08C) +I2C: 01:5e (AT24RF08C) +I2C: 01:5f (AT24RF08C) +PCI: 00:1f.5 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1f.6 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +Unknown device path type: 0 + (unknown) +APIC: 01 (unknown) +SMBIOS tables: 436 bytes. +Writing table forward entry at 0x00000500 +Wrote coreboot table at: 00000500, 0x10 bytes, checksum 9233 +Table forward entry ends at 0x00000528. +... aligned to 0x00001000 +Writing coreboot table at 0xbdaab000 +rom_table_end = 0xbdaab000 +... aligned to 0xbdab0000 + 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES + 1. 0000000000001000-000000000009ffff: RAM + 2. 00000000000c0000-00000000bdaaafff: RAM + 3. 00000000bdaab000-00000000bdbfffff: CONFIGURATION TABLES + 4. 00000000bdc00000-00000000bfffffff: RESERVED + 5. 00000000f0000000-00000000f3ffffff: RESERVED + 6. 0000000100000000-000000023fffffff: RAM +Wrote coreboot table at: bdaab000, 0x8c8 bytes, checksum f79a +coreboot table: 2272 bytes. +CBMEM ROOT 0. bdbff000 00001000 +CAR GLOBALS 1. bdbfe000 00001000 +USBDEBUG 2. bdbfd000 00001000 +CONSOLE 3. bdbdd000 00020000 +TIME STAMP 4. bdbdc000 00001000 +ROMSTAGE 5. bdbdb000 00001000 +GDT 6. bdbda000 00001000 +ACPI RESUME 7. bdada000 00100000 +SMP TABLE 8. bdad9000 00001000 +ACPI 9. bdab5000 00024000 +ACPI GNVS 10. bdab4000 00001000 +SMBIOS 11. bdab3000 00001000 +COREBOOT 12. bdaab000 00008000 +BS: Exiting BS_WRITE_TABLES state. +BS: Entering BS_PAYLOAD_LOAD state. +CBFS: located payload @ ff8341b8, 542448 bytes. +Loading segment from rom address 0xff8341b8 + code (compression=1) + New segment dstaddr 0x8200 memsize 0x17e48 srcaddr 0xff83420c filesize 0x83fc + (cleaned up) New segment addr 0x8200 size 0x17e48 offset 0xff83420c filesize 0x83fc +Loading segment from rom address 0xff8341d4 + code (compression=1) + New segment dstaddr 0x100000 memsize 0x201538 srcaddr 0xff83c608 filesize 0x7c2a0 + (cleaned up) New segment addr 0x100000 size 0x201538 offset 0xff83c608 filesize 0x7c2a0 +Loading segment from rom address 0xff8341f0 + Entry Point 0x00008200 +Bounce Buffer at bd862000, 2393460 bytes +Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017e48 filesz: 0x00000000000083fc +lb: [0x0000000000100000, 0x000000000014703c) +Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017e48 filesz: 0x00000000000083fc +using LZMA +[ 0x00008200, 00018717, 0x00020048) <- ff83420c +Clearing Segment: addr: 0x0000000000018717 memsz: 0x0000000000007931 +dest 00008200, end 00020048, bouncebuffer bd862000 +Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000201538 filesz: 0x000000000007c2a0 +lb: [0x0000000000100000, 0x000000000014703c) +segment: [0x0000000000100000, 0x000000000017c2a0, 0x0000000000301538) + bounce: [0x00000000bd862000, 0x00000000bd8de2a0, 0x00000000bda63538) +Post relocation: addr: 0x00000000bd862000 memsz: 0x0000000000201538 filesz: 0x000000000007c2a0 +using LZMA +[ 0xbd862000, bda63538, 0xbda63538) <- ff83c608 +dest bd862000, end bda63538, bouncebuffer bd862000 +move suffix around: from bd8a903c, to 14703c, amount: 1ba4fc +Loaded segments +BS: Exiting BS_PAYLOAD_LOAD state. +BS: Entering BS_PAYLOAD_BOOT state. +ICH7 watchdog disabled +Jumping to boot code at 00008200 +CPU0: stack: 00142000 - 00143000, lowest used address 00142a28, stack used: 1496 bytes +entry = 0x00008200 +lb_start = 0x00100000 +lb_size = 0x0004703c +buffer = 0xbd862000 diff --git a/site/docs/hardware/text/x200s/cblog02.txt b/site/docs/hardware/text/x200s/cblog02.txt new file mode 100644 index 0000000..3a590dc --- /dev/null +++ b/site/docs/hardware/text/x200s/cblog02.txt @@ -0,0 +1,77 @@ +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +WARNING: Ignoring S4-assertion-width violation. +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using high performance mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 14 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 15 + Max clock: 533 MHz + CAS: 0x01c0 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +Memory configured in dual-channel assymetric mode. +Memory map: +TOM = 384MB +TOLUD = 384MB +TOUUD = 384MB +REMAP: base = 65535MB + limit = 0MB +usedMEsize: 0MB +Performing Jedec initialization at address 0x00000000. +Performing Jedec initialization at address 0x08000000. +Performing Jedec initialization at address 0x10000000. +Final timings for group 0 on channel 0: 6.1.0.3.2 +Final timings for group 1 on channel 0: 6.0.2.6.3 +Final timings for group 2 on channel 0: 6.1.2.0.1 +Final timings for group 3 on channel 0: 6.1.0.7.3 +Timing under-/overflow during receive-enable calibration. diff --git a/site/docs/hardware/text/x200s/cblog03.txt b/site/docs/hardware/text/x200s/cblog03.txt new file mode 100644 index 0000000..d078a48 --- /dev/null +++ b/site/docs/hardware/text/x200s/cblog03.txt @@ -0,0 +1,158 @@ +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +WARNING: Ignoring S4-assertion-width violation. +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using high performance mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:ff +2:51:b +DDR mask 4, DDR 3 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +DIMMs support 666 MHz, but chipset only runs at up to 533. Limiting... +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +Memory configured in single-channel mode. +Memory map: +TOM = 128MB +TOLUD = 128MB +TOUUD = 128MB +REMAP: base = 65535MB + limit = 0MB +usedMEsize: 0MB +Performing Jedec initialization at address 0x00000000. +Final timings for group 0 on channel 1: 6.0.2.6.4 +Final timings for group 1 on channel 1: 6.0.2.6.4 +Final timings for group 2 on channel 1: 6.0.2.8.3 +Final timings for group 3 on channel 1: 6.0.2.8.6 +Lower bound for byte lane 0 on channel 1: 0.0 +Upper bound for byte lane 0 on channel 1: 10.4 +Final timings for byte lane 0 on channel 1: 5.2 +Lower bound for byte lane 1 on channel 1: 0.0 +Upper bound for byte lane 1 on channel 1: 11.2 +Final timings for byte lane 1 on channel 1: 5.5 +Lower bound for byte lane 2 on channel 1: 0.0 +Upper bound for byte lane 2 on channel 1: 10.5 +Final timings for byte lane 2 on channel 1: 5.2 +Lower bound for byte lane 3 on channel 1: 0.0 +Upper bound for byte lane 3 on channel 1: 9.7 +Final timings for byte lane 3 on channel 1: 4.7 +Timing overflow during read training. +Read training failure: lower bound. +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +Interrupted RAM init, reset required. +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using high performance mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:ff +2:51:b +DDR mask 4, DDR 3 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +DIMMs support 666 MHz, but chipset only runs at up to 533. Limiting... +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Setting IGD memory frequencies for VCO #1. +Memory configured in single-channel mode. +Memory map: +TOM = 128MB +TOLUD = 128MB +TOUUD = 128MB +REMAP: base = 65535MB + limit = 0MB +usedMEsize: 0MB +Performing Jedec initialization at address 0x00000000. +Final timings for group 0 on channel 1: 6.0.2.7.6 +Final timings for group 1 on channel 1: 6.0.2.6.6 +Final timings for group 2 on channel 1: 6.0.2.8.7 +Final timings for group 3 on channel 1: 6.1.0.2.5 +Lower bound for byte lane 0 on channel 1: 0.0 +Upper bound for byte lane 0 on channel 1: 10.3 +Final timings for byte lane 0 on channel 1: 5.1 +Lower bound for byte lane 1 on channel 1: 0.0 +Upper bound for byte lane 1 on channel 1: 11.3 +Final timings for byte lane 1 on channel 1: 5.5 +Lower bound for byte lane 2 on channel 1: 0.0 +Upper bound for byte lane 2 on channel 1: 10.5 +Final timings for byte lane 2 on channel 1: 5.2 +Lower bound for byte lane 3 on channel 1: 0.0 +Upper bound for byte lane 3 on channel 1: 9.6 +Final timings for byte lane 3 on channel 1: 4.7 +Timing overflow during read training. +Read training failure: lower bound. diff --git a/site/docs/hardware/x200.md b/site/docs/hardware/x200.md new file mode 100644 index 0000000..c7e1104 --- /dev/null +++ b/site/docs/hardware/x200.md @@ -0,0 +1,192 @@ +--- +title: ThinkPad X200 +x-toc-enable: true +... + +
+
+ThinkPad X200 +
+ +| ***Specifications*** | | +|----------------------------|------------------------------------------------| +| **Manufacturer** | Lenovo | +| **Name** | ThinkPad X200/X200S/X200 Tablet | +| **Released** | July/September 2009 | +| **Chipset** | Intel Cantiga GM45 | +| **CPU** | Intel Core 2 Duo (Penryn family) | +| **Graphics** | Intel GMA X4500MHD | +| **Display** | 1280x800/1440x900 TFT | +| **Memory** | 1,2,3 or 4GB (Upgradable to 8GB, unofficially) | +| **Architecture** | x86_64 | +| **EC** | Proprietary | +| **Original boot firmware** | LenovoBIOS | +| **Intel ME/AMD PSP** | Present. Can be completly disabled. | +| **Flash chip** | SOIC-8/SOIC-16/WSON-8 4MiB/8MiB (Upgradable + to 16MiB) | +``` +W+: Works without blobs; +N: Doesn't work; +W*: Works with blobs; +U: Untested; +P+: Partially works; +P*: Partially works with blobs +``` + +| ***Features*** | | +|----------------|---------------------------------------| +| **Internal flashing with original boot firmware** | N | +| **Display** | W+ | +| **Audio** | W+ | +| **RAM Init** | W+ | +| **External output** | W+ | +| **Display brightness** | P+ | + +| ***Payloads supported*** | | +|---------------------------|-----------| +| **GRUB** | Works | +| **SeaBIOS** | Works | +| **SeaBIOS with GRUB** | Works | +
+Dell Latitude E6400 +=================== + +**If you haven't bought an X200 yet: the [Dell Latitude +E6400](../../news/e6400.md) is much easier to flash; no disassembly required, +it can be flashed entirely in software from Dell BIOS to Libreboot. It is the +same hardware generation (GM45), with same CPUs, video processor, etc.** + +Introduction +============ + +It is believed that all X200 laptops are compatible. X200S and X200 +Tablet will also work, [depending on the configuration](#x200s). + +It may be possible to put an X200 motherboard in an X201 chassis, though this +is currently untested by the libreboot project. The same may also apply between +X200S and X201S; again, this is untested. *It's most likely true.* + +There are two possible flash chip sizes for the X200: 4MiB (32Mbit) or +8MiB (64Mbit). This can be identified by the type of flash chip below +the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. + +*The X200 laptops come with the ME (and sometimes AMT in addition) +before flashing libreboot. libreboot disables and removes it by using a +modified descriptor: see [../install/ich9utils.md](../install/ich9utils.md)* +(contains notes, plus instructions) + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +EC update {#ecupdate} +========= + +It is recommended that you update to the latest EC firmware version. The +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from +libreboot, so we don't actually provide that, but if you still have +Lenovo BIOS then you can just run the Lenovo BIOS update utility, which +will update both the BIOS and EC version. See: + +- [../install/#flashrom](../install/#flashrom) +- +- [X200, X200s, X200si BIOS Update](http://pcsupport.lenovo.com/au/en/products/laptops-and-netbooks/thinkpad-x-series-laptops/thinkpad-x200/downloads/ds015007) +- [X200t BIOS Update](http://pcsupport.lenovo.com/au/en/products/laptops-and-netbooks/thinkpad-x-series-tablet-laptops/thinkpad-x200-tablet/downloads/ds018814) + +NOTE: this can only be done when you are using Lenovo BIOS. How to +update the EC firmware while running libreboot is unknown. libreboot +only replaces the BIOS firmware, not EC. + +Updated EC firmware has several advantages e.g. better battery +handling. + +Battery Recall {#batteryrecall} +============== + +[On 21 April 2015, Lenovo expanded a recall on Lenovo batteries found in some ThinkPad models, which includes the X200 and X200S.](https://pcsupport.lenovo.com/cr/en/solutions/hf004122) +To find out if you are affected, use [this Lenovo tool.](https://lenovobattery2014.orderz.com/) +Lenovo advises that owners of the recalled models "should turn off the system, remove the battery, +and only power your ThinkPad by plugging in the AC adapter and power cord." +Upon battery verification, Lenovo will replace recalled batteries free of charge. +Battery replacement instructions for the X200/X200s are found [on this page.](https://pcsupport.lenovo.com/cr/en/parts/pd003507/) + +LCD compatibility list {#lcd_supported_list} +---------------------- + +LCD panel list (X200 panels listed there): + + +All LCD panels for the X200, X200S and X200 Tablet are known to work. + +### AFFS/IPS panels {#ips} + +#### X200 + +Adapted from + + +Look at wikipedia for difference between TN and IPS panels. IPS have +much better colour/contrast than a regular TN, and will typically have +good viewing angles. + +These seem to be from the X200 tablet. You need to find one without the +glass touchscreen protection on it (might be able to remove it, though). +It also must not have a digitizer on it (again, might be possible to +just simply remove the digitizer). + +- BOE-Hydis HV121WX4-120, HV121WX4-110 or HV121WX4-100 - cheap-ish, + might be hard to find + +- Samsung LTN121AP02-001 - common to find, cheap + +*If your X200 has an LED backlit panel in it, then you also need to get +an inverter and harness cable that is compatible with the CCFL panels. +To see which panel type you have, see +[\#led\_howtotell](#led_howtotell). If you need the inverter/cable, here +are part numbers: 44C9909 for CCFL LVDS cable with bluetooth and camera +connections, and 42W8009 or 42W8010 for the inverter.* + +There are glossy and matte versions of these. Matte means anti-glare, +which is what you want (in this authors opinion). + +Refer to the HMM (hardware maintenance manual) for how to replace the +screen. + +Sources: + +- [ThinkPad Forums - Matte AFFS Panel on + X200](http://forum.thinkpads.com/viewtopic.php?f=2&t=84941) +- [ThinkPad Forums - Parts for X200 AFFS + Mod](http://forum.thinkpads.com/viewtopic.php?p=660662#p660662) +- [ThinkWiki.de - X200 Displayumbau](http://thinkwiki.de/X200_Displayumbau) + +### X200S + + explains that the +X200S screens/assemblies are thinner. You need to replace the whole lid with +one from a normal X200/X201. + +How to tell if it has an LED or CCFL? {#led_howtotell} +------------------------------------- + +Some X200s have a CCFL backlight and some have an LED backlight, in their LCD +panel. This also means that the inverters will vary, so you must be careful if +ever replacing either the panel and/or inverter. (a CCFL inverter is +high-voltage and will destroy an LED backlit panel). + +CCFLs contain mercury. An X200 with a CCFL backlight will (unless it has been +changed to an LED, with the correct inverter. Check with your supplier!) say +the following: *"This product contains Lithium Ion Battery, Lithium Battery and +a lamp which contains mercury; dispose according to local, state or federal +laws"* (one with an LED backlit panel will say something different). + +Hardware register dumps {#regdumps} +----------------------- + +The coreboot wiki +[shows](http://www.coreboot.org/Motherboard_Porting_Guide) how to +collect various logs useful in porting to new boards. Following are +outputs from the X200: + +- BIOS 3.15, EC 1.06 + - [hwdumps/x200/](hwdumps/x200/) + diff --git a/site/docs/hardware/x200.uk.md b/site/docs/hardware/x200.uk.md new file mode 100644 index 0000000..73b8735 --- /dev/null +++ b/site/docs/hardware/x200.uk.md @@ -0,0 +1,185 @@ +--- +title: ThinkPad X200 +x-toc-enable: true +... + +
+
+ThinkPad X200 +
+ +| ***Характеристики*** | | +|----------------------------|------------------------------------------------| +| **Виробник** | Lenovo | +| **Назва** | ThinkPad X200/X200S/X200 Tablet | +| **Випущено** | Липень/Вересень 2009 року | +| **Чіпсет** | Intel Cantiga GM45 | +| **ЦП** | Intel Core 2 Duo (сімейство Penryn) | +| **Графіка** | Intel GMA X4500MHD | +| **Дісплей** | 1280x800/1440x900 TFT | +| **Пам'ять** | 1,2,3 or 4GB (оновлюється до 8GB, неофіційно) | +| **Архітектура** | x86_64 | +| **EC** | Пропрієтарний | +| **Оригінальна прошивка** | LenovoBIOS | +| **Intel ME/AMD PSP** | Наявний. Можна повністю вимкнути. | +| **Флеш-чіп** | SOIC-8/SOIC-16/WSON-8 4MiB/8MiB (Оновлюється + до 16MБ) | +``` +W+: Працює без бінарних компонентів; +N: Не працює; +W*: Працює з бінарними компонентами; +U: Не перевірялось; +P+: Частково працює; +P*: Частково працює з бінарними компонентами +``` + +| ***Функції*** | | +|----------------|---------------------------------------| +| **Внутрішня прошивка з оригінальною прошивкою** | N | +| **Дісплей** | W+ | +| **Аудіо** | W+ | +| **Ініціалізація ПДД** | W+ | +| **Зовнішній вивід** | W+ | +| **Яскравість дісплею** | P+ | + +| ***Корисні навантаження*** | | +|-----------------------------|-----------| +| **GRUB** | Працює | +| **SeaBIOS** | Працює | +| **SeaBIOS з GRUB** | Працює | +
+ +Вступ +============ + +Вважається що всі ноутбуки X200 сумісні. X200S та X200 +Tablet також працюватимуть, [залежно від конфігурації](#x200s). + +Можливо, можна розмістити материнську плату X200 у шасі X201, хоча це +наразі не перевірено проектом libreboot. Те ж саме може стосуватися +X200S та X201S; знову ж таки, це неперевірено. *Швидше за все, це правда.* + +Є два можливих розміра флеш-чіпа для X200: 4MБ (32 Мбіт) або +8МБ (64 Мбіт). Це можна визначити за типом флеш-чіпа під +упором для рук: 4МБ це SOIC-8, 8МБ це SOIC-16. + +*Ноутбуки X200 постачаються з ME (та іноді AMT додатково) +перед перепрошивкою libreboot. libreboot вимикає та видаляє його за допомогою +модифікованого дескриптора: дивіться [../install/ich9utils.md](../install/ich9utils.md)* +(містить примітки та інструкції) + +Інструкції з перепрошивки можна знайти за адресою +[../install/\#flashrom](../install/#flashrom) + +Оновлення EC {#ecupdate} +========= + +Рекомендується оновити мікропрограму EC до останньої версії. +[Прошивка EC](../../faq.md#ec-embedded-controller-firmware) є окремою від +libreboot, тому ми її фактично не надаємо, але якщо у вас все ще є +Lenovo BIOS, ви можете просто запустити утиліту оновлення BIOS Lenovo, яка +оновить як BIOS, так і версію EC. Дивіться: + +- [../install/#flashrom](../install/#flashrom) +- +- [Оновлення BIOS X200, X200s, X200i](http://pcsupport.lenovo.com/au/en/products/laptops-and-netbooks/thinkpad-x-series-laptops/thinkpad-x200/downloads/ds015007) +- [Оновлення BIOS X200t](http://pcsupport.lenovo.com/au/en/products/laptops-and-netbooks/thinkpad-x-series-tablet-laptops/thinkpad-x200-tablet/downloads/ds018814) + +ПРИМІТКА: це можна зробити, лише якщо ви використовуєте Lenovo BIOS. Як +оновити мікропрограму EC, користуючись libreboot, невідомо. libreboot +тільки замінює прошивку BIOS, не EC. + +Оновлена мікропрограма EC має декілька переваг, напр. краще поводження +з акумулятором. + +Відкликання батареї {#batteryrecall} +============== + +[21 квітня 2015 року, Lenovo розширила відкликання акумуляторів Lenovo, які були встановлені в деяких моделях Thinkpad, зокрема X200 та X200S.](https://pcsupport.lenovo.com/cr/en/solutions/hf004122) +Щоб дізнатися, чи вас це стосується, використовуйте [цей інструмент Lenovo.](https://lenovobattery2014.orderz.com/) +Lenovo радить власникам відкликаних моделей "вимкнути систему, вийняти батарею, +та живити ThinkPad лише шляхом підключення адаптера змінного струму та шнура живлення." +Після перевірки батареї, Lenovo безкоштовно замінить відкликані батареї. +Інструкції щодо заміни батареї для X200/X200s [можна знайти на цій сторінці.](https://pcsupport.lenovo.com/cr/en/parts/pd003507/) + +Список сумісності LCD {#lcd_supported_list} +---------------------- + +Список РК-панелей (там перераховані панелі X200): + + +Відомо, що всі РК-панелі для X200, X200S та X200 Tablet працюють. + +### AFFS/IPS панелі {#ips} + +#### X200 + +Адаптовано з + + +Подивіться у Вікіпедії різницю між панелями TN та IPS. IPS мають +набагато кращий колір/контраст, ніж звичайний TN, і зазвичай мають +хороші кути огляду. + +Це, здається, з X200 tablet. Вам потрібно знайти таку +без скляного захисту сенсорного екрана (проте її можна зняти). +На ньому також не повинно бути дигітайзера (знову ж таки, можна +просто видалити дигітайзер). + +- BOE-Hydis HV121WX4-120, HV121WX4-110 або HV121WX4-100 - дешево, + може бути тяжко знайти + +- Samsung LTN121AP02-001 - звичайно знайти, недорого + +*Якщо ваш X200 має панель зі світлодіодним підсвічуванням, вам також потрібно придбати +інвертор і кабель, сумісний з панелями CCFL. +Щоб дізнатися, який у вас тип панелі, перегляньте +[\#led\_howtotell](#led_howtotell). Якщо вам потрібен інвертор/кабель, ось +номери деталей: 44C9909 для кабелю CCFL LVDS із підключенням bluetooth і камери, +та 42W8009 або 42W8010 для інвертора.* + +Існують глянцеві та матові варіанти. Матовий означає антивідблиск,, +чого ви і хочете (на думку авторів). + +Зверніться до HMM (посібник з обслуговування обладнання), щоб дізнатися, як +замінити екран. + +Джерела: + +- [Форуми ThinkPad - матова панель AFFS на + X200](http://forum.thinkpads.com/viewtopic.php?f=2&t=84941) +- [Форуми ThinkPad - Частини для мода X200 AFFS + Mod](http://forum.thinkpads.com/viewtopic.php?p=660662#p660662) +- [ThinkWiki.de - X200 Displayumbau](http://thinkwiki.de/X200_Displayumbau) + +### X200S + + пояснює, що +екрани/блоки X200S тонші. Вам потрібно замінити всю кришку на одну від +звичайного X200/X201. + +Як визначити, чи у нього LED, чи CCFL? {#led_howtotell} +------------------------------------- + +Деякі X200 мають підсвічування CCFL, а деякі - світлодіодне підсвічування на РК-панелі. +Це також означає, що інвертори відрізнятимуться, тому ви повинні бути обережними, +коли замінюєте панель та/або інвертор. (інвертор CCFL має +високу напругу і зруйнює світлодіодну панель із підсвічуванням). + +CCFL містять меркурій. На X200 з CCFL підсвіткою (якщо його не було замінено на світлодіодне з правильним +інвертором. Зверніться до свого постачальника!) буде написано +наступне: *"Цей продукт містить літій-іонну батарею, літієву батарею та лампу, +яка містить ртуть; утилізуйте відповідно до місцевих, державних або федеральних +законів"* (на тому, що має світлодіодне підсвічування, буде написано щось інше). + +Дампи апаратного регістру {#regdumps} +----------------------- + +Вікі coreboot +[показує](http://www.coreboot.org/Motherboard_Porting_Guide) як +збирати різноманітні логи, корисні для портування на нові плати. Нижче наведено +вихідні дані X200: + +- BIOS 3.15, EC 1.06 + - [hwdumps/x200/](hwdumps/x200/) + diff --git a/site/docs/index.md b/site/docs/index.md new file mode 100644 index 0000000..e5f6149 --- /dev/null +++ b/site/docs/index.md @@ -0,0 +1,36 @@ +--- +title: Documentation +... + +Always check [libreboot.org](https://libreboot.org/) for the latest updates to +libreboot. News, including release announcements, can be found in +the [main news section](../news/). + +[Answers to Frequently Asked Questions about libreboot](../faq.md). + +Installing libreboot +==================== + +- [What systems can I use libreboot on?](hardware/) +- [How to install libreboot](install/) + +Documentation related to operating systems +============================ + +- [How to install BSD on an x86 host system](bsd/) +- [Linux Guides](linux/) + +Information for developers +========================== + +- [How to compile the libreboot source code](build/) +- [Build system developer documentation](maintain/) +- [GRUB payload](grub/) +- [U-Boot payload](uboot/) + +Other information +================= + +- [Miscellaneous](misc/) +- [List of codenames](misc/codenames.md) + diff --git a/site/docs/index.uk.md b/site/docs/index.uk.md new file mode 100644 index 0000000..2754857 --- /dev/null +++ b/site/docs/index.uk.md @@ -0,0 +1,36 @@ +--- +title: Документація +... + +Завжди перевіряйте [libreboot.org](https://libreboot.org/index.uk.html) для останніх оновлень +libreboot. Новини, включаючи оголошення про випуски, може бути знайдено +в [основній секції новин](../news/). + +[Відповіді на поширені запитання про libreboot](../faq.md). + +Встановлення libreboot +==================== + +- [На яких системах я можу встановлювати libreboot?](hardware/) +- [Як встановити libreboot](install/) + +Документація, яка має відношення до операційних систем +============================ + +- [Як встановити BSD на x86 хостову систему](bsd/) +- [Керівництва Linux](linux/) + +Інформація для розробників +========================== + +- [Як зібрати джерельний код libreboot](build/) +- [Документація розробника системи побудови](maintain/) +- [Корисне навантаження GRUB](grub/) +- [Корисне навантаження U-Boot](uboot/) + +Інша інформація +================= + +- [Різне](misc/) +- [Список кодових назв](misc/codenames.md) + diff --git a/site/docs/install/c201.md b/site/docs/install/c201.md new file mode 100644 index 0000000..d20e8f5 --- /dev/null +++ b/site/docs/install/c201.md @@ -0,0 +1,102 @@ +--- +title: ASUS Chromebook C201 installation guide +x-toc-enable: true +... + +WARNING: This board is known to have non-functioning video init at the time +of writing, 19 February 2023. It is as yet unsolved. + +See: + +Introduction +=========== + +This page contains information about assembly and disassembly, for flashing +the ASUS Chromebook C201 externally. It will also link to internal flashing +instructions, and information about U-Boot. + +Flashrom +-------- + +A special fork of flashrom, maintained by Google, is required for flashing. +More information about this is present in the generic [chromebook flashing +instructions](chromebooks.md). + +Depthcharge payload (obsolete) +------------------------------ + +This board was also supported in Libreboot 20160907, with the Depthcharge +payload. Support was dropped in later releases, and then re-added in the +December 2022 release but with *u-boot* payload (not *depthcharge*). + +Refer to older versions of this page, in `lbwww.git`, if you wish to see +instructions pertaining to Depthcharge: + +* +* + +U-boot payload +============== + +U-Boot was ported to coreboot CrOS devices, courtesy of Alper Nebi +Yasak (`alpernebbi` on Libreboot IRC). + +Read the section pertaining to U-boot payload: + +[u-boot payload documentation for Libreboot](../uboot/) + +Internal flashing +================= + +External flashing is possible, but only necessary in the event of a *brick*. +If you're flashing good firmware, and the machine boots properly, you can +do it in software, from the host CPU. + +In the past, C201 was the only CrOS device so this page contained information +about internal flashing. Libreboot now supports many more CrOS devices, so +the information has moved. + +See: [chromebook flashing instructions](chromebooks.md) + +Write-protect screw +------------------- + +The chromebook flashing instructions, linked above, refer to a *screw* that +can be turned, to disable flash protection. This is necessary, for internally +flashing the C201. This section will tell you how to access that screw. + +To access the screw, the device has to be opened. There are 8 screws to remove +from the bottom of the device, as shown on the picture below. Two are hidden +under the top pads. After removing the screws, the keyboard plastic part can be +carefully detached from the rest. Beware: there are cables attached to it! It +is advised to flip the keyboard plastic part over, as shown on the picture +below. The write protect screw is located next to the SPI flash chip, circled +in red in the picture below. It has to be removed. Refer to the following +photos: + +[![Screws](https://av.libreboot.org/c201/screws.jpg)](https://av.libreboot.org/c201/screws.jpg) + +[![WP screw](https://av.libreboot.org/c201/wp-screw.jpg)](https://av.libreboot.org/c201/wp-screw.jpg) + +The write protect screw can be put back in place later, when the device +is known to be in a working state. + +External flashing +================= + +If the machine is no longer booting, due to bad firmware, you can unbrick +it externally. Refer to [external flash instructions](spi.md). + +[![SPI flash +layout](https://av.libreboot.org/c201/spi-flash-layout.jpg)](https://av.libreboot.org/c201/spi-flash-layout.jpg) + +[![Battery +connector](https://av.libreboot.org/c201/battery-connector.jpg)](https://av.libreboot.org/c201/battery-connector.jpg) + +You do not need to correct the `WP#` pin because it is held high via pull-up +resistor to 3.3v, when the write-protect screw is loosened (when tightened, +the screw grounds this pin; the pull-up resistor is to prevent a dead short). + +You must remove the battery, prior to flashing. The connector is shown in +the 2nd photo, above (the big black connector, with the black, green, yellow, +white and red wires going into it). Simply unplug that. diff --git a/site/docs/install/chromebooks.md b/site/docs/install/chromebooks.md new file mode 100644 index 0000000..de5c910 --- /dev/null +++ b/site/docs/install/chromebooks.md @@ -0,0 +1,201 @@ +--- +title: Chromebook flashing instructions +x-toc-enable: true +... + +NOTE: daisy, peach and veyron boards were temporarily removed from +lbmk. They should be re-added to Libreboot at a later date. The reasons +are written on the hardware compatibility page. For now, Libreboot only +officially supports the `gru` chromebooks. + +This page attempts to give a brief, general overview of how to flash +custom firmware on ChromeOS devices. This guide usually refers to all of +them as "Chromebook"s since it's the most common form factor. + +Flashrom +======== + +A special fork of flashrom, maintained by Google, is required for flashing +these Chromebook devices. See: + + + +You must then compile this from source, and run it. + +Enable ChromeOS "Developer Mode" +================================ + +Chromebooks are locked-down by default to only run ChromeOS. Most things +you will want to do on these require you unlock it by enabling their +[Developer Mode](https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_mode.md). +On most devices, you would press the `Escape + Refresh + Power` key +combination to restart into the Recovery Mode, then press `Ctrl + D` and +finally confirm enabling Developer Mode with `Enter`. + +On your next boot, it will show you an "OS Verification is disabled" +screen. Waiting for 30 seconds or pressing `Ctrl + D` on this screen will +proceed to boot into ChromeOS, which then erases all data on the device +and reboots again into a clean ChromeOS installation. + +With Developer Mode enabled, you can launch a terminal emulator inside +ChromeOS by pressing the `Ctrl + Alt + T` key combination. Run `shell` +inside the resulting `crosh` prompt to actually get to a `bash` session +where you can run programs. Most of the root file system is read-only, +except for `/usr/local` and any mounted drives under `/media/removable`. + +Identify your device +==================== + +It's more common to refer to ChromeOS boards by their codenames, and +many compatible devices can share a single codename. Libreboot ROM +images also use these, you should only use the one corresponding to your +device's. There are a number of ways to find it, some are: + +- Check the "Model" on the Recovery Mode or Developer Mode screens +- Visit `chrome://version` in ChromeOS and check the "Firmware Version" +- Run `crossystem hwid` or `crossystem fwid` in a terminal + +Back up stock firmware +====================== + +The stock firmware on your device comes with some irreplaceable data +that is unique to your device. This can include the serial number and +hardware ID of the device, network MAC address, HDCP keys, maybe more. +The stock firmware is also the only one that will properly boot and run +ChromeOS. + +Make sure you back up the original firmware before trying to replace it. +The version of flashrom in ChromeOS understands `host` as a programmer +to flash firmware internally. To back up stock firmware you can run: + + sudo flashrom -p host -r depthcharge.rom + sudo flashrom -p host -v depthcharge.rom + +Keep the resulting `depthcharge.rom` file safe and properly backed up on +another device. + +If you can already boot a conventional Linux distro on your Chromebook, +you may be able to use `flashrom -p linux_mtd` on that system instead. + +Check external flashability +=========================== + +If a ROM image you flash is broken, you may need to restore the stock +firmware to fix the board to get internal flashing working. Refer to the +[external flashing guide](spi.md), and check that the result of +`flashrom -r` matches what you get when you run it from the device. +Chromebooks may have 1.8V as the supply voltage for the SPI NOR chip, be +extra careful about that. + +On newer Chromebooks, there is a root-of-trust chip providing a +[Closed Case Debugging](https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md) +mechanism that lets you flash externally using a special USB debugging +cable. However, most boards that Libreboot supports do not have this. + +Disable write protection +======================== + +Chromebooks have the SPI flash chip partially write-protected by +default, but thankfully this protection can be disabled by the device +owner. How to do so depends on the board, refer to the +[ChromiumOS documentation on Write Protection](https://chromium.googlesource.com/chromiumos/docs/+/HEAD/write_protection.md) +for more info. You will usually need to do this only once for the +board's lifetime, unless you manually enable it again. + +On most boards that Libreboot supports, write-protection is enforced by +a physical screw. When screwed in, it forms an electrical connection +that asserts the WP pin on the flash chip. The screw can be identified +by the fact that it bridges electrical contacts, but finding and +removing it might require you to disassemble most of the board. + +Newer boards have a root-of-trust chip enforcing write-protection. The +[Closed Case Debugging](https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md) +mechanism should be used to disable hardware write-protection. Opening +the case and disconnecting the battery might also disable it. + +Disabling the write-protect signal doesn't directly make the chip stop +protecting its data, it just allows you to disable its write-protection +in software. That also needs to be done in ChromeOS afterwards: + + sudo flashrom -p host --wp-status + sudo flashrom -p host --wp-disable + sudo flashrom -p host --wp-range 0x0,0x0 + +The *--wp* arguments are only available on the +[ChromiumOS fork of flashrom](https://sites.google.com/a/chromium.org/dev/chromium-os/packages/cros-flashrom). +If you are using another OS or an external flasher, you may need to +compile and use that flashrom fork to disable write-protection. There is +no `lbmk` support yet for automatically building it. + +Prepare the ROM image +===================== + +Libreboot ROM image layouts are currently incompatible with the regions +that should be carried over from the stock firmware. However, the +released images should still be somewhat usable, since the Chromebooks +supported so far don't require any non-redistributable blobs to be +injected by the end user. + +Future Libreboot versions will likely require post-processing to +preserve irreplaceable data in the firmware image. For now, make sure to +keep backups of the original firmware. + +TODO: Instructions to preserve vital data when FMAPs are compatible. + +Flash the ROM image +=================== + +WARNING: Although none are supported yet, make sure not to flash ROM +images on x86 Chromebooks without injecting non-redistributable blobs +first (like Intel ME firmware). This is not yet documented here. + +You can flash the ROM image both internally and externally. For the +latter, see the [external flashing guide](spi.md) and the ChromiumOS +[Closed Case Debugging](https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md) +documentation if your board supports it. + +To flash the entire ROM image internally, run within ChromeOS: + + sudo flashrom -p host -w libreboot.rom + sudo flashrom -p host -v libreboot.rom + +If you can already boot a conventional Linux distro on your Chromebook, +you may be able to use `flashrom -p linux_mtd` on that system instead. + +Install an operating system (experimental research) +=========================== + +In general, ARM-compatible distros targeting U-boot can be used. There are +three general methods for installing that vary depending on the distribution: + +1. EFI - common u-boot methodology used by both arm64 and amd64 systems. +2. boot.scr - an older u-boot specific script used by some distributions. +3. extlinux.conf - a newer flat, bootloader-spec text file that typically lives + in /boot/extlinux/extlinux.conf + +Successful installations: +------------------------- + +* [ArchLinuxARM on RK3399-based Chromebooks](../uboot/uboot-archlinux.md). +* [Debian Bookworm on Samsung Chromebook Plus XE513C24](../uboot/uboot-debian-bookworm.md). +* [Debian on Asus Chromebook C201](https://wiki.debian.org/InstallingDebianOn/Asus/C201). + +Unsuccessful installations: +--------------------------- + +* [OpenBSD on Samsung Chromebook Plus XE513C24](../uboot/uboot-openbsd.md). + +Other promising ARM-compatible distros: +--------------------------------------- + +* [Armbian](https://www.armbian.com/uefi-arm64/). + +See also +======== + +* [ChromiumOS Documentation](https://chromium.googlesource.com/chromiumos/docs/+/HEAD/) +* [ChromiumOS Firmware Test Manual](https://chromium.googlesource.com/chromiumos/docs/+/HEAD/firmware_test_manual.md) +* [ChromiumOS Flashrom Fork Information](https://www.chromium.org/chromium-os/packages/cros-flashrom/) +* [MrChromebox's Unbricking Guide](https://wiki.mrchromebox.tech/Unbricking) +* [MrChromebox's Write-Protection Notes](https://wiki.mrchromebox.tech/Firmware_Write_Protect) +* [Coreboot Tutorial as used in ChromeOS](https://docs.google.com/presentation/d/1eGPMu03vCxIO0a3oNX8Hmij_Qwwz6R6ViFC_1HlHOYQ/preview) diff --git a/site/docs/install/d510mo.md b/site/docs/install/d510mo.md new file mode 100644 index 0000000..3c3f7de --- /dev/null +++ b/site/docs/install/d510mo.md @@ -0,0 +1,20 @@ +--- +title: D510MO flashing tutorial +... + +This guide is for those who want libreboot on their Intel D510MO +motherboard while they still have the original BIOS present. + +NOTE: D410PT is another designation and it's the same board. Flash the same ROM. + +Flash chip size {#flashchips} +=============== + +Use this to find out: + + flashrom -p internal + +Flashing instructions {#clip} +===================== + +Refer to [spi.md](spi.md) for how to re-flash externally. diff --git a/site/docs/install/d945gclf.md b/site/docs/install/d945gclf.md new file mode 100644 index 0000000..6dbdba4 --- /dev/null +++ b/site/docs/install/d945gclf.md @@ -0,0 +1,23 @@ +--- +title: Intel D945GCLF flashing tutorial +... + +NOTE: On newer Libreboot revisions, boot issues were reported so this board +was temporarily removed. It will be re-added at a later date, after testing +has been done. + +This guide is for those who want libreboot on their Intel D945GCLF +motherboard while they still have the original BIOS present. + +D945GCLF2D also reported working by a user. + +For information about this board, go to +[../hardware/d945gclf.md](../hardware/d945gclf.md) + +Flashing instructions {#clip} +===================== + +Refer to [spi.md](spi.md) for how to re-flash externally. + +Here is an image of the flash chip:\ +![](https://av.libreboot.org/d945gclf/d945gclf_spi.jpg) diff --git a/site/docs/install/e6400.md b/site/docs/install/e6400.md new file mode 100644 index 0000000..7a8d8fa --- /dev/null +++ b/site/docs/install/e6400.md @@ -0,0 +1,163 @@ +--- +title: Flashing the Dell Latitude E6400 +x-toc-enable: true +... + +Introduction +============ + +Initial flashing instructions for the E6400. DO NOT flash the Nvidia GPU +variant. This page pertains only to the Intel GPU variant. + +This guide is for those who want libreboot on their Latitude E6400 while +they still have the original Dell BIOS present. This guide can also be +followed (adapted) if you brick your E6400, and you want to recover it. + +This board can boot entirely blob-free in the flash. The hardware is similar +to that of ThinkPad X200, T400 etc where no-ME setup is possible. + +A note about GPUs +----------------- + +Models with Intel graphics are GM45, and fully supported in Libreboot +with native initialisation; ROM images are available since. +**The Intel video initialisation is libre, implemented with publicly available +source code via libgfxinit, from the coreboot project.** + +Flash chip size {#flashchips} +=============== + +Use this to find out: + + flashrom -p internal + +We believe most/all are 4MB (32Mb) flash sizes, but larger ROM images are +provided for people who wish to upgrade. + +MAC address {#macaddress} +=========== + +The MAC address is part of the ROM image that you're flashing. You can change +it at any time, before or after you've flashed Libreboot; you can also change +it in the *Dell* BIOS, if you really want to. This is for the onboard gigabit +ethernet device. + +Refer to [mac\_address.md](../hardware/mac_address.md). + +It is recommended that you run *nvmutil*. See: + +[nvmutil usage manual](nvmutil.md) + +The `nvmutil` software is specifically designed for changing MAC addresses, +and it implements a few more safeguards (e.g. prevents multicast/all-zero +MAC addresses) and features (MAC address randomisation, ability to correct or +intententionally corrupt(disable) GbE sections if you wish, swap GbE parts, +etc). You can *also* run ich9gen, if you wish: + +[ich9gen usage manual](ich9utils.md) + +Intel GPU: libre video initialisation available +=============================================== + +Libreboot uses coreboot's native `libgfxinit` on this platform, for +variants with Intel graphics. + +How to flash internally (no diassembly) +======================================= + +Warning for BSD users +--------------------- + +BSD *boots* and works properly on these machines, but take note: + +Nicholas's [e6400-flash-unlock](https://browse.libreboot.org/lbmk.git/plain/util/e6400-flash-unlock/e6400_flash_unlock.c) +utility has not yet been ported to BSD systems. The `flashrom` software is +available on BSD systems. Libreboot's build system has not yet been ported to +the BSDs. + +BSD users could run Linux from USB to run `flashrom` and `e6400-flash-unlock`. +Virtualisation is available in BSDs, where it should be feasible to run the +Libreboot build system, in Linux, under virtualisation. + +Flashing from Linux +------------------- + +MAKE SURE you boot with this Linux kernel parameter: `iomem=relaxed` - this +disables memory protections, permitting `/dev/mem` access needed by flashrom. +The flash is memory mapped and flashrom accesses it via `/dev/mem`. + +You can flash Libreboot directly from the vendor (Dell) BIOS, without taking +the machine apart. It can be done entirely from Linux. It will probably also +work on BSD systems, but it has only been testing on Linux thus far. + +Check `util/e6400-flash-unlock` in the `lbmk.git` repository, or releases. + +Go in there: + + cd util/e6400-flash-unlock + make + +With this program, you can unlock the flash in such a way where everything +is writeable. Information about how to use it is in the `README.md` file which +is included in that program's directory, or you can read it online here: + + + +Literally just run that program, and do what it says. You run it once, and shut +down, and when you do, the system brings itself back up automatically. Then +you run it and flash it unlocked. Then you run it again. The source code is +intuitive enough that you can easily get the gist of it; it's writing some EC +commands and changing some chipset config bits. The EC on this machine is +hooked up to the `GPIO33` signal, sometimes called `HDA_DOCK_EN`, which sets +the flash descriptor override thus disabling any flash protection by the IFD. +It also bypasses the SMM BIOS lock protection by disabling SMIs, and Dell's +BIOS doesn't set any other type of protection either such as writing to +Protected Range registers. + +When you flash it, you can use this command: + + flashrom -p internal -w libreboot.rom + +Where `libreboot.rom` is your E6400 ROM. *Make sure* it's the right one. +If flashrom complains about multiple flash chips detected, just pick one of +them (doesn't matter which one). On *most* Dell machines, the most correct +would probably be this option in flashrom: `-c MX25L3205D/MX25L3208D`. + +So: + + flashrom -p internal -w libreboot.rom -c MX25L3205D/MX25L3208D + +When you see flashrom say `VERIFIED` at the end, that means the flash was +successful. If you don't see that, or you're unsure, please [contact the +Libreboot project via IRC](../../contact.md). + +BACK UP THE FACTORY BIOS +======================== + +The `-w` option flashes `libreboot.rom`. You may consider *backing up* the +original Dell BIOS first, using the -r option: + + flashrom -p internal -r backup.rom -c MX25L3205D/MX25L3208D + +Do this while in a flashable state, after the 2nd run of `e6400-flash-unlock`. + +Make sure the `backup.rom` file gets backed up to an external storage media, +not the E6400 itself. + +With this method, you can probably flash it within 5 minutes. Again, zero +disassembly required! + +How to flash externally +========================= + +Refer to [spi.md](spi.md) as a guide for external re-flashing. + +The SPI flash chip shares a voltage rail with the ICH9 southbridge, which is +not isolated using a diode. As a result, powering the flash chip externally +causes the ICH9 to partially power up and attempt to drive the SPI clock pin +low, which can interfere with programmers such as the Raspberry Pi. See +[RPi Drive Strength](spi.md#rpi-drive-strength) for a workaround. + +Have a look online for videos showing how to disassemble, if you wish to +externally re-flash. + diff --git a/site/docs/install/ga-g41m-es2l.md b/site/docs/install/ga-g41m-es2l.md new file mode 100644 index 0000000..9a655ae --- /dev/null +++ b/site/docs/install/ga-g41m-es2l.md @@ -0,0 +1,70 @@ +--- +title: GA-G41M-ES2L flashing tutorial +x-toc-enable: true +... + +This guide is for those who want libreboot on their Intel GA-G41M-ES2L +motherboard while they still have the original BIOS present. + +MAC ADDRESS +=========== + +NOTE: due to a bug in the hardware, the MAC address is hardcoded in +coreboot. Therefore, you must set your own MAC address in your +operating system. + +Use [macchanger](http://www.gnu.org/software/macchanger) in your +distro, to set a valid MAC address. By doing this, your NIC should +work nicely. + +Flash chip size {#flashchips} +=============== + +Use this to find out: + + flashrom -p internal + +Flashing instructions {#clip} +===================== + +Refer to [spi.md](spi.md) for how to set up an SPI programmer for +external flashing. *You can only externally reprogram one of the chips +at a time, and you need to disable the chip that you're not flashing, +by connecting 3v3 to /CS of that chip, so you will actually need second test +clip or IC pin mini grabber.* + +NOTE: on GA-G41M-ES2L, the flash shares a common voltage plane with the +southbridge, which draws a lot of current. This will cause under-voltage on +most SPI flashers, so do not use the 3.3V rail from your flasher. Do not +connect +3.3V to the chip. Instead, turn the board on and then turn it off by +holding the power button. With the board powered down, but plugged in, there +will be a 3.3V supply from the ATX PSU. You can then flash, but DO NOT connect +the +3.3V supply from your SPI flasher! + +NOTE: You should use a resistor in series, between 1K to 10K ohms, for the 3.3v +connection to the CS pin. This is to protect from over-current. + +Here is an image of the flash chip:\ +![](https://av.libreboot.org/ga-g41m-es2l/ga-g41m-es2l.jpg) + +Internal flashing is possible. Boot with the proprietary BIOS and +Linux. There are 2 flash chips (one is backup). + +Flash the first chip: + + ./flashrom -p internal:dualbiosindex=0 -w libreboot.rom + +Flash the second chip: + + ./flashrom -p internal:dualbiosindex=1 -w libreboot.rom + +NOTE: you can still boot the system with just the main flash chip +connected, after desoldering the backup chip. This has been tested while +libreboot was already installed onto the main chip. + +NOTE: If you don't flash both chips, the recovery program from the default +factory BIOS will kick in and your board will be soft bricked. Make sure that +you flash both chips! + +NOTE: You need the latest flashrom. Just get it on flashrom.org from +their SVN or Git repos. diff --git a/site/docs/install/ich9utils.md b/site/docs/install/ich9utils.md new file mode 100644 index 0000000..8c170e7 --- /dev/null +++ b/site/docs/install/ich9utils.md @@ -0,0 +1,554 @@ +--- +title: ich9utils +x-toc-enable: true +... + +If all you want to do is change the MAC address, you might use `nvmutil` +instead. See: [nvmutil documentation](../install/nvmutil.md). + +Introduction +============ + +The `ich9utils` utility from Libreboot is used to manipulate Intel Flash +Descriptors for ICH9M on laptops such as ThinkPad X200 or T400. Specifically, +the `ich9gen` utility can generate 12KiB descriptor+GbE files for inserting +into the start of a ROM, where everything after that is the BIOS region. These +are special descriptors with the Intel ME region disabled, and Intel ME itself +fully disabled. + +ich9utils is handled by the `lbmk` (libreboot-make) build system, but the code +itself is hosted in a separate repository. You can check the Git repositories +linked on [../../git.md](../../git.md) if you wish to download and use it. + +It is very *uncommon*, on GM45/ICH9M systems, to have an Intel Flash Descriptor +and GbE but *without* an Intel ME. On *most* of these systems (without libreboot, +Libreboot or coreboot), there is either descriptor+GbE+ME+BIOS or just BIOS, +where on systems with just the BIOS region an Intel GbE NIC is not present. +In libreboot (and Libreboot), we provide descriptor+GbE images with Intel ME +disabled and not present in the ROM; this enables the Intel GbE NIC to be used, +while not having an Intel ME present. A consequence of this is that the +malicious features of ME (such as AMT) are not present, however the Intel ME +also handles TPM which is therefore disabled in this setup. + +NOTE: If you accidentally flash a ROM *without* descriptor+GbE, it will still +work but the Intel GbE NIC will be dysfunctional. If you do that, just boot up +and correct the problem (and you can use a USB/cardbus/expresscard NIC or WiFi +for internet if necessary). That is the *main reason* why `ich9utils` was +written in the first place; it was already very possible to boot without an +Intel ME by simply not having a descriptor or anything in ROM, just coreboot. +The purpose of `ich9gen` specifically is to get the Intel GbE NIC working but +without the Intel ME being enabled! + +ICH9 based systems were the last generation that could be booted *without* an +Intel ME. Future platforms (such as Sandybridge and Ivybridge) require an +Intel ME since the ME on those platforms also handles power management and +some minor initialization functions. On ICH9 based systems (such as X200 or +T400) the Intel ME only handles AMT and TPM, and there's no 30 minute timer +(if you boot later platforms without an Intel ME and descriptor, or invalid +Intel ME firmware, the system will either not boot or will turn off after 30 +minutes per a watchdog reset timer). + +More information about the ME can be found at + and +. + +Another project: + +ich9utils +========= + +You can find `ich9utils` on the [Git page](../../git.md) or you can download +`lbmk` from the same page and run the following command in there: + + ./build module ich9utils + +You may also find it in the source code tar archives, on releases. + +In `lbmk`, you can use the following command to generate descriptors: + + ./build descriptors ich9m + +The libreboot build system will use the descriptors under `descriptors/ich9m` +when building ROM images for these machines. + +Alternatively, you can just clone `ich9utils` directly and run `make` in the +directory, and run the `ich9gen` program directly. + +ICH9 show utility {#ich9show} +================ + +The *ich9show* utility outputs the entire contents of the descriptor and GbE +regions in a given ROM image as supplied by the user. Output is in Markdown +format (Pandoc variant) so that it can be converted easily into various +formats. It could even be piped *directly* into pandoc! + +ICH9 gen utility {#ich9gen} +================ + +When you simply run `ich9gen` without any arguments, it generates +descriptor+GbE images with a default MAC address in the GbE region. If you wish +to use a custom macaddress, you can supply an argument like so: + + ich9gen --macaddress 00:1f:16:80:80:80 + +The above MAC address is just an example. It is recommended that you use the +MAC address officially assigned to your NIC. + +Three new files will be created: + +- `ich9fdgbe_4m.bin`: this is for GM45 laptops with the 4MB flash + chip. +- `ich9fdgbe_8m.bin`: this is for GM45 laptops with the 8MB flash + chip. +- `ich9fdgbe_16m.bin`: this is for GM45 laptops with the 16MB flash + chip. + +These files contain the descriptor+GbE region and are suitable for systems +that have an Intel GbE NIC present. The flash regions (as defined by the +Intel Flash Descriptor) are set *read-write* which means that you can also +re-flash using `flashrom -p internal` in your operating system running on +that machine. This is the default setup used when libreboot's build system +compiles ROM images. + +Alternative versions of these files are also created, which have `ro` in the +filename. If you use *those* versions, all flash regions (as defined by the +Intel Flash Descriptor) will be set to *read only*. This can be useful, for +security purposes, if you wish to ensure that malicious software in your +operating system cannot simply re-flash new firmware. + +The region setup created by these descriptors is as follows: + +* First 4KiB of flash is: Intel Flash Descriptor +* Next 8KiB after Descriptor: Intel GbE region +* Rest of the flash, after GbE: BIOS region (BIOS region will have libreboot) + +The GbE region contains configuration data for your Intel GbE NIC. You can +find information about this in Intel datasheets, and it is very well described +in the `ich9utils` source code. + +Assuming that your libreboot image is named **libreboot.rom**, copy the +file to where **libreboot.rom** is located and then insert the +descriptor+gbe file into the ROM image. + +For 16MiB flash chips: + + dd if=ich9fdgbe_16m.bin of=libreboot.rom bs=12k count=1 conv=notrunc + +For 8MiB flash chips: + + dd if=ich9fdgbe_8m.bin of=libreboot.rom bs=12k count=1 conv=notrunc + +For 4MiB flash chips: + + dd if=ich9fdgbe_4m.bin of=libreboot.rom bs=12k count=1 conv=notrunc + +If you wish to have read-only flash (write protected flash), substitute the +above examples with descriptor+GbE images that have `ro` in the filename. RO +here means *read only*, not *Romania*! + +The above commands assume that in coreboot you have specified the CBFS size +as no more than the size of the flash, minus 12KiB. + +NOTE: `ich9gen` also generates descriptors without a GbE region, where in +those descriptors the Intel GbE is not specified. Those are highly experimental, +and *theoretical* since no such system exists in the wild where ICH9 is used, +no Intel GbE NIC present *and* descriptor present; on such systems, the vendor +will just supply a descriptor-less setup. Those GbE-less descriptor images +created by `ich9gen` are only 4KiB in size, and should *never be used* except +for fun, like, basically shits and/or giggles. + +For shits and giggles, R500 ROM images in libreboot use these no-GbE descriptor +images generated by ich9gen. However, a descriptorless setup would also work +just fine. ThinkPad R500 doesn't have an Intel PHY in it, and it instead uses +a Broadcom NIC for ethernet. In descriptorless mode, ICH9M works very similarly +to older ICH7 chipsets. + +Your libreboot.rom image is now ready to be flashed on the system. Refer +back to [../install/\#flashrom](../install/#flashrom) for how to flash +it. + +Write-protecting the flash chip +------------------------------- + +The `ich9gen` utility (see below) generates two types of descriptor+GbE setup: + +* read-write +* read-only + +Read on for more information. Use the `ro` files mentioned below, and your +flash will be read-only in software (you can still externally re-flash and read +the contents of flash). + +For ease of use, libreboot provides ROMs that are read-write by default. In +practise, you can boot a Linux kernel with access to lower memory disabled +which will make software re-flashing impossible (unless you reboot with such +memory protections disabled, e.g. `iomem=relaxed` kernel parameter). + +ICH9 deblob utility {#ich9deblob} +=================== + +This was the tool originally used to disable the ME on X200 (later +adapted for other systems that use the GM45 chipset). +[ich9gen](#ich9gen) now supersedes it; ich9gen is better because it does +not rely on dumping the factory.rom image (whereas, ich9deblob does). + +Simply speaking, `ich9deblob` takes an original dump of the boot flash, where +that boot flash contains a descriptor that defines the existence of Intel ME, +and modifies it. The Intel Flash Descriptor is modified to disable the ME +region. It disables the ME itself aswell. The GbE region is moved to the +location just after the descriptor. The BIOS region is specified as being +after the descriptor+GbE regions, filling the rest of the boot flash. + +The GbE region is largely unedited when using this utility. + +Run it like so, with `factory.rom` in the same directory: + + ./ich9deblob + +The `factory.rom` file is your dump of the vendor boot flash. Older versions +of this utility have this file name hardcoded, and for compatibility reasons +it will still work in this manner. However, you can now specify your own file +name. + +For example: + + ./ich9deblob lenovo.rom + +A 12kiB file named **deblobbed\_descriptor.bin** will now appear. **Keep +this and the factory.rom stored in a safe location!** The first 4KiB +contains the descriptor data region for your system, and the next 8KiB +contains the gbe region (config data for your gigabit NIC). These 2 +regions could actually be separate files, but they are joined into 1 +file in this case. + +A 4KiB file named **deblobbed\_4kdescriptor.bin** will alternatively +appear, if no GbE region was detected inside the ROM image. This is +usually the case, when a discrete NIC is used (eg Broadcom) instead of +Intel. Only the Intel NICs need a GbE region in the flash chip. + +Assuming that your libreboot image is named **libreboot.rom**, copy the +**deblobbed\_descriptor.bin** file to where **libreboot.rom** is located +and then run: + + dd if=deblobbed_descriptor.bin of=libreboot.rom bs=12k count=1 conv=notrunc + +Alternatively, if you got a the **deblobbed\_4kdescriptor.bin** file (no +GbE defined), do this: + + dd if=deblobbed_4kdescriptor.bin of=libreboot.rom bs=4k count=1 conv=notrunc + +(it's very unlikely that you would ever see this. Descriptor without GbE is +very rare, probably non-existant, but theoretically possible and this functionality +is implemented based on Intel datasheets) + +The utility will also generate 4 additional files: + +* `mkdescriptor.c` +* `mkdescriptor.h` +* `mkgbe.c` +* `mkgbe.h` + +These are *self-written* by `ich9deblob`. The `ich9gen` utility was created, +based on this very functionality, with some tweaks made afterwards. + +These are C source files that can re-generate the very same Gbe and +Descriptor structs (from ich9deblob/ich9gen). To use these, place them +in src/ich9gen/ in ich9deblob, then re-build. The newly +build `ich9gen` executable will be able to re-create the very same 12KiB +file from scratch, based on the C structs, this time **without** the +need for a` factory.rom` dump! + +You should now have a **libreboot.rom** image containing the correct 4K +descriptor and 8K gbe regions, which will then be safe to flash. Refer +back to [index.md/\#gm45](index.md/#gm45) for how to flash +it. + +demefactory utility {#demefactory} +=================== + +This utility has never been tested, officially, but it *should* work. + +This takes a `factory.rom` dump and disables the ME/TPM, but leaves the +region intact. It also sets all regions read-write. Simply put, this means +that you can use the original factory firmware but without the Intel ME enabled. + +The ME interferes with flash read/write in flashrom, and the default +descriptor locks some regions. The idea is that doing this will remove +all of those restrictions. + +Simply run (with `factory.rom` in the same directory): + + ./demefactory + +It will generate a 4KiB descriptor file (only the descriptor, no GbE). +Insert that into a factory.rom image (NOTE: do this on a copy of it. +Keep the original factory.rom stored safely somewhere): + + dd if=demefactory_4kdescriptor.bin of=factory_nome.rom bs=4k count=1 conv=notrunc + +Use-case: a factory.rom image modified in this way would theoretically +have no flash protections whatsoever, making it easy to quickly switch +between factory/libreboot in software, without ever having to +disassemble and re-flash externally unless you brick the device. + +The sections below are adapted from (mostly) IRC logs related to early +development getting the ME removed on GM45. They are useful for +background information. This could not have been done without sgsit's +help. + +Early notes {#early_notes} +----------- + +- + page 230 mentions about descriptor and non-descriptor mode (which + wipes out gbe and ME/AMT). +- ~~**See reference to HDA\_SDO (disable descriptor security)**~~ + strap connected GPIO33 pin is it on ICH9-M (X200). HDA\_SDO applies + to later chipsets (series 6 or higher). Disabling descriptor + security also disables the ethernet according to sgsit. sgsit's + method involves use of 'soft straps' (see IRC logs below) instead + of disabling the descriptor. +- **and the location of GPIO33 on the x200s: (was an external link. + Putting it here instead)** + [https://av.libreboot.org/x200/gpio33_location.jpg](https://av.libreboot.org/x200/gpio33_location.jpg) - + it's above the number 7 on TP37 (which is above the big intel chip + at the bottom) +- The ME datasheet may not be for the mobile chipsets but it doesn't + vary that much. This one gives some detail and covers QM67 which is + what the X201 uses: + + +Flash chips {#flashchips} +----------- +- X200 laptop (Mocha-1): + ICH9-M overrides ifd permissions with a strap connected to GPIO33 pin (see IRC notes below) + + - The X200 can be found with any of the following flash + chips: + - ATMEL AT26DF321-SU 72.26321.A01 - this is a 32Mb (4MiB) chip + - MXIC (Macronix?) MX25L3205DM2I-12G 72.25325.A01 - another 32Mb + (4MiB) chip + - MXIC (Macronix?) MX25L6405DMI-12G 41R0820AA - this is a 64Mb + (8MiB) chip + - Winbond W25X64VSFIG 41R0820BA - another 64Mb (8MiB) chip + + sgsit says that the X200s (Pecan-1) with the 64Mb flash chips are (probably) + the ones with AMT (alongside the ME), whereas the 32Mb chips contain + only the ME. + +Early development notes {#early_development_notes} +----------------------- + +``` +Start (hex) End (hex) Length (hex) Area Name +----------- --------- ------------ --------- +00000000 003FFFFF 00400000 Flash Image + +00000000 00000FFF 00001000 Descriptor Region +00000004 0000000F 0000000C Descriptor Map +00000010 0000001B 0000000C Component Section +00000040 0000004F 00000010 Region Section +00000060 0000006B 0000000C Master Access Section +00000060 00000063 00000004 CPU/BIOS +00000064 00000067 00000004 Manageability Engine (ME) +00000068 0000006B 00000004 GbE LAN +00000100 00000103 00000004 ICH Strap 0 +00000104 00000107 00000004 ICH Strap 1 +00000200 00000203 00000004 MCH Strap 0 +00000EFC 00000EFF 00000004 Descriptor Map 2 +00000ED0 00000EF7 00000028 ME VSCC Table +00000ED0 00000ED7 00000008 Flash device 1 +00000ED8 00000EDF 00000008 Flash device 2 +00000EE0 00000EE7 00000008 Flash device 3 +00000EE8 00000EEF 00000008 Flash device 4 +00000EF0 00000EF7 00000008 Flash device 5 +00000F00 00000FFF 00000100 OEM Section +00001000 001F5FFF 001F5000 ME Region +001F6000 001F7FFF 00002000 GbE Region +001F8000 001FFFFF 00008000 PDR Region +00200000 003FFFFF 00200000 BIOS Region + +Start (hex) End (hex) Length (hex) Area Name +----------- --------- ------------ --------- +00000000 003FFFFF 00400000 Flash Image + +00000000 00000FFF 00001000 Descriptor Region +00000004 0000000F 0000000C Descriptor Map +00000010 0000001B 0000000C Component Section +00000040 0000004F 00000010 Region Section +00000060 0000006B 0000000C Master Access Section +00000060 00000063 00000004 CPU/BIOS +00000064 00000067 00000004 Manageability Engine (ME) +00000068 0000006B 00000004 GbE LAN +00000100 00000103 00000004 ICH Strap 0 +00000104 00000107 00000004 ICH Strap 1 +00000200 00000203 00000004 MCH Strap 0 +00000ED0 00000EF7 00000028 ME VSCC Table +00000ED0 00000ED7 00000008 Flash device 1 +00000ED8 00000EDF 00000008 Flash device 2 +00000EE0 00000EE7 00000008 Flash device 3 +00000EE8 00000EEF 00000008 Flash device 4 +00000EF0 00000EF7 00000008 Flash device 5 +00000EFC 00000EFF 00000004 Descriptor Map 2 +00000F00 00000FFF 00000100 OEM Section +00001000 00002FFF 00002000 GbE Region +00003000 00202FFF 00200000 BIOS Region + +Build Settings +-------------- +Flash Erase Size = 0x1000 +``` + +It's a utility called 'Flash Image Tool' for ME 4.x that was used for +this. You drag a complete image into in and the utility decomposes the +various components, allowing you to set soft straps. + +This tool is proprietary, for Windows only, but was used to deblob the +X200. End justified means, and the utility is no longer needed since the +ich9deblob utility (documented on this page) can now be used to create +deblobbed descriptors. + +GBE (gigabit ethernet) region in SPI flash {#gbe_region} +------------------------------------------ + +Of the 8K, about 95% is 0xFF. The data is the gbe region is fully +documented in this public datasheet: + + +The only actual content found was: + +``` +00 1F 1F 1F 1F 1F 00 08 FF FF 83 10 FF FF FF FF +08 10 FF FF C3 10 EE 20 AA 17 F5 10 86 80 00 00 +01 0D 00 00 00 00 05 06 20 30 00 0A 00 00 8B 8D +02 06 40 2B 43 00 00 00 F5 10 AD BA F5 10 BF 10 +AD BA CB 10 AD BA AD BA 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 01 00 40 28 12 07 40 FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF D9 F0 +20 60 1F 00 02 00 13 00 00 80 1D 00 FF 00 16 00 +DD CC 18 00 11 20 17 00 DD DD 18 00 12 20 17 00 +00 80 1D 00 00 00 1F +``` + +The first part is the MAC address set to all 0x1F. It's repeated haly +way through the 8K area, and the rest is all 0xFF. This is all +documented in the datasheet. + +The GBe region starts at 0x20A000 bytes from the \*end\* of a factory +image and is 0x2000 bytes long. In libreboot (deblobbed) the descriptor +is set to put gbe directly after the initial 4K flash descriptor. So the +first 4K of the ROM is the descriptor, and then the next 8K is the gbe +region. + +### GBE region: change MAC address {#gbe_region_changemacaddress} + +According to the datasheet, it's supposed to add up to 0xBABA but can +actually be others on the X200. + + +*"One of those engineers loves classic rock music, so they selected +0xBABA"* + +In honour of the song *Baba O'Reilly* by *The Who* apparently. We're +not making this stuff up... + +0x3ABA, 0x34BA, 0x40BA and more have been observed in the main Gbe +regions on the X200 factory.rom dumps. The checksums of the backup +regions match BABA, however. We think `0xBABA` is the only correct checksum, +because those other, similar checksums were only ever found in the "backup" +GbE regions on factory ROM dumps. In libreboot, we simply use `0xBABA` and +ensure that both 4KiB regions in GbE NVM have that checksum. + +By default, the X200 (as shipped by Lenovo) actually has an invalid main +gbe checksum. The backup gbe region is correct, and is what these +systems default to. Basically, you should do what you need on the +\*backup\* gbe region, and then correct the main one by copying from the +backup. + +Look at `ich9deblob.c` in ich9utils. + +- Add the first 0x3F 16bit numbers (unsigned) of the GBe descriptor + together (this includes the checksum value) and that has to add up + to 0xBABA. In other words, the checksum is 0xBABA minus the total of + the first 0x3E 16bit numbers (unsigned), ignoring any overflow. + +Flash descriptor region {#flash_descriptor_region} +----------------------- + + +from page 850 onwards. This explains everything that is in the flash +descriptor, which can be used to understand what libreboot is doing +about modifying it. + +How to deblob: + +- patch the number of regions present in the descriptor from 5 - 3 +- originally descriptor + bios + me + gbe + platform +- modified = descriptor + bios + gbe +- the next stage is to patch the part of the descriptor which defines + the start and end point of each section +- then cut out the gbe region and insert it just after the region +- all this can be substantiated with public docs (ICH9 datasheet) +- the final part is flipping 2 bits. Halting the ME via 1 MCH soft + strap and 1 ICH soft strap +- the part of the descriptor described there gives the base address + and length of each region (bits 12:24 of each address) +- to disable a region, you set the base address to 0xFFF and the + length to 0 +- and you change the number of regions from 4 (zero based) to 2 + +There's an interesting parameter called 'ME Alternate disable', which +allows the ME to only handle hardware errata in the southbridge, but +disables any other functionality. This is similar to the 'ignition' in +the 5 series and higher but using the standard firmware instead of a +small 128K version. Useless for libreboot, though. + +To deblob GM45, you chop out the platform and ME regions and correct the +addresses in flReg1-4. Then you set meDisable to 1 in ICHSTRAP0 and +MCHSTRAP0. + +How to patch the descriptor from the factory.rom dump + +- map the first 4k into the struct (minus the gbe region) +- set NR in FLMAP0 to 2 (from 4) +- adjust BASE and LIMIT in flReg1,2,3,4 to reflect the new location of + each region (or remove them in the case of Platform and ME) +- set meDisable to 1/true in ICHSTRAP0 and MCHSTRAP0 +- extract the 8k GBe region and append that to the end of the 4k + descriptor +- output the 12k concatenated chunk +- Then it can be dd'd into the first 12K part of a coreboot image. +- the GBe region always starts 0x20A000 bytes from the end of the ROM + +This means that libreboot's descriptor region will simply define the +following regions: + +- descriptor (4K) +- gbe (8K) +- bios (rest of flash chip. CBFS also set to occupy this whole size) + +The data in the descriptor region is little endian, and it represents +bits 24:12 of the address (bits 12-24, written this way since bit 24 is +nearer to left than bit 12 in the binary representation). + +So, *x << 12 = address* + +If it's in descriptor mode, then the first 4 bytes will be 5A A5 F0 0F. + +platform data partition in boot flash (factory.rom / lenovo bios) {#platform_data_region} +----------------------------------------------------------------- + +Basically useless for libreboot, since it appears to be a blob. Removing +it didn't cause any issues in libreboot. We think it's just random data that +the manufacturer can put there, to use in their firmware. Intel datasheets seem +to suggest that the platform region serves no specific function except to +provide a region in flash for the hardware manufacturer to use, for whatever +purpose (probably just to store other configuration data, to be used by software +running from the BIOS region as per region layout specified in the descriptor). + +This is a 32K region from the factory image. It could be data +(non-functional) that the original Lenovo BIOS used, but we don't know. + +It has only a 448 byte fragment different from 0x00 or 0xFF, on the X200 +thinkpads that were tested. diff --git a/site/docs/install/index.md b/site/docs/install/index.md new file mode 100644 index 0000000..38d6b8e --- /dev/null +++ b/site/docs/install/index.md @@ -0,0 +1,609 @@ +--- +title: Installation instructions +x-toc-enable: true +... + +This section relates to installing libreboot on supported targets. + +NOTE: if running `flashrom -p internal` for software based flashing, and you +get an error related to `/dev/mem` access, you should reboot with +`iomem=relaxed` kernel parameter before running flashrom, or use a kernel that +has `CONFIG_STRICT_DEVMEM` not enabled. + +PRECAUTIONS +=========== + +libreboot flashing can be risky business. Please ensure that you have external +flashing equipment, in case anything goes wrong. The general rule of thumb with +firmware is this: if it's non-free, replace it, but if you're already running +free firmware and it works nicely for you, you do not need to update it. +However, you might want to tweak it or try out newer releases of libreboot if +they have bug fixes for your board, and/or new security fixes. + +If you're already running libre firmware on your board, you should decide for +sure whether you wish to risk it. See changelogs on +the [release announcements via the news page](/news/) and decide for yourself. + +About ROM image file names +========================== + +Init types and display mode +--------------------------- + +NOTE: regardless of init type, on desktops, an external/add-on GPU can always +be used. On laptop hardware in libreboot, libgfxinit will always be used. On +desktop/server hardware, if available, libgfxinit will also always be used by +default (but in that setup, SeaBIOS can be used if you want to use an add-on +graphics card, e.g. on KCMA-D8, KGPE-D16, GA-G41M-ES2L) + +**This means that on desktop hardware such as KCMA-D8, KGPE-D16, G43T-AM3, +GA-G41M-ES2L and others, you can use either the internal GPU or an add-on +PCI-E graphics card. Simply use a ROM image that starts with SeaBIOS, and you +can use both. On desktop/server hardware, libgfxinit simply means that you +CAN use the internal graphics chip, but you don't have to; external add-on +GPUs will also still work! However, if libgfxinit is enabled, that disables +coreboot from loading/executing PCI option ROMs which means you MUST use SeaBIOS +if you wish to use the add-on cards!** + +### libgfxinit + +In this setup, on supported systems, coreboot's own native video initialization +code is used. This is referred to generically as libgfxinit, which is coreboot's +library in `3rdparty/libgfxinit` but not all boards with native video +initialization use libgfxinit; some of them are using coreboot's older style +of video initialization method, written purely in C. + +#### corebootfb (libgfxinit) + +high resolution coreboot framebuffer used on startup + +#### txtmode (libgfxinit) + +int10h text mode is used on startup. + +### vgarom + +NOTE: no configs in libreboot are currently available that use this method. + +With this method, coreboot is finding, loading and executing a VGA option ROM +for your graphics hardware. This would not be done on laptops, because that +implies supplying non-free binary blobs in libreboot, so this setup would only +ever be provided on desktop hardware where no GPU exists or where it is +desirable for you to use an external/add-on graphics card + +#### vesafb (vgarom) + +high resolution VESA framebuffer used on startup. This is equivalent +to `corebootfb` (high resolution framebuffer), but for setups where a VGA +Option ROM is used. + +#### txtmode (vgarom) + +int10h text mode is used on startup + +### normal + +int10h text mode startup is implied here. The `vesafb` mode is unavailable here. +For `vesafb` mode, please use init type `vgarom`; most useful for GRUB payloads +or perhaps Tianocore. + +In this setup, coreboot is neither implementing libgfxinit / native graphics +initialization nor is it finding/loading/executing VGA option ROMs. In this +setup, SeaBIOS would most likely be used for that. + +The `normal` setup is supported in the libreboot build system, but not +currently used. It is there for desktop hardware that will be added in the +future, where those desktop boards do not have an onboard GPU and therefore an +add-on GPU is always used.. + +Payload names +------------- + +### grub + +ROM images with just `grub` in the file name will start first with the GRUB +payload. They may or may not also provide other payloads in the menu, such as +memtest86+, SeaBIOS, Tianacore and so on. + +### seabios + +ROM images with just `seabios` in the file name will start first with the +SeaBIOS payload. They will only contain SeaBIOS, but may also contain memtest as +an option in the boot menu. + +### seabios\_withgrub + +ROM images that have `seabios_withgrub` in the file name start with SeaBIOS +first, but also have GRUB available in the boot menu when you press ESC. + +### seabios\_grubfirst (DEFUNCT) + +**DEFUNCT** + +This build option is obsolete, and should not be used. It was deleted +in lbmk revision `e1bbdadc9584291cf062660d67128e9f17ab788e`. + +It was believed, in earlier theory, that VGA ROM initialisation could +be used in SeaBIOS and then SeaBIOS boots into a GRUB payload (built +for coreboot), where the initialisation would continue to be used, but +it didn't work that way. + +It's best to use PC GRUB (normal BIOS GRUB), but compile it into a floppy +image to insert inside CBFS, to then be executed by SeaBIOS. This is referred +to as SeaGRUB by the Libreboot project, and it would be quite useful +for desktop users, but it's largely irrelevant on laptops where +coreboot's own `libgfxinit` is usually available (or the option ROM is +easy to extract from vendor firmware and insert). + +Where direct bare metal GRUB is desired, but you use a desktop system with +an add-on graphics card, you must extract the VGA ROM for your card and +insert it into the coreboot ROM, for coreboot itself to execute. This will +require custom configuration on your part, and it is thus beyond the scope +of the Libreboot project, in context of lbmk (automated build system). + +Some older Libreboot releases included ROM images built using this option, +and those specific ROM images (`seabios_grubfirst` ones) should not be +used; you should only use `seabios_grubfirst` or `seabios`, in most +scenarios, if SeaBIOS is required. + +For most desktop users, if running an external graphics card, it's easier +to simply boot in text mode with a SeaBIOS payload and use only that. This +will Just Work with almost all graphics cards, allowing you to use an +operating system with a full display and (drivers permitting) full 2D/3D +acceleration. + +Which systems are supported? +============================ + +[Refer to the hardware compatibility page](../hardware/) + +Install via host CPU (internal flashing) +======================================== + +On all mainboards is a built-in programmer, which can read, erase and rewrite +the boot flash. However, it is not always usable by default. For example, it +may be configured to restrict write privileges by the host CPU. + +In some situations, the host CPU can rewrite/erase/dump the boot flash. +This is called *internal flashing*. This means that you will run software, +namely `flashrom`, to read/erase/write the contents of the boot flash from a +running operating system on the target device. + +NOTE: please also read the sections further down this page. On some systems, +external flashing is required. This means that you power the system down and +use a special tool that connects to and reprograms the boot flash. + +NOTE: in some cases, external flashing is possible but special steps are +required. This depends on your mainboard. Again, please read this page +carefully. + +Run flashrom on host CPU +------------------------ + +You can simply take any ROM image from the libreboot project, and flash it. +Boot a Linux distribution on the target device, and install flashrom. + +In some cases, this is not possible or there are other considerations. Please +read this section *carefully*. + +### Flash chip size + +Use this to find out: + + flashrom -p internal + +In the output will be information pertaining to your boot flash. + +### Howto: read/write/erase the boot flash + +How to read the current chip contents: + + sudo flashrom -p internal:laptop=force_I_want_a_brick,boardmismatch=force -r dump.bin + +You should still make several dumps, even if you're flashing internally, to +ensure that you get the same checksums. Check each dump using `sha1sum` + +How to erase and rewrite the chip contents: + + sudo flashrom -p internal:laptop=force_I_want_a_brick,boardmismatch=force -w libreboot.rom + +If you are re-flashing a GM45+ICH9M laptop (e.g. ThinkPad X200/X200S/X200T, +T400, T500, R400, W500 etc - but not R500), you should run the ich9gen utility +to preserve your mac address. +Please read the ich9utils documentation: +[/docs/install/ich9utils.html](/docs/install/ich9utils.html) + +NOTE: `force_I_want_a_brick` is not scary. Do not be scared! This merely disables +the safety checks in flashrom. Flashrom and coreboot change a lot, over the years, +and sometimes it's necessary to use this option. If you're scared, then just +follow the above instructions, but remove that option. So, just use `-p internal`. +If that doesn't work, next try `-p internal:boardmismatch=force`. If that doesn't +work, try `-p internal:boardmismatch=force,laptop=force_I_want_a_brick`. So long +as you *ensure* you're using the correct ROM for your machine, it will be safe +to run flashrom. These extra options just disable the safetyl checks in flashrom. +There is nothing to worry about. + +If successful, it will either say `VERIFIED` or it will say that the chip +contents are identical to the requested image. + +NOTE: there are exceptions where the above is not possible. Read about them in +the sections below: + +### Exceptions + +#### If your boot flash is currently write-protected + +[You must flash it externally](spi.md) + +#### DELL Latitute E6400 laptop (easy to flash, similar to X200/T400) + +See: [Dell Latitute E6400 Libreboot Installation Guide](e6400.md) + +#### ThinkPad X200/T400/T500/W500/R400/R500 vendor BIOS + +If you're running one of these, it cannot be flashed internally if you're still +running the non-free Lenovo BIOS firmware. + +[You must flash it externally](spi.md) + +See notes further down on this page. We have guides for specific thinkpads, +related to disassembly and reassembly so that you can access the flash. + +Please also see notes about the built-in MAC address inside the boot flash, for +the onboard NIC (ethernet one); not relevant on R500, which doesn't use an +Intel NIC. + +#### Intel D510MO and D410PT running non-free Intel BIOS + +[You must flash it externally](spi.md) + +D410PT is more or less the same board as D510MO, but we would like more info +about this board. If you have a D410PT mainboard, please contact the libreboot +project via IRC and ping `leah` before you flash it. When you do so, please +reference this paragraph on this web page. + +#### Gigabyte GA-G41M-ES2l (any firmware) + +Ignore this section. Internal flashing *is* possible, but there are two chips +and you must flash both chips. Refer to the guide:\ +[Gigabyte GA-G41M-ES2L installation guide](ga-g41m-es2l.html) + +#### Macbook1,1 running non-free Apple EFI firmware + +This laptop requires external flashing. Remove the mainboard and refer to +the [external flashing guide](spi.md); if libreboot is already running, you +can flash internally. + +MacBook2,1 can be flashed internally. + +#### ASUS KFSN4-DRE? + +Simply boot Linux with the default vendor firmware, and flash it internally, +but before you do: take a push pin, remove the metal pin, and superglue the +plastic part to the chip. Then remove the chip after you booting your +Linux system. Install a new chip, and flash *that*. + +This board uses LPC flash in a PLCC32 socket. This coreboot page shows an +example of the push pin as a proof of concept: + + +#### ASUS KGPE-D16 running non-free ASUS BIOS + +[You must flash it externally](spi.md) + +#### ASUS KCMA-D8 running non-free ASUS BIOS + +[You must flash it externally](spi.md) + +#### ASUS D945GCLF running non-free Intel BIOS + +[You must flash it externally](spi.md) + +#### ThinkPad X60/X60S/X60T/T60 with Lenovo BIOS {#flashrom_lenovobios} + +NOTE: If BIOS password auth is enabled, you can clear it by shorting pins on +an EEPROM and then resetting the password in Lenovo BIOS, prior to flashing +Libreboot. For T60, see: + +(TODO: link something here for X60) + +X60 BIOS password (Lenovo): you might find info here: + + +You can just get bucts from the libreboot project, same thing for the patched +flashrom. In the Libreboot 20160907 release, there is a *utility* archive, which +has statically compiled executables. They still work just fine on modern +systems, and they can be used for this purpose. + +Here are a list of targets: + +* ThinkPad X60/X60S/X60T: flash the X60 ROM +* ThinkPad T60 with Intel GPU: flash the T60 ROM +* ThinkPad T60 with ATI GPU: flash the Headless T60 ROM (no video init, but you + can get a serial console on the RS232 port if you use the Advanced Dock or + Advanced Mini Dock. Connect to it from another machine, using null modem + cable and USB serial adapter; *Screen* can connect to the serial console + and you will run it at 115200 baud rate. agetty/fgetty in Linux can give + you a serial console in your OS) + +Download and build flashrom, using the instructions +on [the Git page](../../git.md), and download the `bucts` software using the +notes on that very same page. + +You can replace Lenovo BIOS with libreboot, using flashrom running on the host +CPU. However, there are some considerations. + +Firstly, make sure that the yellow CMOS battery is installed, and functioning +correctly. You could check the voltage. The battery is a CR2032 +coin cell and it *should* be providing a 3V signal. You should check this while +it is connected to the board, because this will give a more accurate reading +(if the battery is weak, it will have severe voltage drop when there is any +load on it, which there will be. This coincell powers the real-time clock and +CMOS memory). + +Lenovo BIOS restricts write access, but there is a weakness in it. With a +specially patched flashrom binary, you can easily flash it but the top 64KiB +region of the boot flash, containing your bootblock, cannot be flashed just +yet. However, there is a register called the *Backup Control* or *BUC* register +and in that register is a status bit called *Top Swap* or *TS*. + +There are *2* bootblocks possible. The *other* bootblock is below the upper +64KiB one, which can't be flashed, but the lower one can. By using bucts, you +can set the machine to boot using that lower 64KiB bootblock, which is +read-write. You do this by setting the BUC.TS register to 1, using the `bucts` +program referenced below. + +The libreboot ROM images already have the upper 64KiB bootblock copied to the lower +one, so you don't have to worry about copying it yourself. + +If you build flashrom using the libreboot build system, there will be three +binaries: + +* `flashrom` +* `flashrom_i945_sst` +* `flashrom_i945_mx` + +It's these last two binaries that you should use. Now compile bucts (just +run `make` in the bucts source directory). + +Run the bucts tool: + + sudo ./bucts 1 + +Ensure that your CMOS battery is connected too. Now you must determine whether +you have Macronix or SST. An X60/T60 thinkpad will have either an SST or a +Macronix chip. The Macronix chip will have "MX" written on the chip. You will +use `flashrom_i945_sst` for the SST chip, and `flashrom_i945_mx` for the +Macronix chip. + +Now run flashrom (for SST): + + sudo ./flashrom_i945_sst -p internal -w coreboot.rom + +Or Macronix: + + sudo ./flashrom_i945_mx -p internal -w coreboot.rom + +NOTE: you *can* just run both. One of them will succeed. It is perfectly +harmless to run both versions of flashrom. In fact, you should do so! + +You'll see a lot of errors. This is normal. You should see something like: + +``` +Reading old flash chip contents... done. +Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0 +Reading current flash chip contents... done. Looking for another erase function. +spi_block_erase_52 failed during command execution at address 0x0 +Reading current flash chip contents... done. Looking for another erase function. +Transaction error! +spi_block_erase_d8 failed during command execution at address 0x1f0000 +Reading current flash chip contents... done. Looking for another erase function. +spi_chip_erase_60 failed during command execution +Reading current flash chip contents... done. Looking for another erase function. +spi_chip_erase_c7 failed during command execution +Looking for another erase function. +No usable erase functions left. +FAILED! +Uh oh. Erase/write failed. Checking if anything has changed. +Reading current flash chip contents... done. +Apparently at least some data has changed. +Your flash chip is in an unknown state. +``` + +If you see this, rejoice! It means that the flash was successful. Please do not +panic. Shut down now, and wait a few seconds, then turn back on again. + +**WARNING: if flashrom complains about `/dev/mem` access, please +run `sudo ./bucts 0`. If flashrom is complaining about `/dev/mem`, it means +that you have `CONFIG_STRICT_DEVMEM` enabled in your kernel. Reboot with the +following kernel parameter added in your bootloader: `iomem=relaxed` and try +again with the above instructions. DO NOT continue until the above works, and +you see the expected flashrom output as indicated above.** + +If you *did* run flashrom and it failed to flash, but you set bucts to 1 and +shut down, don't worry. Just remove the yellow coin-cell battery (it's underneath +the keyboard, connected to the mainboard), wait a minute or two, reconnect the +coin-cell and try again from scratch. In this instance, if flashrom didn't do +anything, and didn't flash anything, it means you still have Lenovo BIOS but +if bucts is set to 1, you can flush it and set it back to 0. BUC.TS is stored in +volatile memory, powered by that CR2032 coin-cell battery. + +Assuming that everything went well: + +Flash the ROM for a second time. For this second flashing attempt, the upper +64KiB bootblock is now read-write. Use the *unpatched* flashrom binary: + + sudo ./flashrom -p internal -w libreboot.rom + +To reset bucts, do this: + + sudo ./bucts 0 + +ONLY set bucts back to 0 if you're sure that the upper 64KiB bootblock is +flashed. It is flashed if flashrom said VERIFIED when running the above +command. + +If it said VERIFIED, shut down. If it didn't say VERIFIED, make sure bucts is +still set to 1, and consult the libreboot project on IRC for advice, and avoid +shutting down your system until you get help. + +If all went well, libreboot should now be booting and you should be able to +boot into your operating system. + +If you messed up, there are external flashing instructions. See main navigation +menu on this page. These "external" instructions teach you how to flash +externally, using special equipment (requires disassembling your laptop and +removing the mainboard). + +Install using external flashing equipment +========================================= + +In many situations, the host CPU is restricted from rewriting/erasing/dumping +the boot flash. In this situations, you must re-flash the chip (containing the +boot firmware) externally. This is called *external flashing*. + +DO NOT buy CH341A! Read the above link, which explains why you shouldn't use it. +CH341A will damage your flash chip, and other components on your mainboard. + +How to use external flashing equipment +-------------------------------------- + +Refer to the following article:\ +[Externally rewrite 25xx NOR flash via SPI protocol](spi.md) + +DELL Latitude E6400 laptop (easy to flash, similar to X200/T400) +------------------------- + +See: [Dell Latitute E6400 Libreboot Installation Instructions](e6400.md) + +ASUS KFSN4-DRE +-------------- + +The KFSN4-DRE has an LPC chip. Most people have been flashing these +internally, hot-swapping the chip out after boot, preserving the original chip, +and using flashrom on a new chip as described above. + +TODO: Document PLCC32 (LPC) flashing. +The [FlexyICE](https://www.coreboot.org/FlexyICE) has been used to flash these +chips, but it is hard to find now. A custom flasher may be made such as +[flashrom serprog stm32](https://github.com/wosk/stm32-vserprog-lpc) or +[teensy flasher](https://www.flashrom.org/Teensy_3.1_SPI_%2B_LPC/FWH_Flasher) + +TARGET: Apple Macbook2,1, Macbook1,1 and iMac5,2 (i945 platform) +---------------------------------------------------------------- + +iMac5,2 is essentially the same board as Macbook2,1, and it is compatible with +libreboot. + +Refer to the following article:\ +[Macbook2,1 and MacBook1,1 installation guide](../hardware/macbook21.md) + +iMac5,2 isn't documented but you can find the flash chip on that board quite +easily. See the generic flashing guide:\ +[Externally rewrite 25xx NOR flash via SPI protocol](spi.md) + +TARGET: Gigabyte GA-G41M-ES2L mainboard +--------------------------------------- + +Refer to the following article:\ +[Gigabyte GA-G41M-ES2L](ga-g41m-es2l.md) + +TARGET: Intel D510MO and D410PT mainboards +------------------------------------------ + +Refer to the following article:\ +[Intel D510MO and D410PT boards](d510mo.md) + +TARGET: Intel D945GCLF mainboard +-------------------------------- + +Refer to the following article:\ +[Intel D945GCLF](d945gclf.md) + +TARGET: ASUS KGPE-D16 mainboard +------------------------------- + +Refer to the following article:\ +[ASUS KGPE-D16](kgpe-d16.md) + +TARGET: ASUS KCMA-D8 mainboard +------------------------------ + +Refer to the following article:\ +[ASUS KCMA-D8](../hardware/kcma-d8.md) + +TARGET: ASUS Chromebook C201 laptop +---------------------------- + +Refer to the following article:\ +[ASUS Chromebook C201](c201.md) + +TARGET: Lenovo ThinkPad X60 laptop +---------------------------------- + +Refer to the following article:\ +[ThinkPad X60](x60_unbrick.md) + +TARGET: Lenovo ThinkPad X60 Tablet laptop +----------------------------------------- + +Refer to the following article:\ +[ThinkPad X60 Tablet](x60tablet_unbrick.md) + +TARGET: Lenovo ThinkPad T60 laptop +---------------------------------- + +Refer to the following article:\ +[ThinkPad T60](t60_unbrick.md) + +TARGET: Lenovo ThinkPad X200 laptop +----------------------------------- + +Refer to the following article:\ +[ThinkPad X200](x200_external.md) + +TARGET: Lenovo ThinkPad X200S or X200 Tablet laptop +--------------------------------------------------- + +Software-wise, identical to regular X200 but SMD rework skills are required. +You must de-solder the default flash chip, and replace it with another one. + +Refer to the following article:\ +[25xx NOR flashing guide](spi.md) + +That guide, linked above, has instructions for how to deal with these machines. + +TARGET: Lenovo ThinkPad T400 laptop +----------------------------------- + +Refer to the following article:\ +[ThinkPad T400](t400_external.md) + +TARGET: Lenovo ThinkPad T400S laptop +------------------------------------ + +Software-wise, identical to regular T400 but SMD rework skills are required. +You must de-solder the default flash chip, and replace it with another one. + +Refer to the following article:\ +[25xx NOR flashing guide](spi.md) + +TARGET: Lenovo ThinkPad R400 laptop +----------------------------------- + +Refer to the following article:\ +[ThinkPad R400](r400_external.md) + +TARGET: Lenovo ThinkPad T500 or W500 laptop +------------------------------------------- + +These two laptops have identical mainboard, except for a few minor changes. + +Refer to the following article:\ +[ThinkPad T500/W500](t500_external.md) + +TARGET: Lenovo ThinkPad R500 laptop +----------------------------------- + +Refer to the following laptop:\ +[ThinkPad R500](../hardware/r500.md) diff --git a/site/docs/install/kgpe-d16.md b/site/docs/install/kgpe-d16.md new file mode 100644 index 0000000..1496fe3 --- /dev/null +++ b/site/docs/install/kgpe-d16.md @@ -0,0 +1,32 @@ +--- +title: KGPE-D16 external flashing instructions +x-toc-enable: true +... + +These will be re-added to Libreboot at a later date, once proper testing +has been done. + +Initial flashing instructions for KGPE-D16. + +This guide is for those who want libreboot on their ASUS KGPE-D16 +motherboard, while they still have the proprietary ASUS BIOS present. +This guide can also be followed (adapted) if you brick you board, to +know how to recover. + +*Memory initialization is still problematic, for some modules. We +recommend avoiding Kingston modules.* + +For more general information about this board, refer to +[../hardware/kgpe-d16.md](../hardware/kgpe-d16.md). + +TODO: show photos here, and other info. + +External programmer +=================== + +Refer to [spi.md](spi.md) for a guide on how to re-flash externally. + +The flash chip is in a PDIP 8 socket (SPI flash chip) on the +motherboard, which you take out and then re-flash with libreboot, using +the programmer. *DO NOT* remove the chip with your hands. Use a chip +extractor tool. diff --git a/site/docs/install/nvmutil.md b/site/docs/install/nvmutil.md new file mode 100644 index 0000000..6ca8329 --- /dev/null +++ b/site/docs/install/nvmutil.md @@ -0,0 +1,520 @@ +--- +title: nvmutil manual +x-toc-enable: true +... + +With this software, you can change the MAC address inside GbE regions +on any system that uses an Intel Flash Descriptor. + +You can use the documentation below, if you wish to use `nvmutil` manually. +Continue reading... + +Introduction +============ + +This is the manual for `nvmutil`, included in the Libreboot, +build system (lbmk) under `util/nvmutil/`. This program lets you modify +the MAC address, correct/verify/invalidate checksums, +swap/copy and dump regions on Intel PHY NVM images, +which are small binary configuration files that go +in flash, for Gigabit (ethernet) Intel NICs. + +This software is largely targeted at coreboot users, +but it can be used on most modern Intel systems, or +most systems from about 2008/2009 onwards. + +NOTE: Libreboot X200/X200T/X200S/T400/T400S/T500/W500/R400 +users should know that this software does *not* +replace `ich9gen`, because that program generates entire +ICH9M IFD+GbE regions, in addition to letting you set the +MAC address. *This* program, `nvmutil`, can *also* set +the MAC address on those machines, but it operates on a +single GbE dump that is already created. + +This program is operated on dumps of the GbE NVM image, +which normally goes in the boot flash (alongside BIOS/UEFI +or coreboot, IFD and other regions in the flash). The first +half of this README is dedicated to precisely this, telling +you how to dump or otherwise acquire that file; the second +half of this README then tells you how to operate on it, +using `nvmutil`. + +How to download newer versions +============================== + +Simply pull down the latest changes in `lbmk.git`. The `nvmutil` +software is now part of lbmk, since 17 November 2022. + +More info about git: + +* + +Context +======= + +On many Intel systems with an IFD (Intel Flash Descriptor), the +Intel PHY (Gigabit Ethernet) stores its configuration, binary +encoded, into a special region of the main boot flash, alongside +other flash regions such as: IFD, ME, BIOS. + +This includes many configurations, such as your MAC address. +The purpose of nvmutil project, is precisely to allow you to change your +MAC address. Many other useful features are also provided. + +Intel defines this as the *Gigabit Ethernet Non-Volative Memory* or +just *NVM* for short. It is a 128-byte section, consisting of 64 +words that are 2 bytes, stored in little-endian byte order. + +Newer Intel PHYs define an *extended* area, which starts +immediately after the main one, but the `nvmutil` program +does not modify or manipulate these in any way. + +The final word in the NVM section is the *checksum*; all words +must add up, truncated, to the value `0xBABA`. The hardware +itself does not calculate or validate this, and will in +fact work nicely, but software such as Linux will check +that this is correct. If the checksum is invalid, your +kernel will refuse to make use of the NIC. + +This NVM section is the first 128 bytes of a 4KB region in flash. +This 4KB region is then repeated, to make an 8KB region in +flash, known as the *GbE region*. In `nvmutil`, the first part +is referred to as *part 0* and the second part as *part 1*. + +Known compatible PHYs +--------------------- + +TODO: write a full list her ofe what actual PHYs are known to work. + +It's probably all of them, but some newer ones might have +changed the standard by which they are configured. This +program actively avoids working on files that have +invalid checksums, on most commands, precisely so that +the user does not inadvertently use it on incompatible +files; it is assumed that intel would later change the +file size and/or checksum value and/or checksum location. + +How to obtain the GbE file +========================== + +The chip containing your BIOS/UEFI firmware (or coreboot) has +it, if you have an Intel PHY for gigabit ethernet. + +The sections below will teach you how to obtain the GbE file, +containing your NIC's configuration. This is the part that +many people will struggle with, so we will dedicated an +entire next section to it: + +Use flashrom +------------ + +If you wish to operate on the GbE section that's already +flashed, you should *dump* the current full ROM image. +If you already have a ROM image, you do not need to dump +it, so you can skip this section. + +Download flashrom here: + +* + +Using recent flashrom versions, you can extract this region. If +your regions are unlocked, you can run flashrom on the target +system, like so: + + flashrom -p internal -r rom.bin + +If your system has two flash chips, the GbE region is usually +stored on SPI1 (not SPI2). Otherwise, it may be that you have +a single-flash setup. In that case, it's recommended to dump +both chips, as `spi1.rom` and `spi2.rom`; you can then cat +them together: + + cat spi1.rom spi2.rom > rom.bin + +If your GbE region is locked (per IFD settings), you can dump +and flash it using external flashing equipment. The Libreboot +project has a handy guide for this; it can be used for reading +from and writing to the chip. See: + +* + +If you're using an external programmer, the `-p internal` +option should be changed accordingly. Read flashrom +documentation, and make sure you have everything +properly configured. + +Use ifdtool +----------- + +NOTE: This has only been tested on systems that use IFDv1 +(Intel Flash Descriptor, version 1). This distinction, between +v1 and v2, is made in the `ifdtool` source code, which you +should read if you're interested. Intel`s v2 specification +has more regions in it, whereas v1 systems usually +defined: IFD, GbE, PD, ME and BIOS regions. + +The `ifdtool` program is a powerful tool, allowing you to +manipulate Intel Flash Descriptors. It's part of coreboot, +available in the `coreboot.git` repository +under `util/ifdtool/`. Just go in there and build it +with `make`, to get an ifdtool binary. + +To make internal flashing possible later on, you might do: + + ifdtool --unlock rom.bin + +Running this command will create a modified image, +named `rom.bin.new`. This file will have all regions set +to read-write, per configuration in the Intel Flash Descriptor. + +In addition to unlocked regions, you may wish to *neuter* the +Intel Management Engine, removing all the nasty spying features +from it, using `me_cleaner`. See: + +* +* Also available in `coreboot.git`, undir `util/` + +The `me_cleaner` program is outside the scope of this +article, so you should read their documentation. + +Now run this: + + ifdtool -x rom.bin + +Several files will be created, and the one you need to +operate on is named `flashregion_3_gbe.bin` so please +ensure that you have this file. + +Read the notes below about how to use the `nvmutil` program, +operating on this file. When you're done, you can insert the +modified GbE file back into your ROM image, like so: + + ifdtool -i gbe:flashregion_3_gbe.bin rom.bin + +This will create the file `rom.bin.new`, which contains +your modified GbE section with the NVM images inside; this +includes your MAC address. + +Refer to flashrom documentation. You may flash the new ROM +like so, if running on the same system and the regions are +read-write: + + flashrom -p internal -w rom.bin.new + +Newer versions of flashrom support flashing just the specified +region, like so: + + flashrom -p internal --ifd -i gbe -w rom.bin.new + +If you're running flashrom from host CPU on the target +system, and it's dual flash, you can just flash the +concatenated image, which you created earlier by running +the `cat` program; dual-IC flash configurations appear to +your operating system as one large flash area, as though +it were a single chip. + +If you're using an external programmer, you should change +the `-p internal` parameter to something else. In this +situation, you should re-split the file accordingly, if +you have a dual-IC flash set, like so: + + dd if=rom.bin.new of=spi2.rom bs=1M skip=8 + dd if=rom.bin.new of=spi1.rom bs=1M count=8 + +These files would then be flashed externally, separately, +using an external programmer. + +The *above* example (using `dd`) is for setups with 12MB +flash, where you have 8MB as SPI1 and 4MB as SPI2. SPI1 +would contain the IFD, and SPI2 is the upper flash area +containing your bootblock; GbE is probably located in +SPI1. You should adjust the above parameters, according +to your configuration. + +How to compile source code +========================== + +The nvmutil source code is located under `util/nvmutil/` in the +lbmk repository. A makefile is included there, for you to build an +executable. + +The nvmutil programs will work just fine, on any modern BSD Unix operating +system, or unix-like system such as Linux. + +You must be sure to have toolchains installed, for +building; a normal libc, C compiler and linker should be enough. +GCC and LLVM have all these things included, so use whichever one +you want. + +If the code is compiled on OpenBSD, +[pledge(2)](https://man.openbsd.org/pledge.2) is used. +This is done with an `ifdef` rule, so that the code still compiles +on other systems. When the `dump` command is specified, pledge +will use these promises: `stdio rpath`. When any other command +is used, these pledge promises will be used: `stdio wpath`. + +The `nvmutil` software has been build-tested on `Clang`, `GCC` +and `tcc`. Only standard library functions (plus `err.h`) are +used, so you don't need any extra libraries. + +How to compile it +----------------- + +First, ensure that the current working directory is your +copy of the nvmutil source code! + +You may run this in your terminal: + + make + +This will result in a binary being created named `nvm`. +Install this to wherever you want, such as `/usr/bin` (or +whatever is in your `$PATH` for userspace programs). + +TODO: Add `make install` to the Makefile, portably. + +How to use nvmutil +================== + +You run it, passing as argument the path to a file, and you run +commands on that file. This section will tell you how to +perform various tasks, by using these commands. + +In these examples, it is assumed that you have installed +the `nvm` binary to somewhere in your `$PATH`. If you haven't +done that, you could still run it in cwd for instance: + + ./nvm bla bla bla + +Exit status +----------- + +The `nvmutil` program uses `errno` extensively. The best error +handling is done this way, the Unix way. Error handling is extremely +strict, in nvmutil; on program exit, the errno message is printed (if not +zero) and the value of errno is returned (upon exit from `int main`). + +The `main` function always returns `errno`, no matter what. This style +of programming (set errno and return) is a very old fashioned way of +doing things, and in many cases it is the most *correct* way. + +This is why we say `zero status` and `non-zero status` in Unix +programs, when we talk about exit status. Zero is success, and +anything above zero is fail; errno is zero by default, unless +set, and it will always be set to a value above zero (if set). + +All commands (except `dump`) require read and write access. The `dump` +command only requires read access on files. Where sufficient permission +is not given (read and/or write), nvmutil will exit with non-zero status. + +Non-zero status will also be returned, if the target file is *not* +of size *8KB*. + +Additional rules regarding exit status shall apply, depending on +what command you use. Commands are documented in the following sections: + +Change MAC address +------------------ + +The `nvm` program lets you change the MAC address. It sets +a valid checksum, after changing the MAC address. This program +operates on *both* NVM parts, but it will only modify a given +part if the existing checksum is correct. It will exit with zero +status if at least one part is modified; otherwise, it will +exit with non-zero status. + +The following rules are enforced in code: + +* User cannot specify multicast addresses +* User cannot specify `00:00:00:00:00:00` +* When generating random addresses, if the right + most nibble of the left-most byte is `?` (random), + nvmutil will (in code) force the generated MAC + address to be local (not global), and will prevent + a multicast address from being generated. + +A multicast address is invalid because it represents +multiple devices; you must specify a unicast address. +A global address is one uniquely assigned by the vendor, +and a local address is an overridden one. You *can* set +global MAC addresses in nvmutil, for example if you are +simply copying what was officially assigned to your NIC, +you can do that. For example, if your MAC address +was `00:de:ad:be:ef:69` as assigned by the manufacturer, +which is a global unicast MAC address, you would type: + + nvm gbe.bin setmac 00:de:ad:be:ef:69 + +How to use (the MAC address in just an example): + + nvm gbe.bin setmac 00:de:ad:be:ef:00 + +You can also set random MAC addresses: + + nvm gbe.bin setmac ??:??:??:??:??:?? + +In this example, every character is random. However, you +can mix and match random characters with static ones. For +example: + + nvm gbe.bin setmac 00:1f:16:??:??:?? + +You can also pass it without a MAC address: + + nvm gbe.bin setmac + +If you only type `setmac` without specifying a MAC address, +it will do the same thing as `setmac ??:??:??:??:??:??`. + +This will set the last three bytes randomly, while the +MAC address would begin with `00:1f:16`. + +The *reason* nvmutil doesn't alter a part with an existing +invalid checksum, is precisely so that if the algorithm +changes in future Intel PHYs, nvmutil will just fail and +not modify your file. This is because the checksum would +then be invalid, at all times. However, correct NVM parts +with otherwise invalid checksums do exist, and can be +corrected if you use the `setchecksum` command +in `nvmutil`. It is common for vendor gbe files to contain +one valid part and one invalid part, per checksum rules. + +Verify checksums (and show MAC addresses) +----------------------------------------- + +This command *only* requires *read* access on files. + +The `nvm` program can show a hexdump of both NVM parts, and +tell you whether each one is valid (as per checksum calculation). +It also prints the MAC address from each part. + +How to use: + + nvm gbe.bin dump + +NOTE: This will exit with zero status if at least one part +contains a valid checksum. If both parts are invalid, nvmutil +will exit with non-zero status. + +Copy part +--------- + +This command requires read *and* write access on files. + +The `nvm` program can copy one NVM part to another. It copies +the *entire* 4KB part, within the 8KB file. + +Overwrite part 0 with the contents of part 1: + + nvm gbe.bin copy 1 + +Overwrite part 1 with the contents of part 0: + + nvm gbe.bin copy 0 + +NOTE: If the part to be copied has a bad checksum, no operation +will be performed, and nvmutil will exit with non-zero status. +Otherwise, it will (if all other conditions are met) exit with +zero status. + +Swap parts +---------- + +This command requires read *and* write access on files. + +The `nvm` program can swap both 4KB parts in the GbE +file. It does this, via simple XOR swaps. + +How to use: + + nvm gbe.bin swap + +NOTE: This operation will be aborted if BOTH checksums +are invalid. This is to guard against accidentally +using `nvmutil` on the wrong file. + +If *at least one* part is valid, nvmutil will return +with zero exit status. If both parts are invalid, it will +return non-zero. + +Set valid checksum +------------------ + +This command requires read *and* write access on files. + +The `nvm` program can calculate and sets a valid checksum, on +the desired NVM part. Usage: + +Fix part 0: + + nvm gbe.bin setchecksum 0 + +Fix part 1: + + nvm gbe.bin setchecksum 1 + +*WARNING: NO validity checks are performed. This will simply +set the checksum. There is no feasible way to guard against +use on the wrong file, unlike with the other commands. Please +make SURE you're running this on the correct file!* + +Set invalid checksum +-------------------- + +This command requires read *and* write access on files. + +The `nvm` program can intentionally set an invalid checksum, on +the desired NVM part. Usage: + +Invalidate part 0: + + nvm gbe.bin brick 0 + +Invalidate part 1: + + nvm gbe.bin brick 1 + +NOTE: If the part already has an invalid checksum, no operation +will be performed, and nvmutil will exit with non-zero status. +This is to guard against `nvmutil` being used on the wrong file. + +This may be desirable, if you've made modifications to both +parts but you want to guarantee that only one of them is +used. Also, the `setmac` command will only operate on +parts that already have a valid checksum, so you could +run `brick` before running `setmac` (or run it afterwards). + +The Linux kernel's `e1000` driver will refuse to initialise +Intel gigabit NICs that don't have a valid checksum. This +is software-defined, and not enforced by the hardware. + +LICENSE +======= + +This page is released under different copyright terms than most other pages +on this website. + +The `nvmutil` software and documentation are released under the following +terms: + +Copyright 2022 Leah Rowe + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + diff --git a/site/docs/install/r400_external.md b/site/docs/install/r400_external.md new file mode 100644 index 0000000..eadc7e7 --- /dev/null +++ b/site/docs/install/r400_external.md @@ -0,0 +1,210 @@ +--- +title: Flashing the ThinkPad R400 +x-toc-enable: true +... + +**If you haven't bought an R400 yet: the [Dell Latitude +E6400](../../news/e6400.md) is much easier to flash; no disassembly required, +it can be flashed entirely in software from Dell BIOS to Libreboot. It is the +same hardware generation (GM45), with same CPUs, video processor, etc.** + +Initial flashing instructions for R400. + +This guide is for those who want libreboot on their ThinkPad R400 while +they still have the original Lenovo BIOS present. This guide can also be +followed (adapted) if you brick your R400, to know how to recover. + +Before following this section, please make sure to setup your libreboot +ROM properly first. Although ROM images are provided pre-built in +libreboot, there are some modifications that you need to make to the one +you chose before flashing. (instructions referenced later in this guide) + +Serial port {#serial_port} +----------- + +EHCI debug might not be needed. It has been reported that the docking +station for this laptop has a serial port, so it might be possible to +use that instead. + +A note about CPUs +================= + +[ThinkWiki](http://www.thinkwiki.org/wiki/Category:R400) has a list of +CPUs for this system. The Core 2 Duo P8400 and P8600 are believed to +work in libreboot. The Core 2 Duo T9600 was confirmed to work, so the +T9400 probably also works. *The Core 2 Duo T5870/5670 and Celeron M +575/585 are untested!* + +Quad-core CPUs +-------------- + +Incompatible. Do not use. + +A note about GPUs +================= + +Some models have an Intel GPU, while others have both an ATI and an +Intel GPU; this is referred to as "Dual Graphics" (previously +"switchable graphics"). In the *BIOS setup* program for lenovobios, +you can specify that the system will use one or the other (but not +both). + +libreboot is known to work on systems with only the Intel GPU, using +native graphics initialization. On systems with switchable graphics, the +Intel GPU is used and the ATI GPU is disabled, so native graphics +initialization works all the same. + +CPU paste required +================== + +See [\#paste](#paste). + +Flash chip size {#flashchips} +=============== + +Use this to find out: + + flashrom -p internal + +MAC address {#macaddress} +=========== + +Refer to [mac\_address.md](../hardware/mac_address.md). + +External flashing +================= + +Refer to [spi.md](spi.md) as a guide for external re-flashing. + +Disassembly +----------- + +Remove all screws:\ +![](https://av.libreboot.org/r400/0000.jpg)\ +Remove the HDD and optical drive:\ +![](https://av.libreboot.org/r400/0001.jpg)\ +Remove the hinge screws:\ +![](https://av.libreboot.org/r400/0002.jpg) ![](https://av.libreboot.org/r400/0003.jpg) + +Remove the palm rest and keyboard:\ +![](https://av.libreboot.org/r400/0004.jpg) ![](https://av.libreboot.org/r400/0005.jpg) + +Remove these screws, and then remove the bezel:\ +![](https://av.libreboot.org/r400/0006.jpg) ![](https://av.libreboot.org/r400/0007.jpg) + +Remove the speaker screws, but don't remove the speakers yet (just set +them loose):\ +![](https://av.libreboot.org/r400/0008.jpg) ![](https://av.libreboot.org/r400/0009.jpg) +![](https://av.libreboot.org/r400/0010.jpg) + +Remove these screws, and then remove the metal plate:\ +![](https://av.libreboot.org/r400/0011.jpg) ![](https://av.libreboot.org/r400/0012.jpg) +![](https://av.libreboot.org/r400/0013.jpg) + +Remove the antennas from the wifi card, and then start unrouting them:\ +![](https://av.libreboot.org/r400/0014.jpg) ![](https://av.libreboot.org/r400/0015.jpg) +![](https://av.libreboot.org/r400/0016.jpg) ![](https://av.libreboot.org/r400/0017.jpg) +![](https://av.libreboot.org/r400/0018.jpg) ![](https://av.libreboot.org/r400/0019.jpg) + +Disconnect the LCD cable from the motherboard:\ +![](https://av.libreboot.org/r400/0020.jpg) ![](https://av.libreboot.org/r400/0021.jpg) +![](https://av.libreboot.org/r400/0022.jpg) ![](https://av.libreboot.org/r400/0023.jpg) + +Remove the hinge screws, and then remove the LCD panel:\ +![](https://av.libreboot.org/r400/0024.jpg) ![](https://av.libreboot.org/r400/0025.jpg) +![](https://av.libreboot.org/r400/0026.jpg) ![](https://av.libreboot.org/r400/0027.jpg) + +Remove this:\ +![](https://av.libreboot.org/r400/0028.jpg) ![](https://av.libreboot.org/r400/0029.jpg) + +Remove this long cable (there are 3 connections):\ +![](https://av.libreboot.org/r400/0030.jpg) ![](https://av.libreboot.org/r400/0031.jpg) +![](https://av.libreboot.org/r400/0032.jpg) ![](https://av.libreboot.org/r400/0033.jpg) + +Disconnect the speaker cable, and remove the speakers:\ +![](https://av.libreboot.org/r400/0034.jpg) + +Remove the heatsink screws, remove the fan and then remove the +heatsink/fan:\ +![](https://av.libreboot.org/r400/0035.jpg) ![](https://av.libreboot.org/r400/0036.jpg) +![](https://av.libreboot.org/r400/0037.jpg) ![](https://av.libreboot.org/r400/0038.jpg) + +Remove the NVRAM battery:\ +![](https://av.libreboot.org/r400/0039.jpg) ![](https://av.libreboot.org/r400/0040.jpg) + +Remove this screw:\ +![](https://av.libreboot.org/r400/0041.jpg) ![](https://av.libreboot.org/r400/0042.jpg) + +Disconnect the AC jack:\ +![](https://av.libreboot.org/r400/0043.jpg) ![](https://av.libreboot.org/r400/0044.jpg) + +Remove this screw and then remove what is under it:\ +![](https://av.libreboot.org/r400/0045.jpg) + +Remove this:\ +![](https://av.libreboot.org/r400/0046.jpg) + +Lift the motherboard (which is still inside the cage) from the side on +the right, removing it completely:\ +![](https://av.libreboot.org/r400/0047.jpg) ![](https://av.libreboot.org/r400/0048.jpg) + +Remove all screws, marking each hole so that you know where to re-insert +them. You should place the screws in a layout corresponding to the order +that they were in before removal: ![](https://av.libreboot.org/r400/0049.jpg) +![](https://av.libreboot.org/r400/0050.jpg) + +Remove the motherboard from the cage, and the SPI flash chip will be +next to the memory slots:\ +![](https://av.libreboot.org/r400/0051.jpg) ![](https://av.libreboot.org/r400/0052.jpg) + +Now, you should be ready to install libreboot. + +Read [this article](spi.md) to learn how you may flash the chip, which is near +to the RAM. + +Thermal paste (IMPORTANT) +========================= + +Because part of this procedure involved removing the heatsink, you will +need to apply new paste. Arctic MX-4 is ok. You will also need isopropyl +alcohol and an anti-static cloth to clean with. + +When re-installing the heatsink, you must first clean off all old paste +with the alcohol/cloth. Then apply new paste. Arctic MX-4 is also much +better than the default paste used on these systems. + +![](https://av.libreboot.org/t400/paste.jpg) + +NOTE: the photo above is for illustration purposes only, and does not +show how to properly apply the thermal paste. Other guides online detail +the proper application procedure. + +Memory +====== + +In DDR3 machines with Cantiga (GM45/GS45/PM45), northbridge requires sticks +that will work as PC3-8500 (faster PC3/PC3L sticks can work as PC3-8500). +Non-matching pairs may not work. Single module (meaning, one of the slots +will be empty) will currently only work in slot 0. + +NOTE: according to users reports, non matching pairs (e.g. 1+2 GiB) might +work in some cases. + +Make sure that the RAM you buy is the 2Rx8 configuration when buying 4GiB sticks +(In other words: maximum of 2GiB per rank, 2 ranks per card). + +[This page](http://www.forum.thinkpads.com/viewtopic.php?p=760721) might +be useful for RAM compatibility info (note: coreboot raminit is +different, so this page might be BS) + +The following photo shows 8GiB (2x4GiB) of RAM installed:\ +![](https://av.libreboot.org/t400/memory.jpg) + +Boot it! +-------- + +You should see something like this: + +![](https://av.libreboot.org/t400/boot0.jpg) ![](https://av.libreboot.org/t400/boot1.jpg) + +Now [install Linux](../linux/). diff --git a/site/docs/install/spi.md b/site/docs/install/spi.md new file mode 100644 index 0000000..f3bd5d1 --- /dev/null +++ b/site/docs/install/spi.md @@ -0,0 +1,953 @@ +--- +title: Read/write 25XX NOR flash via SPI protocol +x-toc-enable: true +... + +This guide will teach you how to use various tools for externally reprogramming +a 25xx NOR flash via SPI protocol. This is the most common type of flash IC for +computers that coreboot runs on. Almost every system currently supported by +libreboot uses this type of boot flash; the only exception is ASUS KFSN4-DRE, +which uses LPC flash in a PLCC32 socket, which you can simply hot-swap after +booting the vendor firmware, and then flash internally. Simple! + +We will be using +the [flashrom](https://flashrom.org/Flashrom) software which is written to +dump, erase and rewrite these flash chips. + +libreboot currently documents how to use these SPI programmers: + +* Raspberry Pi (RPi) +* BeagleBone Black (BBB) +* Libre Computer 'Le Potato' + +Many other SPI programmers exist. More of them will be documented on this page, +at a date in the future. You can otherwise figure it out on your own; certain +parts of this page are still useful, even if you're using a programmer that +Libreboot does not yet document. + +Most systems in libreboot have to be re-flashed externally, using instructions +on this and similar guides, the first time you flash. However, on all currently +supported systems, it's possible that you can re-flash *internally* when +libreboot is running. + +*Internal* flashing means that the host CPU on your system can re-program the +SPI flash, using an on-board SPI programmer (which all boards have). You do this +from Linux, with flashrom. + +*This* guide that you're reading now is for using an *external* programmer. It +is called *external* because it's not the *internal* one on your mainboard. + +Do not use CH341A! +================== + +NOR flashes on libreboot systems run on 3.3V DC or 1.8V DC, and this includes +data lines. CH341A has 5V logic levels on data lines, which will damage your +SPI flash and also the southbridge that it's connected to, plus anything else +that it's connected to. + +These ch341a programmers are unfortunately very popular. DO NOT use it unless +you have fixed the issue. You CAN fix it so that the data lines are 3.3v, if +you follow the notes here: + + + +In practise, most people will not fix their ch341a and instead just risk it, +so no documentation will be provided for ch341a on this website. It is best +to discourage use of that device. + +**Not covered on that eevblog page: the WP/HOLD pins (pins 3 and 7) must be +held high via pull-up resistors, but on CH341A dongles, they are directly +connected to 3.3V DC (continuity with pin 8). It is advisable to cut these +two connections, to the WP and HOLD pins, and jump the cuts using pull-up +resistors instead. A value between 1k to 10k (ohms) should be fine.** + +**In the event of a surge, like for example you connect the clip wrongly and +cause a short circuit between two pins, lack of pull-up resistors on WP/HOLD +could cause a direct short between VCC/ground, which would cause a lot of heat +build up and possibly fire (and definitely damaged circuitry). On SOIC8, pin 3 +is WP and 4 is GND, so a direct 3.3v connection there is quite hazardous for +that reason; all the more reason to use a pull-up resistor.** + +The mainboard that you want to flash (if using e.g. pomona clip) will probably +have pull-up resistors on it already for WP/HOLD, so simply cutting WP/HOLD +on the CH341A would also be acceptable. The pull-up resistors that you +place (in such a mod) on the CH341A are only useful if you also want to flash +chips in the ZIF socket. If pull-up resistors exist both on e.g. the laptop +mainboard and on the CH341A, it just means the equivalent series resistance +will be of the two resistors (on each line) in parallel. If we assume that +a laptop is likely to have a resistor size of ~3.3k for pull-ups, then a value +of ~5.6k ohms on the CH341A side seems reasonable. + +Alternatively, you might work around the voltage issue by using an adapter with +logic-level converter, making sure to have matching vcc going into the flash. +Use of a logic level converter would be quite flexible, in this scenario, and +you could use it to set many voltages such as 1.8v or 3.3v. + +In case it's not clear: + +**Please do not buy the ch341a!** It is incorrectly engineered for the purpose +of ROM flashing on systems with 3.3v SPI (which is most coreboot systems). DO +NOT USE IT! This issue still isn't fixed by the manufacturer, and it doesn't +look like they will ever fix it. + +If you see someone talking about CH341A, please direct them to this page and +tell them why the CH341A is bad. + +These photos show both modifications (3.3v logic and WP/HOLD pull-up +resistors) performed, on the black CH341A:\ + + + +The green version (not shown above) may come with 3.3v logic already wired, but +still needs to have pull-up resistors placed for WP/HOLD. + +Identify which flash type you have +================================== + +In all of them, a dot or marking shows pin 1 (in the case of WSON8, pad 1). + +Use the following photos and then look at your board. When you've figured out +what type of chip you have, use that knowledge and the rest of this guide, to +accomplish your goal, which is to read from and/or write to the boot flash. + +SOIC8 +----- + +![](https://av.libreboot.org/chip/soic8.jpg) + +SOIC16 +------ + +![](https://av.libreboot.org/chip/soic16.jpg) + +SOIC8 and SOIC16 are the most common types, but there are others: + +WSON8 +----- + +It will be like this on an X200S or X200 Tablet:\ + +![](https://av.libreboot.org/x200t_flash/X200T-flashchip-location.jpg) + +On T400S, it is in this location near the RAM:\ +![](https://av.libreboot.org/t400s/soic8.jpg)\ +NOTE: in this photo, the chip has been replaced with SOIC8 + +DIP8 +---- + +![](https://av.libreboot.org/dip8/dip8.jpg) + +Supply Voltage +-------------- + +Historically, all boards that Libreboot supports happened to have SPI NOR chips +which work at 3.3V DC. With the recent addition of Chromebooks whose chips are +rated for 1.8V DC, this can no longer be assumed. + +Inspect the chip on your board for a part number, look up the datasheet for it. +Find out and make note of the power supply voltage it needs. If it doesn't +match the voltage output by your external flashing hardware, you should only +connect it to the chip through an adapter or logic level converter, never +directly. + +Software configuration +====================== + +General/Le potato +----------------- + +The [generic guide](spi_generic.md) is intended to help those looking to use an +SBC which is not listed in this guide. +The guide will, however, use the libre computer 'Le Potato' as a reference board. +If you have that board, you should refer to the [generic guide.](spi_generic.md) + +BeagleBone Black (BBB) +---------------------- + +SSH into your BeagleBone Black. It is assumed that you are running Debian 9 on +your BBB. You will run `flashrom` from your BBB. + +NOTE: This section is out of date, because it is written for Debian 9 (running +on the BBB) + +Run the following commands as root to enable spidev: + +``` +config-pin P9.17 spi_cs +config-pin P9.18 spi +config-pin P9.21 spi +config-pin P9.22 spi_sclk +``` + +Verify that the spidev devices now exist: + + ls /dev/spidev* + +Output: + + /dev/spidev1.0 /dev/spidev1.1 /dev/spidev2.0 /dev/spidev2.1 + +Now the BBB is ready to be used for flashing. The following systemd service +file can optionally be enabled to make this persistent across reboots. + +``` +[Unit] +Description=Enable SPI function on pins + +[Service] +Type=oneshot +ExecStart=config-pin P9.17 spi_cs +ExecStart=config-pin P9.18 spi +ExecStart=config-pin P9.21 spi +ExecStart=config-pin P9.22 spi_sclk +RemainAfterExit=yes + +[Install] +WantedBy=multi-user.target +``` + +Now test flashrom: + + ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 + +It is important to use `spispeed=512` or a lower number such as 256 or 128, +because otherwise the BBB will be quite unstable. + +Example output: + +``` +Calibrating delay loop... OK. +No EEPROM/flash device found. +Note: flashrom can never write if the flash chip isn't found automatically. +``` + +This means that it's working (the clip isn't connected to any flash +chip, so the error is fine). + +Caution about BBB +----------------- + +BeagleBone Black is not recommended, because it's very slow and unstable for +SPI flashing, and nowadays much better options exist. We used to mainly +recommend the BBB, because of the fact that it can be used with entirely Free +Software on it, but nowadays there are superior options. + +TODO: document other SPI flashers + +Rasberry Pi (RPi) +----------------- + +SSH into your Raspberry Pi. You will run `flashrom` from your Raspberry Pi. + +You must configure `spidev` on your Raspberry Pi. This is a special driver in +the Linux kernel; technically, the driver name is `spi-bcm2835`. + +This page has info:\ + + +In your Raspberry Pi, which we assume you're running the latest Raspbian version +on, do this: + + sudo raspi-config + +Under the Interface section, you can enable SPI. + +The device for communicating via SPI as at `/dev/spidev0.0` + +RPi Drive Strength +------------------ +Flashrom on the RPi may not be able to detect the SPI flash chip on some +systems, even if your wiring and clip are set up perfectly. This may be due to +the drive strength of the Raspberry Pi GPIOs, which is 8mA by default. Drive +strength is essentially the maximum current the pin can output while also +maintaining the minimum high-level voltage. In the case of the Pi, this voltage +is 3.0V. + +Similarly, the SPI flash chip has a minimum voltage it will accept as a high +logic value. This is commonly 0.7\*VCC for SPI flash, which is 2.31V for 3.3V +chips. If the drive strength is too low, the voltage at the pins of the flash +chip may fall below this minimum voltage, causing it to register as a low logic +value instead of the high value that was sent. + +On many systems, the VCC pin of the SPI flash is shared with other chips on the +system, causing them to be powered through the voltage supplied through your +programming clip. In this case, parts of the chipset may power up, and it may +attempt to set the SPI lines high or low, interfering with the data the Pi is +trying to send. If the Pi and chipset are trying to set a pin to different +values, the side with a greater drive strength will be able to "pull" the +voltage toward the level it wants to set. + +Fortunately, the drive strength of the Raspberry Pi can be increased up to +16mA. There are a few tools that can set this, such as the pigs utility from +the pigpio project. On the Raspberry Pi OS, the following commands should +install pigpio and set the drive strength to 16mA: + +Install pigpio: + + sudo apt install pigpio + +Start the pigpiod daemon, which the pigs utility communicates with to interact +with the gpios: + + sudo pigpiod + +Set the drive strength of GPIO group 0, which contains the spi0 pins, to 16mA: + + pigs pads 0 16 + +Note that the drive strength hardware works in multiples of 2mA, and pigs will +round odd values up to the next multiple of 2. You can check the current drive +strength using + + pigs padg 0 + +WARNING: If the chipset is very strongly trying to drive a pin to a value +opposite that of the Pi, more than 16mA pass through the Pi's GPIO pins, which +may damage them as they are only designed for 16mA. The drive strength is NOT a +current limit. That said, this is a risk to the Pi regardless of the drive +strength. Resistors between the chipset and the flash should protect against +this, though not all boards have these. + +See + +for more information about the drive strength control on the Pi. + +Caution about RPi +----------------- + +Basically, the Raspbian project, now called Raspberry Pi OS, put in their repo +an update that added a new "trusted" repository, which just so happened to be +a Microsoft software repository. They seem to have done this for VS Code, but +the problem here is that it gave Microsoft free reign to define whatever +dependencies they liked (as per apt-get rules), and every time you updated, +you would be pinging Microsoft servers. Do you think that is strange? + +Microsoft shouldn't have *any* access to your Linux system! This was the +commit that Raspbian added to their distro, which added this what should rightly +be called a security vulnerability, intentionally: + +* + +They then removed it, after a public backlash, via the following commits: + +* +* + +Libre firmware on RPi +--------------------- + +The boot firmware on older Raspberry Pi models can be replaced, with entirely +libre firmware. This may be a useful additional step, for some users. See: + + + +Website: + + + +Install flashrom +---------------- + +If you're using a BBB or RPi, you will do this while SSH'd into those. + +Flashrom is the software that you will use, for dumping, erasing and rewriting +the contents of your NOR flash. + +In the libreboot build system, from the Git repository, you can download and +install flashrom. Do this after downloading the +[lbmk Git repository](https://codeberg.org/libreboot/lbmk): + + cd lbmk + sudo ./build dependencies ubuntu2004 + +NOTE: debian, arch or void can be written instead of ubuntu2004. the debian +script is also applicable to newer ubuntu versions + + ./download flashrom + ./build module flashrom + +If the `ubuntu2004` script complains about missing dependencies, just modify +the script and remove those dependencies. The script is located +at `resources/scripts/build/dependencies/ubuntu2004` and it is written for +Ubuntu 20.04, but it should work fine in other Linux distributions that use +the `apt-get` package manager. + +A `flashrom/` directory will be present, with a `flashrom` executable inside +of it. If you got an error about missing package when running the dependencies +command above, tweak `resources/scripts/build/dependencies/ubuntu2004`. That +script downloads and installs build dependencies in apt-get and it is intended +for use on x86-64 systems running Ubuntu 20.04, but it should work in Raspbian +on the Raspberry Pi. + +Alternatively, you may download flashrom directly from upstream +at + +If you're flashing a Macronix flashchip on a ThinkPad X200, you will want to +use a special patched version of flashrom, which you can download here: + - patched source code is available, and a +binary is also available that you can simply run. Pass the `--workaround-mx` +argument in flashrom. This mitigates stability issues. + +If you downloaded the flashrom source code directly, you can go into the +directory and simply type `make`. In the libreboot build system, build +dependencies are documented in script located +at `resources/scripts/build/dependencies/` which you can install +using the `apt-get` software. + +How to use flashrom +=================== + +Read past these sections, further down this page, to learn about specific chip +types and how to wire them. + +Reading +------- + +Before flashing a new ROM image, it is highly advisable that you dump the +current chip contents to a file. + +Run this command to see if 25xx flash is detected, with your RPi properly +wired. + + sudo ./flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=32768 + +For BBB, you must use a lower speed and a different device path: + + sudo ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 + +On BBB, never use a speed higher than `spispeed=512`. In some cases, you may +even need to go as low as `spispeed=128`. The BBB is highly unstable and +unreliable for SPI flashing. When you're reading, take multiple dumps and +verify that the checksums match, before you flash. You may have to flash your +chip several times! + +NOTE: On some systems, higher speeds will be unstable. On those systems, try +lower speed like `spispeed=4096` or even `spispeed=2048` which should, in most +cases, work just fine but it will obviously be slower. The `spispeed=32768` +setting works just fine on most setups if you use short wires, within 10cm. + +If flash chip is detected you may try reading (dumping) the flash contents now, +or you can try flashing it with a new ROM. + +Dump it like so (RPi): + + sudo ./flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=32768 -r dump.bin + +For BBB, do this: + + sudo ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r dump.bin + +It is advisable to take a *2nd* dump, e.g. `dump2.bin`, and then check sha1sum: + + sha1sum dump*.bin + +If the checksums match, it indicates that you have a good dump. If they do not, +check your wiring. Wires should be within 10cm length for best stability, and +they should all be the same length (VCC and GND wires can be longer). + +This advice is *especially* applicable to the BBB, which is highly unreliable. + +Writing +------- + +Next, run this command (RPi): + + sudo ./flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=32768 -w /path/to/libreboot.rom + +If using BBB: + + sudo ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w /path/to/libreboot.rom + +If using BBB, you may have to use a lower speed than 512. You may also have to +re-flash several times before it works fully. + +Again, use a lower `spispeed` value if you need to, for stability. + +Once that command outputs the following, the flash has completed +successfully. If not, just flash again. + +``` +Reading old flash chip contents... done. +Erasing and writing flash chip... Erase/write done. +Verifying flash... VERIFIED. +``` + +If it says "VERIFIED" or says that the chip contents are identical to the +requested image, then the chip is properly flashed. + +Hardware configuration +====================== + +Refer to the above guidance about software configuration. The following advice +will teach you how to wire each type of flash chip. + +WARNINGS +-------- + +Do not connect the power source until your chip is otherwise properly +wired. For instance, do not connect a test clip that has power attached. + +Do not *disconnect* your chip from the flasher until you've disconnected or +turned off the power source. + +BE CAREFUL that you are indeed supplying the appropriate supply voltage to the +chip. SPI flashes on most of the currently supported libreboot hardware run on +3.3V DC and logic at that level too. Some of them (at least Chromebooks) can +have chips that run on 1.8V DC. You should make sure to check the part number +and datasheet of the SPI flash chip for the supply voltage it requires. If your +external flashing hardware doesn't match it, use an adapter or logic level +converter to flash. + +It is important to CHECK that you are running on the correct voltage, when you +do anything with these chips. Lower than the rated supply voltage won't damage +anything, but higher will fry your chip (on most 3.3V chips, the tolerated +voltage range is between 2.7V and 3.6V, but 3.3V is the most ideal level). + +DO NOT connect more than 1 DC power source to your flash chip either! +Mixing voltages like that can easily cause damage to your equipment, and to +your chip/mainboard. + +MISO/MOSI/CS/CLK lines +---------------------- + +You may want to add 47ohm series resistors on these lines, when flashing the +chips. Only do it on those lines (NOT the VCC or GND lines). This provides +some protection from over-current. On Intel platforms, the SPI flash is usually +connected via such resistors, directly to the Southbridge chipset. + +ISP programming and VCC diode +----------------------------- + +ISP means in-system programming. It's when you flash a chip that is already +mounted to the mainboard of your computer that you wish to install libreboot +on. + +It may be beneficial to modify the mainboard so that the SPI flash is powered +(on the VCC pin) through a diode, but please note: a diode will cause a voltage +drop. The tolerated range for a chip expecting 3.3V VCC is usually around 2.7V +to 3.6V DC, and the drop may cause the voltage to fall outside that. If you do +this, please also ensure that the WP and HOLD pins are still held to a high +logic state; each via their own resistor (1K to 10K ohms) connected to the +*same* power source going through the diode. + +The reason is simple: on most systems, the flash shares a common power rail +with many other components on the board, which draw a lot of current. Further, +if you accidentally provide too much voltage or cause an overcurrent, you could +fry those other components but if there is diode protection, you'll only fry +the boot flash (and it is very easy to replace, if you have good soldering +skills). + +When you've placed the diode, ensure that VCC on the chip is isolated from all +other components on that board, which share the same power rail. Further, +ensure that the pull-up resistors for WP/HOLD are *only* connected to the side +of the diode that has continuity with the VCC pin (this is important because if +they're not, they won't be held high while doing ISP flashing, even if they're +still held high when the mainboard is fully powered on). + +Furthermore: ensure that the SPI flash is operating at the appropriate supply +voltage (2.7V to 3.6V for a 3.3V chip) when fully powered on, after installing +the diode. + +If it's a desktop/workstation/server board (not a laptop), you could de-solder +the SOIC8/WSON8 if it uses that, and replace with an IC socket (for SOIC8, +WSON8 or DIP8, whatever you want), because then you could easily just insert +the flash into a breadboard when flashing. + +TODO: Make a page on libreboot.org, showing how to do this on all mainboards +supported by libreboot. + +GPIO pins on BeagleBone Black (BBB) +----------------------------------- + +Use this image for reference when connecting the pomona to the BBB: + (D0 = MISO or connects +to MISO). + +On that page, look at the *P9 header*. It is what you will use to wire up your +chip for flashing. + +GPIO pins on Raspberry Pi (RPi) 40 Pin +-------------------------------------- + +This diagram shows the pinout for most modern Pi's and Pi derivatives. +The diagram shows the pins of an RPi on the left and the two SOIC clips +on the left. + +![](https://av.libreboot.org/rpi/wiring.webp) + +GPIO pins on Raspberry Pi (RPi) 26 Pin +------------------------------- + +Diagram of the 26 GPIO Pins of the Raspberry Pi Model B (for the Model +B+ with 40 pins, start counting from the right and leave 14 pins): + +![](https://av.libreboot.org/rpi/0012.png) ![](https://av.libreboot.org/rpi/0013.png) + +Use this as a reference for the other sections in this page, seen below: + +SOIC8/DIP8/WSON8 wiring diagram +------------------------------- + +Refer to this diagram: + + Pin \# 25xx signal RPi(GPIO) BBB(P9 header) + ------ ----------- ---------- -------------- + 1 CS 24 17 + 2 MISO 21 21 + 3 *not used* *not used* *not used* + 4 GND 25 1 + 5 MOSI 19 18 + 6 CLK 23 22 + 7 *not used* *not used* *not used* + 8 VCC 1 3 + +On your SOIC8, there will be a dot in one of the corners. The dot is pin 1. + +NOTE: pins 3 and 7 are WP/HOLD pins. If flashing a chip on a breadboard, please +use pull-up resistors on those (see notes below), and decoupling capacitor on +pin 8 (VCC). + +NOTE: On X60/T60 thinkpads, don't connect pin 8. Instead, plug in your the PSU +to the charging port on your mainboard, but do not power on the mainboard. This +will provide a stable 3.3V voltage, with adequate current levels. On those +laptops, this is necessary because the flash shares a common 3.3V DC rail with +many other ICs that all draw quite a lot of current. + +SOIC16 wiring diagram (Raspberry Pi) +------------------------------------ + +RPi GPIO header:\ +![](https://av.libreboot.org/rpi/0009.png) +![](https://av.libreboot.org/rpi/0010.png) + +BBB P9 header:\ + + +Refer to this diagram: + + Pin \# 25xx signal RPi(GPIO) BBB(P9 header) + -------- -------------- ----------- -------------- + 1 *not used* *not used* *not used* + 2 VCC 1 3 + 3 *not used* *not used* *not used* + 4 *not used* *not used* *not used* + 5 *not used* *not used* *not used* + 6 *not used* *not used* *not used* + 7 CS\# 24 17 + 8 MISO 21 21 + 9 *not used* *not used* *not used* + 10 GND 25 1 + 11 *not used* *not used* *not used* + 12 *not used* *not used* *not used* + 13 *not used* *not used* *not used* + 14 *not used* *not used* *not used* + 15 MOSI 19 18 + 16 SCLK 23 22 + +Refer to the RPi GPIO guide above, on this page. + +On your SOIC16, there will be a dot in one of the corners. The dot is pin 1. + +NOTE: pins 1 and 9 are WP/HOLD pins. If flashing a chip on a breadboard, please +use pull-up resistors on those (see notes below), and decoupling capacitor on +pin 2 (VCC). + +Pull-up resistors and decoupling capacitors +------------------------------------------- + +**Do this for chips mounted to a breadboard. Ignore this section if you're +flashing a chip that is already soldered to a mainboard.** + +This section is only relevant if you're flashing a new chip that is not yet +mounted to a mainboard. You need pull-up resistors on the WP and HOLD pins, +and decoupling capacitors on the VCC pin. If the chip is already mounted to a +board, whether soldered or in a socket, these capacitors and resistors will +probably already exist on the board and you can just flash it without pulling +WP/HOLD high, and without capacitors(just connect your external power source). + +The best way is as follows: + +* Insert the DIP8 IC into a breadboard (2.54mm holes), if it's DIP8 +* Insert WSON8 into a WSON8 socket and put on a breadboard, if WSON8 +* Insert SOIC8 into a SOIC8 socket and put on a broadboard, if SOIN8 +* Wire an SPI flasher, using 2.54mm dupont leads, to the breadboard, using + the correct wiring (see link to SPI flashing guides below) + +SOIC8/WSON8/DIP8: pin 3 and 7 must be held to a high logic state, which means +that each pin has its own pull-up resistor to VCC (from the voltage plane that +pin 8 connects to); anything from 1Kohm to 10Kohm will do. When you're flashing +a chip that's already on a laptop/desktop/server mainboard, pin 3 and 7 are +likely already held high, so you don't need to bother. + +SOIC8/WSON8/DIP8: pin 8, which is VCC, will already have decoupling capacitors on it +if the chip is on a mainboard, but lone chip flashing means that these capacitors +do not exist. A capacitor passes AC but blocks DC. Due to electromagnetic +indunctance, and RF noise from high-speed switching ICs, a DC voltage line isn't +actually straight (when viewed on an oscilloscope), but actually has low voltage +AC mixed in; on a particularly noisy line under high load, noise of around 300mV +or more is common. To smooth out that noise, you wire capacitors from the DC +line to ground, with the side of the capacitor on VCC as close to the IC's VCC +pin as possible. We recommend that you use ceramic capacitors for this purpose. +The recommended capacitors for this are: 100nF and 4.7uF ceramic capacitors. +Electrolytic capacitors are inferior for this, because they have higher ESR +(ceramic capacitors have super low ESR, which is very good for decoupling). + +The result of using a decoupling capacitor is that some of the noise on the DC +line is filtered to ground, making the DC signal much cleaner/straighter (when +seen on an oscilloscope). + +SOIC16: same as above, but use a SOIC16 socked on a breadboard. On SOIC16, +WP/HOLD are not pin 3/7 like above, but instead pins 1 and 9, so wire your +pull-up resistors on those. VCC on SOIC16 is pin 2, so wire your decoupling +capacitors up on that. + +SOIC8/WSON8/DIP8/SOIC16 not mounted to a mainboard +-------------------------------------------------- + +If your system has lower capacity SPI flash, you can upgrade. On *most* systems, +SPI flash is memory mapped and the maximum (in practise) that you can use is a +16MiB chip. For example, KGPE-D16 and KCMA-D8 mainboards in libreboot have +2MiB flash by default, but you can easily upgrade these. Another example is the +ThinkPad X200S, X200 Tablet and T400S, all of which have WSON8 where the best +course of action is to replace it with a SOIC8 flash chip. + +In all such cases, flashing a new chip should be done using a breadboard, not +a test clip. You will use 2.54mm dupont leads to connect your Raspberry Pi. +For data lines, make sure that all wires are the same length, and about 10cm +in length (don't use longer lengths than this). + +Some advice: + +* DIP8: Strong choice is Winbond W25Q128FVIQ. It is a direct drop-in replacement +* SOIC8 is possible: Winbond W25Q128FVSIG is a strong choice. +* DIP8 using adapter and SOIC8 is also possible. Use a 208-mil 1.27mm SOP8/SOIC8 + to DIP8 adapter PCB with a + 2.54mm 4-pin header on each side (square pins), then you can slot that in as + though it were a normal P-DIP 8 IC. This page shows a perfect example: + +* The above SOP8/DIP8 adapter is actually what we recommend, if you're going + that route. It's made by Sparkfun and widely available; you don't have to buy + from that particular website. The part number is: BOB-13655 +* If you use a SOP/DIP adapter with a SOIC8 IC, you'll have to solder it + obviously. K tip is a nice choice for soldering ICs like these. Use good + flux and 60/40 leaded solder (or 63/37), none of that Rohs lead-free crap. + +If you go for a SOIC8, mounted it to the SOP to DIP adapter (208mil 1.27mm one) +and solder 2.54mm headers to it. You could put the 2.54mm pins in a breadboard, +then solder the chip to the adapter PCB and mount that to the pins on the +breadboard, to keep it aligned, and solder that. Whith the PCB on the pins, and +the pins in the breadboard, push the pins inwards a little bit. + +This is for a new SOIC8 chip, but you can get sockets similar to the one in the +video, but for WSON8. Sometimes they are called DFN8 or QFN8 sockets. Get one +that is 1.27mm pitch. + +If you're flashing/dumping a lone WSON8, get a WSON8/QFN8/DFN8 socket (1.27mm +pitch) and mount it to a breadboard for flashing. If your mainboard's landing +pads for the flash IC can take a SOIC8, we recommend that you use a SOIC8 +instead because a test clip is possible later on when you wish to re-flash it, +however you may be dealing with a board where replacing existing WSON8 with +SOIC8 is desirable; in that case, you might still want to dump the contents of +the original WSON8. + +Here is a SOIC8 in a socket, mounted to a breadboard, for flashing:\ +![](https://av.libreboot.org/rpi/soic8_socket.jpg) + +Here is a photo of a DIP8 IC:\ +![](https://av.libreboot.org/dip8/dip8.jpg) + +Here is a photo of a SOIC8 in 1.27mm 208mil SOP to DIP adapter:\ +![](https://av.libreboot.org/dip8/sop8todip8.jpg) + +NOTE: DIP8 and WSON8-in-socket, and SOIC16-in-socket, are basically the same, +just adapt accordingly. + +If you're replacing a DIP8 but using SOIC8 on an adapter, solder it to the +adapter first, then insert 2.54mm headers (square pins) into a breadboard to +keep them aligned. Put the SOIC8 on the PCB, onto the pins, and push the pins +inwards a little bit, and solder that. Alternatively to the breadboard, you +can just put the 2.54mm pins directly in the DIP8 socket and mount the SOIC8 + +adapter onto that, and solder that. Use quality rosin flux (not acid based) +and good 60/40 or 63/37 leaded solder (don't use lead-free): + +![](https://av.libreboot.org/dip8/adapter_breadboard.jpg) +![](https://av.libreboot.org/dip8/adapter.jpg) +![](https://av.libreboot.org/dip8/sop8todip8.jpg) + +SOIC8/SOIC16 soldered to a mainboard +------------------------------------ + +This is an example of *in-system programming* or *ISP* for short. + +SOIC8:\ +Pomona 5250 is a SOIC8 test clip. There are others available, but this is the +best one. Use that. Use the SOIC8 diagram (see above) to wire up your Raspberry +Pi. +Your mainboard likely already pulls WP/HOLD (pins 3 and 7) high, so don't +connect these. VCC on SOIC8's pin 8 probably already has decoupling +capacitors on the mainboard, so just hook that up without using a capacitor. + +SOIC16:\ +Pomona 5252 is a SOIC16 test clip. There are others available, but this is the +best one. Use that. Use the SOIC16 diagram (see above) to wire up your Raspberry +Pi. WP/HOLD pins are pins 1 and 9, and likely already held high, so no pull-up +resistors needed. You do not need a decoupling capacitor for pin 2 (VCC) either +because the mainboard will already have one. + +Here is an example of a test clip connected for SOIC16:\ +![](https://av.libreboot.org/rpi/0002.jpg) + +And here is an example photo for SOIC8:\ +![](https://av.libreboot.org/x60/th_bbb_flashing.jpg) + +DIP8 soldered to the mainboard +------------------------------ + +It is extremely cursed for DIP8 to be soldered directly to the mainboard. It is +usually mounted to a socket. + +The pins are large enough that you can just use test hooks to wire up your chip +for flashing. You might want to de-solder the chip, using a solder vacuum +(extractor) tool, and then you can install a socket in its place. You can then +insert the DIP8 IC into the socket. + +In the libreboot project, we have never heard of a board where the DIP8 is +directly soldered. It is almost always mounted in a socket. + +Your DIP8 IC has the same pinout as a SOIC8 IC. + +Replace WSON8 IC with SOIC8 +--------------------------- + +You *can* connect a SOIC8 test clip, but you will struggle to get good +connections and it will be extremely unreliable. DO NOT solder to the pads of +the WSON8 directly; some people do this, but you shouldn't do it, because you +can easily damage the pads that way. + +WSON8 has the same pinout as SOIC8, but it's a ball mounted QFN (quad flat +pack, no leads). There are no clips for it. Sometimes referred to as QFN8 + +On all currently supported libreboot hardware, boards that have WSON8 can also +have a SOIC8 because the pads are long enough to accomodate either type of +chip. + +A good choice of soldering iron would be a T12-D08 or T12-K tip, on a T12 +soldering station. KSGER makes nice soldering stations:\ + + +The case on that KSGER station is not grounded by default, so you should +modify it to ground the case, in case of an electrical fault. This is for your +safety. This video shows how to do it:\ + + +Use quality 60/40 or 63/37 lead+tin solder. Do not use lead-free! Lead-free is +not suitable for hobbyist use such as this. Use quality *rosin* flux. Fluxes +with an acid base should never be used. Amtech and MG Chemicals make good flux +pastes. Use it in a dispenser tube. Some of these fluxes will contain adapic +acid which has a low pH level, and it is simply used as a mild activator. So +long as you clean the flux afterwards, you should be fine. + +Make sure to have a copper wire brush and a wet sponge handy. You wipe the iron +on the wire brush and tap it on the wet sponge(to remove oxides) to keep it +clean. Always clean your tip constantly. Also, after cleaning it, always re-tin +the tip with fresh solder, to prevent the tip from oxidizing! + +Make sure to buy 99.9% isopropyl alcohol. Don't buy weaker solutions because +they contain water, and don't use other chemicals because most other chemicals +are corrosive. You use the isopropyl to clean the area you're soldering, before +soldering it, and then soak up the wet alcohol with a cloth. You will also use +it to clean off any flux that you used. + +Use of flux is very important, to get a good solder joint, because it removes +oxides and prevents further oxidation during soldering, ensuring that the solder +flows properly, otherwise the solder will ball up and you won't get a good +joint. + +In case you're not comfortable with soldering, we have some excellent videos +linked on the [FAQ page](../../faq.md) which you can watch. + +WSON8 IC:\ +![](https://av.libreboot.org/rpi/wson8/0001.jpg) + +Surround a large area around the chip with layers of kapton tape, and then +aluminium foil. This will act as a heat shield, to reduce the risk of re-flowing +other solder joints (which can make them turn into cold joints, and you risk +knocking them off of the board):\ +![](https://av.libreboot.org/rpi/wson8/0002.jpg)\ +Notice that the kapton+foil does not cover the chip itself, or the solder pads. +It's important that these are exposed to the heat. + +Use a hot air rework station, set to about 330-340C. The reason for the higher +temperature is because air doesn't conduct heat as efficiently as an iron, so +you must use a higher temperature. You should put lots of rosin flux above the +IC. Do not hold the nozel too close to the board. The diameter of the nozel +should be slightly higher than the length of the chip. Apply even heat, at high +air flow. + +While blasting the chip with hot air, hold the chip with tweezers but do not +use any real force. Do not try to forcefully pry off the chip. Simply hold the +chip with your tweezers, gently nudging it until it feels like the chip can +move freely. While in this state, the solder is fully melted and the chip can +be lifted off with ease. + +If you're doing it correctly, the chip will come off within 1 minute, like so:\ +![](https://av.libreboot.org/rpi/wson8/0003.jpg) + +Add fresh solder to the pads, including the thermal pad:\ +![](https://av.libreboot.org/rpi/wson8/0004.jpg) + +Now wick it out using a copper braid, dunked in rosin flux:\ +![](https://av.libreboot.org/rpi/wson8/0005.jpg) + +Ensure that all of the solder is removed:\ +![](https://av.libreboot.org/rpi/wson8/0006.jpg)\ +You will notice that one of the pads doesn't have all of the solder removed. +The pad on the top-left in this photo. This is intentional, to show you a +comparison for reference. The other pads are free of solder. + +You *can* simply solder the chip unflashed, and flash it using a test clip. +Alternatively, you can put the SOIC8 in a socket on a breadboard, and flash it +before soldering it. If you wish to dump the contents of the WSON8, you can +put the removed WSON8 in a socket on a breadboard and dump it using your +SPI flasher. + +Align the new SOIC8, and tack it in the corner pins. Then solder it fully. Use +lots of flux!\ +![](https://av.libreboot.org/rpi/wson8/0007.jpg)\ +A T12-D08 tip is being used in this photo, but a mini chisel, mini hoof or +knife (e.g. T12-K) tip would be ideal. + +Ensure that all the joints are perfect. A good solder joint is shiny, and with +concave fillets where the solder has flowed. Observe:\ +![](https://av.libreboot.org/rpi/wson8/0008.jpg) + +After you're done, use a soft bristle brush and 99.9% isopropyl alcohol to +break up the remaining flux, then soak up the flux using a cloth, while the +alcohol is still wet. 99.9% isopropyl is the best liquid to use, because it +evaporates quickly and it does not leave a corrosive residue. + +------------------------------------------------------------------------------- + +LICENSING +========= + +This page is released under different copyright terms than most other pages +on this website. + +This page and the photos on it are available under +[CC BY SA 4.0](https://creativecommons.org/licenses/by-sa/4.0/legalcode.txt) +Check the Git repository for history of who owns what part of the document. + +Some of these resources originate from the *old* Libreboot git repository, +before Libreboot split into separate repositories that include its `lbmk` +repository. + +Photos showing a BeagleBone Black are under the normal GNU Free Documentation +license like other pages and images on this website, or you can use them under +the CC-BY-SA 4.0 license if you wish (I, Leah Rowe, own all BBB photos shown +on this page, except for the one on the beaglebone website, and that one is +merely linked here, instead of being hosted on the av.libreboot.org server). + +This version of the page is hosted in the `lbwww` git repository, with images +for it hosted in the `lbwww-img` repository (from libreboot). diff --git a/site/docs/install/spi_generic.md b/site/docs/install/spi_generic.md new file mode 100644 index 0000000..bc6525c --- /dev/null +++ b/site/docs/install/spi_generic.md @@ -0,0 +1,103 @@ +--- +title: Generic SPI Flashing Guide +x-toc-enable: true +... + +There are a plethora of single board computers with which you can flash libreboot to a SOIC chip. +Some users might be daunted by the price of a raspberry pi. +This guide is intended to help users looking to use a programmer which is not listed in the [main guide.](spi.md) +As an example, this guide will use the [libre computer 'le potato.'](https://libre.computer/products/aml-s905x-cc/) +You should note however, that this guide is intended to demonstrate how to set up any SBC with SPI programming capabilities for flashing libreboot. + +If you are wondering about which SBC to buy, keep these things in mind: + ++ The board *must* support SPI (look at the specs/pinout to find out if it does) ++ It is easier to use a board that supports raspbian/raspberry pi OS ++ Boards often require their own kernel patches which rarely get upstreamed + +All of this means that you should try to find a board that is *known* to support SPI on an OS for which there are available images. +It is *not* enough to know that the board itself supports SPI. + +Selecting an Operating System +============================= + +In theory, any linux based operating system will do. +In practice, many distros are highly limited when it comes to single-board-computers. +SBCs often require specialized kernel patches which are rarely upstreamed. +Additionally, armhf boards (like the le potato) are not supported in most modern distros. + +In light of the above facts, it is a good general rule to use a distro aimed at supporting SBCs. +[Armbian](https://www.armbian.com/) is one such distro you might use. +Note that not all armbian images support SPI. +If your SBC supports [Raspbian](https://www.raspberrypi.com/software/) then using it will make your work much easier. +As a bonus, you may refer to the [main guide](spi.md) if the SBC you have supports raspbian, should you get confused with this guide. + +Connecting to your Programmer +============================= + +Many SBC operating systems enable ssh by default. +If the OS you chose does not enable ssh on first boot, try checking the distro documentation and looking for terms such as 'headless install.' + +You will need the IP address of your programmer to continue. +Connecting via ethernet is generally easier than doing so with WiFi. +Check your distro's docs if you wish to connect with WiFi only. +To determine the IP address of your programmer, log in to your AP/Router web interface. +If you're not sure the IP address of your AP, it is likely `192.168.1.1.` +You can determine the correct IP address with `ip r` on a linux machine. +You should see your programmer somewhere on the homepage, depending on your router firmware. +This author recommends using [https://openwrt.org/](https://openwrt.org/) for your router firmware. + +SSH to your programmer using the default credentials as specified in your distro's docs. +The IP address is the one determined in the earlier step. +For example: + +`ssh root@192.168.0.167` + +Finding GPIO Pins +================= + +If you have determined that a board supports SPI then the only step left is to +determine the correct location of the SPI pins. +The board will have the pinout in its documentation. +The Le potato board has the same pinout as the raspberry pi so you can refer to the [main SPIC documentation.](spi.md#gpio-pins-on-raspberry-pi-rpi-40-pin) + +If your board is not raspberry pi compatible, refer to the [wiring table.](spi.html#soic8dip8wson8-wiring-diagram) +Match each of the categories in the 'signal' column with those in the 'pin' column. +Using this method, you can theoretically use any single board computer with SPI support. + +Enabling SPI +============ + +The modules needed and methods to enable SPI vary based on the SBC you choose. +You should always make sure there is a well documented method for enabling SPI on your SBC before purchasing. +In the case of the *le potato,* SPI is enabled by activating the correct overlays as such (raspbian): + +``` +sudo ldto enable spicc spicc-spidev +sudo ldto merge spicc spicc-spidev +``` + +Using Flashrom +============== + +Most linux distros will provide flashrom in their default repositories. +You can also download flashrom in binary form with [libreboot utils.](https://libreboot.org/download.html#https) +Here is an example using raspbian: + +``` +sudo apt update +sudo apt install flashrom +``` + +Reading/writing from SPI works respectively as such: + +``` +sudo ./flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=32768 -r /path/to/read.bin +sudo ./flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=32768 -w /path/to/libreboot.rom +``` + +Note that `spispeed` varies based on the board in question. +A standard lower limit is *512.* +For example, to read on a board with a lower SPI speed, you may try: + + sudo ./flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r /path/to/read.bin diff --git a/site/docs/install/t400_external.md b/site/docs/install/t400_external.md new file mode 100644 index 0000000..3bcb9fe --- /dev/null +++ b/site/docs/install/t400_external.md @@ -0,0 +1,235 @@ +--- +title: Flashing the ThinkPad T400 externally +x-toc-enable: true +... + +Dell Latitude E6400 +=================== + +**If you haven't bought an T400 yet: the [Dell Latitude +E6400](../../news/e6400.md) is much easier to flash; no disassembly required, +it can be flashed entirely in software from Dell BIOS to Libreboot. It is the +same hardware generation (GM45), with same CPUs, video processor, etc.** + +Introduction +============ + +Initial flashing instructions for T400. + +This guide is for those who want libreboot on their ThinkPad T400 while +they still have the original Lenovo BIOS present. This guide can also be +followed (adapted) if you brick your T400, to know how to recover. + +An +["HMM"](https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/43y6629_05.pdf#page=386) +(Hardware Maintenance Manual) detailing the process of [dis]assembly +is available for this model. Be careful when reassembling the laptop as +the screws on page 114 (with title "1130 Keyboard bezel") are swapped +and if you follow the HMM you will punch a hole through the bezel in the +upper right corner. + +Serial port {#serial_port} +----------- + +EHCI debug might not be needed. It has been reported that the docking +station for this laptop has a serial port, so it might be possible to +use that instead. + +A note about CPUs +================= + +[ThinkWiki](http://www.thinkwiki.org/wiki/Category:T400) has a list of +CPUs for this system. The Core 2 Duo P8400, P8600 and P8700 are believed +to work in libreboot. + +T9600, T9500, T9550 and T9900 are all compatible, as reported by users. + +Quad-core CPUs +-------------- + +Very likely to be compatible, but requires hardware modification. +Based on info from German forum post about installing Core Quad CPU on T500 found in coreboot mailing list. Currently work in progress and no guide available. + +- [Coreboot mailing list post](https://mail.coreboot.org/pipermail/coreboot/2016-November/082463.html) +- [German forum post about install Core Quad on T500](https://thinkpad-forum.de/threads/199129) + + +A note about GPUs +================= + +Some models have an Intel GPU, while others have both an ATI and an +Intel GPU; this is referred to as "switchable graphics". In the *BIOS +setup* program for lenovobios, you can specify that the system will use +one or the other (but not both). + +libreboot is known to work on systems with only the Intel GPU, using +native graphics initialization. On systems with switchable graphics, the +Intel GPU is used and the ATI GPU is disabled, so native graphics +initialization works all the same. + +CPU paste required +================== + +See [\#paste](#paste). + +Flash chip size {#flashchips} +=============== + +Use this to find out: + + flashrom -p internal + +MAC address {#macaddress} +=========== + +Refer to [mac\_address.md](../hardware/mac_address.md). + +How to flash externally +========================= + +Refer to [spi.md](spi.md) as a guide for external re-flashing. + +The procedure +------------- + +Remove *all* screws, placing them in the order that you removed them:\ +![](https://av.libreboot.org/t400/0001.jpg) ![](https://av.libreboot.org/t400/0002.jpg) + +Remove those three screws then remove the rear bezel:\ +![](https://av.libreboot.org/t400/0003.jpg) ![](https://av.libreboot.org/t400/0004.jpg) +![](https://av.libreboot.org/t400/0005.jpg) ![](https://av.libreboot.org/t400/0006.jpg) + +Remove the speakers:\ +![](https://av.libreboot.org/t400/0007.jpg) ![](https://av.libreboot.org/t400/0008.jpg) +![](https://av.libreboot.org/t400/0009.jpg) ![](https://av.libreboot.org/t400/0010.jpg) +![](https://av.libreboot.org/t400/0011.jpg) + +Remove the wifi:\ +![](https://av.libreboot.org/t400/0012.jpg) ![](https://av.libreboot.org/t400/0013.jpg) + +Remove this cable:\ +![](https://av.libreboot.org/t400/0014.jpg) ![](https://av.libreboot.org/t400/0015.jpg) +![](https://av.libreboot.org/t400/0016.jpg) ![](https://av.libreboot.org/t400/0017.jpg) +![](https://av.libreboot.org/t400/0018.jpg) + +Unroute those antenna wires:\ +![](https://av.libreboot.org/t400/0019.jpg) ![](https://av.libreboot.org/t400/0020.jpg) +![](https://av.libreboot.org/t400/0021.jpg) ![](https://av.libreboot.org/t400/0022.jpg) +![](https://av.libreboot.org/t400/0023.jpg) + +Remove the LCD assembly:\ +![](https://av.libreboot.org/t400/0024.jpg) ![](https://av.libreboot.org/t400/0025.jpg) +![](https://av.libreboot.org/t400/0026.jpg) ![](https://av.libreboot.org/t400/0027.jpg) +![](https://av.libreboot.org/t400/0028.jpg) ![](https://av.libreboot.org/t400/0029.jpg) +![](https://av.libreboot.org/t400/0030.jpg) ![](https://av.libreboot.org/t400/0031.jpg) + +Disconnect the NVRAM battery:\ +![](https://av.libreboot.org/t400/0033.jpg) + +Disconnect the fan:\ +![](https://av.libreboot.org/t400/0034.jpg) + +Unscrew these:\ +![](https://av.libreboot.org/t400/0035.jpg) ![](https://av.libreboot.org/t400/0036.jpg) +![](https://av.libreboot.org/t400/0037.jpg) ![](https://av.libreboot.org/t400/0038.jpg) + +Unscrew the heatsink, then lift it off:\ +![](https://av.libreboot.org/t400/0039.jpg) ![](https://av.libreboot.org/t400/0040.jpg) + +Disconnect the power jack:\ +![](https://av.libreboot.org/t400/0041.jpg) ![](https://av.libreboot.org/t400/0042.jpg) + +Loosen this:\ +![](https://av.libreboot.org/t400/0043.jpg) + +Remove this:\ +![](https://av.libreboot.org/t400/0044.jpg) ![](https://av.libreboot.org/t400/0045.jpg) +![](https://av.libreboot.org/t400/0046.jpg) ![](https://av.libreboot.org/t400/0047.jpg) +![](https://av.libreboot.org/t400/0048.jpg) + +Unscrew these:\ +![](https://av.libreboot.org/t400/0049.jpg) ![](https://av.libreboot.org/t400/0050.jpg) + +Remove this:\ +![](https://av.libreboot.org/t400/0051.jpg) ![](https://av.libreboot.org/t400/0052.jpg) + +Unscrew this:\ +![](https://av.libreboot.org/t400/0053.jpg) + +Remove the motherboard (the cage is still attached) from the right hand +side, then lift it out:\ +![](https://av.libreboot.org/t400/0054.jpg) ![](https://av.libreboot.org/t400/0055.jpg) +![](https://av.libreboot.org/t400/0056.jpg) + +Remove these screws, placing the screws in the same layout and marking +each screw hole (so that you know what ones to put the screws back into +later): ![](https://av.libreboot.org/t400/0057.jpg) ![](https://av.libreboot.org/t400/0058.jpg) +![](https://av.libreboot.org/t400/0059.jpg) ![](https://av.libreboot.org/t400/0060.jpg) +![](https://av.libreboot.org/t400/0061.jpg) ![](https://av.libreboot.org/t400/0062.jpg) + +Separate the motherboard:\ +![](https://av.libreboot.org/t400/0063.jpg) ![](https://av.libreboot.org/t400/0064.jpg) + +Connect your programmer, then connect GND and 3.3V\ +![](https://av.libreboot.org/t400/0065.jpg) ![](https://av.libreboot.org/t400/0066.jpg) +![](https://av.libreboot.org/t400/0067.jpg) ![](https://av.libreboot.org/t400/0069.jpg) +![](https://av.libreboot.org/t400/0070.jpg) ![](https://av.libreboot.org/t400/0071.jpg) + +A dedicated 3.3V PSU was used to create this guide, but at ATX PSU is +also fine:\ +![](https://av.libreboot.org/t400/0072.jpg) + +Of course, make sure to turn on your PSU:\ +![](https://av.libreboot.org/x200/disassembly/0013.jpg) + +Now, you should be ready to install libreboot. + +Refer to the external flashing instructions [here](spi.md), and when you're +done, re-assemble your laptop. + +Thermal paste (IMPORTANT) +========================= + +Because part of this procedure involved removing the heatsink, you will +need to apply new paste. Arctic MX-4 is ok. You will also need isopropyl +alcohol and an anti-static cloth to clean with. + +When re-installing the heatsink, you must first clean off all old paste +with the alcohol/cloth. Then apply new paste. Arctic MX-4 is also much +better than the default paste used on these systems. + +![](https://av.libreboot.org/t400/paste.jpg) + +NOTE: the photo above is for illustration purposes only, and does not +show how to properly apply the thermal paste. Other guides online detail +the proper application procedure. + +Memory +====== + +In DDR3 machines with Cantiga (GM45/GS45/PM45), northbridge requires sticks +that will work as PC3-8500 (faster PC3/PC3L sticks can work as PC3-8500). +Non-matching pairs may not work. Single module (meaning, one of the slots +will be empty) will currently only work in slot 0. + +NOTE: according to users reports, non matching pairs (e.g. 1+2 GiB) might +work in some cases. + +Make sure that the RAM you buy is the 2Rx8 configuration when buying 4GiB sticks +(In other words: maximum of 2GiB per rank, 2 ranks per card). + +[This page](http://www.forum.thinkpads.com/viewtopic.php?p=760721) might +be useful for RAM compatibility info (note: coreboot raminit is +different, so this page might be BS) + +The following photo shows 8GiB (2x4GiB) of RAM installed:\ +![](https://av.libreboot.org/t400/memory.jpg) + +Boot it! +-------- + +You should see something like this: + +![](https://av.libreboot.org/t400/boot0.jpg) ![](https://av.libreboot.org/t400/boot1.jpg) + +Now [install Linux](../linux/). diff --git a/site/docs/install/t500_external.md b/site/docs/install/t500_external.md new file mode 100644 index 0000000..0e44599 --- /dev/null +++ b/site/docs/install/t500_external.md @@ -0,0 +1,266 @@ +--- +title: ThinkPad T500 external flashing +x-toc-enable: true +... + +**If you haven't bought a T500 yet: the [Dell Latitude +E6400](../../news/e6400.md) is much easier to flash; no disassembly required, +it can be flashed entirely in software from Dell BIOS to Libreboot. It is the +same hardware generation (GM45), with same CPUs, video processor, etc.** + +Initial flashing instructions for T500. + +This guide is for those who want libreboot on their ThinkPad T500 while +they still have the original Lenovo BIOS present. This guide can also be +followed (adapted) if you brick your T500, to know how to recover. + +W500 is also mostly compatible with this guide. + +Serial port {#serial_port} +----------- + +EHCI debug might not be needed. It has been reported that the docking +station for this laptop has a serial port, so it might be possible to +use that instead. + +A note about CPUs +================= + +[ThinkWiki](http://www.thinkwiki.org/wiki/Category:T500) has a list of +CPUs for this system. The Core 2 Duo P8400, P8600 and P8700 are believed +to work in libreboot. The T9600 was also tested on the T400 and +confirmed working. + +T9550 and T9900 was tested by a user, and is compatible as reported in the IRC channel. +T9500 and T9400 may also work, but YMMV. + +Quad-core CPUs +-------------- +Very likely to be compatible, but requires hardware modification. +Based on info from German forum post about installing Core Quad CPU on T500 found in coreboot mailing list. Currently work in progress and no guide available. + +Q9100 is compatible and confirmed working (after hw mod), as reported by users in the IRC +channel + +- [Coreboot mailing list post](https://mail.coreboot.org/pipermail/coreboot/2016-November/082463.html) +- [German forum post about install Core Quad on T500](https://thinkpad-forum.de/threads/199129) + +This video from FrostKiwi (Libera IRC) does a nice illustration and explains +everything nicely: + + + +A note about GPUs +================= + +Some models have an Intel GPU, while others have both an ATI and an +Intel GPU; this is referred to as "switchable graphics". In the *BIOS +setup* program for lenovobios, you can specify that the system will use +one or the other (but not both). + +libreboot is known to work on systems with only the Intel GPU, using +native graphics initialization. On systems with switchable graphics, the +Intel GPU is used and the ATI GPU is disabled, so native graphics +initialization works all the same. + +CPU paste required +================== + +See [\#paste](#paste). + +Flash chip size {#flashchips} +=============== + +Use this to find out: + + flashrom -p internal + +MAC address {#macaddress} +=========== + +Refer to [mac\_address.md](../hardware/mac_address.md). + +Clip wiring +=========== + +Refer to [spi.md](spi.md) as a guide for external re-flashing. + +The procedure +------------- + +Remove all screws:\ +![](https://av.libreboot.org/t500/0000.jpg)\ +It is also advisable to, throughout the disassembly, place any screws +and/or components that you removed in the same layout or arrangement. +The follow photos demonstrate this:\ +![](https://av.libreboot.org/t500/0001.jpg) ![](https://av.libreboot.org/t500/0002.jpg) + +Remove the HDD/SSD and optical drive:\ +![](https://av.libreboot.org/t500/0003.jpg) ![](https://av.libreboot.org/t500/0004.jpg) + +Remove the palm rest:\ +![](https://av.libreboot.org/t500/0005.jpg) ![](https://av.libreboot.org/t500/0006.jpg) + +Remove the keyboard and rear bezel:\ +![](https://av.libreboot.org/t500/0007.jpg) ![](https://av.libreboot.org/t500/0008.jpg) +![](https://av.libreboot.org/t500/0009.jpg) ![](https://av.libreboot.org/t500/0010.jpg) +![](https://av.libreboot.org/t500/0011.jpg) ![](https://av.libreboot.org/t500/0012.jpg) + +If you have a WWAN/3G card and/or sim card reader, remove them +permanently. The WWAN-3G card has proprietary firmware inside; the +technology is identical to what is used in mobile phones, so it can also +track your movements:\ +![](https://av.libreboot.org/t500/0013.jpg) ![](https://av.libreboot.org/t500/0017.jpg) +![](https://av.libreboot.org/t500/0018.jpg) + +Remove this frame, and then remove the wifi chip:\ +![](https://av.libreboot.org/t500/0014.jpg) ![](https://av.libreboot.org/t500/0015.jpg) +![](https://av.libreboot.org/t500/0016.jpg) + +Remove the speakers:\ +![](https://av.libreboot.org/t500/0019.jpg) ![](https://av.libreboot.org/t500/0020.jpg) +![](https://av.libreboot.org/t500/0021.jpg) ![](https://av.libreboot.org/t500/0022.jpg) +![](https://av.libreboot.org/t500/0023.jpg) ![](https://av.libreboot.org/t500/0024.jpg) +![](https://av.libreboot.org/t500/0025.jpg) + +Remove the NVRAM battery (already removed in this photo):\ +![](https://av.libreboot.org/t500/0026.jpg) + +When you re-assemble, you will be replacing the wifi chip with another. +These two screws don't hold anything together, but they are included in +your system because the screw holes for half-height cards are a +different size, so use these if you will be installing a half-height +card:\ +![](https://av.libreboot.org/t500/0027.jpg) + +Unroute the antenna wires:\ +![](https://av.libreboot.org/t500/0028.jpg) ![](https://av.libreboot.org/t500/0029.jpg) +![](https://av.libreboot.org/t500/0030.jpg) ![](https://av.libreboot.org/t500/0031.jpg) + +Disconnect the LCD cable from the motherboard:\ +![](https://av.libreboot.org/t500/0032.jpg) ![](https://av.libreboot.org/t500/0033.jpg) + +Remove the LCD assembly hinge screws, and then remove the LCD assembly:\ +![](https://av.libreboot.org/t500/0034.jpg) ![](https://av.libreboot.org/t500/0035.jpg) +![](https://av.libreboot.org/t500/0036.jpg) + +Remove the fan and heatsink:\ +![](https://av.libreboot.org/t500/0037.jpg) ![](https://av.libreboot.org/t500/0038.jpg) +![](https://av.libreboot.org/t500/0039.jpg) + +Remove this screw:\ +![](https://av.libreboot.org/t500/0040.jpg) + +Remove these cables, keeping note of how and in what arrangement they +are connected:\ +![](https://av.libreboot.org/t500/0041.jpg) ![](https://av.libreboot.org/t500/0042.jpg) +![](https://av.libreboot.org/t500/0043.jpg) ![](https://av.libreboot.org/t500/0044.jpg) +![](https://av.libreboot.org/t500/0045.jpg) ![](https://av.libreboot.org/t500/0046.jpg) +![](https://av.libreboot.org/t500/0047.jpg) ![](https://av.libreboot.org/t500/0048.jpg) +![](https://av.libreboot.org/t500/0049.jpg) + +Disconnect the power jack:\ +![](https://av.libreboot.org/t500/0050.jpg) ![](https://av.libreboot.org/t500/0051.jpg) + +Remove the motherboard and cage from the base (the marked hole is where +those cables were routed through):\ +![](https://av.libreboot.org/t500/0052.jpg) ![](https://av.libreboot.org/t500/0053.jpg) + +Remove all screws, arranging them in the same layout when placing the +screws on a surface and marking each screw hole (this is to reduce the +possibility of putting them back in the wrong holes):\ +![](https://av.libreboot.org/t500/0054.jpg) ![](https://av.libreboot.org/t500/0055.jpg) + +Also remove this:\ +![](https://av.libreboot.org/t500/0056.jpg) ![](https://av.libreboot.org/t500/0057.jpg) + +Separate the motherboard from the cage:\ +![](https://av.libreboot.org/t500/0058.jpg) ![](https://av.libreboot.org/t500/0059.jpg) + +The flash chip is next to the memory slots. On this system, it was a +SOIC-8 (4MiB or 32Mb) flash chip:\ +![](https://av.libreboot.org/t500/0060.jpg) + +Connect your programmer, then connect GND and 3.3V\ +![](https://av.libreboot.org/t500/0061.jpg)\ +![](https://av.libreboot.org/t400/0067.jpg) ![](https://av.libreboot.org/t400/0069.jpg) +![](https://av.libreboot.org/t400/0070.jpg) ![](https://av.libreboot.org/t400/0071.jpg) + +Now flash Libreboot. + +Thermal paste (IMPORTANT) +========================= + +Because part of this procedure involved removing the heatsink, you will +need to apply new paste. Arctic MX-4 is ok. You will also need isopropyl +alcohol and an anti-static cloth to clean with. + +When re-installing the heatsink, you must first clean off all old paste +with the alcohol/cloth. Then apply new paste. Arctic MX-4 is also much +better than the default paste used on these systems. + +![](https://av.libreboot.org/t400/paste.jpg) + +NOTE: the photo above is for illustration purposes only, and does not +show how to properly apply the thermal paste. Other guides online detail +the proper application procedure. + +Wifi +==== + +The T500 typically comes with an Intel wifi chipset, which does not work +without proprietary software. For a list of wifi chipsets that work +without proprietary software, see +[../hardware/\#recommended\_wifi](../hardware/#recommended_wifi). + +Some T500 laptops might come with an Atheros chipset, but this is +802.11g only. + +It is recommended that you install a new wifi chipset. This can only be +done after installing libreboot, because the original firmware has a +whitelist of approved chips, and it will refuse to boot if you use an +'unauthorized' wifi card. + +The following photos show an Atheros AR5B95 being installed, to replace +the Intel chip that this T500 came with:\ +![](https://av.libreboot.org/t400/0012.jpg) ![](https://av.libreboot.org/t400/ar5b95.jpg) + +WWAN +==== + +If you have a WWAN/3G card and/or sim card reader, remove them +permanently. The WWAN-3G card has DMA, and proprietary firmware inside; +the technology is identical to what is used in mobile phones, so it can +also track your movements. + +Not to be confused with wifi (wifi is fine). + +Memory +====== + +In DDR3 machines with Cantiga (GM45/GS45/PM45), northbridge requires sticks +that will work as PC3-8500 (faster PC3/PC3L sticks can work as PC3-8500). +Non-matching pairs may not work. Single module (meaning, one of the slots +will be empty) will currently only work in slot 0. + +NOTE: according to users reports, non matching pairs (e.g. 1+2 GiB) might +work in some cases. + +Make sure that the RAM you buy is the 2Rx8 configuration when buying 4GiB sticks +(In other words: maximum of 2GiB per rank, 2 ranks per card). + +[This page](http://www.forum.thinkpads.com/viewtopic.php?p=760721) might +be useful for RAM compatibility info (note: coreboot raminit is +different, so this page might be BS) + +The following photo shows 8GiB (2x4GiB) of RAM installed:\ +![](https://av.libreboot.org/t400/memory.jpg) + +Boot it! +-------- + +You should see something like this: + +![](https://av.libreboot.org/t500/0062.jpg) + +Now [install Linux](../linux/). diff --git a/site/docs/install/t60_unbrick.md b/site/docs/install/t60_unbrick.md new file mode 100644 index 0000000..ffd9b7d --- /dev/null +++ b/site/docs/install/t60_unbrick.md @@ -0,0 +1,221 @@ +--- +title: ThinkPad T60 Recovery guide +x-toc-enable: true +... + +This section documents how to recover from a bad flash that prevents +your ThinkPad T60 from booting. + +This section documents how to recover from a bad flash that prevents +your ThinkPad X60 from booting. + +ROM images for this machine are well-tested in libreboot, so bricks are rare. +The most common cause of a brick is operator error, when flashing a ROM image. +In *most* cases, the cause will be that there is no bootblock, or an invalid +one. + +Brick type 1: bucts not reset. {#bucts_brick} +============================== + +You still have Lenovo BIOS, or you had libreboot running and you flashed +another ROM; and you had bucts 1 set and the ROM wasn't dd'd.\* or if +Lenovo BIOS was present and libreboot wasn't flashed. + +There are *2* 64KiB bootblocks possible, in the upper part of the ROM image. +By default (bucts set to 0), the top one is used. If bucts is set to 1, the +lower one (the one before the top one) is used. This bootblock is the first +code that executes, during *romstage* as per coreboot hardware initialization. + +BUC is short for *Backup Control* and TS is short for *Top Swap*. This is a +special register on Intel platforms. Lenovo BIOS sets PRx registers, preventing +software re-flashing, but there is a bug in the protection, allowing everything +*except* the upper 64KiB from being flashed. By default, coreboot only puts a +bootblock in the upper region. If you flash such a ROM, while bucts is set to 1, +the system won't boot because there's not a valid bootblock; this is common if +you're re-flashing when coreboot is already installed, and you didn't set bucts +back to 0. + +When you install on X60/T60 the first time, you set this bucts bit to 1, then +you re-flash a second time and set it back to 0. + +In this case, unbricking is easy: reset BUC.TS to 0 by removing that +yellow cmos coin (it's a battery) and putting it back after a minute or +two:\ +![](https://av.libreboot.org/t60_dev/0006.JPG) + +\*Those dd commands should be applied to all newly compiled T60 ROM +images (the ROM images in libreboot binary archives already have this +applied!): + + dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k + dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump + dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc + +(doing this makes the ROM suitable for use when flashing a system that +still has Lenovo BIOS running, using those instructions: +. (it says x60, +but instructions for t60 are identical) + +Brick type 2: bad ROM image {#recovery} +=========================================== + +In this instance, you might have flashed a ROM without the top bootblock copied +to the lower 64KiB section in the ROM, and you flashed the ROM for the first +time (from Lenovo BIOS), in which case there is not a valid bootblock. + +In this scenario, you compiled a ROM that had an incorrect +configuration, or there is an actual bug preventing your system from +booting. Or, maybe, you set BUC.TS to 0 and shut down after first flash +while Lenovo BIOS was running. In any case, your system is bricked and +will not boot at all. + +"Unbricking" means flashing a known-good (working) ROM. The problem: +you can't boot the system, making this difficult. In this situation, +external hardware (see hardware requirements above) is needed which can +flash the SPI chip (where libreboot resides). + +Remove those screws and remove the HDD:\ +![](https://av.libreboot.org/t60_dev/0001.JPG) ![](https://av.libreboot.org/t60_dev/0002.JPG) + +Lift off the palm rest:\ +![](https://av.libreboot.org/t60_dev/0003.JPG) + +Lift up the keyboard, pull it back a bit, flip it over like that and +then disconnect it from the board:\ +![](https://av.libreboot.org/t60_dev/0004.JPG) ![](https://av.libreboot.org/t60_dev/0005.JPG) +![](https://av.libreboot.org/t60_dev/0006.JPG) + +Gently wedge both sides loose:\ +![](https://av.libreboot.org/t60_dev/0007.JPG) ![](https://av.libreboot.org/t60_dev/0008.JPG) + +Remove that cable from the position:\ +![](https://av.libreboot.org/t60_dev/0009.JPG) ![](https://av.libreboot.org/t60_dev/0010.JPG) + +Now remove that bezel. Remove wifi, nvram battery and speaker connector +(also remove 56k modem, on the left of wifi):\ +![](https://av.libreboot.org/t60_dev/0011.JPG) + +Remove those screws:\ +![](https://av.libreboot.org/t60_dev/0012.JPG) + +Disconnect the power jack:\ +![](https://av.libreboot.org/t60_dev/0013.JPG) + +Remove nvram battery:\ +![](https://av.libreboot.org/t60_dev/0014.JPG) + +Disconnect cable (for 56k modem) and disconnect the other cable:\ +![](https://av.libreboot.org/t60_dev/0015.JPG) ![](https://av.libreboot.org/t60_dev/0016.JPG) + +Disconnect speaker cable:\ +![](https://av.libreboot.org/t60_dev/0017.JPG) + +Disconnect the other end of the 56k modem cable:\ +![](https://av.libreboot.org/t60_dev/0018.JPG) + +Make sure you removed it:\ +![](https://av.libreboot.org/t60_dev/0019.JPG) + +Unscrew those:\ +![](https://av.libreboot.org/t60_dev/0020.JPG) + +Make sure you removed those:\ +![](https://av.libreboot.org/t60_dev/0021.JPG) + +Disconnect LCD cable from board:\ +![](https://av.libreboot.org/t60_dev/0022.JPG) + +Remove those screws then remove the LCD assembly:\ +![](https://av.libreboot.org/t60_dev/0023.JPG) ![](https://av.libreboot.org/t60_dev/0024.JPG) +![](https://av.libreboot.org/t60_dev/0025.JPG) + +Once again, make sure you removed those:\ +![](https://av.libreboot.org/t60_dev/0026.JPG) + +Remove the shielding containing the motherboard, then flip it over. +Remove these screws, placing them on a steady surface in the same layout +as they were in before you removed them. Also, you should mark each +screw hole after removing the screw (a permanent marker pen will do), +this is so that you have a point of reference when re-assembling the +system: + +![](https://av.libreboot.org/t60_dev/0027.JPG) ![](https://av.libreboot.org/t60_dev/0028.JPG) +![](https://av.libreboot.org/t60_dev/0029.JPG) ![](https://av.libreboot.org/t60_dev/0031.JPG) +![](https://av.libreboot.org/t60_dev/0032.JPG) ![](https://av.libreboot.org/t60_dev/0033.JPG) + +This photo shows the flash chip, near the RAM, with numbers of pins written: + +![](https://av.libreboot.org/t60_dev/0030.JPG) + +Refer to the external flashing guide: + +[Externally rewrite 25xx NOR flash via SPI protocol](spi.md) + +NOTE: Do not use the 3.3v rail from your SPI programmer. Leave that disconnected. +For 3.3v, plug your charger into the mainboard (but do not power on the mainboard) +when the clip is connected. Before removing the clip, disconnect the charger. +This will provide adequate 3.3v DC at correct current levels. The SPI flash on an +X60 shares a common 3.3V rail with many other components on the mainboard, +which all draw a lot of current, more than your flasher can provide. + +Example command: + + sudo ./flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=4096 -w libreboot.rom -V + +If flashrom complains about multiple flash chips detected, just pass the `-c` +option as it suggests, and pick any of the chips it lists. `spispeed=4096` or +lower (e.g. `spispeed=512`) is recommended on this board. The flashing becomes +unstable, on this machine, when you use higher speeds. + +Reverse the steps to re-assemble your system, after you've flashed the chip. + +It should be `Verifying flash... VERIFIED` at the end. If flashrom +complains about multiple flash chip definitions detected, then choose +one of them following the instructions in the output. + +Put those screws back:\ +![](https://av.libreboot.org/t60_dev/0047.JPG) + +Put it back into lower chassis:\ +![](https://av.libreboot.org/t60_dev/0048.JPG) + +Attach LCD and insert screws (also, attach the lcd cable to the board):\ +![](https://av.libreboot.org/t60_dev/0049.JPG) + +Insert those screws:\ +![](https://av.libreboot.org/t60_dev/0050.JPG) + +On the CPU (and there is another chip south-east to it, sorry forgot to +take pic) clean off the old thermal paste (with the alcohol) and apply +new (Artic Silver 5 is good, others are good too) you should also clean +the heatsink the same way\ +![](https://av.libreboot.org/t60_dev/0051.JPG) + +Attach the heatsink and install the screws (also, make sure to install +the AC jack as highlighted):\ +![](https://av.libreboot.org/t60_dev/0052.JPG) + +Reinstall that upper bezel:\ +![](https://av.libreboot.org/t60_dev/0053.JPG) + +Do that:\ +![](https://av.libreboot.org/t60_dev/0054.JPG) ![](https://av.libreboot.org/t60_dev/0055.JPG) + +Re-attach modem, wifi, (wwan?), and all necessary cables. Sorry, forgot +to take pics. Look at previous removal steps to see where they go back +to. + +Attach keyboard and install nvram battery:\ +![](https://av.libreboot.org/t60_dev/0056.JPG) ![](https://av.libreboot.org/t60_dev/0057.JPG) + +Place keyboard and (sorry, forgot to take pics) reinstall the palmrest +and insert screws on the underside:\ +![](https://av.libreboot.org/t60_dev/0058.JPG) + +It lives!\ +![](https://av.libreboot.org/t60_dev/0071.JPG) ![](https://av.libreboot.org/t60_dev/0072.JPG) +![](https://av.libreboot.org/t60_dev/0073.JPG) + +Always stress test ('stress -c 2' and xsensors. below 90C is ok) when +replacing cpu paste/heatsink:\ +![](https://av.libreboot.org/t60_dev/0074.JPG) diff --git a/site/docs/install/x200_external.md b/site/docs/install/x200_external.md new file mode 100644 index 0000000..2a61d0b --- /dev/null +++ b/site/docs/install/x200_external.md @@ -0,0 +1,161 @@ +--- +title: First-time ThinkPad X200 flashing +x-toc-enable: true +... + +**If you haven't bought an X200 yet: the [Dell Latitude +E6400](../../news/e6400.md) is much easier to flash; no disassembly required, +it can be flashed entirely in software from Dell BIOS to Libreboot. It is the +same hardware generation (GM45), with same CPUs, video processor, etc.** + +This guide is for those who want libreboot on their ThinkPad X200 while +they still have the original Lenovo BIOS present. This guide can also be +followed (adapted) if you brick your X200, to know how to recover. + +If you have the original Lenovo firmware running, you will need to take the +keyboard and palmrest off so that you can access the flash chip, which is just +underneath the palm rest. You will then connect an external SPI programmer, to +re-flash the chip externally while it is powered off with the battery removed. + +NOTE: This guide only applies to the regular X200. For X200S and X200 Tablet +flashing, please read other guides available on libreboot.org. + +Flash chip size +=============== + +Run this command on x200 to find out flash chip model and its size: + + flashrom -p internal + +MAC address +=========== + +Refer to [mac\_address.md](../hardware/mac_address.md). + +The procedure +------------- + +This section is for the X200. This does not apply to the X200S or X200 +Tablet (for those systems, you have to remove the motherboard +completely, since the flash chip is on the other side of the board). + +Remove these screws:\ +![](https://av.libreboot.org/x200/disassembly/0003.jpg) + +Gently push the keyboard towards the screen, then lift it off, and optionally +disconnect it from the board:\ +![](https://av.libreboot.org/x200/disassembly/0004.jpg) +![](https://av.libreboot.org/x200/disassembly/0005.jpg) + +Disconnect the cable of the fingerpring reader, and then pull up the palm rest, +lifting up the left and right side of it:\ +![](https://av.libreboot.org/x200/disassembly/0006.1.jpg) +![](https://av.libreboot.org/x200/disassembly/0006.jpg) + +This shows the location of the flash chip, for both SOIC-8 and SOIC-16:\ +![](https://av.libreboot.org/x200/x200_soic16.jpg) +![](https://av.libreboot.org/x200/x200_soic8.jpg) + +Lift back the tape that covers a part of the flash chip, and then +connect the clip:\ +![](https://av.libreboot.org/x200/disassembly/0008.jpg) + +Now, you should be ready to install libreboot. + +Refer to the [SPI programming instructions](spi.md). + +When you're done, put the system back together. If it doesn't boot, try other +RAM modules because raminit is very unreliable on this platform (in coreboot). + +Memory +====== + +In DDR3 machines with Cantiga (GM45/GS45/PM45), northbridge requires sticks +that will work as PC3-8500 (faster PC3/PC3L sticks can work as PC3-8500). +Non-matching pairs may not work. Single module (meaning, one of the slots +will be empty) will currently only work in slot 0. + +NOTE: according to users reports, non matching pairs (e.g. 1+2 GiB) might +work in some cases. + +Make sure that the RAM you buy is the 2Rx8 configuration when buying 4GiB sticks +(In other words: maximum of 2GiB per rank, 2 ranks per card). + +In this photo, 8GiB of RAM (2x4GiB) is installed: + +![](https://av.libreboot.org/x200/disassembly/0018.jpg) + +Boot it! +-------- + +You should see something like this: + +![](https://av.libreboot.org/x200/disassembly/0019.jpg) + +Now [install Linux](../linux/). + +X200S and X200 Tablet users: GPIO33 trick will not work. +-------------------------------------------------------- + +sgsit found out about a pin called GPIO33, which can be grounded to +disable the flashing protections by the descriptor and stop the ME from +starting (which itself interferes with flashing attempts). The theory +was proven correct; however, it is still useless in practise. + +Look just above the 7 in TP37 (that's GPIO33): + +![](https://av.libreboot.org/x200/gpio33_location.jpg) + +By default we would see this in lenovobios, when trying flashrom -p +internal -w rom.rom: + +``` +FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. +FREG2: Warning: Management Engine region (0x00001000-0x005f5fff) is locked. +``` + +With GPIO33 grounded during boot, this disabled the flash protections as +set by descriptor, and stopped the ME from starting. The output changed +to: + +``` +The Flash Descriptor Override Strap-Pin is set. Restrictions implied by +the Master Section of the flash descriptor are NOT in effect. Please note +that Protected Range (PR) restrictions still apply. +``` + +The part in bold is what got us. This was still observed: + +``` +PR0: Warning: 0x007e0000-0x01ffffff is read-only. +PR4: Warning: 0x005f8000-0x005fffff is locked. +``` + +It is actually possible to disable these protections. Lenovobios does, +when updating the BIOS (proprietary one). One possible way to go about +this would be to debug the BIOS update utility from Lenovo, to find out +how it's disabling these protections. Some more research is available +here: + + +Of course, it's likely that the Lenovo BIOS is checking for some bit in memory +that tells it not to disable flashing, and then it won't set PRx registers. The +way the Lenovo BIOS updater works is, it is executed in Windows first and then +a reboot happens, triggering the re-flashing to happen during early boot. It is +probably setting something in memory and loading the ROM, plus a payload program +that does the flashing; Lenovo BIOS then probably sees that and runs that, instead +of setting PRx and going for normal boot. It is theoretically possible that we +could discover how this works, by debugging the Lenovo BIOS update utility (in +Windows), and then replicate what it is doing, with some tool for Linux, +then load a flashrom binary into memory and the ROM to flash (for the BIOS +region). You would do this with GPIO33 grounded, and the payload program would +actually flash the entire chip, with just a normal libreboot image. + +It's possible. The above is likely the only way that the Lenovo BIOS updater +program works. So if we discover precisely how to do that, then you could +just connect some pogo pins to ground GPIO33, then boot up, run some software +(which would have to be written) that does the above. + +On a related note, libreboot has a utility that could help with +investigating this: +[ich9utils.md#demefactory](ich9utils.md#demefactory) diff --git a/site/docs/install/x200_external.uk.md b/site/docs/install/x200_external.uk.md new file mode 100644 index 0000000..92cdbc4 --- /dev/null +++ b/site/docs/install/x200_external.uk.md @@ -0,0 +1,155 @@ +--- +title: Прошивка ThinkPad X200 вперше +x-toc-enable: true +... + +**If you haven't bought an X200 yet: the [Dell Latitude +E6400](../../news/e6400.md) is much easier to flash; no disassembly required, +it can be flashed entirely in software from Dell BIOS to Libreboot. It is the +same hardware generation (GM45), with same CPUs, video processor, etc.** + +Цей посібник призначений для тих, хто бажає libreboot на своєму ThinkPad X200, +поки у нього все ще є оригінальний Lenovo BIOS в наявності. Цього керівництва також можна +дотримуватися (адаптувати), якщо ви перетворили ваш X200 на цеглину, щоб знати, як його відновити. + +Якщо у вас виконується оригінальна мікропрограма Lenovo, вам потрібно буде зняти +клавіатуру та підставку для рук, щоб мати доступ до мікросхеми флеш-пам'яті, яка знаходиться прямо +під підставкою для рук. Потім ви підключите зовнішній програматор SPI, щоб +повторно прошити мікросхему зовні, коли вона вимкнена та акумулятор висунуто. + +ПРИМІТКА: Цей посібник стосується лише звичайного X200. Для перепрошивки X200S та X200 Tablet, +будь-ласка прочитайте інші посібники, доступні на libreboot.org. + +Розмір флеш-чіпа +=============== + +Виконайте цю команду на x200, щоб дізнатися модель флеш-чіпа та його розмір: + + flashrom -p internal + +MAC адреса +=========== + +Зверніться до [mac\_address.md](../hardware/mac_address.md). + +Процедура +------------- + +Цей розділ стосується X200. Цей не стосується X200S або X200 +Tablet (для цих систем потрібно повністю видалити материнську плату, +оскільки мікросхема флеш-пам'яті знаходиться з іншого боку плати). + +Викрутіть ці гвинти:\ +![](https://av.libreboot.org/x200/disassembly/0003.jpg) + +Обережно притисніть клавіатуру до екрана, потім підніміть її та за бажанням +від'єднайте від плати:\ +![](https://av.libreboot.org/x200/disassembly/0004.jpg) +![](https://av.libreboot.org/x200/disassembly/0005.jpg) + +Від'єднайте кабель пристрою для зчитування відбитків пальців, а потім потягніть упор для рук, +піднявши його ліву та праву сторону:\ +![](https://av.libreboot.org/x200/disassembly/0006.1.jpg) +![](https://av.libreboot.org/x200/disassembly/0006.jpg) + +Тут показано розташування мікросхеми флеш-пам'яті, для обох SOIC-8 та SOIC-16:\ +![](https://av.libreboot.org/x200/x200_soic16.jpg) +![](https://av.libreboot.org/x200/x200_soic8.jpg) + +Підніміть стрічку, яка закриває частину флеш-пам'яті, а потім +приєднайте затискач:\ +![](https://av.libreboot.org/x200/disassembly/0008.jpg) + +Тепер ви повинні бути готові до встановлення libreboot. + +Зверніться до [інструкцій програмування SPI](spi.md). + +Закінчивши, знову зберіть систему. Якщо вона не завантажується, спробуйте інші +модулі оперативної пам'яті, тому що raminit дуже ненадійний на цій платформі (в coreboot). + +Пам'ять +====== + +У машинах DDR3 з Cantiga (GM45/GS45/PM45), північний міст потребує стіків, +які працюватимуть як PC3-8500 (швидші стіки PC3/PC3L можуть працювати як PC3-8500). +Пари, що не збігаються, можуть не працювати. Один модуль (тобто один із слотів +буде порожнім) наразі працюватиме лише в слоті 0. + +ПРИМІТКА: згідно зі звітами користувачів, у деяких випадках невідповідні пари ( 1+2 ГБ) можуть +працювати в деяких випадках. + +Переконайтесь, що оперативна пам'ять, яку ви купуєте, має конфігурацію 2Rx8, купуючи стіки по 4 ГБ +(Іншими словами: максимально 2 ГБ на ранг, 2 ранга на картку). + +На цьому фото встановлено 8 ГБ оперативної пам'яті (2x4ГБ): + +![](https://av.libreboot.org/x200/disassembly/0018.jpg) + +Завантажуйтесь! +-------- + +Ви маєте побачити щось подібне цьому: + +![](https://av.libreboot.org/x200/disassembly/0019.jpg) + +Тепер [встановлюйте Linux](../linux/). + +Користувачі X200S та X200 Tablet: трюк GPIO33 не спрацює. +-------------------------------------------------------- + +sgsit дізнався про контакт під назвою GPIO33, який можна заземлити, +щоб вимкнути захист прошивки за допомогою дескриптора та зупинити ME від +запуску (який сам по собі перешкоджає спробам прошивки). Теорія була +доведена правильною; однак на практиці це все одно марно. + +Подивіться трохи вище 7 у TP37 (це GPIO33): + +![](https://av.libreboot.org/x200/gpio33_location.jpg) + +Це замовчуванням ми побачимо це в lenovobios, під час спроби flashrom -p +internal -w rom.rom: + + FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. + FREG2: Warning: Management Engine region (0x00001000-0x005f5fff) is locked. + +Коли GPIO33 було заземлено під час завантаження, це вимкнуло захист флеш-пам'яті, +встановлений дескриптором, і зупинило запуск ME. Результат змінився +на: + + The Flash Descriptor Override Strap-Pin is set. Restrictions implied by + the Master Section of the flash descriptor are NOT in effect. Please note + that Protected Range (PR) restrictions still apply. + +Частина, виділена жирним шрифтом, - це те, що нас дістало. Це все ж спостерігалось: + + PR0: Warning: 0x007e0000-0x01ffffff is read-only. + PR4: Warning: 0x005f8000-0x005fffff is locked. + +Насправді ці засоби захисту можна відключити. Lenovobios робить це, +під час оновлення BIOS (пропрієтарного). Одним із можливих способів вирішити цю проблему +було б відлагодити утиліту оновлення BIOS від Lenovo, для віднаходження, +як вона вимикає ці засоби захисту. Додаткові дослідження доступні +тут: + + +Звичайно, ймовірно, що Lenovo BIOS перевіряє якийсь біт в пам'яті, +який говорить йому не вимикати перепрошивку, а потім він не встановлює регістри PRx. Принцип +роботи програми оновлення BIOS Lenovo полягає в тому, що вона спочатку виконується в Windows, +а потім відбувається перезавантаження, ініціюючи перепрошивку під час раннього завантаження. Ймовірно, +це встановлює щось у пам'яті та завантажує ROM, плюс програму корисного навантаження, +яка виконує перепрошивання; тоді Lenovo BIOS, ймовірно, бачить це та запускає це замість +встановлення PRx і переходу до нормального завантаження. Теоретично можливо, що ми +зможемо дізнатися, як це працює, налагодивши утиліту оновлення BIOS Lenovo (у +Windows), а потім відтворивши її дії за допомогою якогось інструменту для Linux, +а потім завантаживши двійковий файл flashrom в пам'ять та ROM для прошивки (для BIOS +регіона). Ви б зробили це з заземленням GPIO33, і програма корисного навантаження +фактично прошиє весь чіп, лише звичайним образом libreboot. + +Це можливо. Ймовірно, це єдиний спосіб роботи програми оновлення BIOS Lenovo. +Отже, якщо ми дізнаємося, як саме це зробити, тоді ви можете просто підключити кілька +контактів pogo для заземлення GPIO33, потім завантажитися, запустити програмне забезпечення +(яке потрібно було б написати), яке виконує вищезазначене. + +У зв'язку з цим у libreboot є утиліта, яка може допомогти +розслідувати це: +[ich9utils.md#demefactory](ich9utils.md#demefactory) diff --git a/site/docs/install/x60_unbrick.md b/site/docs/install/x60_unbrick.md new file mode 100644 index 0000000..44621f7 --- /dev/null +++ b/site/docs/install/x60_unbrick.md @@ -0,0 +1,214 @@ +--- +title: ThinkPad X60 Recovery guide +x-toc-enable: true +... + +This section documents how to recover from a bad flash that prevents +your ThinkPad X60 from booting. + +ROM images for this machine are well-tested in libreboot, so bricks are rare. +The most common cause of a brick is operator error, when flashing a ROM image. +In *most* cases, the cause will be that there is no bootblock, or an invalid +one. + +Brick type 1: bucts not reset. {#bucts_brick} +============================== + +You still have Lenovo BIOS, or you had libreboot running and you flashed +another ROM; and you had bucts 1 set and the ROM wasn't dd'd.\* or if +Lenovo BIOS was present and libreboot wasn't flashed. + +There are *2* 64KiB bootblocks possible, in the upper part of the ROM image. +By default (bucts set to 0), the top one is used. If bucts is set to 1, the +lower one (the one before the top one) is used. This bootblock is the first +code that executes, during *romstage* as per coreboot hardware initialization. + +BUC is short for *Backup Control* and TS is short for *Top Swap*. This is a +special register on Intel platforms. Lenovo BIOS sets PRx registers, preventing +software re-flashing, but there is a bug in the protection, allowing everything +*except* the upper 64KiB from being flashed. By default, coreboot only puts a +bootblock in the upper region. If you flash such a ROM, while bucts is set to 1, +the system won't boot because there's not a valid bootblock; this is common if +you're re-flashing when coreboot is already installed, and you didn't set bucts +back to 0. + +When you install on X60/T60 the first time, you set this bucts bit to 1, then +you re-flash a second time and set it back to 0. + +In this case, unbricking is easy: reset BUC.TS to 0 by removing that +yellow cmos coin (it's a battery) and putting it back after a minute or +two:\ +![](https://av.libreboot.org/x60_unbrick/0004.jpg)\ + +\*Those dd commands should be applied to all newly compiled X60 ROM +images (the ROM images in libreboot binary archives already have this +applied!): + + dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k + dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump + dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc + +(doing this makes the ROM suitable for use when flashing a system that +still has Lenovo BIOS running, using those instructions: +. + +Brick type 2: bad ROM image {#recovery} +=========================================== + +In this instance, you might have flashed a ROM without the top bootblock copied +to the lower 64KiB section in the ROM, and you flashed the ROM for the first +time (from Lenovo BIOS), in which case there is not a valid bootblock. + +In this scenario, you compiled a ROM that had an incorrect +configuration, or there is an actual bug preventing your system from +booting. Or, maybe, you set BUC.TS to 0 and shut down after first flash +while Lenovo BIOS was running. In any case, your system is bricked and +will not boot at all. + +"Unbricking" means flashing a known-good (working) ROM. The problem: +you can't boot the system, making this difficult. In this situation, +external hardware (see hardware requirements above) is needed which can +flash the SPI chip (where libreboot resides). + +Remove those screws:\ +![](https://av.libreboot.org/x60_unbrick/0000.jpg) + +Push the keyboard forward (carefully):\ +![](https://av.libreboot.org/x60_unbrick/0001.jpg) + +Lift the keyboard up and disconnect it from the board:\ +![](https://av.libreboot.org/x60_unbrick/0002.jpg) + +Grab the right-hand side of the chassis and force it off (gently) and +pry up the rest of the chassis:\ +![](https://av.libreboot.org/x60_unbrick/0003.jpg) + +You should now have this:\ +![](https://av.libreboot.org/x60_unbrick/0004.jpg) + +Disconnect the wifi antenna cables, the modem cable and the speaker:\ +![](https://av.libreboot.org/x60_unbrick/0005.jpg) + +Unroute the cables along their path, carefully lifting the tape that +holds them in place. Then, disconnect the modem cable (other end) and +power connection and unroute all the cables so that they dangle by the +monitor hinge on the right-hand side:\ +![](https://av.libreboot.org/x60_unbrick/0006.jpg) + +Disconnect the monitor from the motherboard, and unroute the grey +antenna cable, carefully lifting the tape that holds it into place:\ +![](https://av.libreboot.org/x60_unbrick/0008.jpg) + +Carefully lift the remaining tape and unroute the left antenna cable so +that it is loose:\ +![](https://av.libreboot.org/x60_unbrick/0009.jpg) + +Remove the screw that is highlighted (do NOT remove the other one; it +holds part of the heatsink (other side) into place):\ +![](https://av.libreboot.org/x60_unbrick/0011.jpg) + +Remove those screws:\ +![](https://av.libreboot.org/x60_unbrick/0012.jpg) + +Carefully remove the plate, like so:\ +![](https://av.libreboot.org/x60_unbrick/0013.jpg) + +Remove the SATA connector:\ +![](https://av.libreboot.org/x60_unbrick/0014.jpg) + +Now remove the motherboard (gently) and cast the lcd/chassis aside:\ +![](https://av.libreboot.org/x60_unbrick/0015.jpg) + +Lift back that tape and hold it with something. Highlighted is the SPI +flash chip:\ +![](https://av.libreboot.org/x60_unbrick/0016.jpg) + +Here is another photo, with the numbers of the pins written:\ +![](https://av.libreboot.org/x60_unbrick/0017.jpg)\ + +This photo shows an SPI flasher used, with SOIC8 test clip:\ +![](https://av.libreboot.org/x60/th_bbb_flashing.jpg) + +Refer to the following guide:\ +[Externally rewrite 25xx NOR flash via SPI protocol](spi.md) + +NOTE: Do not use the 3.3v rail from your raspberry pi. Leave that disconnected. +For 3.3v, plug your charger into the mainboard (but do not power on the mainboard) +when the clip is connected. Before removing the clip, disconnect the charger. +This will provide adequate 3.3v DC at correct current levels. The SPI flash on an +X60 shares a common 3.3V rail with many other components on the mainboard, +which all draw a lot of current, more than your programmer can provide. + +When you're finished flashing, remove the programmer and put it away somewhere. +Put back the tape and press firmly over it:\ +![](https://av.libreboot.org/x60_unbrick/0026.jpg) + +Your empty chassis:\ +![](https://av.libreboot.org/x60_unbrick/0027.jpg) + +Put the motherboard back in:\ +![](https://av.libreboot.org/x60_unbrick/0028.jpg) + +Reconnect SATA:\ +![](https://av.libreboot.org/x60_unbrick/0029.jpg) + +Put the plate back and re-insert those screws:\ +![](https://av.libreboot.org/x60_unbrick/0030.jpg) + +Re-route that antenna cable around the fan and apply the tape:\ +![](https://av.libreboot.org/x60_unbrick/0031.jpg) + +Route the cable here and then (not shown, due to error on my part) +reconnect the monitor cable to the motherboard and re-insert the +screws:\ +![](https://av.libreboot.org/x60_unbrick/0032.jpg) + +Re-insert that screw:\ +![](https://av.libreboot.org/x60_unbrick/0033.jpg) + +Route the black antenna cable like so:\ +![](https://av.libreboot.org/x60_unbrick/0034.jpg) + +Tuck it in neatly like so:\ +![](https://av.libreboot.org/x60_unbrick/0035.jpg) + +Route the modem cable like so:\ +![](https://av.libreboot.org/x60_unbrick/0036.jpg) + +Connect modem cable to board and tuck it in neatly like so:\ +![](https://av.libreboot.org/x60_unbrick/0037.jpg) + +Route the power connection and connect it to the board like so:\ +![](https://av.libreboot.org/x60_unbrick/0038.jpg) + +Route the antenna and modem cables neatly like so:\ +![](https://av.libreboot.org/x60_unbrick/0039.jpg) + +Connect the wifi antenna cables. At the start of the tutorial, this +system had an Intel wifi chip. Here you see I've replaced it with an +Atheros AR5B95 (supports 802.11n and can be used without blobs):\ +![](https://av.libreboot.org/x60_unbrick/0040.jpg) + +Connect the modem cable:\ +![](https://av.libreboot.org/x60_unbrick/0041.jpg) + +Connect the speaker:\ +![](https://av.libreboot.org/x60_unbrick/0042.jpg) + +You should now have this:\ +![](https://av.libreboot.org/x60_unbrick/0043.jpg) + +Re-connect the upper chassis:\ +![](https://av.libreboot.org/x60_unbrick/0044.jpg) + +Re-connect the keyboard:\ +![](https://av.libreboot.org/x60_unbrick/0045.jpg) + +Re-insert the screws that you removed earlier:\ +![](https://av.libreboot.org/x60_unbrick/0046.jpg) + +Power on!\ +![](https://av.libreboot.org/x60_unbrick/0047.jpg) + +Operating system:\ +![](https://av.libreboot.org/x60_unbrick/0049.jpg) diff --git a/site/docs/install/x60flashscript.patch b/site/docs/install/x60flashscript.patch new file mode 100644 index 0000000..7f4c830 --- /dev/null +++ b/site/docs/install/x60flashscript.patch @@ -0,0 +1,27 @@ +From 34270811fce1ecf0bcf3b1363b0dc3dbf284ab09 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 10 Jun 2015 22:53:28 +0000 +Subject: flash script: fix a really really really dumb mistake + +--- +diff --git a/flash b/flash +index c96b915..04fd274 100755 +--- a/flash ++++ b/flash +@@ -95,12 +95,12 @@ if [ "$mode" = "i945lenovo_firstflash" ] || [ "$mode" = "i945lenovo_secondflash" + # git or libreboot_src + bucts="./bucts/bucts" + flashrom_lenovobios_sst="./flashrom/flashrom_lenovobios_sst" +- flashrom_lenovobios_macronix="./flashrom/flashrom_lenovobios_sst" ++ flashrom_lenovobios_macronix="./flashrom/flashrom_lenovobios_macronix" + else + # libreboot_util + bucts="./bucts/$arch/bucts" + flashrom_lenovobios_sst="./flashrom/$arch/flashrom_lenovobios_sst" +- flashrom_lenovobios_macronix="./flashrom/$arch/flashrom_lenovobios_sst" ++ flashrom_lenovobios_macronix="./flashrom/$arch/flashrom_lenovobios_macronix" + fi + + # anti-bricking precaution +-- +cgit v0.9.0.2 diff --git a/site/docs/install/x60tablet_unbrick.md b/site/docs/install/x60tablet_unbrick.md new file mode 100644 index 0000000..652ea74 --- /dev/null +++ b/site/docs/install/x60tablet_unbrick.md @@ -0,0 +1,122 @@ +--- +title: ThinkPad X60 Tablet Recovery guide +x-toc-enable: true +... + +This section documents how to recover from a bad flash that prevents +your ThinkPad X60 Tablet from booting. + +ROM images for this machine are well-tested in libreboot, so bricks are rare. +The most common cause of a brick is operator error, when flashing a ROM image. +In *most* cases, the cause will be that there is no bootblock, or an invalid +one. + +Brick type 1: bucts not reset. {#bucts_brick} +============================== + +You still have Lenovo BIOS, or you had libreboot running and you flashed +another ROM; and you had bucts 1 set and the ROM wasn't dd'd.\* or if +Lenovo BIOS was present and libreboot wasn't flashed. + +There are *2* 64KiB bootblocks possible, in the upper part of the ROM image. +By default (bucts set to 0), the top one is used. If bucts is set to 1, the +lower one (the one before the top one) is used. This bootblock is the first +code that executes, during *romstage* as per coreboot hardware initialization. + +BUC is short for *Backup Control* and TS is short for *Top Swap*. This is a +special register on Intel platforms. Lenovo BIOS sets PRx registers, preventing +software re-flashing, but there is a bug in the protection, allowing everything +*except* the upper 64KiB from being flashed. By default, coreboot only puts a +bootblock in the upper region. If you flash such a ROM, while bucts is set to 1, +the system won't boot because there's not a valid bootblock; this is common if +you're re-flashing when coreboot is already installed, and you didn't set bucts +back to 0. + +When you install on X60/T60 the first time, you set this bucts bit to 1, then +you re-flash a second time and set it back to 0. + +In this case, unbricking is easy: reset BUC.TS to 0 by removing that +yellow cmos coin (it's a battery) and putting it back after a minute or +two:\ +![](https://av.libreboot.org/x60t_unbrick/0008.JPG)\ + +\*Those dd commands should be applied to all newly compiled X60 ROM +images (the ROM images in libreboot binary archives already have this +applied!): + + dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k + dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump + dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc + +(doing this makes the ROM suitable for use when flashing a system that +still has Lenovo BIOS running, using those instructions: +. + +Brick type 2: bad ROM image {#recovery} +=========================================== + +In this instance, you might have flashed a ROM without the top bootblock copied +to the lower 64KiB section in the ROM, and you flashed the ROM for the first +time (from Lenovo BIOS), in which case there is not a valid bootblock. + +In this scenario, you compiled a ROM that had an incorrect +configuration, or there is an actual bug preventing your system from +booting. Or, maybe, you set BUC.TS to 0 and shut down after first flash +while Lenovo BIOS was running. In any case, your system is bricked and +will not boot at all. + +"Unbricking" means flashing a known-good (working) ROM. The problem: +you can't boot the system, making this difficult. In this situation, +external hardware (see hardware requirements above) is needed which can +flash the SPI chip (where libreboot resides). + +![](https://av.libreboot.org/x60t_unbrick/0000.JPG) + +Remove those screws:\ +![](https://av.libreboot.org/x60t_unbrick/0001.JPG) + +Remove the HDD:\ +![](https://av.libreboot.org/x60t_unbrick/0002.JPG) + +Push keyboard forward to loosen it:\ +![](https://av.libreboot.org/x60t_unbrick/0003.JPG) + +Lift:\ +![](https://av.libreboot.org/x60t_unbrick/0004.JPG) + +Remove those:\ +![](https://av.libreboot.org/x60t_unbrick/0005.JPG) + +![](https://av.libreboot.org/x60t_unbrick/0006.JPG) + +Also remove that (marked) and unroute the antenna cables:\ +![](https://av.libreboot.org/x60t_unbrick/0007.JPG) + +For some X60T laptops, you have to unroute those too:\ +![](https://av.libreboot.org/x60t_unbrick/0010.JPG) + +Remove the LCD extend board screws. Also remove those screws (see blue +marks) and remove/unroute the cables and remove the metal plate:\ +![](https://av.libreboot.org/x60t_unbrick/0008.JPG) + +Remove that screw and then remove the board:\ +![](https://av.libreboot.org/x60t_unbrick/0009.JPG) + +This photo shows the flash location:\ +![](https://av.libreboot.org/x60t_unbrick/0011.JPG) + +This photo shows an SPI flasher used, with SOIC8 test clip:\ +![](https://av.libreboot.org/x60/th_bbb_flashing.jpg) + +Refer to the external flashing guide: + +[Externally rewrite 25xx NOR flash via SPI protocol](spi.md) + +NOTE: Do not use the 3.3v rail from your SPI programmer. Leave that disconnected. +For 3.3v, plug your charger into the mainboard (but do not power on the mainboard) +when the clip is connected. Before removing the clip, disconnect the charger. +This will provide adequate 3.3v DC at correct current levels. The SPI flash on an +X60 Tablet shares a common 3.3V rail with many other components on the mainboard, +which all draw a lot of current, more than most flashers can provide. + +Reverse the steps to re-assemble your system, after you've flashed the chip. diff --git a/site/docs/linux/encryption.md b/site/docs/linux/encryption.md new file mode 100644 index 0000000..8b774bf --- /dev/null +++ b/site/docs/linux/encryption.md @@ -0,0 +1,102 @@ +# Fully Encrypted Boot and Root Partitions with Libreboot + +The following guide will explain how to create: + ++ A boot partition (/dev/sda1 in this example) that GRUB can decrypt with 'passphrase1' ++ A root partition (/dev/sda2) with stronger encryption using 'passphrase2' + +This guide assumes you are working from a live disk of your preffered distro. + +# Creating Encrypted Boot Partition + +Grub2 currently (Oct 2021) supports luks2 encryption, which is great, but only the (not very strong) PBKDF2 algorithm. +Start by creating a boot partition of around 1GB, you don't have to format it to anything as LUKS will overwrite it anyway. + +**Step 1:** +Create a LUKS2 formatted device with the PBKDF2 algorithm. +You can play around with the iteration count. +A higher iteration is more secure but will take GRUB a **very** long time to decrypt. +The [debian encrypted boot guide](https://cryptsetup-team.pages.debian.net/cryptsetup/encrypted-boot.html) recommends a count of 500,000 which will still take GRUB a very long time (around 25 seconds) but is faster than the default 1000,000. +Use whatever count makes you feel comfortable. +I'll use and arbitrarily low count. +You'll also want to use a different password than you intend to use for your root partition. +We don't want someone to be able to get our root key by brute-forcing our less secure boot key. + +`sudo cryptsetup luksFormat /dev/sda1 --type luks2 --pbkdf pbkdf2 --pbkdf-force-iterations 200000` + +**Step 2:** +Format and mount the new LUKS2 device. + +``` +sudo cryptsetup luksOpen /dev/sda1 boot +sudo mkfs.ext4 -L boot /dev/mapper/boot +sudo mount /dev/mapper/boot /boot +``` +**Note:** +If you wish to change the passphrase for the boot partition in the future then you'll need to pass the same arguments to cryptsetup as when you created it. +If you don't pass any special arguments, the key will be changed to the distro's default encryption and grub won't be able to decrypt it. +The command to use is: + +`cryptsetup luksChangeKey /dev/sda1 --type luks2 --pbkdf pbkdf2 --pbkdf-force-iterations 200000` + +# Root Partition + +Setting up the root partion is generally simple. +Use the same command without the given parametres used to make the device decryptable by GRUB. + +`cryptsetup luksFormat /dev/sda2 root` + +# Set Up Grub and Install + +You will need to pass the correct kernel parametres to your kernel on boot to allow you to use your encryption passphrase to decrypt the root partition. +These parametres can be passed via a grub config in the boot partition by editing `/etc/default/grub.` + +Add the necessary parametres to the line `GRUB_CMDLINE_LINUX_DEFAULT` as follows: + +`GRUB_CMDLINE_LINUX_DEFAULT="loglevel=4 rd.auto=1 cryptdevice=/dev/sda2:root"` + +*rd.auto=1* tells linux that you want to decrypt all disks. +*cryptdevice* tells linux the block device and mapped name you want to use for the root partition. +Note that the mapped name **must** match what you have it `/etc/fstab.` + +From here, you can generally follow the install guide from your distro's docs. +Make sure that the generated `/boot/grub/grub.cfg` file indeed contains the necessary kernel parametres and that the `/etc/default/grub` file on the disk has the same modifications described above. + +# Set up Fstab + +> The device holding the kernel (and the initramfs image) is unlocked by GRUB, but the root device needs to be unlocked again at initramfs stage, regardless whether it’s the same device. This is because GRUB boots with the given vmlinuz and initramfs images, but there is currently no way to securely pass cryptographic material (or Device Mapper information) to the kernel. Hence the Device Mapper table is initially empty at initramfs stage; in other words, all devices are locked, and the root device needs to be unlocked again. +> +> \- [Debian Guide](https://cryptsetup-team.pages.debian.net/cryptsetup/encrypted-boot.html) + +**Step 1:** +Here, we're not trying to store the root key as we don't want to jeopardize the integrity of our root device. +Instead, we want to store the key for the boot device on the root partition. + +``` +sudo mkdir -m0700 /etc/keys +su -c '( umask 0077 && dd if=/dev/urandom bs=1 count=64 of=/etc/keys/boot.key conv=excl,fsync )' +sudo cryptsetup luksAddKey /dev/sda1 /etc/keys/boot.key +``` + +**Step 2:** +Add your boot device to your crypttab. +You'll need to have the device's UUID. +You can obtain the UUID from `blkid` or simply use the linux block device name `/dev/sda1,` acknowleding it may lead to another device if your disk configuration changes. + +```bash +lsblk -o 'PATH,LABEL,UUID' # to get UUID +sudo vim /etc/crypttab + +> boot_crypt UUID=YOUR_UUID /etc/keys/boot.key luks,key-slot=1 +``` +**Step 3:** +Add the crypt device to your fstab. +Use 'mount -a' to test your fstab configuration. +NOTE: you will not be able to mount the device until it has been unlocked and mapped, rebooting with your new crypttab should do this automatically. + +``` +sudo vim /etc/fstab + +> /dev/mapper/boot_crypt /boot ext4 defaults 0 1 +sudo mount -a +``` diff --git a/site/docs/linux/grub_boot_installer.md b/site/docs/linux/grub_boot_installer.md new file mode 100644 index 0000000..f5b8ca8 --- /dev/null +++ b/site/docs/linux/grub_boot_installer.md @@ -0,0 +1,183 @@ +--- +title: Installing Linux +x-toc-enable: true +... + +# Introduction + +This guide assumes that you are using the GRUB bootloader directly. +If you're using SeaBIOS, it's quite intuitive and works similarly to other BIOS +software; refer to the documentation on . + +This guide explains how to prepare a bootable USB for libreboot systems that +can be used to install several Linux distributions. For this guide, you +will only need a USB flash drive and the `dd` utility (it's installed into all +Linux distributions, by default). + +These instructions are intended to be generic, applicable to just about any +Linux distribution. + +## Prepare the USB Drive in Linux +If you downloaded your ISO while on an existing Linux system, here is how +to create the bootable Linux USB drive: + +Connect the USB drive. Check `lsblk`, to confirm its device name +(e.g., **/dev/sdX**): + + lsblk + +For this example, let's assume that our drive's name is `sdb`. Make sure that +it's not mounted: + + sudo umount /dev/sdb + +Overwrite the drive, writing your distro ISO to it with `dd`. For example, if +we are installing *Foobarbaz* Linux, and it's located in our Downloads +folder, this is the command we would run: + + sudo dd if=~/Downloads/foobarbaz.iso of=/dev/sdb bs=8M; sync + +That's it! You should now be able to boot the installer from your USB drive +(the instructions for doing so will be given later). + +## Prepare the USB drive in NetBSD +[This page](https://wiki.netbsd.org/tutorials/how_to_install_netbsd_from_an_usb_memory_stick/) +on the NetBSD website shows how to create a NetBSD bootable USB drive, from +within NetBSD itself. You should the `dd` method documented there. This will +work with any Linux ISO image. + +## Prepare the USB drive in FreeBSD +[This page](https://www.freebsd.org/doc/handbook/bsdinstall-pre.html) on the +FreeBSD website shows how to create a bootable USB drive for installing +FreeBSD. Use the `dd` method documented. This will work with any Linux ISO +image. + +## Prepare the USB drive in LibertyBSD or OpenBSD +If you downloaded your ISO on a LibertyBSD or OpenBSD system, here is how to +create the bootable Linux USB drive: + +Connect the USB drive. Run `lsblk` to determine which drive it is: + + lsblk + +To confirm that you have the correct drive, use `disklabel`. For example, +if you thought the correct drive were **sd3**, run this command: + + disklabel sd3 + +Make sure that the device isn't mounted, with `doas`; if it is, this command +will unmount it: + + doas umount /dev/sd3i + +The `lsblk` command told you what device it is. Overwrite the drive, writing +the OpenBSD installer to it with `dd`. Here's an example: + + doas dd if=linux.iso of=/dev/rsdXc bs=1M; sync + +That's it! You should now be able to boot the installer from your USB drive +(the instructions for doing so will be given later). + +## Debian or Devuan net install +Download the Debian or Devuan net installer. You can download the Debian ISO +from [the Debian homepage](https://www.debian.org/), or the Devuan ISO from +[the Devuan homepage](https://www.devuan.org/). + +Secondly, create a bootable USB drive using the commands in +[#prepare-the-usb-drive-in-linux](#prepare-the-usb-drive-in-linux). + +Thirdly, boot the USB and enter these commands in the GRUB terminal +(for 64-bit Intel or AMD): + + set root='usb0' + linux /install.amd/vmlinuz + initrd /install.amd/initrd.gz + boot + +If you are on a 32-bit system (e.g. some Thinkpad X60's) then you will need to +use these commands (this is also true for 32-bit running on 64-bit machines): + + set root='usb0' + linux /install.386/vmlinuz + initrd /install.386/initrd.gz + boot + +## Booting ISOLINUX Images (Automatic Method) +Boot it in GRUB using the `Parse ISOLINUX config (USB)` option. A new menu +should appear in GRUB, showing the boot options for that distro; this is a GRUB +menu, converted from the usual ISOLINUX menu provided by that distro. + +## Booting ISOLINUX Images (Manual Method) +These are generic instructions. They may or may not be correct for your +distribution. You must adapt them appropriately, for whatever Linux +distribution it is that you are trying to install. + +If the `ISOLINUX parser` or `Search for GRUB configuration` options won't work, +then press `C` in GRUB to access the command line, then run the `ls` command: + + ls + +Get the device name from the above output (e.g., `usb0`). Here's an example: + + cat (usb0)/isolinux/isolinux.cfg + +Either the output of this command will be the ISOLINUX menuentries for that +ISO, or link to other `.cfg` files (e.g, **/isolinux/foo.cfg**). For example, +if the file found were **foo.cfg**, you would use this command: + + cat (usb0)/isolinux/foo.cg` + +And so on, until you find the correct menuentries for ISOLINUX. + +For Debian-based distros (e.g., Ubuntu, Devuan), there are typically +menuentries listed in **/isolinux/txt.cfg** or **/isolinux/gtk.cfg**. For +dual-architecture ISO images (i686 and x86\_64), there may be separate files +directories for each architecture. Just keep searching through the image, +until you find the correct ISOLINUX configuration file. + +**NOTE: Debian 8.6 ISO only lists 32-bit boot options in txt.cfg. +This is important, if you want 64-bit booting on your system. Devuan versions +based on Debian 8.x may also have the same issue.** + +Now, look at the ISOLINUX menuentry; it'll look like this: + + kernel /path/to/kernel append PARAMETERS initrd=/path/to/initrd ... + +GRUB works similarly; here are some example GRUB commands: + +``` +set root='usb0' +linux /path/to/kernel PARAMETERS MAYBE_MORE_PARAMETERS +initrd /path/to/initrd +boot +``` + +Note: `usb0` may be incorrect. Check the output of the `ls` command (in GRUB), +to see a list of USB devices/partitions. Of course, this will vary from distro +to distro. If you did all of that correctly, then it should now be booting your +USB drive in the way that you specified. + +## Troubleshooting +Most of these issues occur when using libreboot with coreboot's `text-mode` +with libgfxinit for video initialization. This mode is useful for text mode +payloads, like `MemTest86+`, which expect `text-mode`, but for Linux +distributions it can be problematic when they are trying to switch to a +framebuffer, because no mode switching support is present (Linux/BSD kernels +do Kernel Mode Setting, so they are able to initialize a frame buffer in bare +metal regardless of whatever coreboot is doing). + +### debian-installer Graphical Corruption in Text-Mode (Debian and Devuan) +When using the ROM images that use Coreboot's `text mode`, instead of the +coreboot framebuffer, while using libgfxinit, booting the Debian or Devuan net +installer results in graphical corruption, because it is trying to switch to a +framebuffer while no mode switching support is present. Use this kernel +parameter on the `linux` line, when booting it: + + fb=false + +This forces debian-installer to start in `text-mode`, instead of trying to +switch to a framebuffer. + +If selecting `text-mode` from a GRUB menu created using the ISOLINUX parser, +you can press `E` on the menu entry to add this. Or, if you are booting +manually (from GRUB terminal), then just add the parameters. diff --git a/site/docs/linux/grub_cbfs.md b/site/docs/linux/grub_cbfs.md new file mode 100644 index 0000000..97bb27c --- /dev/null +++ b/site/docs/linux/grub_cbfs.md @@ -0,0 +1,179 @@ +--- +title: Modifying grub.cfg in CBFS +x-toc-enable: true +... + +Before you follow this guide, it is advisable that you have the ability to +flash externally, just in case something goes wrong. + +This guide assumes that you use the GRUB bootloader as your default +payload. In this configuration, GRUB is flashed alongside coreboot and runs +on *bare metal* as a native coreboot payload and does *not* use BIOS or UEFI +services (but it *can* load and execute SeaBIOS, in addition to any other +coreboot payload, by chainloading it). + +In most circumstances, this guide will not benefit you. libreboot's default +GRUB configuration file contains scripting logic within it that intelligently +searches for GRUB partitions installed onto a partition on your SSD, HDD or +USB drive installed on your computer. If such a file is found, libreboot's +default GRUB configuration is configured to switch automatically to that +configuration. While not perfect, the logic *does* work with most +configurations. + +Therefore, you should only follow *this* guide if the automation (described +above) does not work. It goes without saying that modifying the default GRUB +configuration is risky, because a misconfiguration could create what's called +a *soft brick* where your machine is effectively useless and, in that scenario, +may or may not require external flashing equipment for restoring the machine to +a known state. + +Compile flashrom and cbfstool +============================= + +libreboot does not currently distribute utilities pre-compiled. It only +provides ROM images pre-compiled, where feasible. Therefore, you have to build +the utilities from source. + +As for the ROM, there are mainly three methods for obtaining a libreboot ROM +image: + +1. Dump the contents of the the main *boot flash* on your system, which already + has libreboot installed (with GRUB as the default payload). Extract the + GRUB configuration from *that* ROM image. +2. Extract it from a libreboot ROM image supplied by the libreboot project, on + the libreboot website or mirrors of the libreboot website. +3. Build the ROM yourself, using the libreboot build system. Instructions for + how to do this are covered in the following article: + [How to build libreboot from source](../build/) + +In either case, you will use the `cbfstool` supplied in the libreboot build +system. +This can be found under `coreboot/*/util/cbfstool/` as source code, +where `*` can be any coreboot source code directory for a given mainboard. +The directory named `default` should suffice. + +Install the build dependencies. For Ubuntu 20.04 and similar, you can run +the following command in the libreboot build system, from the root directory +of the libreboot Git repository. + + ./build dependencies ubuntu2004 + +Then, download coreboot: + + ./download coreboot + +Finally, compile the `cbutils` module: + + ./build module cbutils + +Among other things, this will produce a `cbfstool` executable under any of the +subdirectories in `coreboot/` under `util/cbfstool/cbfstool + +For example: `coreboot/default/util/cbfstool/cbfstool` + +The `cbfstool` utility is what you shall use. It is used to manipulate CBFS +(coreboot file system) which is a file system contained within the coreboot +ROM image; as a *coreboot distribution*, libreboot inherits this technology. + +You will also want to build `flashrom` which libreboot recommends for reading +from and/or writing to the boot flash. In the libreboot build system, you can +build it by running this command: + + ./build module flashrom + +An executable will be available at `flashrom/flashrom` after you have done +this. + +Dump the boot flash +=================== + +If you wish to modify your *existing* libreboot ROM, which was installed on +your computer, you can use `flashrom` to acquire it. + +Simply run the following, after using libreboot's build system to compile +flashrom: + + sudo ./flashrom/flashrom -p internal -r dump.bin + +If flashrom complains about multiple flash chip definitions, do what it says to +rectify your command and run it again. + +You may want to use the following, instead of `-p internal`: +`-p internal:laptop=force_I_want_a_brick,boardmismatch=force` + +Do not let the word *brick* fools you. This merely disables the safety checks +in flashrom, which is sometimes necessary depending on what ROM was already +flashed, versus the new ROM image. + +The `internal` option assumes that internal read/write is possible; this is +when you read from and/or write to the boot flash from an operating systems +(usually Linux) that is *running on* the target system. + +In other cases, you may need to connect an SPI programmer externally (with the +machine powered down) and read the contents of the boot flash. + +[Learn how to externally reprogram these chips](../install/spi.md) + +Extract grub.cfg +================ + +libreboot images that use the GRUB bootloader will have *two* configuration +files in CBFS: + +* `grub.cfg` +* `grubtest.cfg` + +We recommend that you modify `grubtest.cfg` first, and boot. Select the boot +menu option for loading `grubtest.cfg` and verify that your new config works +correctly. If it doesn't, keep modifying `grubtest.cfg` until it does work. +When that it done, copy the changes over to `grub.cfg + +You can use the following commands to modify the contents of CBFS, where +GRUB's configuration file is concerned (dump.bin is the ROM that you dumped, +or it could refer to the libreboot ROM image that you compiled or otherwise +acquired). + +Show the contents of CBFS, in your ROM: + + cbfstool dump.bin print + +Extract `grub.cfg` (substitude with `grubtest.cfg` as desired): + + cbfstool dump.bin extract -n grub.cfg -f grub.cfg + +You will now have a file named `grub.cfg`. + +Make your desired modifications. You should then delete the old `grub.cfg` +from your ROM image. + +Insert new grub.cfg +=================== + +Remove the old `grub.cfg` (substitute with `grubtest.cfg` as desired): + + cbfstool dump.bin remove -n grub.cfg + +Add your modified `grub.cfg` (substitute with `grubtest.cfg` as desired): + + cbfstool dump.bin add -f grub.cfg -n grub.cfg -t raw + +Flash the modified ROM image +============================ + +Your modified `dump.bin` or other modified libreboot ROM can then be re-flashed +using: + + sudo ./flashrom -p internal -w dump.bin + +If a `-c` option is required, use it and specify a flash chip name. This is +only useful when `flashrom` complains about multiple flash chips being +detected. + +If flashrom complains about wrong chip/board, make sure that your ROM is for +the correct system. If you're sure, you can disable the safety checks by running +this instead: + + sudo ./flashrom -p internal:laptop=force_I_want_a_brick,boardmismatch=force -w dump.bin + +If you need to use external flashing equipment, see the link above to the +Raspberry Pi page. diff --git a/site/docs/linux/grub_hardening.md b/site/docs/linux/grub_hardening.md new file mode 100644 index 0000000..ac0279b --- /dev/null +++ b/site/docs/linux/grub_hardening.md @@ -0,0 +1,275 @@ +--- +title: Hardening GRUB +x-toc-enable: true +... + +This article only applies to those people who use the GRUB bootloader as +their default payload (options besides GRUB are also available in +libreboot). Whenever this article refers to GRUB, or configuration files +used in GRUB, it is referring exclusively to those files hosted in CBFS +(coreboot file system) in the libreboot ROM image. In this configuration, +GRUB is running on *bare metal* as a coreboot payload (instead of relying on +BIOS or UEFI services, like it does on *most* x86 based configurations). + +This guide deals with various ways in which you can harden your GRUB +configuration, for security purposes. These steps are optional, but *strongly* +recommended by the libreboot project. + +GRUB provides *many* advanced security features, which most people don't +know about but are fully documented on the libreboot website. Read on! + +This article doesn't cover how to dump your ROM, or flash a new one. Please +read other sections in the libreboot documentation if you don't know how to do +that. As such, this is an *expert only* guide. There is a great possibility for +bricking your system if you follow this guide incorrectly, or otherwise don't +know what you're doing. + +GRUB secure boot with GPG +========================= + +GRUB contains code, based on [GPG](https://gnupg.org/), that can verify +PGP signatures on *any* type of file, on any storage medium supported by +GRUB (it supports basically everything, including CBFS which is short +for coreboot file system and it is what we will focus on in this article). +We will be using this functionality to verify the signature of a Linux kernel, +at boot time. In conjunction with reproducible builds (both libreboot and your +Linux kernel), this can greatly improve system security; Debian is an excellent +example of a project striving towards this goal; see: + + +For your reference: a reproducible build is one where, given a precise (and +well documented) development setup, the exact same binary can be produced each +time the source code is compiled when that *very same development setup* is +replicated by another person. In other words, the file checksum (e.g. +SHA512 hash) will be exactly the same at all times. In practise, this means +that metadata such as time stamps are not included in the binary, or if they +are, they are constant (in many scenarios, it's based on the date of a Git +commit ID that the build is based on, if the software is built from a Git +repository). More information about reproducible builds can be found here: + + + +Reproducibility is a key goal of the libreboot project, though it has not yet +achieved that goal. However, it is an important part of any secure system. We +suggest that, when securing your libreboot system as instructed by this guide, +you should also use a reproducible Linux distribution (because checking GPG +signatures on a non-reproducible binary, such as a Linux kernel, is meaningless +if that binary can be compromised as a result of literally not being able to +verify that the source code *actually* corresponds to the provided binary, +which is exactly what reproducible builds allow). If *someone else* compiles an +executable for you, and that executable is non-reproducible, you have no way to +verify that the source code they provided *actually* corresponds to the binary +they gave you. Based on these facts, we can observe that checking GPG +signatures will improve your *operational* security, but only in specific +circumstances under *controlled conditions*. + +This tutorial assumes you have a libreboot image (ROM) that you wish to modify, +which from now on we will refer to simply as *`my.rom`*. It should go without +saying that this ROM uses the GRUB bootloader as payload. This page shows +how to modify grubtest.cfg, which means that signing and password protection +will work after switching to it in the main boot menu and bricking due to +incorrect configuration will be impossible. After you are satisfied with the +new setup, you should transfer the new settings to grub.cfg to make your +machine truly secure. + +First, extract the old grubtest.cfg and remove it from the libreboot +image: + + cbfstool my.rom extract -n grubtest.cfg -f my.grubtest.cfg + cbfstool my.rom remove -n grubtest.cfg + +You can build `cbfstool` in the libreboot build system. Run this command: + + ./build module cbutils + +This assumes that you already downloaded coreboot: + + ./download coreboot + +This, in turn, assumes that you have installed the build dependencies for +libreboot. On Ubuntu 20.04 and other apt-get distros, you can do this: + + ./build dependencies ubuntu2004 + +The `cbfstool` executables will be under each coreboot directory, under +each `coreboot/boardname/` directory for each board. Just pick one, presumably +from the coreboot directory for your board. libreboot creates multiple coreboot +archives for different board revisions, on different boards. + +References: + +* [GRUB manual](https://www.gnu.org/software/grub/manual/html_node/Security.html#Security) +* [GRUB info pages](http://git.savannah.gnu.org/cgit/grub.git/tree/docs/grub.texi) +* [SATA connected storage considered dangerous.](../../faq.md#hddssd-firmware) +* [Coreboot GRUB security howto](https://www.coreboot.org/GRUB2#Security) + +GRUB Password +============= + +The security of this setup depends on a good GRUB password as GPG signature +checking can be disabled through the interactive console: + + set check_signatures=no + +This is useful because it allows you to occasionally boot unsigned live CD/USB +media and such. You might consider supplying signatures on a USB stick, but the +signature checking code currently looks for `/path/to/filename.sig` when +verifying `/path/to/filename` and, as such, it will be impossible to supply +signatures in any other location (unless the software is modified accordingly). + +It's worth noting that this is not your LUKS password but, rather, a password +that you must enter in order to use *restricted* functionality (such as the +GRUB terminal for executing commands). This behaviour protects your system +from an attacker simply booting a live USB key (e.g. live Linux +distribution) for the purpose of flashing modified boot firmware, which from +your perspective is *compromised* boot firmware. *This should be different than +your LUKS passphrase and user password.* + +GRUB supports storing salted, hashed passwords in the configuration file. +This is a far more secure configuration, because an attacker cannot simply read +your password as *plain text* inside said file. + +Use of the *diceware method* is *strongly* recommended, for generating secure +passphrases (as opposed to passwords). The diceware method involves rolling +dice to generate random numbers, which are then used as an index to pick a +random word from a large dictionary of words. You can use any language (e.g. +English, German). Look it up on a search engine. Diceware method is a way to +generate secure passphrases that are very hard (almost impossible, with enough +words) to crack, while being easy enough to remember. On the other hand, most +kinds of secure passwords are hard to remember and easier to crack. Diceware +passphrases are harder to crack because of far higher entropy (there are many +words available to use, but only about 50 commonly used symbols in +pass*words*). This high level of entropy is precisely what makes such pass +phrases secure, even if an attacker knows exactly which dictionary you used! + +The GRUB password can be stored in one of two ways: + +* plaintext +* protected with [PBKDF2](https://en.wikipedia.org/wiki/Pbkdf2) + +We will *obviously* use the latter method. Generating the PBKDF2 derived key is +done using the `grub-mkpasswd-pbkdf2` utility. You can get it by +installing GRUB version 2. Generate a key by giving it a password: + +NOTE: This utility is included under the `grub/` directory, when you build +GRUB using the libreboot build system. Run the following commands (assuming +you have the correct build dependencies installed) to build GRUB, from the +libreboot Git repository: + + ./download grub + + ./build module grub + +The following executable will then be available under the `grub/` directory: + + grub-mkpasswd-pbkdf2 + +Its output will be a string of the following form: + + grub.pbkdf2.sha512.10000.HEXDIGITS.MOREHEXDIGITS + +Now open my.grubtest.cfg and put the following before the menu entries +(prefered above the functions and after other directives). Of course use +the pbdkf string that you had generated yourself: + + set superusers="root" + password_pbkdf2 root grub.pbkdf2.sha512.10000.711F186347156BC105CD83A2ED7AF1EB971AA2B1EB2640172F34B0DEFFC97E654AF48E5F0C3B7622502B76458DA494270CC0EA6504411D676E6752FD1651E749.8DD11178EB8D1F633308FD8FCC64D0B243F949B9B99CCEADE2ECA11657A757D22025986B0FA116F1D5191E0A22677674C994EDBFADE62240E9D161688266A711 + +Obviously, replace it with the correct hash that you actually obtained for the +password you entered. In other words, *do not use the hash that you see above!* + +With this configuration in place, you must now enter the passphrase *every +single time you boot your computer*. This completely restricts an attacker in +such a way that they cannot simply boot an arbitrary operating system on your +computer. NOTE: An attacker could still open your system and re-flash new +firmware externally. You should implement some detection mechanism, such as +epoxy applied in a *random pattern* on every screw; this slows down the attack +and means that you will know someone tampered with it because they cannot +easily re-produce the exact same blob of epoxy in the same pattern (when you +apply it, swirl it around a bit for a few minutes while it cures. The purpose +is not to prevent disassembly, but to slow it down and make it detectable when +it has occured). + +Another good thing to do, if we chose to load signed on-disk GRUB +configurations, is to remove (or comment out) `unset superusers` in +function try\_user\_config: + +``` +function try_user_config { + set root="${1}" + for dir in boot grub grub2 boot/grub boot/grub2; do + for name in '' autoboot_ libreboot_ coreboot_; do + if [ -f /"${dir}"/"${name}"grub.cfg ]; then + #unset superusers + configfile /"${dir}"/"${name}"grub.cfg + fi + done + done +} +``` + +The `unset superusers` command disables password authentication, which will +allow the attacker to boot an arbitrary operating system, regardless of +signature checking. The default libreboot configuration is tweaked for *easy of +use* by end users, and it is *not* done with security in mind (though security +is preferred). Thus, libreboot is less restrictive by default. What you are +doing, per this article, is making your system *more secure* but at the expense +of user-friendliness. + +That just about covers it, where password setup is concerned! + +GPG keys +======== + +First, generate a GPG keypair to use for signing. Option RSA (sign only) +is ok. + +WARNING: GRUB does not read ASCII armored keys. When attempting to +trust ... a key filename it will print `error: bad signature` on the screen. + +``` +mkdir --mode 0700 keys +gpg --homedir keys --gen-key +gpg --homedir keys --export-secret-keys --armor > boot.secret.key # backup +gpg --homedir keys --export > boot.key +``` + +Now that we have a key, we can sign some files with it. We must sign: + +- a kernel +- (if we have one) an initramfs +- (if we wish to transfer control to it) an on-disk `grub.cfg` +- `grubtest.cfg` (so that you can go back to `grubtest.cfg` after signature + checking is enforced. You can always get back to `grub.cfg` by pressing ESC, + but, afterwards, `grubtest.cfg` is not signed and it will not load. + +Suppose that we have a pair of `my.kernel` and `my.initramfs` and an +on-disk `libreboot_grub.cfg`. We will sign them by running the following +commands: + +``` +gpg --homedir keys --detach-sign my.initramfs +gpg --homedir keys --detach-sign my.kernel +gpg --homedir keys --detach-sign libreboot_grub.cfg +gpg --homedir keys --detach-sign my.grubtest.cfg +``` + +Of course, some further modifications to my.grubtest.cfg will be required. We +need to *trust* the key and enable signature enforcement (put this before menu +entries): + +``` +trust (cbfsdisk)/boot.key +set check_signatures=enforce +``` + +What remains now is to include the modifications into the libreboot image +(ROM): + +``` +cbfstool my.rom add -n boot.key -f boot.key -t raw +cbfstool my.rom add -n grubtest.cfg -f my.grubtest.cfg -t raw +cbfstool my.rom add -n grubtest.cfg.sig -f my.grubtest.cfg.sig -t raw +``` + +Now, flash it. If it works, copy it over to `grub.cfg` in CBFS. diff --git a/site/docs/linux/index.md b/site/docs/linux/index.md new file mode 100644 index 0000000..79b2bc9 --- /dev/null +++ b/site/docs/linux/index.md @@ -0,0 +1,93 @@ +--- +title: Linux guides +x-toc-enable: true +... + +NOTE: This guide pertains to x86 hosts, and does not cover supported CrOS/ARM +chromebooks. For ARM targets, you should refer to u-boot documentation. + +This page is useful for those who wish to use the GRUB GRUB payload directly. +If you're using SeaBIOS, the boot process will work similarly to traditional +BIOS systems; refer to the SeaBIOS documentation +on + +Linux is generally assumed, especially for Libreboot development, but Libreboot +also works quite nicely with [BSD systems](../bsd/). + +Useful links +============ + +Refer to the following pages: + +* [How to Prepare and Boot a USB Installer in libreboot Systems](grub_boot_installer.md) +* [Modifying the GRUB Configuration in libreboot Systems](grub_cbfs.md) +* [How to Harden Your GRUB Configuration, for Security](grub_hardening.md) + +Encrypted (LUKS/dm-crypt) installations +======================================= + +A better solution for encryption would be a Linux payload in flash, handling the +encryption, at least if you want to use Linux, because then it'll have +perfect LUKS support. + +GRUB otherwise has good filesystem support, so if you have a valid `grub.cfg` +in `/boot/grub` on your installed system, Libreboot's GRUB configuration has +logic in it that will try to automatically use whatever you have installed, +by switching to it. In this way, most installations Just Work, so long as +the `/boot` partition is accessible. + +Full encryption for basic LUKS2 is supported in libreboot. +See [the guide](encryption.md) for more detail. + +Rebooting system in case of freeze +=================================== + +Linux kernel has a feature to do actions to the system any time, even +with it freezes, this is called a +[Magic SysRq keys](https://en.wikipedia.org/wiki/Reisub). You can do these +actions with Alt + Sysrq + Command. These are the actions: + +* Alt + SysRq + B: Reboot the system +* Alt + SysRq + I: Send SIGKILL to every process except PID 1 +* Alt + SysRq + O: Shut off the system + +If some of them don't work, you have to enable it in the kernel +command line paramter. So append `sysrq_always_enabled=1` to your +`GRUB_CMDLINE_LINUX_DEFAULT` in `/etc/default/grub` + +You can also run `# sysctl kernel.sysrq=1` to enable them. + +Fedora won't boot? +================== + +This may also apply to CentOS or Redhat. Chroot guide can be found on +[fedora website](https://docs.fedoraproject.org/en-US/quick-docs/bootloading-with-grub2/#restoring-bootloader-using-live-disk) + +linux16 issue +------------- + +Libreboot's default GRUB config sources fedora's grub config +`grub.cfg` (in `/boot/grub2/grub.cfg`), fedora by default makes use of the +`linux16` command, where it should be saying `linux` + +Do this in fedora: + +Open `/etc/grub.d/10_linux` + +Set the `sixteenbit` variable to an empty string, then run: + + grub2-mkconfig -o /boot/grub2/grub.cfg + +BLS issue +--------- + +With [newer versions of fedora](https://fedoraproject.org/wiki/Changes/BootLoaderSpecByDefault), +scripts from grub package default to generating [BLS](https://www.freedesktop.org/wiki/Specifications/BootLoaderSpec/) +instead of `grub.cfg`. To change that behaviour add following line +to `/etc/default/grub` (or modify existing one if it already exists): + + GRUB_ENABLE_BLSCFG=false + +Then generate `grub.cfg` with: + + grub2-mkconfig -o /boot/grub2/grub.cfg diff --git a/site/docs/maintain/index.md b/site/docs/maintain/index.md new file mode 100644 index 0000000..3a73381 --- /dev/null +++ b/site/docs/maintain/index.md @@ -0,0 +1,1355 @@ +--- +title: lbmk maintenance manual +x-toc-enable: true +... + +Automated build system +====================== + +This manual describes the nature of `lbmk` (LibreBoot MaKe), the automated +build system used to produce libreboot releases. It is provided as a reference +for *libreboot development*. + +If you simply wish to compile libreboot from source, you should instead refer +to the [build instructions](../build/) + +Generally speaking, *testing* releases of libreboot will not come with +documentation; if you're later using *old* testing releases, it is prudent to +check the `lbwww.git` repository on a revision from around the same time as +those releases. Future stable releases of libreboot will come with a snapshot of +the `lbwww.git` repository, for documentation pertaining to such releases. One +way to do this, all testing releases of libreboot, will be to simply run `git log` +on the `news/` section of `lbwww.git` and find the revision that added +the *announcement* for a given release (when available), and then you can +just reset to that revision. + +As such, you should always refer to the *live* version of this page, on +libreboot.org, when working on the `lbmk.git` repository; the live version is +provided for development on the Git repository! + +What is lbmk? +============== + +In the same way that that *Trisquel* is a *GNU+Linux distribution*, Libreboot +is a **coreboot distribution**. The `lbmk` build system *is* that distro, +providing the glue necessary to integrate coreboot plus anything else that's +needed, unifying everything in a completely automated and pre-configured +fashion, so as to provide a distribution that is ease to install and use by +non-technical users. + +In the past, installation of coreboot **required** extensive amounts of +configuration by the user, because there was no automation available. It was a +problem, and one that `lbmk` has *solved*; it is a problem, because most users +simply want to *install* coreboot without giving it much thought. The `lbmk` +build system is written for *those* people, while also providing some +flexibility for those who do want to tinker and get their hands dirty. + +The `lbmk` build system is designed to be simple. Each part of it is its own +separate program, which is to run independently. *Write one program that does +one thing well*. + +Technically, `lbmk` isn't necessarily a build system, but rather, a handful of +small scripts that run other scripts, or even C programs if you wish. What +makes `lbmk` *be* `lbmk` is what each individual script does, and how scripts +interact with or call each other to produce working ROM images. It takes +a *light touch* approach, providing only the most minimal glue necessary to +build working ROM images that the user can install, with sane defaults, while +also providing some ability to customize the firmware, with documentation +describing how to do just that. User-friendly documentation is provided, with +simple installation steps, automating as much of it as possible. + +*This* document is different. The document you're reading right now is written +for *technical* users who want to know how libreboot is put together. + +The lbmk design also helps to ease copyright licensing and compliance, because +each part of lbmk is literally its own separate program. With this design, it +means that most scripts do not directly link/embed/include each other. Because +of this, it's much easier to have different licenses in use for different +files. Generally speaking, lbmk is GPLv3+, but it's perfectly OK, for +example, to add files that are GPLv2 or other licenses. By comparison, if you +were to have a C program under GPLv3, you could not \#include C libraries that +are GPLv2, at least not directly, or there would be many pitfalls to avoid at +the very least. With lbmk's design, you can think of it as like when you have +many programs running in your operating system, and not all of those programs +are under the same license, and most of those different licenses are not +compatible with each other; this is perfectly OK there, and it's OK here too. + +The purpose of this document is to (hopefully) cause you to understand the +entire build system in libreboot, so that you can contribute patches or +otherwise make whatever changes you like. As such, this is a reference guide +for libreboot development. + +Libreboot is a *coreboot distro*, focusing on integration. As such, direct +development on software such as coreboot, GRUB, SeaBIOS etc should ideally +be done upstream, or if it's a project hosted by libreboot (such as ich9utils) +developed in the corresponding separate repository. + +This document is written for developers and power users alike, or otherwise for +anyone who is curious enough to learn more about what *makes* libreboot! + +A major planned addition to lbmk in the future is: use it to implement a small +busybox+linux distribution, with musl libc, plus u-root, and implement a +linux-based bootloader setup similar to Heads, but do it *lbmk-style*. The +lbmk build system is designed for absolute simplicity and modularity, making +it easy to understand and maintain. It intentionally avoids use of rather +complicated programs such as Autoconf; the Makefile in lbmk is just bolted +on but it not required. The `lbmk` build system is a *non-design*; it evolved +over time, into what it is today. Its modularity and simplicity of non-design +allows you to easily rewrite large parts of it, whenever you want to do so. + +lbmk is written in POSIX shell scripts, and this is unlikely to change in the +future. However, lbmk integrates several projects such as coreboot, GRUB +or SeaBIOS, and these all have *their* own build systems aswell. The `lbmk` +build system is the glue that puts all of these together to produce ROM images +for users, in a completely automated fashion. The purpose of `lbmk` is to +provide an *unattended* build process, with as little user interaction as +possible. Thus, `lbmk` is an *automated build system*. It says on the libreboot +home page that libreboot is a *coreboot distribution* in much the same way that +Alpine Linux is a *Linux distribution*, and `lbmk` is what implements that! + +Continue reading, and you will learn of each file contained in `lbmk`. This +document largely pertains to the version of `lbmk` as hosted in `lbmk.git`, +but this manual also covers source code archives containing the full downloaded +set of modules such as coreboot and GRUB. + +In general, it is advisable to open *every* file in lbmk, after you downloaded +it (from the Git repository), and study the logic in great detail. This manual +attempts to explain all of it, and provide a general idea, but nothing beats +simply *studying* the logic directly. + +AUTOMATED automation +==================== + +Every part of lbmk checks if the prerequisite steps are done, and does them +automatically if not. The `roms_helper` script is no different; for example, it +automatically downloads coreboot if not present, aswell as GRUB and everything +else. You can run each and every part of lbmk without having to worry about +running something before it, because it is handled automatically; if that is +ever not the case, it's a bug that should be fixed immediately (in Libreboot +20160907, such fine tuned automation did not exist and you did have to run +specific parts of the build system manually, in a precise order, but this is +no longer the case in modern `lbmk` or `lbmk`). + +Another example: if you run `./build payload grub` but `./build module grub` is +not completed, it will automatically run that first, to produce +the `grub-mkstandalone` binary which is then used by `./build payload grub` + +Another example: if you run `./build boot roms` and crossgcc isn't yet built +for the revision used on each given board, it will automatically compile that +version of it, using *that* coreboot tree's own build system to do it. + +This level of automation means that modern `lbmk` is much +easier to use, compared to the build system present in Libreboot 20160907. +Massive improvements to that build system were made, during most of 2021, when +implementing the `lbmk` build system. + +All sections below pertain to actual files in lbmk: + +.gitcheck +========= + +This checks whether Git credentials are set, and sets placeholder credentials +if required, locally for the given project. + +If something went wrong during build, these placeholder credentials will still +be in effect, but only within `lbmk`. You can unset them like so: + + ./.gitcheck Clean + +This is important, when working on Libreboot. Ordinarily, temporary credentials +are cleared after running lbmk, but may not be cleared in error conditions. + +A bit of a hack, but it avoids build issues when the user hasn't set a name +and email address in Git. If you've set a *global* one, then this script is +irrelevant. + +NOTE: In a git repository, the directory `.git` and files like `.gitignore` +or `.gitmodules` are used by the Git software. The name of this script begins +with `.git`, but the Git software does not make use of this file. It is +a *shell script*, executed by lbmk when you run commands in it. + +More context about Git name/email can be found in +the [Libreboot build instructions](../build/). + +.git +==== + +Metadata used by git-scm, the version control system that Libreboot uses for +development. This directory will be present in the Git repository. It is not +provided in Libreboot *releases*. Learn more about Git here: + + + +.gitignore +========== + +This file is used by Git. It tells Git to *ignore* certain files, so that they +do not get added accidentally to commits for the Libreboot Git repository, +named `lbmk.git`. + +You can learn more about `.gitignore` files here: + + + +COPYING +======= + +This file contains a copy of the GNU General Public License, version 3.0. It is +the license that most parts of `lbmk` are released under. + +NOTE: Not all of Libreboot is released under this license, but it is heavily +used in the Libreboot *build system*. Much of coreboot is GPL version 2 and +in some cases, other licenses (such as BSD-style licenses) are used. This is +inevitable, with Libreboot being an *aggregate distribution* of software, +namely coreboot and *payloads*, plus utilities. + +Including a `COPYING` file is a good, conservative first step in adhering +to *good practise* when it comes to software, and it is *mostly* technically +correct in the context of *lbmk*, because *most* of lbmk is under GPLv3. This +is a legacy from when Libreboot started, where that license was chosen, and +it has just been *de facto* standard for Libreboot (build system) ever since. + +You should perform an audit, to learn more about other licenses. This can be +done by inspecting the various projects that lbmk makes use of, like coreboot. +For aggregate distributions such as coreboot distributions or Linux distros, +it's not trivial to keep track of every license in a simple way, so such an +audit is inevitable if you want to know more. + +Makefile +======== + +For use with *GNU* Make, this is a frontend to `lbmk`, which can be used to run +various commands in `lbmk`. + +Use of this file is purely optional, and largely beneficial if you simply want +to build all of `lbmk` (just run `make` when the current work directory is the +root directory of `lbmk`). + +README*.*md +=========== + +This file contains a brief description of libreboot, along with information +about the project + +It's basically a copy of the homepage text, relative to libreboot.org. + +build +===== + +This is the main shell script, part of `lbmk`, used for running most `lbmk` +commands. You could say that this file *is* `lbmk`. Run `./build help` for +usage instructions. + +It calls scripts in `resources/scripts/build/`. For example, the +command `./build boot roms` will execute `resources/scripts/build/boot/roms`. +When running such commands, additional parameters can be given, which will +be passed along to the corresponding script. For example, try: + + ./build boot roms x60 x200_8mb w500_16mb + +This will run: + + ./resources/scripts/build/boot/roms x60 x200_8mb w500_16mB + +The `list` function is very helpful. For example: + + ./build boot list + +At the time of writing this section, this would output something like: + +```` +Available options for mode 'boot': + +roms +roms_helper +``` + +Another use of `list` would be: + + ./build boot roms list + +However, the `roms` script merely happens to implement a `list` command. For +example, `./build payload grub list` does nothing differently +than `./build payload grub`. + +You may also refer to the [build instructions](../build) + +download +======== + +This is the main shell script for downloading various components used by `lbmk`. +For example, this script downloads coreboot. Scripts called by `download` may +also apply patches and such, to the corresponding project; for example, it will +apply custom patches to GRUB. + +This runs scripts in `resources/scripts/download`. For example: + + ./download coreboot + +This would run: + + ./resources/scripts/download/coreboot + +Additional parameters can be given, for example: + + ./download coreboot default + +This would run: + + ./resources/scripts/download/coreboot default + +For a full list of all `download` commands, run: + + ./download help + +*Most* download modules are defined in `resources/git/revisions`, showing the +link to git repositories and info about revisions, for each given project. +More on this is available in the page you're reading now (keep reading). + +gitclone +======== + +This script is used by the `download` script, specifically for cloning of +Git repositories, for certain projects as defined in the file at location, +path `resources/git/revisions` within lbmk. + +It downloads a project, from a main Git repository or a backup if defined and +the main one is down. It then resets to a defined revision (commit ID). If +patches are supplied for that project, by lbmk, then those patches are applied. +The patches are applied as per: ascending, alphanumerical order of patch file +name. + +modify +====== + +This can be used to modify SeaBIOS, coreboot and U-Boot configs. It calls +scripts in `resources/scripts/modify/`, for example: + + ./modify coreboot configs + +This runs: + + ./resources/scripts/modify/coreboot/configs + +Additional parameters can be given, for example: + + ./modify coreboot configs x200_8mb x60 + +This would run: + + ./resources/scripts/modify/coreboot/configs x200_8mb x60 + +If you run it without arguments, help text is shown. + +projectname +=========== + +This file contains a single line of text, with the string "libreboot". + +If you were to fork libreboot, you could very easily just modify this file, so +as to rename your fork in a largely automated way. Many parts of lbmk use this +file. + +resources/coreboot/ +=================== + +This directory contains configuration, patches and so on, for each mainboard +supported in the `lbmk` build system. These directories contain such +configuration, so that `lbmk` can build working ROM images. + +The scripts in `resources/scripts/build/boot/` make heavy use of this +directory. + +resources/coreboot/BOARDNAME/ +============================= + +Each `BOARDNAME` directory defines configuration for a corresponding mainboard. +It doesn't actually have to be for a board; it can also be used to just define +a coreboot revision, with patches and so on. + +resources/coreboot/BOARDNAME/board.cfg +====================================== + +This file can contain several configuration lines, each being a string, such +as: + +* `cbtree="default"` (example entry) +* `romtype="normal"` (example entry) +* `cbrevision="ad983eeec76ecdb2aff4fb47baeee95ade012225"` (example entry) +* `arch="x86_64"` (example entry) +* `payload_grub="y"` (example entry) +* `payload_grub_withseabios="y"` (example entry) +* `payload_seabios="y"` (example entry) +* `payload_memtest="y"` (example entry) +* `payload_uboot="y"` (example entry) +* `payload_seabios_withgrub="y"` (example entry) +* `grub_scan_disk="ata"` +* `uboot_config=default` + +More information about these and other variables will be provided throughout +this document. + +The `cbtree` entry is actually a link, where its value is a directory name +under `resources/coreboot`. For example, `cbtree="default"` would refer +to `resources/coreboot/default` and the corresponding coreboot source tree +created (when running `./download coreboot`, which makes use of `board.cfg`) +would be `coreboot/default/`. In other words: a `board.cfg` file +in `resources/coreboot/foo` might refer to `resources/coreboot/bar` by +specifying `cbtree="bar"`, and the created coreboot source tree would +be `coreboot/bar/`. ALSO: + +FUN FACT: such references are infinitely checked until resolved. For +example, `foo` can refer to `bar` and `bar` can refer to `baz` but if there is +an infinite loop, this is detected and handled by `lbmk`. For example, +if `bar` refers to `foo` which refers back to `bar`, this is not permitted +and will throw an error in `lbmk`. + +The `romtype` entry largely defines what `./build boot roms` does once the ROM +is built; for example, `romtype="4MiB ICH9 IFD NOR flash"` would specify that +an Intel Flash Descriptor for ICH9M, generated by `ich9gen`, would have to be +inserted. + +The `cbrevision` entry defines which coreboot revision to use, from the +coreboot Git repository. *At present, lbmk only supports use of the official +repository from the upstream coreboot project*. + +The `arch` entry specifies which CPU architecture is to be used: currently +recognized entries are `x86_32`, `x86_64`, `ARMv7` and `AArch64`. *Setting it +to a non-native arch means that necessary crossgcc-arch will be compiled and be +available when building roms, but not necessarily built or discovered when +individual scripts are called manually.* + +The `payload_grub` entry specifies whether or not GRUB is to be included in +ROM images. + +The `payload_grub_withseabios` entry specifies whether or not SeaBIOS is to +be included *with* GRUB, in ROM images. Turning this on also turns +on `payload_seabios_withgrub`, unless that option is explicitly turned off. + +The `payload_seabios` entry specifies whether or not SeaBIOS is to be included +in ROM images. This option is *automatically* enabled +if `payload_grub_withseabios` and/or `payload_seabios_withgrub` are also turned +on. + +The `payload_memtest` entry specifies whether or not MemTest86+ is to be +included in ROM images; it will only be included in ROM images for *text mode* +startup, on x86 machines. + +The `payload_uboot` entry specifies whether or not U-Boot is to be included in +ROM images. + +The `uboot_config` option specifies which U-Boot board configuration file +variant should be used. It currently doesn't make sense for this to be anything +other than `default`, which is the default if the option is missing. + +The `grub_scan_disk` option specifies can be `ahci`, `ata` or `both`, and it +determines which types of disks are to be scanned, when the `grub.cfg` file in +GRUB payloads tries to automatically find other `grub.cfg` files supplied by +your Linux distribution. On some machines, setting it to `ata` or `ahci` +can improve boot speed by reducing delays; for example, trying to scan `ata0` +on a ThinkPad X60 with the optical drive may cause GRUB to hang, so on that +machine it is advisable to set this option to `ahci` (becuse the default HDD +slot is AHCI). + +resources/coreboot/BOARDNAME/config/\* +====================================== + +Files in this directory are *coreboot* configuration files. + +Configuration file names can be as follows: + +* `libgfxinit_corebootfb` +* `libgfxinit_txtmode` +* `vgarom_vesafb` +* `vgarom_txtmode` +* `normal` + +Information pertaining to this can be found on +the [installation manual](../install/) + +In `lbmk`, a board-specific directory under `resources/coreboot/` should never +specify a coreboot revision. Rather, a directory *without* coreboot configs +should be created, specifying a coreboot revision. For example, the +directory `resources/coreboot/default/` specifies a coreboot revision. In the +board-specific directory, your `board.cfg` could then +specify `cbtree="default"` but without specifying a coreboot revision (this +is specified by `resources/coreboot/default/board.cfg`). + +When you create a coreboot configuration, you should set the payload to *none* +because `lbmk` itself will assume that is the case, and insert payloads itself. + +Configurations with `libgfxinit` will use coreboot's native graphics init code +if available on that board. If the file name has `txtmode` in it, coreboot +will be configured to start in *text mode*, when setting up the display. If +the file name has `corebootfb` in it, coreboot will be configured to set up a +high resolution *frame buffer*, when initializing the display. + +NOTE: If the configuration file is `libgfxinit_txtmode`, the SeaBIOS payload +can still run *external* VGA option ROMs on graphics cards, and this is the +recommended setup (SeaBIOS in text mode) if you have a board with both onboard +and an add-on graphics card (e.g. PCI express slot) installed. + +Configuration files with `vgarom` in the name have coreboot itself configured +to run VGA option ROMs (and perhaps other option ROMs). *This* setup is not +strictly recommended for *SeaBIOS*, and it is recommended that you only run +GRUB in this setup. As such, if you wish for a board to have coreboot initialize +the VGA ROM (on an add-on graphics card, as opposed to onboard chipset), you +should have a *separate* directory just for that, under `resources/coreboot/`; +another directory for that board will have configs with `libgfxinit`. HOWEVER: + +It *is* supported in lbmk to have SeaBIOS used, on either setup. In the +directory `resources/seabios/` there are SeaBIOS configs for both; the vgarom +one sets VGA hardware type to *none* while the libgfxinit one sets it +to *coreboot linear framebuffer*. However, if you use SeaBIOS on a setup with +coreboot also doing option ROM initialization, such initialization is being +performed *twice*. As such, if you want to use an add-on graphics card in +SeaBIOS, but the board has libgfxinit, it is recommended that you do it from +a `libgfxinit` ROM. + +HOWEVER: there's no hard and fast rule. For example, you could make a vgarom +configuration, on a board in lbmk, but in its coreboot configuration, don't +enable native init *or* oproms, and do SeaBIOS-only on that board. + +On `vgarom` setups, coreboot can be configured to start with a high resolution +VESA frame buffer (NOT to be confused with the coreboot frame buffer), or just +normal text mode. Text mode startup is always recommended, and in that setup, +GRUB (including coreboot GRUB, but also PC GRUB) can use VGA modes. + +The name `libgfxinit` is simply what `./build boot roms` uses, but it may be +that a board uses the old-school native video init code written in C. On some +platforms, coreboot implemented a 3rd party library called `libgfxinit`, which +is written in Ada and handles video initialization. In this setup, coreboot +*itself* should *never* be configured to run any option ROMs, whether you +start in text mode or with the coreboot framebuffer initialization. + +The `normal` config type is for desktop boards that lack onboard graphics +chipsets, where you would always use an add-on graphics card (or *no* graphics +card, which would be perfectly OK on servers). + +Even if your board doesn't actually use `libgfxinit`, the config for it should +still be named as such. From a user's perspective, it really makes no +difference. + +COREBOOT build system +--------------------- + +If you wish to know about coreboot, refer here:\ + + +This and other documents from coreboot shall help you to understand *coreboot*. + +You create a config, for `resources/coreboot/BOARDNAME/configs`, by running +the `make menuconfig` command in the *coreboot* build system. You should do +this after running `./download coreboot` in lbmk. + +You can simply clone coreboot upstream, add whatever patches you want, and +then you can make your config. It will appear afterwards in a file +named `.config` which is your config for inside `resources/coreboot/BOARDNAME/`. + +You can then use `git format-patch -nX` where `X` is however many patches you +added to that coreboot tree. You can put them in the patches directory +under `resources/coreboot/BOARDNAME`. + +The *base* revision, upon which any custom patches you wrote are applied, +shall be the `cbrevision` entry. + +REMINDER: Do not enable a payload in coreboot's build system. Set it +to *none*, and enable whatever payload you want in lbmk. + +If a payload is not supported in lbmk, patches are very much welcome! It is +the policy of libreboot, to only ever use the *coreboot* build system inside +coreboot, but not use any of *coreboot's* own integration for payloads. It is +far more flexible and *robust* to handle payloads externally, relative to the +coreboot build system. + +Scripts exist in `lbmk` for automating the modification/updating of *existing* +configs, but not for adding them. Adding them is to be done manually, based on +the above guidance. + +ALSO: + +If the option exists, for a given board, please configure coreboot to clear +all DRAM upon boot. This is for security reasons. An exception is made when +such functionality is not available, on the specific board/revision that you're +configuring in coreboot. + +resources/coreboot/BOARDNAME/patches/\* +======================================= + +In cases where `cbrevision` is specified, where the given directory +under `resources/coreboot/` does in fact define a version of coreboot to +download, you can add custom *patches* on top of that revision. When you run +the command `./download coreboot`, those patches will be applied chronologically +in alphanumerical order as per patch file names. + +The patch files should be named with `.patch` file extensions. All other files +will be ignored. By having `lbmk` do it this way, you could add a `README` file +for instance, and `lbmk` will not erroneously try to apply `README` as though +it were a patch file. This might be useful if you have a *lot* of patches, and +you want to provide some explanations about specific files. + +resources/git/revisions +======================= + +This defines git repositories and commit IDs (revisions) to reset to, for +various projects used by Libreboot. *This* file is used, for projects that +are relatively simple to handle when downloading (coreboot is not defined +here). + +In the past, Libreboot had bespoke logic for *each* program, to download it. +This was repetitive, so much of the download logic was centralised with the +use of the `gitclone` script, which references this file. + +resources/grub/background/ +========================== + +Splash screen images applied duing startup when using the GRUB payload. + +resources/grub/config/grub.cfg +============================== + +This is a configuration file. It is used to program GRUB's shell. + +This is inserted (as `grub.cfg`) into the root of CBFS, in the ROM image. It +contains a lot of logic in it, for booting various system configurations, when +the GRUB payload is in use. + +resources/grub/config/grub\_memdisk.cfg +======================================== + +This is a configuration file. It is used to program GRUB's shell. + +This file is inserted (as `grub.cfg`) into the GRUB *memdisk*, when building +the GRUB payload (for coreboot), using GRUB's `grub-mkstandalone` utility. It +simply loads the `grub.cfg` file from CBFS (see above). + +resources/grub/keymap/ +====================== + +This directory contains keymaps for GRUB. They allow for different keyboard +layouts to be used. The `lbmk` build system uses these to produce ROM images +with various keyboard layouts used by default, when the GRUB payload is to be +used. + +They are stored here, directly in GRUB's own `.gkb` file format, which is a +binary format defining which scancodes correspond to which character input. + +This binary format is documented by GRUB; the code for it is easy to +understand. Please read `grub-core/commands/keylayouts.c` in the GRUB source +code. + +resources/grub/modules.list +=========================== + +This file defines all modules that are to be included in builds of GRUB. +They are standalone builds, created using the `grub-mkstandalone` utility. + +resources/grub/patches/ +======================= + +This directory contains custom patches for GRUB. + +resources/me\_cleaner/patches +============================= + +Patches applied to `me_cleaner` when downloading it. + +resources/memtest86plus/patches/ +============================== + +Patches applied to Memtest86+ when downloading it. Libreboot includes +memtest86+ as a secondary payload, loaded from SeaBIOS *or* GRUB when booted +via int10h text mode on x86 hosts. + +(using it with corebootfb mode is also possible, if your machine has a viable +serial output on it with memtest86+ configured accordingly, and this was done +on some older Libreboot releases in the past, but current Libreboot releases +only provide memtest86+ in text mode, for use directly on the machine) + +resources/scripts/ +================== + +These scripts implement the *core* logic of Libreboot's *automated build +system*, to produce coreboot ROM images with payloads. + +resources/scripts/build/ +======================== + +This directory contains shell scripts for compiling various binaries from +available sources. + +resources/scripts/build/boot/ +============================= + +This directory contains shell scripts for compiling ROM images. Many other +scripts in lbmk are called by these scripts; for example, GRUB payload scripts. + +resources/scripts/build/boot/roms +================================= + +This script builds coreboot ROM images. It is largely a shim, which calls +the `roms_helper` script, which does most of the legwork. + +Command: `./build boot roms` + +Additional parameters can be provided. This lists all boards available: + + ./build boot roms list + +Pass several board names if you wish to build only for specific targets. For +example: + + ./build boot roms x60 x200_8mb + +Since November 2022, this script can build images for x86 *and* ARM targets. +The *ARM* targets are ChromeOS devices (chromebooks and such); Libreboot uses +the *U-Boot* payload, rather than Google's *depthcharge* bootloader. In this +setup, U-Boot is running on the bare metal, as enabled by *coreboot*. + +For x86 targets, these scripts build with the GRUB and/or SeaBIOS payloads +inserted into the ROM images; secondary payloads like Memtest86+ are also +handled and inserted here. + +resources/scripts/build/boot/roms\_helper +========================================= + +This script builds coreboot ROM images. It is not to be executed directory; +user interaction must be done via the main `roms` script. + +It heavily makes use of the `board.cfg` file, for a given board. This script +will *only* operate on a single target, from a directory +in `resources/coreboot/`. + +If `grub_scan_disk` is set, it sets that in the `grub.cfg` file that is to be +inserted into a ROM image, when `payload_grub` is turned on. + +It automatically detects if `crossgcc` is to be compiled, on a given coreboot +tree (in cases where it has not yet been compiled), and compiles it for a +target based on the `arch` entry in `board.cfg`. + +It creates ROM images with GRUB, SeaBIOS, U-Boot, optionally with Memtest86+ +also included, in various separate configurations in many different ROM images +for user installation. + +The `romtype` entry in `board.cfg` tells this script what to do with the ROM, +after it has been built. Currently, it operates based on these possible values +for `romtype`: + +* `d8d16sas` will cause *fake* (empty) files named `pci1000,0072.rom` + and `pci1000,3050.rom` to be inserted in CBFS. This prevents SeaBIOS from + loading or executing the option ROM stored on PIKE2008 modules, present on + certain configurations with the ASUS KCMA-D8 or KGPE-D16 mainboards. Those + option ROMs cause the system to hang, so they should never be executed (this + means however that booting Linux kernels from SAS devices is impossible on + those boards, unless a Linux payload is used; Linux can use those SAS drives, + without relying on the PIKE2008 option ROMs). When SeaBIOS runs, it will + default to loading the corresponding option ROM from CBFS, if it exists, for + a given PCI device, overriding whatever option ROM is present on the device + itself, but if the option ROM is invalid/empty, SeaBIOS will not attempt to + load another one, until the empty/invalid one (in CBFS) is deleted. +* `4MiB ICH9 IFD NOR flash`: the `ich9gen` program will be used to insert an + Intel Flash Descriptor and Gigabit Ethernet Non-volatile memory file into + the ROM image. This is used on GM45/ICH9M based laptops, such as: ThinkPad + X200, T400, T500, W500, X200 Tablet, X200S, T400S, X301 +* `8MiB ICH9 IFD NOR flash`: Same as the 4MB one as described above, but for + ROM images with 8MB (64Mbit) of boot flash. The one above is for systems + with 4MB (32Mbit) of flash. +* `16MiB ICH9 IFD NOR flash`: ditto, but for 16MB (128Mbit) flash. In this and + the other two cases as described above, the first 4KB is the Intel Flash + Descriptor, the next 8KB is GbE NVM and the rest is BIOS (for the coreboot + part). In all cases, the default *ME* (Intel Management Engine) region is + disabled, as is the ME itself, based on bits set to disable it in the Intel + Flash Descriptor. The descriptor is used in such a setup, because on all + such boards in libreboot, GbE NVM is needed to get gigabit ethernet working + correctly; it is the sole reason `ich9gen` was written, because it is + otherwise possible to boot these machines in a *descriptorless* setup, where + ICH9M behaves similarly to ICH7: all one region of flash, for the boot + firmware (coreboot), but it results in a non-functional gigabit enternet + device. +* `4MiB ICH9 IFD NOGBE NOR flash`: Intel Flash Descriptor *on its own*, without + ME or GbE NVM. Just IFD and BIOS. This is used on the ThinkPad R500. +* `8MiB ICH9 IFD NOGBE NOR flash`: Same as above, but for 8MB (64Mbit) ROMs +* `16MiB ICH9 IFD NOGBE NOR flash`: Same as above, but for 16MB (128Mbit) ROMs +* `i945 laptop`: in this configuration, the upper 64KB section of the ROM is + copied into the 64KB section below that. This results in there being two + bootblocks in the ROM, and you can decide which one is used by setting `bucts` + +If no payload is defined in `board.cfg`, the `roms_helper` script will exit +with error status. + +If SeaBIOS is to be used, on `libgfxinit` setups, SeaVGABIOS will also be +inserted. This provides a minimal VGA compatibility layer on top of the +coreboot framebuffer, but does not allow for *switching* the VGA mode. It is +currently most useful for directly executing ISOLINUX/SYSLINUX bootloaders, +and certain OS software (some Windows setups might work, poorly, depending on +the board configuration, but don't hold your breath; it is far from complete). + +If SeaBIOS is to be used, in `vgarom` setups or `normal` setups, SeaVGABIOS +is not inserted and you rely on either coreboot and/or SeaBIOS to execute VGA +option ROMs. + +In all cases, this script automatically inserts several SeaBIOS runtime +configurations, such as: `etc/ps2-keyboard-spinup` set to 3000 (PS/2 spinup +wait time), `etc/pci-optionrom-exec` set to 2 (despite that already being +the default anyway) to enable *all* option ROMs, unless `vgarom` setups are +used, in which case the option is set to *0* (disabled) because coreboot is +then expected to handle option ROMs, and SeaBIOS should not do it. + +This script handles U-Boot separately, for ARM-based chromeos devices. + +Essentially, the `roms_helper` script makes use of each and every part of +lbmk. It is the heart of libreboot. + +When the ROM is finished compiling, it will appear under a directory in `bin/` + +resources/scripts/build/clean/cbutils +===================================== + +This simply runs `make clean` on various utilities from coreboot, which lbmk +makes use of. + +Command: `./build clean cbutils` + +resources/scripts/build/clean/crossgcc +====================================== + +This runs `make crossgcc-clean` on all of the coreboot revisions present in +lbmk. + +Command: `./build clean crossgcc` + +resources/scripts/build/clean/flashrom +====================================== + +This runs `make clean` in the `flashrom/` directory. + +Command: `./build clean flashrom` + +resources/scripts/build/clean/grub +================================== + +This runs `make clean` in the `grub/` directory. + +It does not delete anything in `payload/grub/`. + +Command: `./build clean grub` + +resources/scripts/build/clean/ich9utils +======================================= + +This runs `make clean` in the `ich9utils/` directory. + +Command: `./build clean ich9utils` + +resources/scripts/build/clean/memtest86plus +=========================================== + +This runs `make clean` in the `memtest86plus/` directory. + +Command: `./build clean memtest86plus` + +resources/scripts/build/clean/payloads +====================================== + +This deletes the `payload/` directory. + +Command: `./build clean payloads` + +resources/scripts/build/clean/rom\_images +========================================= + +This deletes the `bin/` directory, containing compiled coreboot ROM images. + +Command: `./build clean rom_images` + +resources/scripts/build/clean/seabios +===================================== + +This runs `make clean` in the `seabios/` directory. + +Command: `./build clean seabios` + +resources/scripts/build/clean/u-boot +====================================== + +This runs `make distclean` and `git clean -fdx` on all of the U-Boot revisions +present in lbmk. + +Command: `./build clean u-boot` + +resources/scripts/build/dependencies/arch +========================================= + +Using `pacman`, this installs build dependencies in Arch. It may also work on +similar distros like Manjaro or Artix. + +Command: `./build dependencies arch` + +resources/scripts/build/dependencies/debian +=========================================== + +Using `apt-get`, this installs build dependencies in Debian. It may work on +other `apt-get` distros. + +Command: `./build dependencies debian` + +resources/scripts/build/dependencies/fedora35 +============================================= + +Using `dnf`, this installs build dependencies in Fedora 35. + +Command: `./build dependencies fedora35` + +resources/scripts/build/dependencies/ubuntu2004 +=============================================== + +Using `apt-get`, this installs build dependencies for Ubuntu 20.04 (for later +versions, you might use the Debian script). + +Command: `./build dependencies ubuntu2004` + +resources/scripts/build/dependencies/void +========================================= + +Using `xbps`, this installs build dependencies for Void. + +Command: `./build dependencies void` + +resources/scripts/build/descriptors/ich9m +========================================= + +This runs `ich9gen` to generate descriptors for ICH9M platforms. These are +then stored in `descriptors/ich9m/` + +Command: `./build descriptors ich9m` + +resources/scripts/build/module/cbutils +====================================== + +This compiles various coreboot utilities (such as cbfstool). + +Command: `./build module cbutils` + +resources/scripts/build/module/flashrom +======================================= + +This compiles flashrom. + +Command `./build module flashrom` + +resources/scripts/build/module/grub +=================================== + +This compiles GRUB utilities. It does not build the actual payloads. + +Command: `./build module grub` + +resources/scripts/build/module/ich9utils +======================================== + +This compiles `ich9utils`, which includes the `ich9gen` utility. + +Command: `./build module ich9utils` + +resources/scripts/build/module/memtest86plus +============================================ + +This compiles Memtest86+. + +Command: `./build module memtest86plus` + +resources/scripts/build/payload/grub +==================================== + +This builds the GRUB payloads. + +Command: `./build payload grub` + +resources/scripts/build/payload/seabios +======================================= + +This builds the SeaBIOS payloads. + +Command: `./build payload seabios` + +resources/scripts/build/payload/u-boot +====================================== + +This builds the U-Boot payloads. Usually a target board and a cross-compiler +appropriate for the board must be specified for it to work, because trying to +build for all boards of varying architectures using only the host compiler will +not work. + +Command: `CROSS_COMPILE=aarch64-gnu-linux- ./build payload u-boot qemu_arm64_12mb` + + +resources/scripts/build/release/roms +==================================== + +This builds release archives, containing ROM images. You must only run this +after you've built all of the ROM images that you wish to release. + +Command: `./build release roms` + +resources/scripts/build/release/src +=================================== + +This builds source archives. You must only run this after compiling crossgcc +on all coreboot source trees. + +Command: `./build release src` + +resources/scripts/download/coreboot +=================================== + +This downloads, and patches coreboot, as per `board.cfg` files +in `resources/coreboot/`. + +Command: `./download coreboot` + +NOTE: This version of the script also performs the full git checkout in each +coreboot tree, like so: + + git submodule update --init + +NOTE: `--checkout` is excluded, because such exclusion skips a lot +of blobs during submodule update. This saves work for the project. + +resources/scripts/download/flashrom +=================================== + +This downloads and patches flashrom. + +Command: `./download flashrom` + +resources/scripts/download/grub +=============================== + +This downloads and patches GRUB. + +Command: `./download grub` + +resources/scripts/download/memtest86plus +======================================== + +This downloads and patches Memtest86+. + +Command: `./download memtest86plus` + +resources/scripts/download/seabios +================================== + +This downloads and patches SeaBIOS. + +Command: `./download seabios` + +resources/scripts/download/u-boot +================================= + +This downloads, and patches U-Boot, as per `board.cfg` files +in `resources/u-boot/`. + +Command: `./download u-boot` + +resources/scripts/misc/versioncheck +=================================== + +This updates the text file containing version information. It is used by many +other build scripts. It also updates the files containing the version date. + +You need not run this yourself, directly. + +resources/scripts/modify/coreboot/configs +========================================= + +Loads coreboot configs into coreboot trees, and runs `make menuconfig`, so +that you can easily modify them in an ncurses interface. Additional parameters +are accepted, for example: + + ./modify coreboot configs x60 x200_8mb + +With no additional parameters given, it simply cycles through all configs +under `resources/coreboot/`. + +Command: `./modify coreboot configs` + +resources/scripts/modify/seabios/configs +======================================== + +This lets you modify SeaBIOS configs. + +Command: `./modify seabios configs` + +resources/scripts/modify/u-boot/configs +======================================= + +Loads U-Boot configs into U-Boot trees, and runs `make menuconfig`, so +that you can easily modify them in an ncurses interface. Additional parameters +are accepted, for example: + + ./modify u-boot configs gru_kevin gru_bob + +With no additional parameters given, it simply cycles through all configs +under `resources/u-boot/`. + +Command: `./modify u-boot configs` + +resources/scripts/update/coreboot/configs +========================================= + +This runs `make oldconfig` on coreboot configs under `resources/coreboot/`. +It is most useful when updating a coreboot revision, per `board.cfg`. It allows +additional parameters, for example: + + ./update coreboot configs x60 x200_8mb + +With no additional parameters given, it simply cycles through all configs +under `resources/coreboot/`. + +Command: `./update coreboot configs` + +resources/scripts/update/seabios/configs +======================================== + +This runs `make oldconfig` on SeaBIOS configs. It is most useful when updating +the version of SeaBIOS used by lbmk. + +Command: `./update seabios configs` + +resources/scripts/update/u-boot/configs +========================================= + +This runs `make oldconfig` on U-Boot configs under `resources/u-boot/`. +It is most useful when updating a U-Boot revision, per `board.cfg`. It allows +additional parameters, for example: + + ./update u-boot configs gru_kevin gru_bob + +With no additional parameters given, it simply cycles through all configs +under `resources/u-boot/`. + +However, using `make oldconfig` is not optimal for U-Boot, as their Kconfig +dependencies/defaults are not as well specified as coreboot's is. When updating +configs for an upstream board, it's usually better (but not automated) to: + +- Turn `lbmk` config into a defconfig in the old version +- Compare it with the old version's upstream defconfig +- Apply the difference to the new version's upstream defconfig +- Create an updated config in the new version + +Command: `./update u-boot configs` + +resources/seabios/config/libgfxinit +=================================== + +SeaBIOS configuration file, when `libgfxinit` is to be used. It enables +the `coreboot linear framebuffer` option in the SeaBIOS `make menuconfig` +configuration interface. + +resources/seabios/config/vgarom +=============================== + +This version is for normal SeaBIOS configurations, where `libgfxinit` is not +to be used; coreboot itself handles VGA ROM initialisation. + +resources/seabios/config/normal +=============================== + +This version is for normal SeaBIOS configurations, where `libgfxinit` is not +to be used; coreboot itself does *not* handle VGA ROM initialisation, and it +is assumed that SeaBIOS payload will be used in text mode. In this setup, +SeaBIOS executes VGA ROMs. + +resources/seabios/patches/ +========================== + +This directory contains patch files, automatically applied to SeaBIOS after +downloading it. + +update +====== + +This can be used to update SeaBIOS, coreboot and U-Boot configs. It calls +scripts in `resources/scripts/update/`, for example: + + ./update coreboot configs + +This runs: + + ./resources/scripts/update/coreboot/configs + +Additional parameters can be given, for example: + + ./update coreboot configs x200_8mb x60 + +This would run: + + ./resources/scripts/update/coreboot/configs x200_8mb x60 + +resources/u-boot/ +================= + +This directory contains configuration, patches and so on, for each mainboard +that can use U-Boot as a payload in the `lbmk` build system. U-Boot doesn't yet +have reliable generic configurations that can work across all coreboot boards +(per-architecture), so these are used to build it per-board. + +resources/u-boot/BOARDNAME/ +=========================== + +Each `BOARDNAME` directory defines configuration for a corresponding mainboard. +It doesn't actually have to be for a board; it can also be used to just define +a U-Boot revision, with patches and so on. To enable use as a payload in ROM +images, this must have the same name as its `resources/coreboot/BOARDNAME/` +counterpart. + +resources/u-boot/BOARDNAME/board.cfg +==================================== + +This file can contain several configuration lines, each being a string, such +as: + +* `ubtree="default"` (example entry) +* `ubrevision="4debc57a3da6c3f4d3f89a637e99206f4cea0a96"` (example entry) +* `arch="AArch64"` (example entry) + +These are similar in meaning to their coreboot counterparts. + +The `ubtree` entry is actually a link, where its value is a directory name +under `resources/u-boot`. For example, `ubtree="default"` would refer to +`resources/u-boot/default` and the corresponding U-Boot source tree created +(when running `./download u-boot`, which makes use of `board.cfg`) would be +`u-boot/default/`. In other words: a `board.cfg` file in `resources/u-boot/foo` +might refer to `resources/u-boot/bar` by specifying `ubtree="bar"`, and the +created u-boot source tree would be `u-boot/bar/`. ALSO: + +FUN FACT: such references are infinitely checked until resolved. For +example, `foo` can refer to `bar` and `bar` can refer to `baz` but if there is +an infinite loop, this is detected and handled by `lbmk`. For example, +if `bar` refers to `foo` which refers back to `bar`, this is not permitted +and will throw an error in `lbmk`. + +The `ubrevision` entry defines which U-Boot revision to use, from the U-Boot +Git repository. *At present, lbmk only supports use of the official repository +from the upstream U-Boot project*. + +The `arch` entry specifies which CPU architecture is to be used: currently +recognized entries are `x86_32`, `x86_64`, `ARMv7` and `AArch64`. *Setting it +to a non-native arch means that necessary crossgcc-arch will be compiled and be +available when building roms, but not necessarily built or discovered when +individual scripts are called manually.* + +resources/u-boot/BOARDNAME/config/\* +==================================== + +Files in this directory are *U-Boot* configuration files. Configuration file +names can be anything, but for now `default` is the only one used. + +In `lbmk`, a board-specific directory under `resources/u-boot/` should never +specify a U-Boot revision. Rather, a directory *without* U-Boot configs should +be created, specifying a U-Boot revision. For example, the directory +`resources/u-boot/default/` specifies a U-Boot revision. In the board-specific +directory, your `board.cfg` could then specify `ubtree="default"` but without +specifying a U-Boot revision (this is specified by +`resources/u-boot/default/board.cfg`). + +Normally, the U-Boot build process results in the U-Boot executable and a +device-tree file for the target board, which must further be packaged together +to make things work. When you create a U-Boot configuration, you should enable +`CONFIG_REMAKE_ELF` or `CONFIG_OF_EMBED` that handles this. The former option +enables creation of a `u-boot.elf` that bundles them together after the build, +and the latter option embeds it into the `u-boot` executable. + +When making a U-Boot configuration, you should also pay special attention to +the `CONFIG_SYS_TEXT_BASE` (`CONFIG_TEXT_BASE` in later versions), whose defaults +may cause it to overlap coreboot, in which case it won't boot. Normally, the +upstream coreboot build system checks for this when given `CONFIG_PAYLOAD_ELF`, +but `lbmk` injects the payload itself and doesn't check for this yet. + +Another interesting config option is `CONFIG_POSITION_INDEPENDENT` for ARM +boards, which has been so far enabled in the ones `lbmk` supports, just to be +safe. + +U-Boot build system +------------------- + +If you wish to know about U-Boot, refer here:\ + + +This and other documents from U-Boot shall help you to understand *U-Boot*. + +You create a config, for `resources/u-boot/BOARDNAME/configs`, by finding the +corresponding board name in the upstream U-Boot `configs` directory, and +running `make BOARDNAME_defconfig` and `make menuconfig` commands in the +*U-Boot* build system. You should do this after running `./download u-boot` in +`lbmk`. + +You might want to consider basing your config on the upstream `coreboot` boards +when possible, but such a board is not available upstream for ARM yet. + +You can simply clone U-Boot upstream, add whatever patches you want, and +then you can make your config. It will appear afterwards in a file +named `.config` which is your config for inside `resources/u-boot/BOARDNAME/`. + +You can then use `git format-patch -nX` where `X` is however many patches you +added to that U-Boot tree. You can put them in the patches directory +under `resources/u-boot/BOARDNAME`. + +The *base* revision, upon which any custom patches you wrote are applied, +shall be the `ubrevision` entry. + +Scripts exist in `lbmk` for automating the modification/updating of *existing* +configs, but not for adding them. Adding them is to be done manually, based on +the above guidance. + +resources/u-boot/BOARDNAME/patches/\* +===================================== + +In cases where `ubrevision` is specified, where the given directory +under `resources/u-boot/` does in fact define a version of U-Boot to +download, you can add custom *patches* on top of that revision. When you run +the command `./download u-boot`, those patches will be applied chronologically +in alphanumerical order as per patch file names. + +The patch files should be named with `.patch` file extensions. All other files +will be ignored. By having `lbmk` do it this way, you could add a `README` file +for instance, and `lbmk` will not erroneously try to apply `README` as though +it were a patch file. This might be useful if you have a *lot* of patches, and +you want to provide some explanations about specific files. + +util/ +===== + +This directory contains utilities that `lbmk` makes use of. + +util/nvmutil/ +============= + +The `nvmutil` software allows you to set the MAC address on Intel GbE NVM +files. It also allows you to set *random* MAC addresses, in addition to +arbitrary ones. + +This directory contains the source code for `nvmutil`, which you can read +about here: + +[nvmutil manual](../install/nvmutil.md) + +util/ich9utils/ +=============== + +The `ich9utils` utilities handle ICH9M Flash Descriptors, and GbE NVM configs +for Intel Gigabit Ethernet chipsets used on certain laptops of Intel GM45 +platform, combined with ICH9M southbridge. + +This directory contains the source code for `ich9utils`, which you can read +about here: + +[ich9utils manual](../install/ich9utils.html) + +This source code also pertains to `ich9gen`, which is what GM45 laptops in +Libreboot use in order to generate a config that *excludes* Intel ME firmware. + +Patches welcome. + +If you read this manual from start to finish, you've been assimilated. Welcome +to the team! diff --git a/site/docs/maintain/testing.md b/site/docs/maintain/testing.md new file mode 100644 index 0000000..1c8ce2c --- /dev/null +++ b/site/docs/maintain/testing.md @@ -0,0 +1,89 @@ +--- +title: Apply to become board maintainer/tester for Libreboot +x-toc-enable: true +... + +This page is very new, and these guidelines/procedures will be revised over +time. We are, as of April 2023, formalising our testing / release engineering +procedures somewhat. The Libreboot project is *expanding* to support a lot +more hardware these days. + +Libreboot strives to make Coreboot accessible for as many users as possible. +To accomplish this goal, we must add as many boards as possible. +As the total number of supported boards increases it becomes more and more difficult +for our main contributors to test every single release for every single supported board. +We therefore need the help of the community in testing releases before they are +distributed to users. + +You do *not* need to be a developer in order to be a board maintainer. +All you need to do in order to become a board maintainer is: + ++ Be contactable via email when new testing binaries are available ++ Have the correct equipment ready to externally flash your board ++ Have the board you wish to maintain + +Once you become a board maintainer, your real name and screen name can +be added to the public list on the Libreboot contributors page. +You can, of course, choose to forego the public listing (we will ask for +permission, before publishing your name). + +To apply for such a posting, ping `leah` or `shmalebx9` on +[irc,](../../contact.html#irc-chatroom) or email +Leah Rowe via [leah@libreboot.org](mailto:leah@libreboot.org) +Do not be afraid to apply to maintain a board with another listed +maintainer or multiple maintainers; more is better. + +Please read the following sections to understand the specifics of +maintaining a board. + +NOTE: If there are already testers for a given mainboard, *you* can still +provide testing for the same mainboard if that's what you have. The more the +merrier! + +Be Contactable +============== + +You should monitor whatever email you provide in your application. +There is no specific time-frame for how long it should take after +you receive the email until you report the status of your board. +You should make best efforts to respond within a few days. +If you are the *only* maintainer for your board then please take +into consideration that your input is especially vital. + +Have External Flashing Equipment +================================ + +The roms you test will of course be untested. +To avoid having a bricked machine, you need to have external flashing +equipment available for your board to recover from a broken rom. + +In most cases you can refer to the [SPI guide.](../install/spi.html) +In rarer cases -such as some ARM chromebooks- your board might be flashed in a different way. +Refer to [Coreboot's documentation](https://doc.coreboot.org/) +or ask on IRC if you are unsure. + +Testing Procedure +================= + +You will receive an email when roms are ready for testing. +The email will link to an open issue on our [current git hosting platform.](/git.html#lbmk-libreboot-make) + +Whether you receive an email from a libreboot.org email +domain or one of our developer's email you should verify (for +your own security) +that the downloaded roms are signed with the [official key.](/download.html#gpg-signing-key) + +When your testing is complete, comment on the issue linked in +the dispatch email as follows: + +board: `your board` + +status: `pass/fail` + +note: [insert any notes if relevant] + +For example, a board status comment might look like this: + + board: x200_8mb + status: fail + note: GRUB throws error 'something_is_b0rked' diff --git a/site/docs/misc/codenames.md b/site/docs/misc/codenames.md new file mode 100644 index 0000000..c56a431 --- /dev/null +++ b/site/docs/misc/codenames.md @@ -0,0 +1,127 @@ +--- +title: Product Codenames +x-toc-enable: true +... + +TODO: this page could do with an update. More info, about more boards + +Introduction +============ + +This document lists product codenames for some hardware. +Please note that just because a certain device is listed here does NOT mean +that it is supported in libreboot. For supported devices refer to the +installation documentation. + +### A note on GPUs + +Some laptops come with and without a discrete GPU (dGPU). Whether the +motherboard includes one or not can be determined by (in descending order +of reliability): + +- often thorough disassembly and searching for the actual chip +- looking at white PCB markings near RAM slots / under keyboard + and comparing with some known codenames (if not available FRU ID sticker) + listed below. +- sometimes by looking at heatsink grills: on + discrete GPU laptops these will look orange and on intergrated ones + they will appear silver. + +List of models and codenames +============================ + +### Codenames + +- Samsung Chromebook 2 13": peach-pi +- Samsung Chromebook 2 11": peach-pit +- HP Chromebook 11 G1: spring +- Samsung Chromebook XE303: snow +- HP Chromebook 14 G3: nyan-blaze +- Acer Chromebook 13: (CB5-311, C810) nyan-big +- ASUS Chromebit CS10: veyron-mickey +- ASUS Chromebook Flip C100PA: veyron-minnie +- ASUS Chromebook C201PA: veyron-speedy +- Hisense Chromebook C11 and more: veyron-jerry +- ASUS Chromebook Flip C101: bob +- Samsung Chromebook Plus (v1): kevin + +- ThinkPad X60: KS Note (Sumo) +- ThinkPad X60s (slim): KS Note-2 / KS-2 (Kabuki) +- ThinkPad X60 Tablet: Dali (Same PCB as KS Note-2, different EC firmware) + +- ThinkPad X200: Mocha-1 +- ThinkPad X200s (slim): Pecan-1 +- ThinkPad X200 Tablet: Caramel-1 + +- ThinkPad R400/T400: Malibu-3 + - with discrete GPU (dGPU), at board revision 0: "MLB3D-0 + - with only integrated GPU (iGPU), at board revision 0: "MLB3I-0" + +- ThinkPad T500/W500: Coronado-5 + - with dGPU (radeon): "COR5D-0" (last number is the board revision) + - with only iGPU: "COR5I-0" + +- ThinkPad T400s (slim): Shinai-MV +- ThinkPad R500: Waikiki-3 + +- T6x (whole family): Davinci. They don't have codename label in +silkscreen so you need to use FRU label of the board, which is placed +under RAM sticks. +- T60: + - with dGPU (radeon): Magi-0 (last number is the board revision) + - with iGPU: Lisa-0 + +- R60(e): RP-1, RP-2 - Rockwell / Picasso + +- With ThinkPads on Intel platforms newer than Montevina (Except T410), + the codenames become more consistent. All boards have the following + appended based on the type of graphics they have: + - with dGPU: SWG (SWitchable Graphics) + - with only iGPU: UMA (Unified Memory Access) + +- These are the known model codenames: + - ThinkPad T410: NOZOMI-1 # EXT/INT + - ThinkPad T410s: SHINAI-2 # SWG/UMA + - ThinkPad T420: NOZOMI-3 # SWG/UMA + - ThinkPad T420s: SHINAI-3 # SWG/UMA + - ThinkPad T430: NOZOMI-4 # SWG/UMA + - ThinkPad T430s: SHINAI-4 # SWG/UMA + - ThinkPad T520: KENDO-1 + - ThinkPad W520: KENDO-1 WS + - ThinkPad T520: KENDO-3 + - ThinkPad W520: KENDO-3 WS + - ThinkPad T530: KENDO-4 + - ThinkPad W530: KENDO-4 WS +- ThinkPad T-series dock codenames: + - Advanced Mini Dock - Donatello + - Advanced Mini Dock (lacking SuperIO) - Donatello-lite + - Advanced Dock - Rodin + - Dock II - Aswan + - Mini Dock - Seville + - Port Replicator II - Seville-lite + +### Miscellaneous +- [Calistoga](https://ark.intel.com/products/codename/5950/Calistoga): +945GM/945PM chipset family name +- Napa: calistoga based platform +- [Cantiga](https://ark.intel.com/products/codename/26552/Cantiga): +GM45/GS45/PM45 chipset family name. + This is the chipset used in T400,X200 and similar. +- Montevina: cantiga based platform. +- PMH: the Power Management Hub is a gate array for managing the power + up/down sequence. It is additionally tasked with extending EC's I/O. + Its later version was called "Thinker-1", and eventually it was merged + with PMIC (Rinkan) as ThinkEngine (Do not confuse it with EC chip which is also + has ThinkEngine logo on ThinkPad boards) +- Kozak, Tsurumai, Rinkan: These are successive versions of power management + ICs for Notebook PCs. Tsurumai chip marking is "TB62501F" and datasheet + of it fully describes its operation. + +See also +======== +- Many more Intel codenames can be found at + [Wikipedia](https://en.wikipedia.org/wiki/List_of_Intel_codenames). +- For ThinkPads see [Documentation/thinkpad/codenames.csv @ Coreboot] +(https://review.coreboot.org/cgit/coreboot.git/tree/Documentation/thinkpad/codenames.csv) +- For Chromebooks see [Developer information for ChromeOS devices] +(https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices/) diff --git a/site/docs/misc/emulation.md b/site/docs/misc/emulation.md new file mode 100644 index 0000000..617b975 --- /dev/null +++ b/site/docs/misc/emulation.md @@ -0,0 +1,50 @@ +--- +title: Building Libreboot for Emulation +x-toc-enable: true +... + +Introduction +============ + +Libreboot supports building for qemu as a target board. +The resulting rom can then be tested using qemu. + +The qemu board is mostly intended to speed up development by removing the need to flash to bare metal during initial tests. +Qemu may also be useful for end users who intend to make changes to their libreboot rom without having to flash and reboot their machine. + +Building and Testing +==================== + +Libreboot can be built for qemu just like any other board. + +`./build boot roms qemu_x86_12mb` + +In order to test the resulting roms, you must have qemu installed on the host machine. +Test the roms by pointing qemu to the rom in bios mode. +For example: + +`qemu-system-x86_64 -bios bin/qemu_x86_12mb/grub_qemu_x86_12mb_libgfxinit_corebootfb_usqwerty.rom` + +`qemu-system-x86_64 -bios bin/qemu_x86_12mb/uboot_payload_qemu_x86_12mb_libgfxinit_corebootfb.rom -serial stdio` + +There is basic support for an arm64 virtual machine as well, although the payloads are not as developed as the x86 one: + + ./build boot roms qemu_arm64_12mb + +``` +qemu-system-aarch64 -bios bin/qemu_arm64_12mb/uboot_payload_qemu_arm64_12mb_libgfxinit_corebootfb.rom \ + -M virt,secure=on,virtualization=on,acpi=on -cpu cortex-a53 -m 768M -serial stdio -vga none -display none +``` + +Use Cases +========= + +While development is the primary motivation for qemu support, the board makes it easy to test minor changes to release roms. +For example one can use *cbfstool* from coreboot to edit the background image in a libreboot rom as follows: + +``` +cbfstool /path/to/rom remove -n background.png +cbfstool /path/to/rom add -f mynewbackground.png -n background.png -t raw +``` + +Using qemu allows the user to verify that the background image renders properly before performing the same operation on their release rom. diff --git a/site/docs/misc/index.md b/site/docs/misc/index.md new file mode 100644 index 0000000..820f4de --- /dev/null +++ b/site/docs/misc/index.md @@ -0,0 +1,296 @@ +--- +title: Miscellaneous +x-toc-enable: true +... + +TODO: this page is very old, and could do with an update. + +High Pitched Whining Noise on Idle in Debian or Devuan +====================================================================== + +Start powertop automatically at boot time. + +Included with libreboot is a script called 'powertop.debian'. Run this +as root and it will setup powertop to run with --auto-tune at boot +time. Load the file in your text editor to see how it does that. + + sudo ./resources/scripts/misc/powertop.debian + +Might want to run with --calibrate first + +If powertop doesn't work, another way (reduces battery life slightly) +is to add *processor.max\_cstate=2* to the *linux* line in grub.cfg, +using [this guide](../linux/grub_cbfs.md). + +High Pitched Whining Noise on Idle in Arch-based distros +============================================================== + +The following removes most of the noise. It reduces what is a high +frequency whine (that not everyone can hear) to a slight buzz (which +most people can't hear or doesn't bother most people). + +This is not perfect! The full solution is still not discovered but this +is a step towards that. Also, in some instances you will need to run +'sudo powertop --auto-tune' again. This needs to be implemented +properly in coreboot itself! + +On the X60 with coreboot or libreboot, there is a high pitched sound +when idle. So far we have use processor.max\_cstate=2 or idle=halt in +GRUB. These consume power. Stop using them! + +Be root + + su - + +Installed powertop: + + pacman -S powertop + +and added the following to /etc/systemd/system/powertop.service : + +``` +[Unit] +Description=Powertop tunings + +[Service] +Type=oneshot +RemainAfterExit=no +ExecStart=/usr/bin/powertop --auto-tune +"powertop --auto-tune" still needs a terminal for some reason. Possibly a bug? +Environment="TERM=xterm" + +[Install] +WantedBy=multi-user.target +``` + +Finally, as root do that: + + systemctl enable powertop + systemctl start powertop + +The next time you boot the system, the buzz will be gone. + +Might want to run with --calibrate first + +If powertop doesn't work, another way (reduces battery life slightly) +is to add *processor.max\_cstate=2* to the *linux* line in grub.cfg, +using [this guide](../linux/grub_cbfs.md). + +X60/T60: Serial port - how to use (for dock owners) + +[Note: using a grsec enabled kernel will disable the powertop function. ](https://en.wikibooks.org/wiki/Grsecurity/Appendix/Grsecurity_and_PaX_Configuration_Options) +=================================================== + +For the Thinkpad X60 you can use the "UltraBase X6" dock (for the +X60 Tablet it is called X6 Tablet UltraBase). For the ThinkPad T60, you +can use the "Advanced Mini Dock". + +If you are using one of the ROM images with 'serial' in the name, then +you have serial port enabled in libreboot and you have memtest86+ +included inside the ROM. Connect your null modem cable to the serial +port on the dock and connect the other end to a 2nd system using your +USB Serial adapter. + +On the 2nd system, you can try this (using `screen`): + + sudo screen /dev/ttyUSB0 115200 + +How to quit Screen: Ctrl+A then release and press K, and then press +Y. + +There are also others like Minicom but Screen works nicely. + +By doing this before booting the X60/T60, you will see console output +from libreboot. You will also see GRUB displaying on the serial output, +and you will be able to see MemTest86+ on the serial output aswell. You +can also configure your distro so that a terminal (TTY) is accessible +from the serial console. + +The following guide is for Ubuntu, but it should work in Debian and +Devuan, to enable a serial console using GeTTY:\ + + +Note: part of the tutorial above requires changing your grub.cfg. Just +change the `linux` line to add instructions for enabling getty. See +[../linux/grub\_cbfs.md](../linux/grub_cbfs.md). + +Finetune backlight control on intel gpu's +========================================= + +Sometimes the backlight control value (BLC\_PWM\_CTL) set by libreboot +is not ideal. The result is either flicker, which could cause nausea or +epilepsy or an uneven backlight and/or coil whine coming from the +display. To fix this a different value for the gpu reg BLC\_PWM\_CTL +needs to be set. See p94 of + +for more information on this reg. The tool for setting registry values +on intel gpu's is included in intel-gpu-tools. Install intel-gpu-tools: + + sudo apt-get install intel-gpu-tools + +You can set values: + + sudo intel_reg write 0x00061254 your_value_in_C_hex_format + +NOTE: on older versions of this utility, use `intel_reg_write` instead. + +The value set has the following structure: bits [31:16] is PWM +divider. PWM / PWM\_divider = frequency bits [15:0] is the duty cycle +and determines the portion of the backlight modulation frequency. A +value of 0 will mean that the display is off. A value equal to the +backlight modulation frequency means full on. The value should not be +larger than the backlight modulation frequency. + +On displays with a CCFL backlight start from: 0x60016001 To verify if +all modes work as desired use: `xbacklight -set 10` and gradually +increase until 100. Displays with an LED backlight need a lower +backlight modulation. Do the same thing but start from 0x01290129 . Try +setting different values until you have found a value which presents no +issue. + +It is important to know that there are four failure modes: + +1. flickering very fast, which could cause epilepsy (frequency is too + low. decrease divider) +2. randomly flickering in random intervals - driver IC cannot keep up + with toggling the mosfet (frequency too fast, increase divider) +3. frequency is in audible range and causes coils to whine (frequency + is too high. increase divider) +4. backlight is uneven. (CCFL specific, frequency is too high. increase + divider) + +To check for flickering try moving your laptop while looking at it. + +A higher frequency equals higher power consumption. You want to find the +highest good working value. + +Next this value should be set at boot: either add + + intel_reg write 0x00061254 + +NOTE: on older versions of this utility, use `intel_reg_write` instead. + +before exit 0 in /etc/rc.local or create a systemd service file +/etc/systemd/system/backlight.service: + +``` +[Unit] +Description=Set BLC_PWM_CTL to a good value +[Service] +Type=oneshot +RemainAfterExit=no +ExecStart=/usr/bin/intel_reg write 0x00061254 +[Install] +WantedBy=multi-user.target +``` + +Now start and enable it: + + sudo systemctl start backlight && sudo systemctl enable backlight + +Special note on i945: + +i945 behaves differently. Bit 16 needs to be 1 and the duty cycle is not +updated when backlight is changed. There are no available datasheets on +this target so why it behaves in such a way is not known. So to find a +working value BLC\_PWM\_CTL set bit 16 to 1 and make sure PWM divider == +duty cycle. see on bit 16. The +cause of this issue is that i945, in contrast with to GM45, is set to +work in BLM Legacy Mode. This makes backlight more complicated since the +duty cycle is derived from 3 instead of 2 registers using the following +formula: if(BPC[7:0] <> xFF) then BPCR[15:0] \* BPC[7:0] +Else BPCR[15:0] BPC is LBB - PCI Backlight Control Register, described +on on page 315. BPCR +is BLC\_PWM\_CTL described in + +on page 94. More research needs to be done on this target so proceed +with care. + +Power Management Beeps on Thinkpads +=================================== + +When disconnecting or connecting the charger, a beep occurs. When the +battery goes to a critically low charge level, a beep occurs. Nvramtool +is included in libreboot, and can be used to enable or disable this +behaviour. + +You need to write changes in a libreboot rom image, and flash it, in order +to apply them. You can either use a pre-compiled rom image, or create an image +from the current one in your computer. See here + for +more information on how to do that. + +Once you have a libreboot rom image, say 'libreboot.rom', you can write +changes on the image with the following commands. + +Disable or enable beeps when removing/adding the charger: + + sudo ./nvramtool -C libreboot.rom -w power_management_beeps=Enable + sudo ./nvramtool -C libreboot.rom -w power_management_beeps=Disable + +Disable or enable beeps when battery is low: + + sudo ./nvramtool -C libreboot.rom -w low_battery_beep=Enable + sudo ./nvramtool -C libreboot.rom -w low_battery_beep=Disable + +You can check that the parameters are set in the image with : + + sudo ./nvramtool -C libreboot.rom -a + +Finally, you need to flash the rom with this new image. See here + +for a detailed explanation. + +Get EDID: Find out the name (model) of your LCD panel +===================================================== + +Get the panel name: + + sudo get-edid | strings + +Or look in `/sys/class/drm/card0-LVDS-1/edid` + +Alternatively you can use i2cdump. In Debian and Devuan, this is in the +package i2c-tools. + + sudo modprobe i2c-dev + sudo i2cdump -y 5 0x50 (you might have to change the value for -y) + + sudo rmmod i2c-dev + +You'll see the panel name in the output (from the EDID dump). + +If neither of these options work (or they are unavailable), physically +removing the LCD panel is an option. Usually, there will be information +printed on the back. + +e1000e driver trouble shooting (Intel NICs) +=========================================== + +Example error, ¿may happen on weird and complex routing schemes(citation +needed for cause): + + e1000e 0000:00:19.0 enp0s25: Detected Hardware Unit Hang + +Possible workaround, tested by Nazara: Disable C-STATES. + +*NOTE: this also disables power management, because disabling C-States +means that your CPU will now be running at full capacity (and therefore +using more power) non-stop, which will drain battery life if this is a +laptop. If power usage is a concern, then you should not use this. +(we're also not sure whether this workaround is appropriate)* + +To disable c-states, do this in Linux: + +``` +for i in /sys/devices/system/cpu/cpu/cpuidle/state/disable; +do + echo 1 > $i; +done +``` + +You can reproduce this issue more easily by sending lots of traffic +across subnets on the same interface (NIC). + +More information, including logs, can be found on [this +page](http://web.archive.org/web/20210416010634/https://notabug.org/libreboot/libreboot/issues/23). diff --git a/site/docs/uboot/index.md b/site/docs/uboot/index.md new file mode 100644 index 0000000..7413705 --- /dev/null +++ b/site/docs/uboot/index.md @@ -0,0 +1,82 @@ +--- +title: U-Boot payload +x-toc-enable: true +... + +U-Boot integration in Libreboot is currently at a proof-of-concept +stage, with most boards completely untested and most likely not working. +ROM images for them are mostly intended for further testing and +development. If you have one of these machines and want to help fix +things, you can ping `alpernebbi` on Libera IRC, who ported these boards +to Libreboot. + +As of 14 December 2022, building of U-Boot images has been tested on +Debian. Make sure you have the latest `lbmk` from the Git repository, +and the build dependencies are installed like so, from `lbmk/` as root: + + ./build dependencies debian + +This installs everything needed for `./build boot roms`, and part of the +build process makes use of coreboot's own cross-compile toolchain. + +[QEMU x86/ARM64 virtual machines](../misc/emulation.md) are also +supported, which should be easy targets to start tinkering on if you +want to contribute. + +Usage +===== + +When your board is powered on, U-Boot will ideally turn on the display +and start printing console messages there. After a countdown of a few +seconds it will proceed to automatically boot whatever it can find. +U-Boot will fall back to an interactive prompt if its boot sequence +fails or if you interrupt the countdown. + +U-Boot supports UEFI to some extent, enough to run a GRUB package that +would be installed by whatever OS you want to have on your device. The +boot sequence checks for the standard UEFI removable media paths like +`/efi/boot/bootaa64.efi`, so you should be able to use your desired OS' +generic installer images. For details, see upstream documentation for +[UEFI on U-Boot](https://u-boot.readthedocs.io/en/latest/develop/uefi/uefi.html). + +Otherwise, the boot sequence also checks an `extlinux.conf` file that +can configure which kernel, initramfs, device-tree file and kernel +command line arguments should be used. See upstream documentation for +[Generic Distro Configuration Concept](https://u-boot.readthedocs.io/en/latest/develop/distro.html). + +If you want to work inside the U-Boot shell, see an incomplete list of +[shell commands](https://u-boot.readthedocs.io/en/latest/usage/index.html#shell-commands), +or use the `help` command inside the prompt. Configuration is done via +[environment variables](https://u-boot.readthedocs.io/en/latest/usage/environment.html) +inside the shell, which can be saved to and automatically loaded from +persistent storage configured at build-time. + +WARNING: Environment variable storage has not been explicitly configured +so far and is untested in the context of Libreboot. It may cause data +loss or even brick your device by overwriting your disk's partition +table, unexpected parts of the SPI ROM image, or do something else +entirely. + +Known issues +============ + +U-Boot integration in Libreboot is incomplete. Here is a list of known +issues that affect all boards: + +- Branding is U-Boot with their logo (Libreboot only in version number) +- Splash screen might be better instead of console messages +- Cursor/drawing bugs with video improvements patches +- Environment storage is likely dangerously broken +- SMBIOS info is missing, `Unknown`, `Unknown Product`, etc. +- Coreboot tables are ignored, unavailable to the OS +- Re-inits display instead of using coreboot framebuffer +- Chromebook FMAP layouts should match stock layout for GBB, VPD +- Chromebook GBB, VPD are not handled, data may be unavailable to OS +- U-Boot "coreboot\*" defconfigs needs more work and an ARM64 version +- UEFI support is incomplete + +See also +======== +- [U-Boot documentation](https://u-boot.readthedocs.io/en/latest/) +- [U-Boot documentation (unmigrated files)](https://source.denx.de/u-boot/u-boot/-/tree/master/doc) +- [U-Boot and generic distro boot](https://marcin.juszkiewicz.com.pl/2021/03/14/u-boot-and-generic-distro-boot/) diff --git a/site/docs/uboot/uboot-archlinux.md b/site/docs/uboot/uboot-archlinux.md new file mode 100644 index 0000000..9fe8d8a --- /dev/null +++ b/site/docs/uboot/uboot-archlinux.md @@ -0,0 +1,181 @@ +--- +title: Installing ArchLinuxARM on a Chromebook with U-Boot installed +x-toc-enable: true +... + +Background +========== + +The following process should theoretically be applicable to other U-Boot devices and GNU/Linux distributions, but the focus here is specifically on ArchLinuxARM. + +Sources used for this guide include the [following guide to install ArchLinuxARM on a RockPro64,](https://jforberg.se/blog/posts/2023-02-19-rockpro64/rockpro64.html) + +And the the instructions from the ArchLinuxARM wiki [here](https://archlinuxarm.org/platforms/armv8/rockchip/asus-chromebook-flip-c101pa) +(Be aware that there will be overlap in my documentation with these guides, so some of this information will be very close to verbatim.) + +The purpose of this guide is to instruct users on how to install an ArchLinuxARM on an external disk that will boot on a gru_bob chromebook, and optionally on the internal eMMC. Many concepts covered in this guide may be familiar to prospective and veteran Libreboot users, with the scope being comprehensive. + +Boot Method +=========== + +There are (at least) three methods that can be used to boot into a Linux distribution from u-boot: +1) EFI - common, modern boot method for amd64 architecture machines. This is not distribution-specific, so if you intend to make a portable drive that is compatible across multiple systems, you may have a use case. + +This is an unlikely use-case, so it's a bit odd to use an EFI partition when not using a UEFI system. + +2) boot.scr - a boot script provided by a distribution. Since it is u-boot specific, you will only be able to boot your device from u-boot. +Despite still being distributed by some distros, boot.scr is a legacy boot method according to the u-boot docs: +"Typically we expect extlinux.conf to be used, but execution of boot.scr is maintained for backwards-compatibility." + +For more information about what actually goes into a boot.scr script, check [this page in the u-boot documentation](https://u-boot.readthedocs.io/en/latest/usage/cmd/source.html?highlight=boot.scr#fit-image) + +3) extlinux.conf - a flat, bootloader-spec text file that lives in /boot/extlinux/extlinux.conf. That's all. Not a binary blob in sight! + +Since extlinux.conf is supported by multiple bootloaders, making your system more portable, is natively supported by u-boot, and requires no binary blobs or extra software, it seems to be the best choice for a chromebook. + +Creating extlinux.conf +====================== + +Here is an example template of extlinux.conf, [similar examples are found in the u-boot docs](https://u-boot.readthedocs.io/en/latest/develop/distro.html): + +``` +default arch +menu title Libre-U-Boot menu +prompt 0 +timeout 50 + + +label arch + menu label Arch Linux ARM + linux /Image + initrd /initramfs-linux.img + fdt /dtbs/rockchip/rk3399-gru-bob.dtb + append root=PARTUUID=$PARTUUID rw console=tty1 console=ttyS2,115200 earlycon rootwait LANG=en_US.UTF-8 + +label archfallback + menu label Arch Linux ARM (FALLBACK) + linux /Image + initrd /initramfs-linux-fallback.img + fdt /dtbs/rockchip/rk3399-gru-bob.dtb + append root=PARTUUID=$PARTUUID rw console=tty1 console=ttyS2,115200 earlycon rootwait LANG=en_US.UTF-8 +``` + +Formatting and Partitioning Your External Media +=============================================== + +Now it's time partition the boot disk. During testing, a microSD card was used in the microSD card slot of the gru-bob chromebook. +The libreboot configuration will boot the microSD card above the onboard eMMC if both are present and bootable. This is useful because it means no knowledge or use of the u-boot console is required. + +Since the eMMC is 16GB of storage space, it's advisable to choose an external storage disk of less than 16GB if you intend to install onto the onboard storage, or to create a root partition of less than 15.8GB. + +Find your device with my favourite command, `lsblk` and open it with `fdisk` + +``` +fdisk /dev/sdX +``` +For users creating a bootable SD card, your device may show up as `/dev/mmcblkX` - if this is the case, make sure to change the commands in this guide to +contain that path instead of `/dev/sdX`. + +In the fdisk tui, create two partitions on a Master Boot Record: +- create a new MBR label +- create boot partition of approx. 200MB or greater +- set bootable flag on this partition +- set type to fat32 (ext2 is also supported by extlinux I believe, but I used fat32) +- create a second partition of up to 15.8GB + +You will find the appropriate options by typing `m` when using the fdisk tui on GNU/Linux distros. + +Now make the filesystems: +``` +mkfs.vfat /dev/sdX1 +mkfs.ext4 /dev/sdX2 + +``` + +It's now time to get the PARTUUID of `/dev/sdX2`: +``` +sudo blkid | grep "/dev/sdX2" +``` +make sure to note down the PARTUUID of your second partition; not your boot partition. +paste this into your extlinux.conf file in the `append` section, e.g.: +``` +append console=ttyS0,115200 console=tty1 rw root=PARTUUID=fc0d0284-ca84-4194-bf8a-4b9da8d66908 +``` +in the template provided above, replace `$PARTUUID` with your own. It's possible to specify root in other ways - check the u-boot docs for more examples. + +Boot-Disk Creation +================== + +Now that we've got an extlinux.conf file, copy it to your /tmp directory, and we'll begin. +``` +cd /tmp +curl -LO http://os.archlinuxarm.org/os/ArchLinuxARM-aarch64-latest.tar.gz +mkdir root +mkdir boot +mount /dev/sdX2 root + +mount /dev/sdX1 boot +tar -C boot --strip-components=2 -xvf ArchLinuxARM-aarch64-latest.tar.gz ./boot/ +tar -C root --exclude=./boot -xvf ArchLinuxARM-aarch64-latest.tar.gz +mkdir boot/extlinux +cp extlinux.conf boot/extlinux/extlinux.conf +sync +umount boot +umount root +``` +Note the use of ArchLinuxARM-aarch64-latest.tar.gz and not ArchLinuxARM-gru-latest.tar.gz + +The current gru build only supports a depthcharge payload and, of course, we're not using depthcharge are we? + +With that, you should now have a (kind of) working boot disk - insert your installation media and boot. + +Extensive testing with ArchLinuxARM-latest release, showed that booting the fallback initramfs image will work, but the main image won't. +If you create an extlinux.conf file with paths to both images - like in the template above - you can select either by number at boot. + +Going Live - Necessary Tweaks +============================= + +Once you're at the login prompt, the fun isn't over! Login & password for root are both `root` by default. +Most Arch users will likely try to update their system now - don't update just yet. + +Run `lsblk` and you'll see that the boot partition is not mounted by default. +Updating with `pacman -Syu` at this stage will cause driver problems if you update without your boot partition mounted, likely meaning you cannot connect to the internet with a USB peripheral. + +To prevent this becoming a problem: +``` +mkdir /boot +mount /dev/sdX1 /boot +``` +With that out of the way, yes, you may now update. +It's worth creating a basic filesystem table to automate mounting at boot - it's blank by default so here's another template: + +``` +# Static information about the filesystems. +# See fstab(5) for details. + +# +# /dev/mmcblk1p2 root +UUID=$UUID1 / ext4 rw,relatime 0 1 + +# /dev/mmcblk1p1 boot +UUID=$UUID0 /boot vfat rw,relatime 0 2 +``` +It should go without saying that you'll replace `$UUID0` and `UUID1` with your boot and root filesystem UUID. +To get the right information in there: +``` +lsblk -o NAME,UUID,FSTYPE,SIZE +``` +`NAME` and `SIZE` are not necessary, but they will help you tell which partition is which. + +Final Steps +=========== + +At this stage, you now have a fully functional ArchLinuxARM system on an external disk, and are ready to configure your system. +If you intend to install onto the eMMC module, you can make your changes permanent with: +``` +dd if=/dev/mmcblk0 of=/dev/mmcblk1 bs=4M status=progress +``` + +If you did not update before `dd`-ing your drive, remember that you may still have to use the fallback initramfs to boot properly until you update the kernel. + +This should be everything you need to do for the time being - enjoy configuring your system! diff --git a/site/docs/uboot/uboot-debian-bookworm.md b/site/docs/uboot/uboot-debian-bookworm.md new file mode 100644 index 0000000..3973a3c --- /dev/null +++ b/site/docs/uboot/uboot-debian-bookworm.md @@ -0,0 +1,187 @@ +--- +title: Debian Bookworm Install on a Samsung Chromebook Plus +x-toc-enable: true +... + +System Configuration +==================== + +Hardware: Samsung Chromebook Plus XE513C24 (gru_kevin) + +Libreboot: 2023-04-23 + +Operating System: Debian Bookworm RC2 + +Note! As of this RC2 version of Debian Bookworm, the system automatically +makes use of non-free firmware during install. If your intention is to avoid +all non-free firmware you should avoid using Debian Bookworm or search for a +downstream version of Debian Bookworm that strips out all non-free firmware. +More info in the link below. + +[https://wiki.debian.org/Firmware](https://wiki.debian.org/Firmware) + +Install Media Preparation +========================= + +Follow the Debian installation instructions in the link below: + +[https://www.debian.org/devel/debian-installer/](https://www.debian.org/devel/debian-installer/) + +At the time of this install Debian Bookworm RC2 was recommended on the download +page and I selected the DVD image to have all the packages available when +offline (3.7 gigabyte iso). See the notes below about alternately using the +netinst version. + +[https://cdimage.debian.org/cdimage/bookworm_di_rc2/arm64/iso-dvd/](https://cdimage.debian.org/cdimage/bookworm_di_rc2/arm64/iso-dvd/) + +Write the iso file to a micro sdcard. Replace "sdcard_device" below +with the appropriate device path on your system. +``` +# dd if=debian-bookworm-DI-rc2-arm64-DVD-1.img of=/dev/sdcard_device bs=1M status=progress; sync +``` + +During the install the system automatically makes use of non-free firmware to +activate the wireless network card. For this reason you could choose the +netinst iso and download files as needed rather than using the DVD iso. + +Installation +============ + +1. Insert the micro sdcard into the slot on the Chromebook. +2. Power on the Chromebook. + +The system automatically found an EFI image (efi/boot/bootaa64.efi), but after +loading it the "Synchronous Abort" handler activated and the chromeboot would +reboot. + +Since libreboot/uboot has a 2 second pause at the beginning to stop autoboot if +desired I paused autoboot and it dropped me to the uboot command line. Per the +suggestion from alpernebbi on libreboot IRC I looked for the grub EFI image on +the micro sdcard and started that up instead. Below are the series of uboot +commands I used to understand the media and partition structure. Device 1 is +the micro sdcard slot, and in this case the efi partition is 2. + +``` +Hit any key to stop autoboot: 0 +=> mmc list +mmc@fe320000: 1 +mmc@fe330000: 0 +=> mmc dev 1 +switch to partitions #0, OK +mmc1 is current device +=> mmc part +Partition Map for MMC device 1 -- Partition Type: DOS +Part Start Sector Num Sectors UUID Type +1 0 7766016 00000000-01 83 +2 7766016 15168 00000000-02 ef Boot +=> ls mmc 1:2 + efi/ +168 ubootefi.var +1 file(s), 1 dir(s) +=> ls mmc 1:2 efi/boot + ./ + ../ +872448 bootaa64.efi +4289984 grubaa64.efi +2 file(s), 2 dir(s) +=> +``` + +The following two commands are the ones that were needed to boot the operating +system. + +``` +=> load mmc 1:2 $loadaddr efi/boot/grubaa64.efi +4289984 bytes read in 187 ms (21.9 MiB/s) +=> bootefi $loadaddr +``` + +The grub text menu popped up at this point. See the screen shot below. I +found the first option "Install" provided the easiest install experience as +everything was in text mode and easy to read. The "Graphical install" worked +also, however the screen resolution was so high that all the text and buttons +were quite small on the display and harder to read. + +![](https://av.libreboot.org/xe513c24/debbook-grub.jpg) + +At this point the installation proceeded normally. + +![](https://av.libreboot.org/xe513c24/debbook-lang.jpg) +![](https://av.libreboot.org/xe513c24/debbook-packages.jpg) + +Note that you will see a message during install asking whether you want to +search for non-free firmware. My experience was that the system would use +non-free firmware regardless what I selected in that dialogue. The system was +able to connect wirelessly to the internet and download packages and updates as +needed. + +![](https://av.libreboot.org/xe513c24/debbook-nonfree.jpg) + +Some users have mentioned experiencing corruption of the first partition after +installing Debian Bookworm on a Libreboot / uboot xe513c24 system. This is +possibly due to the experimental nature of the libreboot / uboot system at this +time. + +One potential workaround is to leave some unused space at the beginning of the +drive before the first partition. This can be done by manually partitioning +during install and configuring the first partition to start 100MB or so from +the start of the drive. + +Also, per instructions from alpernebbi on IRC, when you arrive at the stage +where the grub bootloader is installed take special note to select yes to the +option to "Force installation to removable media path", and also say no to the +option to "Update NVRAM variables". If one selects yes on updating NVRAM +variables this can also lead to partition corruption in some instances. + +Lastly when rebooting into your new system you will likely experience the same +synchronous abort issue mentioned above. You can use the same method to pause +the uboot script and drop to the uboot prompt to load and boot the grub efi +image. Depending on how you partitioned the internal emmc drive during +install, the partition number may vary, but below are the applicable commands +on my system. The internal device is 0, and the efi partition was 1. + +``` +=> load mmc 0:1 $loadaddr efi/boot/grubaa64.efi +4289984 bytes read in 187 ms (21.9 MiB/s) +=> bootefi $loadaddr +``` + +Once booted into your Debian Bookworm system you can open a shell as +root and go to the boot efi path to copy the grubaa64.efi file and overwrite it +onto the bootaa64.efi file. + +``` +# cd /boot/efi/EFI/BOOT +# mv BOOTAA64.EFI BOOTAA64.EFI.bak +# cp grubaa64.efi bootaa64.efi +``` + +By doing this the system will boot from uboot normally without needing to drop +to the uboot prompt. This will only last until the next time debian updates +grub though, so you may need to repeat this as a workaround for now. + +Below are a couple screen shots of the installed system running from the +internal emmc. + +![](https://av.libreboot.org/xe513c24/debbook-desktop.jpg) +![](https://av.libreboot.org/xe513c24/debbook-firefox.jpg) + +System Functionality +==================== + +Things that work: + +* Wireless internet and bluetooth (due to non-free firmware) +* Touch screen and stylus +* Touchpad +* Audio (Speakers and headphone jack) +* Volume buttons on side of laptop. +* Graphics (the open source panfrost driver is impressive) +* Playing videos + +Things that do not work: + +* Powering off. You can shutdown in Debian and the system goes through the + normal shut down sequence, but then remains on indefinitely (blue light on + side near power button). You have to hold the power button down for 10 + seconds or so to completely power off the system. diff --git a/site/docs/uboot/uboot-openbsd.md b/site/docs/uboot/uboot-openbsd.md new file mode 100644 index 0000000..75388b4 --- /dev/null +++ b/site/docs/uboot/uboot-openbsd.md @@ -0,0 +1,44 @@ +--- +title: OpenBSD Install Attempt on a Samsung Chromebook Plus +x-toc-enable: true +... + +System Configuration +==================== + +Hardware: Samsung Chromebook Plus XE513C24 (gru_kevin) + +Libreboot: 2023-04-23 + +Operating System: OpenBSD 7.3 + +Install Media Preparation +========================= + +Follow the OpenBSD arm64 installation instructions in the link below: + +https://ftp.openbsd.org/pub/OpenBSD/snapshots/arm64/INSTALL.arm64 + +Write the install73.img file to a micro sdcard. Replace "sdcard_device" below +with the appropriate device path on your system. +``` +# dd if=install73.img of=/dev/sdcard_device bs=1M status=progress; sync +``` + +Installation Attempt +==================== + +1. Insert the micro sdcard into the slot on the Chromebook. +2. Power on the Chromebook. + +Initially things looked promising as the system automatically found the OpenBSD +EFI image on the micro sdcard and proceeded to the OpenBSD boot prompt. However +there was a strange display issue where the first character on each row of the +display was missing. + +After a brief pause, the OpenBSD boot process continued. A message displayed +indicating an error opening random.seed but continued to load the OpenBSD +kernel. Unfortunately the system then froze indefinitely. See screen shot +below. + +![](https://av.libreboot.org/xe513c24/openbsd-attempt.jpg) diff --git a/site/download.md b/site/download.md new file mode 100644 index 0000000..cabfc15 --- /dev/null +++ b/site/download.md @@ -0,0 +1,189 @@ +--- +title: Downloads +x-toc-enable: true +... + +New releases are announced in the [main news section](news/). + +If you're more interested in libreboot development, go to the +[libreboot development page](../git.md), which also includes links to the +Git repositories. The page on [/docs/maintain/](docs/maintain/) describes how +Libreboot is put together, and how to maintain it. If you wish to build +Libreboot from source, [read this page](docs/build/). + +GPG signing key +--------------- + +**The latest *censored* release is Libreboot c20230710, under the `censored` directory.** + +### NEW KEY + +Full key fingerprint: `98CC DDF8 E560 47F4 75C0 44BD D0C6 2464 FA8B 4856` + +This key is for Libreboot releases *after* the 20160907 release. + +Download the key here: [lbkey.asc](lbkey.asc) + +Libreboot releases are signed using GPG. + +### OLD KEY: + +This key is for Libreboot 20160907, and releases older than 20160907: + +Full key fingerprint: CDC9 CAE3 2CB4 B7FC 84FD C804 969A 9795 05E8 C5B2 + +The GPG key can also be downloaded with this exported dump of the +pubkey: [lbkeyold.asc](lbkeyold.asc). + + sha512sum -c sha512sum.txt + gpg --verify sha512sum.txt.sig + +Git repository +-------------- + +Links to regular release archives are listed on this page. + +However, for the absolute most bleeding edge up-to-date version of Libreboot, +there is a Git repository that you can download from. Go here: + +[How to download Libreboot from Git](git.md) + +HTTPS mirrors {#https} +------------- + +**The latest *censored* release is Libreboot c20230710, under the `censored` directory.** + +These mirrors are recommended, since they use TLS (https://) encryption. + +You can download Libreboot from these mirrors: + +* (University +of Kent, UK) +* (MIT university, USA) +* (Princeton +university, USA) +* (shapovalov.tech, Ukraine) +* (koddos.net, Netherlands) +* (koddos.net, Hong Kong) +* (cyberbits.eu, France) +* (mangohost.net, Moldova) + +RSYNC mirrors {#rsync} +------------- + +The following rsync mirrors are available publicly: + +* (University of Kent, +UK) +* (Princeton university, USA) +* (shapovalov.tech, Ukraine) +* (linux.ro, Romania) +* (koddos.net, Netherlands) +* (koddos.net, Hong Kong) +* (mangohost.net, Moldova) + +Are you running a mirror? Contact the libreboot project, and the link will be +added to this page! + +You can make your rsync mirror available via your web server, and also configure +your *own* mirror to be accessible via rsync. There are many resources online +that show you how to set up an rsync server. + +How to create your own rsync mirror: + +Useful for mirroring Libreboot's entire set of release archives. You can put +an rsync command into crontab and pull the files into a directory on your +web server. + +If you are going to mirror the entire set, it is recommended that you allocate +at least 25GiB. Libreboot's rsync is currently about 12GiB, so allocating 25GiB +will afford you plenty of space for the future. At minimum, you should ensure +that at least 15-20GiB of space is available, for your Libreboot mirror. + +*It is highly recommended that you use the libreboot.org mirror*, if you wish +to host an official mirror. Otherwise, if you simply want to create your own +local mirror, you should use one of the other mirrors, which sync from +libreboot.org. + +Before you create the mirror, make a directory on your web server. For +example: + + mkdir /var/www/html/libreboot/ + +Now you can run rsync, for instance: + + rsync -avz --delete-after rsync://rsync.libreboot.org/mirrormirror/ /var/www/html/libreboot/ + +You might put this in an hourly crontab. For example: + + crontab -e + +Then in crontab, add this line and save/exit (hourly crontab): + + 0 * * * * rsync -avz --delete-after rsync://rsync.libreboot.org/mirrormirror/ /var/www/html/libreboot/ + +**It's extremely important to have the final forward slash (/) at the end of each path, +in the above rsync command. Otherwise, rsync will behave very strangely.** + +**NOTE: `rsync.libreboot.org` is not directly accessible by the public, except +those whose IPs are whitelisted. For bandwidth reasons, the firewall running +on libreboot.org blocks incoming rsync requests, except by specific IPs.** + +**If you wish to run an rsync mirror, sync from one of the third party mirrors +above and set up your mirror. You can then contact Leah Rowe, to have your IP +addresses whitelisted for rsync usage - if the IP addresses match DNS A/AAAA +records for your rsync host, this can be used. A script runs in an hourly +crontab on libreboot.org, that fetches the A/AAAA records of whitelisted +rsync mirrors, automatically adding rules permitting them to get through the +firewall.** + +If you wish to regularly keep your rsync mirror updated, you can add it to a +crontab. This page tells you how to use crontab: + + +HTTP mirrors {#http} +------------ + +**The latest *censored* release is Libreboot c20230710, under the `censored` directory.** + +WARNING: these mirrors are non-HTTPS which means that they are +unencrypted. Your traffic could be subject to interference by +adversaries. Make especially sure to check the GPG signatures, assuming +that you have the right key. Of course, you should do this anyway, even +if using HTTPS. + +* (linux.ro, Romania) +* (in-berlin.de, Germany) + +FTP mirrors {#ftp} +----------- + +**The latest *censored* release is Libreboot c20230710, under the `censored` directory.** + +WARNING: FTP is also unencrypted, like HTTP. The same risks are present. + +* (University +of Kent, UK) +* (linux.ro, Romania) + +Statically linked +------------------ + +Libreboot includes statically linked executables in some releases, built from +the available source code. Those executables have certain libraries built into +them, so that the executables will work on many Linux distros. + +Libreboot 20160907 was built in Trisquel Linux, version 7.0 64-bit. +Some older Libreboot releases will have been built in Trisquel 6.0.1. + +To comply with GPL v2, Trisquel 6 and 7 source ISOs are supplied by the +Libreboot project. You can find these source ISOs in the `ccsource` directory +on the `rsync` mirrors. + +Libreboot releases past version 20160907 do not distribute statically linked +binaries. Instead, these releases are source-only, besides pre-compiled ROM +images for which the regular Libreboot source code archives suffice. These newer +releases instead automate the installation of build dependencies, with instructions +in the documentation for building various utilities from source. + +These executables are utilities such as `flashrom`. diff --git a/site/download.uk.md b/site/download.uk.md new file mode 100644 index 0000000..d672a1b --- /dev/null +++ b/site/download.uk.md @@ -0,0 +1,189 @@ +--- +title: Завантаження +x-toc-enable: true +... + +Нові випуски оголошуються в [основній секції новин](news/). + +Якщо ви більше зацікавлені в розробці libreboot, пройдіть на +[сторінку розробки libreboot](../git.md), яка також включає посилання на +репозиторії Git. Сторінка на [/docs/maintain/](docs/maintain/) описує те, як +Libreboot складається разом, і як підтримувати його. Якщо ви бажаєте зібрати +Libreboot із джерельного кода, [прочитайте цю сторінку](docs/build/). + +Код підпису GPG +--------------- + +**Останнім випуском є Censored-Libreboot c20230710, в директорії `censored`.** + +### НОВИЙ КЛЮЧ + +Повний відбиток ключа: `98CC DDF8 E560 47F4 75C0 44BD D0C6 2464 FA8B 4856` + +Вищезазначений ключ для Censored-Libreboot 20230710, та наступних випусків. + +Завантажте ключ тут: [lbkey.asc](lbkey.asc) + +Випуски Libreboot підписані з використанням GPG. + +### СТАРИЙ КЛЮЧ: + +Цей ключ для Libreboot 20160907 та всіх старіших випусків: + +Повний відбиток ключа: CDC9 CAE3 2CB4 B7FC 84FD C804 969A 9795 05E8 C5B2 + +Ключ GPG також може бути завантажений разом із цим експортованим дампом +публічного ключа: [lbkeyold.asc](lbkeyold.asc). + + sha512sum -c sha512sum.txt + gpg --verify sha512sum.txt.sig + +Репозиторій Git +-------------- + +Посилання на архіви регулярних випусків зазначені на цій сторінці. + +Однак, для абсолютно найновішої версії Libreboot, +існує репозиторії Git, з якого можна завантажити. Ідіть сюди: + +[Як завантажити Libreboot через Git](git.md) + +Дзеркала HTTPS {#https} +------------- + +**Останнім випуском є Censored-Libreboot c20230710, в директорії `censored`.** + +Дані дзеркала є рекомендованими, оскільки використовують TLS (https://) шифрування. + +Ви можете завантажити Libreboot через дані дзеркала: + +* (Кентський +університет, Великобританія) +* (Університет МТІ, США) +* (Прінстонський +університет, США) +* (shapovalov.tech, Україна) +* (koddos.net, Нідерланди) +* (koddos.net, Гонконг) +* (cyberbits.eu, Франція) +* (mangohost.net, Moldova) + +Дзеркала RSYNC {#rsync} +------------- + +Наступні дзеркала rsync доступні публічно: + +* (Кентський університет, +Великобританія) +* (Прінстонський університет, США) +* (shapovalov.tech, Україна) +* (linux.ro, Румунія) +* (koddos.net, Нідерланди) +* (koddos.net, Гонконг) +* (mangohost.net, Moldova) + +Ви підтримуєте роботу дзеркала? Зв'яжіться з проектом libreboot, і посилання буде +додано до цієї сторінки! + +Ви можете зробити своє дзеркало rsync доступним через свій веб-сервер, а також налаштувати +ваше *власне* дзеркало бути доступним через rsync. Є багато онлайн-ресурсів, +які показують вам те, як налаштувати сервер rsync. + +Як створити ваше власне дзеркало rsync: + +Корисно для відзеркалювання повного набору архівів випусків Libreboot. Ви можете розмістити +команду rsync в crontab та витягувать файли в директорію на +вашому веб-сервері. + +Якщо ви збираєтесь відзеркалювати повний набір, рекомендовано, щоб вами було виділено +хоча би 25 ГБ. Rsync Libreboot наразі приблизно 12 ГБ, таким чином виділення 25 ГБ +забезпечить вам багато місця на майбутнє. Мінімально, ви маєте переконатись, що +хоча би 15-20 ГБ простору доступно, для вашого дзеркала Libreboot. + +*Настійно рекомендується, щоб ви використовували дзеркало libreboot.org*, якщо бажаєте +розміщувати офіційне дзеркало. В іншому випадку, якщо ви просто бажаєте створити своє власне +локальне дзеркало, вам варто використовувати одне з інших дзеркал, яке синхронізується з +libreboot.org. + +Перед створенням дзеркала, зробіть директорію на вашому веб-сервері. Для +прикладу: + + mkdir /var/www/html/libreboot/ + +Тепер ви можете виконувати rsync, для прикладу: + + rsync -avz --delete-after rsync://rsync.libreboot.org/mirrormirror/ /var/www/html/libreboot/ + +Ви могли би розмістить це в щогодинний crontab. Для прикладу: + + crontab -e + +Потім в crontab, додайте цей рядок і збережіться/вийдіть (щогодинний crontab): + + 0 * * * * rsync -avz --delete-after rsync://rsync.libreboot.org/mirrormirror/ /var/www/html/libreboot/ + +**Це надзвичайно важливо, щоб мати в кінці косу лінію (/) в кінці кожного шляху, +в вищезазначеній команді rsync. В інакшому випадку, rsync буде поводитись дуже дивно.** + +**ПОМІТКА: `rsync.libreboot.org` не є напряму доступним для громадськості, окрім +тих, чиї IP у білому списку. Через пропускну здатність, Брандмауер, який працює +на libreboot.org, блокує вхідні запити rsync, окрім окремих IP.** + +**Якщо ви бажаєте запустити дзеркало rsync, синхронізуйте з одного з дзеркал третіх сторін +вище і встановіть своє дзеркало. Ви можете потім зв'язатись з Лією Роу, щоб мати ваші адреси +IP внесеним в білий список для використання rsync - якщо адреси IP відповідають DNS A/AAAA +записам для вашого хоста rsync, це може бути використано. Сценарій виконується в щогодинному +crontab на libreboot.org, який отримує A/AAAA записи внесених в білий список дзеркал +rsync, автоматично додаючи правила, які дозволяють їм проходити через +брандмауер.** + +Якщо ви бажаєте регулярно тримати свої дзеркала rsync оновленими, ви можете додати це до +crontab. Ця сторінка розповідає вам, як використовувати crontab: + + +Дзеркала HTTP {#http} +------------ + +**Останнім випуском є Censored-Libreboot c20230710, під директорією `censored`.** + +УВАГА: ці дзеркала є не-HTTPS, що означає, що вони +незашифровані. Ваш трафік може бути об'єктом втручання +противників. Особливо ретельно переконайтесь, щоб перевірити підписи GPG, передбачаючи, що +ви маєте правильний ключ. Звісно, вам варто зробити це в будь-якому випадку, навіть +при використанні HTTPS. + +* (linux.ro, Румунія) +* (in-berlin.de, Німеччина) + +Дзеркала FTP {#ftp} +----------- + +**Останнім випуском є Censored-Libreboot 20230710, під директорією `censored`.** + +УВАГА: FTP є також незашифрованим, подібно HTTP. Ті ж самі ризики присутні. + +* (Кентський +університет, Великобританія) +* (linux.ro, Румунія) + +Статично зв'язані +------------------ + +Libreboot включає статично зв'язані виконувані файли в деяких випусках, побудовані з +доступного джерельного кода. Ці виконувані файли мають деякі бібліотеки, вбудовані в +них, так щоб виконувані файли працювали на багатьох дистрибутивах Linux. + +Libreboot 20160907 було побудовано в Trisquel Linux, версія 7.0 64-біти. +Деякі старіші випуски Libreboot буде побудовано в Trisquel 6.0.1. + +Для дотримання GPL v2, Trisquel 6 та 7 джерельні ISO постачаються +проектом Libreboot. Ви можете знайти ці джерельні ISO в директорії `ccsource` +на дзеркалах `rsync`. + +Попередні випуски Libreboot 20160907 не розповсюджують статично зв'язані двійкові +файли. Натомість ці випуски є лише вихідними кодами, окрім попередньо скомпільованих образів +ПЗП, для яких достатньо звичайних архівів джерельного коду Libreboot. Ці новіші +випуски натомість автоматизують встановлення залежностей побудови, з інструкцієї +в документації для побудови різних утиліт з джерельного коду. + +Ці виконувані файли є утилітами, подібними `flashrom`. diff --git a/site/faq.md b/site/faq.md new file mode 100644 index 0000000..62a8ad0 --- /dev/null +++ b/site/faq.md @@ -0,0 +1,1057 @@ +--- +title: Frequently Asked Questions +x-toc-enable: true +... + +AKA Frequently Questioned Answers + +Important issues +================ + +How to compile libreboot from source +------------------------------------ + +Refer to the [lbmk build instructions](docs/build/). + +How does the build system work? +------------------------------- + +Refer to the [lbmk maintenance manual](docs/maintain/). + +Do not use CH341A! +------------------ + +This SPI flasher will damage your chip, and the mainboard that it is connected +to. + +Read the notes about CH341A on [docs/install/spi.md](docs/install/spi.md) to +learn more. + +How Can I Help +-------------- + +If you have a board supported in Libreboot then please consider becoming a +tester. +Testing involves minimal effort and really helps out the project. +See the [board maintainers documentation](/docs/maintain/testing.md) +if you are interested in testing roms before they are released. + +Flashrom complains about DEVMEM access +-------------------------------------- + +If running `flashrom -p internal` for software based flashing, and +you get an error related to /dev/mem access, you should reboot with +`iomem=relaxed` kernel parameter before running flashrom, or use a kernel +that has `CONFIG_STRICT_DEVMEM` and `CONFIG_IO_STRICT_DEVMEM` not enabled. + +Example flashrom output with both `CONFIG_STRICT_DEVMEM` and `CONFIG_IO_STRICT_DEVMEM` enabled: +``` +flashrom v0.9.9-r1955 on Linux 4.11.9-1-ARCH (x86_64) +flashrom is free software, get the source code at https://flashrom.org + +Calibrating delay loop... OK. +Error accessing high tables, 0x100000 bytes at 0x000000007fb5d000 +/dev/mem mmap failed: Operation not permitted +Failed getting access to coreboot high tables. +Error accessing DMI Table, 0x1000 bytes at 0x000000007fb27000 +/dev/mem mmap failed: Operation not permitted +``` + +The backlight is darker on the left side of the screen when lowering the brightness on my ThinkPad X200/X200S/X200T, T400, T500, R400, W500, R500 and other Intel laptops +--------------------------------------------------------------------------------------------------------------- + +We don't know how to detect the correct PWM value to use in +coreboot, so we just use the default one in coreboot which has +this issue on some CCFL panels, but not LED panels. + +You can work around this in your distribution, by following the notes at +[docs: backlight control](../docs/misc/#finetune-backlight-control-on-intel-gpus). + +The ethernet doesn't work on my X200/T400/X60/T60 when I plug in it +------------------------------------------------------------------- + +This was observed on some systems using network-manager. This happens +both on the original BIOS and in libreboot. It's a quirk in the +hardware. On debian systems, a workaround is to restart the networking +service when you connect the ethernet cable: + + sudo service network-manager restart + +On systemd-based distros, you might try: + + sudo systemctl restart network-manager + +(the service name might be different for you, depending on your +configuration) + +My KCMA-D8 or KGPE-D16 doesn't boot with the PIKE2008 module installed +----------------------------------------------------------------------- + +Loading the option ROM from the PIKE2008 module on either ASUS KCMA-D8 +or KGPE-D16 causes the system to hang at boot. It's possible to use +this in the payload (if you use a linux kernel payload, like linuxboot), +or to boot (with SeaGRUB and/or SeaBIOS) from regular SATA and then use +it in Linux. The Linux kernel is capable of using the PIKE2008 +module without loading the option ROM. + +How to save kernel panic logs on thinkpad laptops? +-------------------------------------------------- + +The easiest method of doing so is by using the kernel's netconsole +and reproducing the panic. Netconsole requires two machines, the one that is +panicky (source) and the one that will receive crash logs (target). The +source has to be connected with an ethernet cable and the target has to be +reachable at the time of the panic. To set this system up, execute the +following commands as root on the source (`source#`) and normal user on +the target (`target$`): + +1. Start a listener server on the target machine (netcat works well): + + `target$ nc -u -l -p 6666` + +2. Mount configfs (only once per boot, you can check if it is already mounted + with `mount | grep /sys/kernel/config`. This will return no output + if it is not). + + `source# modprobe configfs` + + `source# mkdir -p /sys/kernel/config` + + `source# mount none -t configfs /sys/kernel/config` + +3. find source's ethernet interface name, it should be of the form `enp*` or + `eth*`, see `ip address` or `ifconfig` output. + + `source# iface="enp0s29f8u1"` change this + + Fill the target machine's IPv4 address here: + + `source# tgtip="192.168.1.2"` change this + + +4. Create netconsole logging target on the source machine: + + `source# modprobe netconsole` + + `source# cd /sys/kernel/config/netconsole` + + `source# mkdir target1; cd target1` + + `source# srcip=$(ip -4 addr show dev "$iface" | grep -Eo '[0-9]+\.[0-9]+\.[0-9]+\.[0-9]+')` + + `source# echo "$srcip" > local_ip` + + `source# echo "$tgtip" > remote_ip` + + `source# echo "$iface" > dev_name` + + `source# arping -I "$iface" "$tgtip" -f | grep -o '..:..:..:..:..:..' > remote_mac` + + `source# echo 1 > enabled` + +5. Change console loglevel to debugging: + + `source# dmesg -n debug` + +6. Test if the logging works by e.g. inserting or removing an USB + device on the source. There should be a few lines appearing in the + terminal, in which you started netcat (nc), on the target host. + +7. Try to reproduce the kernel panic. + +Hardware compatibility +====================== + +What systems are compatible with libreboot? +----------------------------------------------------------------------------------- + +Any system can easily be added, so *compatibility* merely refers to whatever +boards are integrated in the `lbmk` build system, which libreboot uses. + +Please read the [hardware compatibility list](docs/hardware/). + +Freedom pitfalls with modern Intel hardware {#intel} +---------------------------------------------------- + +Coreboot is nominally Free Software, but requires binary blobs on most x86 +targets that it supports, on both Intel and AMD. + +### Intel Management Engine (ME) {#intelme} + +NOTE: The information below is slightly out of date. Nowadays, Intel ME does +not run on an ARC coprocessor, but instead runs on a modified Intel 486 based +architecture, with the ME firmware written for x86 based on the Minix operating +system. However, the overall design philosophy and operation is mostly the +same. + +On *most* current Intel platforms that have Intel ME, it is now possible +to disable Intel ME after BringUp. See: + +\ + +On all GM45+ICH9M laptops that have an Intel ME in it (additionally, this means +X4X+ICH10 desktops), the ME firmware is not needed in the boot flash. Either a +modified descriptor is used, which disables the ME and removes the region for +it in the boot flash, or a descriptorless setup is used. However, all modern +Intel platforms otherwise require an Intel ME image to be present in the main +boot flash. + +Now onto the main topic: + +Introduced in June 2006 in Intel's 965 Express Chipset Family of +(Graphics and) Memory Controller Hubs, or (G)MCHs, and the ICH8 I/O +Controller Family, the Intel Management Engine (ME) is a separate +computing environment physically located in the (G)MCH chip. In Q3 2009, +the first generation of Intel Core i3/i5/i7 (Nehalem) CPUs and the 5 +Series Chipset family of Platform Controller Hubs, or PCHs, brought a +more tightly integrated ME (now at version 6.0) inside the PCH chip, +which itself replaced the ICH. Thus, the ME is ***present on all Intel +desktop, mobile (laptop), and server systems since mid 2006***. + +The ME consists of an ARC processor core (replaced with other processor +cores in later generations of the ME), code and data caches, a timer, +and a secure internal bus to which additional devices are connected, +including a cryptography engine, internal ROM and RAM, memory +controllers, and a ***direct memory access (DMA) engine*** to access the +host operating system's memory as well as to reserve a region of +protected external memory to supplement the ME's limited internal RAM. +The ME also has ***network access*** with its own MAC address through an +Intel Gigabit Ethernet Controller. Its boot program, stored on the +internal ROM, loads a firmware "manifest" from the PC's SPI flash +chip. This manifest is ***signed with a strong cryptographic key***, +which differs between versions of the ME firmware. If the manifest +isn't signed by a specific Intel key, the boot ROM won't load and +execute the firmware and the ME processor core will be halted. + +The ME firmware is compressed and consists of modules that are listed in +the manifest along with secure cryptographic hashes of their contents. +One module is the operating system kernel, which is based on a +***proprietary real-time operating system (RTOS) kernel*** called +"ThreadX". The developer, Express Logic, sells licenses and source +code for ThreadX. Customers such as Intel are forbidden from disclosing +or sublicensing the ThreadX source code. Another module is the Dynamic +Application Loader (DAL), which consists of a ***Java virtual machine*** +and set of preinstalled Java classes for cryptography, secure storage, +etc. The DAL module can load and execute additional ME modules from the +PC's HDD or SSD. The ME firmware also includes a number of native +application modules within its flash memory space, including Intel +Active Management Technology (AMT), an implementation of a Trusted +Platform Module (TPM), Intel Boot Guard, and audio and video DRM +systems. + +The Active Management Technology (AMT) application, part of the Intel +"vPro" brand, is a Web server and application code that enables remote +users to power on, power off, view information about, and otherwise +manage the PC. It can be ***used remotely even while the PC is powered +off*** (via Wake-on-Lan). Traffic is encrypted using SSL/TLS libraries, +but recall that all of the major SSL/TLS implementations have had highly +publicized vulnerabilities. The AMT application itself has ***[known +vulnerabilities](https://en.wikipedia.org/wiki/Intel_Active_Management_Technology#Known_vulnerabilities_and_exploits)***, +which have been exploited to develop rootkits and keyloggers and +covertly gain encrypted access to the management features of a PC. +Remember that the ME has full access to the PC's RAM. This means that +an attacker exploiting any of these vulnerabilities may gain access to +everything on the PC as it runs: all open files, all running +applications, all keys pressed, and more. + +[Intel Boot Guard](https://mjg59.dreamwidth.org/33981.md) is an ME +application introduced in Q2 2013 with ME firmware version 9.0 on 4th +Generation Intel Core i3/i5/i7 (Haswell) CPUs. It allows a PC OEM to +generate an asymmetric cryptographic keypair, install the public key in +the CPU, and prevent the CPU from executing boot firmware that isn't +signed with their private key. This means that ***coreboot and libreboot +are impossible to port*** to such PCs, without the OEM's private +signing key. Note that systems assembled from separately purchased +mainboard and CPU parts are unaffected, since the vendor of the +mainboard (on which the boot firmware is stored) can't possibly affect +the public key stored on the CPU. + +ME firmware versions 4.0 and later (Intel 4 Series and later chipsets) +include an ME application for ***audio and video +[DRM](https://defectivebydesign.org/what_is_drm_digital_restrictions_management)*** +called "Protected Audio Video Path" (PAVP). The ME receives from the +host operating system an encrypted media stream and encrypted key, +decrypts the key, and sends the encrypted media decrypted key to the +GPU, which then decrypts the media. PAVP is also used by another ME +application to draw an authentication PIN pad directly onto the screen. +In this usage, the PAVP application directly controls the graphics that +appear on the PC's screen in a way that the host OS cannot detect. ME +firmware version 7.0 on PCHs with 2nd Generation Intel Core i3/i5/i7 +(Sandy Bridge) CPUs replaces PAVP with a similar DRM application called +"Intel Insider". Like the AMT application, these DRM applications, +which in themselves are defective by design, demonstrate the omnipotent +capabilities of the ME: this hardware and its proprietary firmware can +access and control everything that is in RAM and even ***everything that +is shown on the screen***. + +The Intel Management Engine with its proprietary firmware has complete +access to and control over the PC: it can power on or shut down the PC, +read all open files, examine all running applications, track all keys +pressed and mouse movements, and even capture or display images on the +screen. And it has a network interface that is demonstrably insecure, +which can allow an attacker on the network to inject rootkits that +completely compromise the PC and can report to the attacker all +activities performed on the PC. It is a threat to freedom, security, and +privacy that can't be ignored. + +Before version 6.0 (that is, on systems from 2008/2009 and earlier), the +ME can be disabled by setting a couple of values in the SPI flash +memory. The ME firmware can then be removed entirely from the flash +memory space. The libreboot project [does this](docs/install/ich9utils.md) on +the Intel 4 Series systems that it supports, such as the [ThinkPad +X200](../docs/install/x200_external.md) and [ThinkPad +T400](../docs/install/t400_external.md). ME firmware versions 6.0 and +later, which are found on all systems with an Intel Core i3/i5/i7 CPU +and a PCH, include "ME Ignition" firmware that performs some hardware +initialization and power management. If the ME's boot ROM does not find +in the SPI flash memory an ME firmware manifest with a valid Intel +signature, the whole PC will shut down after 30 minutes. + +Due to the signature verification, developing free replacement firmware +for the ME is basically impossible. The only entity capable of replacing +the ME firmware is Intel. As previously stated, the ME firmware includes +proprietary code licensed from third parties, so Intel couldn't release +the source code even if they wanted to. And even if they developed +completely new ME firmware without third-party proprietary code and +released its source code, the ME's boot ROM would reject any modified +firmware that isn't signed by Intel. Thus, the ME firmware is both +hopelessly proprietary and "tivoized". + +**In summary, the Intel Management Engine and its applications are a +backdoor with total access to and control over the rest of the PC. The +ME is a threat to freedom, security, and privacy, and the libreboot +project strongly recommends avoiding it entirely. Since recent versions +of it can't be removed, this means avoiding all recent generations of +Intel hardware.** + +The *above* paragraph is only talking about setups where the *full* Intel ME +firmware is used, containing networking code and especially *Active Management +Technology* (AMT). + +More information about the Management Engine can be found on various Web +sites, including [me.bios.io](http://me.bios.io/Main_Page), +[unhuffme](http://io.netgarage.org/me/), [coreboot +wiki](http://www.coreboot.org/Intel_Management_Engine), and +[Wikipedia](https://en.wikipedia.org/wiki/Intel_Active_Management_Technology). +The book ***[Platform Embedded Security Technology +Revealed](https://www.apress.com/9781430265719)*** describes in great +detail the ME's hardware architecture and firmware application modules. + +### Firmware Support Package (FSP) {#fsp} + +On all recent Intel systems, coreboot support has revolved around +integrating a blob (for each system) called the *FSP* (firmware support +package), which handles all of the hardware initialization, including +memory and CPU initialization. Reverse engineering and replacing this +blob is almost impossible, due to how complex it is. Even for the most +skilled developer, it would take years to replace. Intel distributes +this blob to firmware developers, without source. + +Since the FSP is responsible for the early hardware initialization, that +means it also handles SMM (System Management Mode). This is a special +mode that operates below the operating system level. **It's possible +that rootkits could be implemented there, which could perform a number +of attacks on the user (the list is endless). Any Intel system that has +the proprietary FSP blob cannot be trusted at all.** In fact, several +SMM rootkits have been demonstrated in the wild (use a search engine to +find them). + +### CPU microcode updates {#microcode} + +The microcode configures logic gates in your CPU, to implement an instruction +set architecture. Your CPU will already contain them, but it also supplies a +way to update the microcode at boot time, fixing bugs and greatly enhancing +the general reliability of your system. + +This interesting video talks about how a group of people reverse engineered +the microcode on AMD processors: + + + +The git repository for that project is here: + + + +Both the video and the repository give some further insight about CPU +microcode. The way it works on AMD will be very similar to Intel. + +### Intel is uncooperative + +For years, coreboot has been struggling against Intel. Intel has been +shown to be extremely uncooperative in general. Many coreboot +developers, and companies, have tried to get Intel to cooperate; namely, +releasing source code for the firmware components. Even Google, which +sells millions of *chromebooks* (coreboot preinstalled) have been unable +to persuade them. + +Even when Intel does cooperate, they still don't provide source code. +They might provide limited information (datasheets) under strict +corporate NDA (non-disclosure agreement), but even that is not +guaranteed. Even ODMs and IBVs can't get source code from Intel, in +most cases (they will just integrate the blobs that Intel provides). + +Newer Intel graphics chipsets also [require firmware +blobs](https://01.org/linuxgraphics/intel-linux-graphics-firmwares?langredirect=1). + +The `libreboot` project *does* provide some support for newer Intel platforms, but +you should be aware of these issues if you choose to run those machines. + +Freedom pitfalls to consider on AMD hardware {#amd} +---------------------------------------------------------------------------- + +AMD has more or less the same problem as Intel, when it comes to software +freedom. + +### AMD Platform Security Processor (PSP) + +This is basically AMD's own version of the [Intel Management +Engine](#intelme). It has all of the same basic security and freedom +issues, although the implementation is wildly different. + +The Platform Security Processor (PSP) is built in on the AMD CPUs whose +[architecture](https://en.wikipedia.org/wiki/List_of_AMD_CPU_microarchitectures) is Late Family 16h (Puma), Zen 17h or later (and also on +the AMD GPUs which are GCN 5th gen (Vega) or later). On the CPUs, a PSP +controls the main x86 core startup. PSP firmware is cryptographically +signed with a strong key similar to the Intel ME. If the PSP firmware +is not present, or if the AMD signing key is not present, the x86 cores +will not be released from reset, rendering the system inoperable. + +The PSP is an ARM core with TrustZone technology, built onto the main +CPU die. As such, it has the ability to hide its own program code, +scratch RAM, and any data it may have taken and stored from the +lesser-privileged x86 system RAM (kernel encryption keys, login data, +browsing history, keystrokes, who knows!). To make matters worse, the +PSP theoretically has access to the entire system memory space (AMD +either will not or cannot deny this, and it would seem to be required to +allow the DRM "features" to work as intended), which means that it has +at minimum MMIO-based access to the network controllers and any other +PCI/PCIe peripherals installed on the system. + +In theory any malicious entity with access to the AMD signing key would +be able to install persistent malware that could not be eradicated +without an external flasher and a known good PSP image. Furthermore, +multiple security vulnerabilities have been demonstrated in AMD firmware +in the past, and there is every reason to assume one or more zero day +vulnerabilities are lurking in the PSP firmware. Given the extreme +privilege level (ring -2 or ring -3) of the PSP, said vulnerabilities +would have the ability to remotely monitor and control any PSP enabled +machine completely outside of the user's knowledge. + +Much like with the Intel Boot Guard (an application of the Intel +Management Engine), AMD's PSP can also act as a tyrant by checking +signatures on any boot firmware that you flash, making replacement boot +firmware (e.g. libreboot, coreboot) impossible on some boards. Early +anecdotal reports indicate that AMD's boot guard counterpart will be +used on most OEM hardware, disabled only on so-called "enthusiast" +CPUs. + +### AMD IMC firmware + +Read . + +NOTE: This section is oudated, and it is in need of cleanup. + +### AMD SMU firmware + +NOTE: This section may be outdated, and it is in need of cleanup. + +Handles some power management for PCIe devices (without this, your +laptop will not work properly) and several other power management +related features. + +The firmware is signed, although on older AMD hardware it is a symmetric +key, which means that with access to the key (if leaked) you could sign +your own modified version and run it. Rudolf Marek (coreboot hacker) +found out how to extract this key [in this video +demonstration](https://media.ccc.de/v/31c3_-_6103_-_en_-_saal_2_-_201412272145_-_amd_x86_smu_firmware_analysis_-_rudolf_marek), +and based on this work, Damien Zammit (another coreboot hacker) +[partially replaced it](https://github.com/zamaudio/smutool/) with free +firmware, but on the relevant system (ASUS F2A85-M) there were still +other blobs present (Video BIOS, and others). + +### AMD AGESA firmware + +NOTE: More needs to be written about this, to reflect the current reality. +The situation with AMD has evolved in recent years. The information on this FAQ +page is a few years out of date. + +This is responsible for virtually all core hardware initialization on +modern AMD systems. In 2011, AMD started cooperating with the coreboot +project, releasing this as source code under a free license. In 2014, +they stopped releasing source code and started releasing AGESA as binary +blobs instead. This makes AGESA now equivalent to [Intel FSP](#fsp). + +### AMD CPU microcode updates + +Read the Intel section +practically the same, though it was found with much later hardware in +AMD that you could run without microcode updates. It's unknown whether +the updates are needed on all AMD boards (depends on CPU). + +### AMD is uncooperative + +AMD seemed like it was on the right track in 2011 when it started +cooperating with and releasing source code for several critical +components to the coreboot project. It was not to be. For so-called +economic reasons, they decided that it was not worth the time to invest +in the coreboot project anymore. Unfortunately they haven't even shared +the source code of AGESA library for a Family 15h Steamroller/Excavator +architectures (which, like the earlier fam15h Bulldozer/Piledriver, do +not have a PSP) and released it to a coreboot project only as a binary. + +For a company to go from being so good, to so bad, in just 3 years, +shows that something is seriously wrong with AMD. Like Intel, they do +not deserve your money. + +Given the current state of Intel hardware with the Management Engine, it +is our opinion that all performant x86 hardware newer than the AMD +Family 15h CPUs (on AMD's side) or anything post-2009 on Intel's side +is defective by design and cannot safely be used to store, transmit, or +process sensitive data. Sensitive data is any data in which a data +breach would cause significant economic harm to the entity which created +or was responsible for storing said data, so this would include banks, +credit card companies, or retailers (customer account records), in +addition to the "usual" engineering and software development firms. +This also affects whistleblowers, or anyone who needs actual privacy and +security. + +Hi, I have <insert random system here>, is it supported? +-------------------------------------------------------------------------------------------------------- + +If coreboot lacks support for your hardware, you must add support for it. +Please consult the coreboot project for guidance. + +General questions +================= + +How do I install libreboot? +------------------------------------------------------- + +See [installation guide](docs/install/) + +How do I program an SPI flash chip? +--------------------------------------------------------------------------------- + +Refer to:\ +[Externally rewrite 25xx NOR flash via SPI protocol](docs/install/spi.md) + +It's possible to use a 16-pin SOIC test clip on an 8-pin SOIC chip, if you +align the pins properly. The connection is generally more sturdy. + +How do I write-protect the flash chip? +---------------------------------------------------------------------------- + +By default, there is no write-protection on a libreboot system. This is +for usability reasons, because most people do not have easy access to an +external programmer for re-flashing their firmware, or they find it +inconvenient to use an external programmer. + +On some systems, it is possible to write-protect the firmware, such that +it is rendered read-only at the OS level (external flashing is still +possible, using dedicated hardware). For example, on current GM45 +laptops (e.g. ThinkPad X200, T400), you can write-protect (see +[ICH9 gen utility](docs/install/ich9utils.md#ich9gen)). + +It's possible to write-protect on all libreboot systems, but the instructions +need to be written. The documentation is in the main git repository, so you are +welcome to submit patches adding these instructions. + +TODO: Document PRx based flash protection on Intel platforms, and investigate +other methods on AMD systems. + +How do I change the BIOS settings? +------------------------------------------------------------------------ + +Most libreboot setups actually use the [GRUB +payload](http://www.coreboot.org/GRUB2). More information about payloads +can be found at +[coreboot.org/Payloads](http://www.coreboot.org/Payloads). SeaBIOS is also +available. The *CMOS* config is hardcoded in libreboot. + +The libreboot project inherits the modular payload concept from coreboot, which +means that pre-OS bare-metal *BIOS setup* programs are not very +practical. Coreboot (and libreboot) does include a utility called +*nvramtool*, which can be used to change some settings. You can find +nvramtool under *coreboot/util/nvramtool/*, in the libreboot source +archives. + +The *-a* option in nvramtool will list the available options, and *-w* +can be used to change them. Consult the nvramtool documentation on the +coreboot wiki for more information. + +In practise, you don't need to change any of those settings, in most +cases. + +Default libreboot setups lock the CMOS table, to ensure consistent functionality +for all users. You can use: + + nvramtool -C yourrom.rom -w somesetting=somevalue + +To get a full list of available options, do this: + + nvramtool -C yourrom.rom -a + +This will change the default inside that ROM image, and then you can +re-flash it. + +How do I pad a ROM before flashing? +-------------------------------------- + +It is advisable to simply use a larger ROM image. This section was written +mostly for ASUS KCMA-D8 and KGPE-D16 mainboards, where previously we only +provided 2MiB ROM images in libreboot, but we now provide 16MiB ROM images. +Other sizes are not provided because in practise, someone upgrading one of +these chips will just use a 16MiB one. Larger sizes are available, but 16MiB +is the maximum that you can use on all currently supported libreboot systems +that use SPI flash. + +Required for ROMs where the ROM image is smaller than the flash chip +(e.g. writing a 2MiB ROM to a 16MiB flash chip). + +Create an empty (00 bytes) file with a size the difference between +the ROM and flash chip. The case above, for example: + + truncate -s +14MiB pad.bin + +For x86 descriptorless images you need to pad from the *beginning* of the ROM: + + cat pad.bin yourrom.rom > yourrom.rom.new + +For ARM and x86 with intel flash descriptor, you need to pad after the image: + + cat yourrom.rom pad.bin > yourrom.rom.new + +Flash the resulting file. Note that cbfstool will not be able to +operate on images padded this way so make sure to make all changes to +the image, including runtime config, before padding. + +To remove padding, for example after reading it off the flash chip, +simply use dd(1) to extract only the non-padded portion. Continuing with the +examples above, in order to extract a 2MiB x86 descriptorless ROM from a +padded 16MiB image do the following: + + dd if=flashromread.rom of=yourrom.rom ibs=14MiB skip=1 + +With padding removed cbfstool will be able to operate on the image as usual. + +Do I need to install a bootloader when installing a distribution? +--------------------------------------------------------------------------------------------------- + +Most libreboot setups integrate the GRUB bootloader already, as a +*[payload](http://www.coreboot.org/Payloads)*. This means that the GRUB +bootloader is actually *flashed*, as part of the boot firmware +(libreboot). This means that you do not have to install a boot loader on +the HDD or SSD, when installing a new distribution. You'll be able to +boot just fine, using the bootloader (GRUB) that is in the flash chip. + +This also means that even if you remove the HDD or SSD, you'll still +have a functioning bootloader installed which could be used to boot a +live distribution installer from a USB flash drive. See +[How to install Linux on a libreboot system](../docs/linux/grub_boot_installer.md) + +Nowadays, other payloads are also provided. If you're using the SeaBIOS payload, +then the normal MBR bootsector is used on your HDD or SSD, like you would +expect. So the above paragraphs only apply to the GRUB payload. + +Do I need to re-flash when I re-install a distribution? +------------------------------------------------------------------------------------------- + +Not anymore. Recent versions of libreboot (using the GRUB payload) will +automatically switch to a GRUB configuration on the HDD or SSD, if it +exists. You can also load a different GRUB configuration, from any kind +of device that is supported in GRUB (such as a USB flash drive). For +more information, see +[Modifying the GRUB Configuration in libreboot Systems](../docs/linux/grub_cbfs.md) + +If you're using the SeaBIOS payload, it's even easier. It works just like you +would expect. SeaBIOS implements a normal x86 BIOS interface. + +What does a flash chip look like? +----------------------------------------------------------------- + +You can find photos of various chip types on the following page:\ +[External 25xx NOR flashing guide](docs/install/spi.md) + +Inability to modprobe thinkpad\_acpi on Haswell +=============================================== + +This was reported by a user, running Debian 11 with +kernel `5.19.0-0.deb11.2-amd64`. The `thinkpad_acpi` module was not loading, +with the following message: + +``` +modprobe: ERROR: could not insert 'thinkpad_acpi': "No such device" +``` + +Battery info in `/sys` was absent, because of this. The user reported that +the following workaround was effective (in Debian). + +Add this line to `/etc/modprobe.d/thinkpad_acpi.conf`: + +``` +options thinkpad_acpi force_load=1 +``` + +tlp +--- + +You can install the `tlp` package and start that service. For example, on +Debian: + +``` +apt-get install tlp tlp-rdw +systemctl enable tlp +systemctl start tlp +``` + +Now read the manual: + +``` +man tlp-stat +``` + +As root, you can do: + +``` +tlp-stat -b +``` + +This will provide information about the battery. + +What other firmware exists outside of libreboot? +================================================== + +### External GPUs + +The Video BIOS is present on most video cards. For integrated graphics, +the VBIOS (special kind of OptionROM) is usually embedded +in the main boot firmware. For external graphics, the VBIOS is +usually on the graphics card itself. This is usually proprietary; the +only difference is that SeaBIOS can execute it (alternatively, you embed it +in a coreboot ROM image and have coreboot executes it, if you use a +different payload, such as GRUB). + +The *coreboot project* provides free initialization code, on many boards, and +libreboot will use this code when it is available, depending on the configuration. + +In configurations where SeaBIOS and native GPU init are used together, +a special shim VBIOS is added that uses coreboot linear framebuffer. + +### EC (embedded controller) firmware + +Most (all?) laptops have this. The EC (embedded controller) is a small, +separate processor that basically processes inputs/outputs that are +specific to laptops. For example: + +- When you flick the radio on/off switch, the EC will enable/disable + the wireless devices (wifi, bluetooth, etc) and enable/disable an + LED that indicates whether it's turned on or not +- Listen to another chip that produces temperature readings, adjusting + fan speeds accordingly (or turning the fan(s) on/off). +- Takes certain inputs from the keyboard, e.g. brightness up/down, + volume up/down. +- Detect when the lid is closed or opened, and send a signal + indicating this. +- Etc. + +EC is present on nearly all laptops. Other devices use, depending on complexity, +either EC or variant with firmware in Mask ROM - SuperIO. + +### HDD/SSD firmware + +HDDs and SSDs have firmware in them, intended to handle the internal +workings of the device while exposing a simple, standard interface (such +as AHCI/SATA) that the OS software can use, generically. This firmware +is transparent to the user of the drive. + +HDDs and SSDs are quite complex, and these days contain quite complex +hardware which is even capable of running an entire operating system (by +this, we mean that the drive itself is capable of running its own +embedded OS), even Linux. + +SSDs and HDDs are a special case, since they are persistent storage +devices as well as computers. + +Example attack that malicious firmware could do: substitute your SSH +keys, allowing unauthorized remote access by an unknown adversary. Or +maybe substitute your GPG keys. SATA drives can also have DMA (through +the controller), which means that they could read from system memory; +the drive can have its own hidden storage, theoretically, where it could +read your LUKS keys and store them unencrypted for future retrieval by +an adversary. + +With proper IOMMU and use of USB instead of SATA, it might be possible +to mitigate any DMA-related issues that could arise. + +Some proof of concepts have been demonstrated. For HDDs: + For SSDs: + + +Viable free replacement firmware is currently unknown to exist. For +SSDs, the +[OpenSSD](https://web.archive.org/web/20220425071606/http://www.openssd-project.org/wiki/The_OpenSSD_Project) +project may be interesting. + +Apparently, SATA drives themselves don't have DMA but can make use of +it through the controller. This + +(pages 388-414, 420-421, 427, 446-465, 492-522, 631-638) and this + +(pages 59, 67, 94, 99). + +The following is based on discussion with Peter Stuge (CareBear\\) in +the coreboot IRC channel on Friday, 18 September 2015, when +investigating whether the SATA drive itself can make use of DMA. The +following is based on the datasheets linked above: + +According to those linked documents, FIS type 39h is *"DMA Activate FIS +- Device to Host"*. It mentions *"transfer of data from the host to +the device, and goes on to say: Upon receiving a DMA Activate, if the +host adapter's DMA controller has been programmed and armed, the host +adapter shall initiate the transmission of a Data FIS and shall transmit +in this FIS the data corresponding to the host memory regions indicated +by the DMA controller's context."* FIS is a protocol unit (Frame +Information Structure). Based on this, it seems that a drive can tell +the host controller that it would like for DMA to happen, but unless the +host software has already or will in the future set up this DMA transfer +then nothing happens. **A drive can also send DMA Setup**. If a DMA +Setup FIS is sent first, with the Auto-Activate bit set, then it is +already set up, and the drive can initiate DMA. The document goes on to +say *"Upon receiving a DMA Setup, the receiver of the FIS shall +validate the received DMA Setup request."* - in other words, the host +is supposed to validate; but maybe there's a bug there. The document +goes on to say *"The specific implementation of the buffer identifier +and buffer/address validation is not specified"* - so noone will +actually bother. *"the receiver of the FIS"* - in the case we're +considering, that's the host controller hardware in the chipset and/or +the kernel driver (most likely the kernel driver). All SATA devices have +flash-upgradeable firmware, which can usually be updated by running +software in your operating system; **malicious software running as root +could update this firmware, or the firmware could already be +malicious**. Your HDD or SSD is the perfect place for a malicious +adversary to install malware, because it's a persistent storage device +as well as a computer. + +Based on this, it's safe to say that use of USB instead of SATA is +advisable if security is a concern. USB 2.0 has plenty of bandwidth for +many HDDs (a few high-end ones can use more bandwidth than USB 2.0 is +capable of), but for SSDs it might be problematic. USB 3.0 will provide more +reasonable performance, though note that depending on the system, you may have +to deal with binary blob XHCI firmware in your kernel (if that bothers you). + +Use of USB is also not an absolute guarantee of safety, so do beware. +The attack surface becomes much smaller, but a malicious drive could +still attempt a "fuzzing" attack (e.g. sending malformed USB +descriptors, which is how the tyrant DRM on the Playstation 3 was +broken, so that users could run their own operating system and run +unsigned code). (you're probably safe, unless there's a security flaw +in the USB library/driver that your OS uses. USB is generally considered +one of the safest protocols, precisely because USB devices have no DMA) + +Other links: + +- + +It is recommended that you use full disk encryption, on HDDs connected +via USB. There are several adapters available online, that allow you to +connect SATA HDDs via USB, and Libreboot is capable of booting from them the +normal way. Consult the documentation for your Linux/BSD operating system, so +that you can know how to install it with *full disk encryption*. + +The current theory (unproven) is that this will at least prevent +malicious drives from wrongly manipulating data being read from or +written to the drive, since it can't access your LUKS key if it's only +ever in RAM, provided that the HDD doesn't have DMA (USB devices don't +have DMA). The worst that it could do in this case is destroy your data. +Of course, you should make sure never to put any keyfiles in the LUKS +header. **Take what this paragraph says with a pinch of salt. This is +still under discussion, and none of this is proven.** + +### NIC (ethernet controller) + +Ethernet NICs will typically run firmware inside, which is responsible +for initializing the device internally. Theoretically, it could be +configured to drop packets, or even modify them. + +With proper IOMMU, it might be possible to mitigate the DMA-related +issues. A USB NIC can also be used, which does not have DMA. + +### CPU microcode + +Microcode configures logic gate arrays in a microprocessor, to implement the +instruction set architecture. Special *decoders* in the microprocessor will +configure the circuitry, based on that microcode. + +### Sound card + +Sound hardware (integrated or discrete) typically has firmware on it +(DSP) for processing input/output. Again, a USB DAC is a good +workaround. + +### Webcam + +Webcams have firmware integrated into them that process the image input +into the camera; adjusting focus, white balancing and so on. Can use USB +webcam hardware, to work around potential DMA issues; integrated webcams +(on laptops, for instance) are discouraged by the libreboot project, for +security reasons. + +### USB host controller + +USB host controllers require firmware. Sometimes, this has to be supplied +by coreboot itself. + +### WWAN firmware + +Some laptops might have a simcard reader in them, with a card for +handling WWAN, connecting to a 3g/4g (e.g. GSM) network. This is the +same technology used in mobile phones, for remote network access (e.g. +internet). + +NOTE: not to be confused with wifi. Wifi is a different technology, and +entirely unrelated. + +The baseband processor inside the WWAN chip will have its own embedded +operating system, most likely proprietary. Use of this technology also +implies the same privacy issues as with mobile phones (remote tracking +by the GSM network, by triangulating the signal). + +On some laptops, these cards use USB (internally), so won't have DMA, +but it's still a massive freedom and privacy issue. If you have an +internal WWAN chip/card, the libreboot project recommends that you +disable and (ideally, if possible) physically remove the hardware. If +you absolutely must use this technology, an external USB dongle is much +better because it can be easily removed when you don't need it, thereby +disabling any external entities from tracking your location. + +Use of ethernet or wifi is recommended, as opposed to mobile networks, +as these are generally much safer. + +Operating Systems +================= + +Can I use Linux? +-------------------------------------------------- + +Absolutely! It is well-tested in libreboot, and highly recommended. See +[installing Linux](../docs/linux/grub_boot_installer.md) and +[booting Linux](../docs/linux/grub_cbfs.md). + +Any recent distribution should work, as long as it uses KMS (kernel mode +setting) for the graphics. + +Fedora won't boot? (may also be applicable to Redhat/CentOS) +----------------------------------------------------------- + +On Fedora, by default the grub.cfg tries to boot linux in 16-bit mode. You +just have to modify Fedora's GRUB configuration. +Refer to [the Linux page](docs/linux/). + +Can I use BSD? +---------------------------------- + +Absolutely! The libreboot firmware has good support for FreeBSD, NetBSD and +OpenBSD. Other systems are untested, but should work just fine. + +See: +[docs/bsd/](docs/bsd/) + +Are other operating systems compatible? +------------------------------------------------------------------- + +Unknown. Perhaps so, but it's impossible to say without further testing. + +What level of software freedom does libreboot give me? +=================================================== + +The libreboot firmware provides host hardware initialisation inside ROM files, +that can be written to NOR flash, but on many systems there exist +a lot more small computers on the mainboard running blob firmware. +Some of them are not practicable to replace due to being located on Mask ROM. +Most laptops have EC (Embedded Controller) firmware, for example. + +Besides software itself (embedded in ROM or not), most hardware +(from ICs to circuit boards) are not released under open source licenses. +We do not have a single device that can be considered be "100% free", +and such absolutes are nearly impossible to reach. + +Notable proprietary blobs (not a complete list): + +* All devices + * SATA/PATA Hard Drive/Optical Disc Drive Firmware + ([often contain powerful ARM based computer]( + http://spritesmods.com/?art=hddhack&page=1)) + * Pendrives and any USB peripherals - they contain a computer + with code running to at the very least handle the USB protocol +* ThinkPads: + * EC Firmware (H8S until including Sandy Bridge, later ARC based MEC16xx) + * TrackPoint Firmware (8051) + * Penabled devices contain µPD78F0514 MCU on wacom subboard, + and Atmega (AVR) on led indicator/button board + * Battery BMS, bq8030 (CoolRISC C816) +* Chomebooks C201PA/C100PA: + * Battery BMS, bq30z55 + * Elan Touchpad + * eMMC [flash memory controller](https://en.wikipedia.org/wiki/Flash_memory_controller) firmware + +One day, we will live in a world where anyone can get their own chips made, +including CPUs but also every other type of IC. Efforts to make homemade +chip fabrication a reality are now in their infancy, but such efforts do +exist, for example, the work done by Sam Zeloof and the Libre Silicon project: + +* +* +* + +(Sam literally makes CPUs in his garage) + +Where can I learn more about electronics +========================================== + +* Basics of soldering and rework by PACE + Both series of videos are mandatory regardless of your soldering skill. + * [Basic Soldering](https://yewtu.be/playlist?list=PL926EC0F1F93C1837) + * [Rework and Repair](https://yewtu.be/playlist?list=PL958FF32927823D12) + The PACE series above covers classic techniques, but does not cover much + about *modern* electronics. For that, see: + * [iFixit microsoldering lessons, featuring Jessa + Jones](https://yewtu.be/playlist?list=PL4INaL5vWobD_CltiZXr7K46oJ33KvwBt) + * Also see youtube links below, especially Louis Rossman videos, to learn + a (lot) more. +* [edX course on basics of electronics](https://www.edx.org/course/circuits-and-electronics-1-basic-circuit-analysi-2) + In most countries contents of this course is covered during + middle and high school. It will also serve well to refresh your memory + if you haven't used that knowledge ever since. +* Impedance intro + * [Similiarities of Wave Behavior](https://yewtu.be/watch?v=DovunOxlY1k) + * [Reflections in tranmission line](https://yewtu.be/watch?v=y8GMH7vMAsQ) + * Stubs: + * [Wikipedia article on stubs](https://en.wikipedia.org/wiki/Stub_(electronics)) + * [Polar Instruments article on stubs](http://www.polarinstruments.com/support/si/AP8166.html) + With external SPI flashing we only care about unintended PCB stubs +* [How to accurately measure header/connector pitch](https://www.microcontrollertips.com/accurately-measure-headerconnector-pitch/) +* Other YouTube channels with useful content about electronics + * [EEVblog](https://yewtu.be/channel/UC2DjFE7Xf11URZqWBigcVOQ) + (generally about electronics, reviews about equipment, etc, some + repair videos) + * [Louis Rossmann](https://yewtu.be/channel/UCl2mFZoRqjw_ELax4Yisf6w) + (right to repair advocacy, lots of macbook repair videos) + * [mikeselectricstuff](https://yewtu.be/channel/UCcs0ZkP_as4PpHDhFcmCHyA) + * [bigclive](https://yewtu.be/channel/UCtM5z2gkrGRuWd0JQMx76qA) + * [ElectroBOOM](https://yewtu.be/channel/UCJ0-OtVpF0wOKEqT2Z1HEtA) + (he blows stuff up, and shows you how not to do that) + * [Jeri Ellsworth](https://yewtu.be/user/jeriellsworth/playlists) + (has a video showing how to make a *transistor* yourself) + * [Sam Zeloof](https://yewtu.be/channel/UC7E8-0Ou69hwScPW1_fQApA) + (Sam literally makes CPUs in his garage, inspired by Jeri Ellsworth's + work with transistors) + * [iPad Rehab with Jessa Jones](https://yewtu.be/channel/UCPjp41qeXe1o_lp1US9TpWA) + (very precise soldering. she does repairs on mobile phones and such, also + featured in iFixit's series about getting into component repairs) +* Boardview files can be open with [OpenBoardview](https://github.com/OpenBoardView/OpenBoardView), +which is libre software under MIT license. + +Use of `yt-dlp` (an enhanced fork of `youtube-dl`) is recommended for links +to `youtube.com`. See: + +Lastly the most important message to everybody gaining this wonderful new hobby - [Secret to Learning Electronics](https://yewtu.be/watch?v=xhQ7d3BK3KQ) diff --git a/site/faq.uk.md b/site/faq.uk.md new file mode 100644 index 0000000..bdf9c6e --- /dev/null +++ b/site/faq.uk.md @@ -0,0 +1,1048 @@ +--- +title: Часті питання +x-toc-enable: true +... + +Також відомо як Відповіді на часті питання + +Важливі питання +================ + +Як скомпілювати libreboot з джерельного коду +------------------------------------ + +Зверніться до [інструкцій зі збірки lbmk](docs/build/). + +Як працює система збірки? +------------------------------- + +Зверніться до [посібника з обслуговування lbmk](docs/maintain/). + +Не використовуйте CH341A! +------------------ + +Цей програматор SPI пошкодить ваш чіп і материнську плату, до якої він +підключений. + +Прочитайте примітки щодо CH341A на [docs/install/spi.md](docs/install/spi.md), щоб +вивчити більше. + +Flashrom скаржиться на доступ DEVMEM +-------------------------------------- + +Якщо запущено `flashrom -p internal` для програмної перепрошивки та +ви отримуєте помилку, пов'язану з доступом до /dev/mem, вам слід перезавантажити систему з +параметром ядра `iomem=relaxed` перед виконанням flashrom, або використовуйте ядро, +для якого не ввімкнено `CONFIG_STRICT_DEVMEM` та `CONFIG_IO_STRICT_DEVMEM`. + +Приклад виводу flashrom з обома `CONFIG_STRICT_DEVMEM` та `CONFIG_IO_STRICT_DEVMEM` ввімкненими: +``` +flashrom v0.9.9-r1955 on Linux 4.11.9-1-ARCH (x86_64) +flashrom is free software, get the source code at https://flashrom.org + +Calibrating delay loop... OK. +Error accessing high tables, 0x100000 bytes at 0x000000007fb5d000 +/dev/mem mmap failed: Operation not permitted +Failed getting access to coreboot high tables. +Error accessing DMI Table, 0x1000 bytes at 0x000000007fb27000 +/dev/mem mmap failed: Operation not permitted +``` + +Підсвічування в лівій частині екрана стає темнішим, якщо зменшити яскравість мого ноутбука ThinkPad X200/X200S/X200T, T400, T500, R400, W500, R500 та інших ноутбуків Intel +--------------------------------------------------------------------------------------------------------------- + +Ми не знаємо, як визначити правильне значення ШІМ для використання в +coreboot, тому ми просто використовуємо стандартне в coreboot, який має +цю проблему на деяких CCFL панелях, але не LED панелях. + +Ви можете вирішити цю проблему у своєму дистрибутиві, дотримуючись приміток на +[документація: контроль підсвічуванням](../docs/misc/#finetune-backlight-control-on-intel-gpus). + +Ethernet не працює на моєму X200/T400/X60/T60, коли я його підключаю +------------------------------------------------------------------- + +Це спостерігалося в деяких системах, які використовують network-manager. Таке буває +як в оригінальному BIOS, так і в libreboot. Це примха в +обладнанні. У системах debian обхідним шляхом є перезапуск сервіса +мережі, коли ви підключаєте кабель ethernet: + + sudo service network-manager restart + +На systemd ви можете спробувати: + + sudo systemctl restart network-manager + +(назва служби може відрізнятися для вас, залежно від вашої +конфігурації) + +Мій KCMA-D8 або KGPE-D16 не завантажується з встановленим модулем PIKE2008 +----------------------------------------------------------------------- + +Завантаження Option ROM з модуля PIKE2008 на ASUS KCMA-D8 +або KGPE-D16 викликає зависання системи під час завантаження. Можна використовувати +це в корисному навантаженні (якщо ви використовуєте корисне навантаження ядра linux, таке як linuxboot), +або завантажитись (з SeaGRUB та/або SeaBIOS) зі звичайного SATA, а потім використовувати +це в Linux. Ядро Linux здатне використовувати PIKE2008 +модуль без завантаження Option ROM. + +Як зберегти журнали паніки ядра на ноутбуках Thinkpad? +-------------------------------------------------- + +Найпростіший спосіб зробити це за допомогою netconsole ядра +і відтворення паніки. Netconsole вимагає двох машин, тієї, що є +панічною (джерело) і той, яка отримуватиме журнали збоїв (ціль). Джерело +має бути підключеним кабелем ethernet, а ціль також бути доступною +під час паніки. Щоб налаштувати цю систему, виконайте +наступні команди як root на джерелі (`джерело#`) і звичайний користувач +на цілі (`ціль$`): + +1. Запустіть сервер слухача на цільовій машині (netcat працює добре): + + `ціль$ nc -u -l -p 6666` + +2. Монтуйте configfs (тільки один раз на завантаження, ви можете перевірити, чи він уже змонтований + з `mount | grep /sys/kernel/config`. Це не поверне результат, + якщо це не так). + + `джерело# modprobe configfs` + + `джерело# mkdir -p /sys/kernel/config` + + `джерело# mount none -t configfs /sys/kernel/config` + +3. знайдіть назву інтерфейсу ethernet джерела, вона має мати форму `enp*` або + `eth*`, дивіться вивід `ip address` або `ifconfig`. + + `джерело# iface="enp0s29f8u1"` змініть це + + Заповніть адресу IPv4 цільової машини тут: + + `джерело# tgtip="192.168.1.2"` змініть це + + +4. Створіть ціль журналювання netconsole на вихідній машині: + + `джерело# modprobe netconsole` + + `джерело# cd /sys/kernel/config/netconsole` + + `джерело# mkdir target1; cd target1` + + `джерело# srcip=$(ip -4 addr show dev "$iface" | grep -Eo '[0-9]+\.[0-9]+\.[0-9]+\.[0-9]+')` + + `джерело# echo "$srcip" > local_ip` + + `джерело# echo "$tgtip" > remote_ip` + + `джерело# echo "$iface" > dev_name` + + `джерело# arping -I "$iface" "$tgtip" -f | grep -o '..:..:..:..:..:..' > remote_mac` + + `джерело# echo 1 > enabled` + +5. Змініть рівень журналу консолі на налагодження: + + `джерело# dmesg -n debug` + +6. Перевірте, чи працює журнал, наприклад, вставленням або вийманням USB- + пристроїв на джерелі. + Має з'явитись кілька рядків в терміналі, у якому ви запустили netcat (nc), на цільовому хості. + +7. Спробуйте відтворити паніку ядра. + +Апаратна сумісність +====================== + +Які системи сумісні з libreboot? +----------------------------------------------------------------------------------- + +Будь-яку систему можна легко додати, тому *сумісність* посилається до будь-якої +інтегрованої до системи побудови `lbmk` плати, яку libreboot використовує. + +Прочитайте [список сумісного обладнання](docs/hardware/). + +Пастки свободи з сучасним обладнанням Intel {#intel} +---------------------------------------------------- + +Coreboot номінально є вільним програмним забезпеченням, але для більшості x86 +цілей, які він підтримує, потрібні двійкові блоби, як на Intel, так і на AMD. + +### Intel Management Engine (ME) {#intelme} + +ПРИМІТКА: Інформація нижче трохи застаріла. Зараз Intel ME не +працює на співпроцесорі ARC, а працює на архітектурі модифікованого процесора Intel 486, +з прошивкою ME, написаною для x86 на основі операційної системи Minix. +Однак загальна філософія дизайну та функціонування в основному є тою +самою. + +На *більшості* сучасних платформ Intel, які мають Intel ME, зараз можливо відключити +Intel ME після BringUp. Дивіться: + +\ + +На всіх ноутбуках GM45+ICH9M, які мають Intel ME (крім того, це означає настільні комп'ютери +X4X+ICH10), прошивка ME не потрібна у завантажувальній флеш-пам'яті. Або використовується +модифікований дескриптор, який вимикає ME та видаляє регіон для нього +в завантажувальній флеш-пам'яті, або використовується налаштування без дескрипторів. Проте всі сучасні +платформи Intel в іншому випадку вимагають наявності образа Intel ME в основній завантажувальній +флеш-пам'яті. + +Тепер до основної теми: + +Представлений в червні 2006 року в сімействі чіпсетів Intel 965 Express контролерів- +концентраторів (графіки та) пам'яті, або (G)MCH, і сімейство контролерів ICH8 I/O, +Intel Management Engine (ME) є окремим +обчислювальним середовищем, фізично розташованим в чіпі (G)MCH. У третьому кварталі 2009 року, +перше покоління процесорів Intel Core i3/i5/i7 (Nehalem) і п'ята серія +сімейства чіпсетів концентраторів-контролерів платформи, або PCH, принесли +більш тісно інтегрований ME (зараз версії 6.0) всередині чіпа PCH, +який сам по собі замінив ICH. Таким чином, ME ***присутній на всіх настільних, +мобільних (ноутбуки) та серверних системах з середини 2006 року***. + +ME складається з ядра процесора ARC (замінено іншими ядрами процесора +в наступних поколіннях ME), кеша коду та даних, таймера +і безпечної внутрішньої шини, до якої підключаються додаткові пристрої, +включаючи механізм криптографії, внутрішні ROM та RAM, контролери +пам'яті та ***механізм прямого доступу до пам'яті (DMA)*** для доступу до +пам'яті операційної системи хоста, також щоб зарезервувати регіон +захищеної зовнішньої пам'яті для доповнення обмеженої внутрішньої оперативної пам'яті ME. +ME також має ***доступ до мережі*** з власною MAC-адресою через +контролер Intel Gigabit Ethernet. Його програма завантаження, збережена на внутрішній +ROM, завантажує "маніфест" прошивки з чіпа флеш-пам'яті SPI ПК. +Цей маніфест ***підписано надійним криптографічним ключем***, +який відрізняється між версіями мікропрограми ME. Якщо маніфест +не підписано певним ключем Intel, завантажувальна ROM не завантажиться і не +виконається прошивка, і ядро процесора ME буде зупинено. + +Прошивка ME стиснена та складається з модулів, перелічених в +маніфесті, разом із безпечними криптографічними хешами їх змісту. +Одним модулем є ядро операційної системи, яке базується на +***пропрієтарному ядрі операційної системи реального часу (RTOS)***, під назвою +"ThreadX". Розробник, Express Logic, продає ліцензії і джерельний +код для ThreadX. Клієнтам, таким як Intel, заборонено розголошувати +або виконувати субліцензіювання джерельного кода ThreadX. Іншим модулем є +Dynamic Application Loader (DAL), який складається з ***віртуальної машини Java*** +та набора передвстановлених класів Java для криптографії, безпечного зберігання і +так далі. Модуль DAL може завантажувати та виконувати додаткові модулі ME з +HDD або SSD ПК. Прошивка ME також містить ряд нативних +модулів додатків у своєму просторі флеш-пам'яті, включаючи Intel +Active Management Technology (AMT), реалізації Trusted +Platform Module (TPM), Intel Boot Guard, аудіо та відео DRM +системи. + +Програма Active Management Technology (AMT), частина бренда Intel +"vPro", є веб-сервером і програмним кодом, що дозволяє віддаленим +користувачам вмикать, вимикать, дивиться інформацію та тощо +керувати ПК. Це може ***використовуватись дистанційно, навіть коли ПК +вимкнено*** (через Wake-on-Lan). Трафік зашифровано з використанням бібліотек SSL/TLS, +але пам'ятайте, що всі основні реалізації SSL/TLS мали дуже +оприлюднені вразливості. Сама програма AMT має ***[відомі +вразливості](https://uk.wikipedia.org/wiki/Active_Management_Technology#Проблеми_безпеки)***, +які використовувалися для розробки руткітів і кейлоггерів, а також таємного +отримання зашифрованого доступа до функцій керування ПК. +Пам'ятайте, що ME має повний доступ до оперативної пам'яті ПК. Це означає, що +зловмисник, який використовує будь-яку з цих вразливостей, може отримати доступ до +всього на ПК: усі відкриті файли, усі працюючи +програми, усі натиснуті клавіши, тощо. + +[Intel Boot Guard](https://mjg59.dreamwidth.org/33981.md) є застосунком ME, +представленим у другому кварталі 2013 року з мікропрограмою ME, версії 9.0 на четвертому +поколінні процесорів Intel Core i3/i5/i7 (Haswell). Це дозволяє виробникам комплектного обладнання для ПК +згенерувати асиметричну криптографічну пару ключів, встановити публічний ключ +в ЦП і запобігти ЦП від запуску завантажувальної мікропрограми, яка не підписана +з їх приватним ключем. Це означає, що ***coreboot та libreboot +неможливо перенести*** на такі ПК, без приватного ключа підпису +OEM. Зверніть увагу, що системи, зібрані з придбаних окремо материнської плати +та ЦП залишаються незмінними, оскільки постачальник материнської +плати (на якій зберігається завантажувальна прошивка) не може вплинути на +публічний ключ, що зберігається в ЦП. + +Прошивка ME версій 4.0 та пізніше (Intel серії 4 та пізніші чіпсети) +включає програму ME для ***аудіо та відео +[DRM](https://defectivebydesign.org/what_is_drm_digital_restrictions_management)*** +під назвою "Захищений аудіо-відеошлях" (PAVP). ME отримує від операційної системи хоста +зашифрований медіа-потік і зашифрований ключ, +розшифровує ключ і надсилає розшифрований ключ до +GPU, яка потім розшифровує медіа. PAVP також використовується іншим ME +застосунком, щоб намалювати розкладку PIN-код аутентифікації прямо на екрані. +У цьому випадку програма PAVP безпосередньо керує графікою, що +з'являється на екрані ПК, таким чином, що хостова ОС не може виявити. Версія прошивки ME +7.0 на PCH з процесорами Intel Core i3/i5/i7 +(Sandy Bridge) 2-го покоління замінює PAVP подібним застосунком DRM під назвою +"Intel Insider". Як і програма AMT, ці програми DRM, +які самі по собі дефектні за задумом, демонструють всемогутність можливості +ME: це обладнання та його пропрієтарна мікропрограма можуть отримати доступ і контролювати +все, що є в оперативній пам'яті і навіть ***все, що +відображається***. + +Intel Management Engine із власною мікропрограмою мають завершений +доступ до і контроль над ПК: він може вмикати або вимикати ПК, +читати всі відкриті файли, перевіряти всі запущені програми, відстежувати всі натиснуті +клавіши та рухи миші і навіть записувати або відображати зображення на +екрані. І він має мережевий інтерфейс, який явно незахищений, +що може дозволити зловмиснику в мережі ін'єктувати руткіти, які +повністю компрометують ПК і повідомляють зловмиснику про всю +активність, яка відбувається на ПК. Це загроза свободі, безпеці та +приватності, яка не може бути проігнорована. + +До версії 6.0 (тобто в системах 2008/2009 і раніше), +ME можна вимкнути, встановивши пару значень у флеш-пам'яті SPI. +Прошивку ME потім можна повністю видалити з простору флеш- +пам'яті. Проект libreboot [робить це](docs/install/ich9utils.md) на +системах Intel серії 4, які він підтримує, наприклад [ThinkPad +X200](../docs/install/x200_external.uk.md) та [ThinkPad +T400](../docs/install/t400_external.md). Прошивка ME версії 6.0 та +пізніше, яка є на всіх системах з процесорами Intel Core i3/i5/i7 +PCH, включає мікропрограму "ME Ignition", яка виконує деяку апаратну +ініціалізацію та контроль живленням. Якщо завантажувальний ROM ME не знаходить +в флеш-пам'яті SPI маніфест прошивки ME з дійсним підписом Intel, +весь ПК буде вимкнено через 30 хвилин. + +Завдяки перевірці підпису, розробка вільної заміни +для ME в принципі неможлива. Єдина сутність, здатна замінити +прошивку ME - Intel. Як зазначалось раніше, мікропрограма ME містить +пропрієтарний код, ліцензованим третіми сторонами, тому Intel не змогла би +випустити джерельний код, навіть якщо вони би цього хотіли. І навіть якщо вони розробили би повністю +нову прошивку ME без стороннього пропрієтарного коду і +випустили би джерельний код, завантажувальна ROM ME відхиляла би змінену +прошивку, яка не підписана Intel. Таким чином, прошивка ME є і +безнадійно пропрієтарною, і "тивоізованою". + +**Підсумовуючи, Intel Management Engine і його програми є +лазівкою з повним доступом до та контролем над рештою ПК. +ME є загрозою свободі, безпеці та конфіденційності, і проект libreboot +наполегливо рекомендує повністю уникати цього. З останніх версій +його не можна видалити, це означає уникати всіх останніх поколінь обладнання +Intel.** + +У *вищому* параграфі йдеться про використання *повної* прошивки Intel ME, +що містить мережевий код і в особливості *Active Management +Technology* (AMT). + +Більше інформації про Management Engine може бути знайдено на різноманітних веб- +сайтах, включаючи [me.bios.io](http://me.bios.io/Main_Page), +[unhuffme](http://io.netgarage.org/me/), [coreboot +wiki](http://www.coreboot.org/Intel_Management_Engine), та +[Wikipedia](https://uk.wikipedia.org/wiki/Intel_Active_Management_Technology). +Книга ***[Platform Embedded Security Technology +Revealed (Розкрито вбудовану технологію безпеки платформи)](https://www.apress.com/9781430265719)*** чудово описує в +значних подробицях архітектуру апаратного забезпечення ME та прикладні модулі мікропрограми. + +### Firmware Support Package (FSP) {#fsp} + +У всіх останніх системах Intel, підтримка coreboot обертається навколо +інтеграції блоба (для кожної системи) під назвою *FSP* (Firmware Support Package, пакет підтримки +мікропрограми), який обробляє всю ініціалізацію обладнання, включаючи +пам'ять та ініціалізацію ЦП. Зворотня розробка та заміна цього +блоба майже неможлива через те, наскільки він складний. Навіть для найбільш +кваліфікованого розробника, на заміну знадобяться роки. Intel розповсюджує +цей блоб серед розробників прошивки, без джерела. + +Оскільки FSP відповідає за ранню ініціалізацію обладнання, це означає, +що він також підтримує SMM (System Management Mode, режим системного керування). Це особливий +режим, який працює нижче рівня операційної системи. **Це можливо, що руткіти +можуть бути реалізовані там, які можуть виконувати ряд +атак на користувача (список нескінченний). Будь-яка система Intel, яка +має пропрієтарний блоб FSP взагалі не може бути довіреною.** Фактично, декілька +руткітів SMM було продемонстровано в природі (використайте пошукову систему, +щоб знайти їх). + +### Оновлення мікрокода ЦП {#microcode} + +Мікрокод налаштовує логічні вентилі у вашому ЦП, щоб реалізувати архітектуру +набору інструкцій. Ваш ЦП уже містить їх, але він також надає спосіб оновлення +мікрокоду під час завантаження, виправляючи помилки та значно підвищуючи +загальну надійність вашої системи. + +У цьому цікавому відео розповідається про те, як група людей +провела зворотню розробку мікрокода на процесорах AMD: + + + +Репозиторій git для цього проекту тут: + + + +І відео, і репозиторій дають деяку додаткову інформацію про мікрокод +ЦП. Те, як це працює на AMD, буде дуже схожим на Intel. + +### Intel не співпрацює + +Роками coreboot бореться з Intel. Виявилося, що Intel загалом +вкрай відмовляється від співпраці. Багато розробників coreboot +і компаній намагалися залучити Intel до співпраці; а саме, +випуск джерельного коду для компонентів мікропрограми. Навіть Google, що +продає мільйони *хромбуків* (з попередньо встановленим coreboot) не змогла їх +переконати. + +Навіть коли Intel співпрацює, вони все одно не надають джерельний код. +Вони можуть надавати обмежену інформацію (таблиці даних) відповідно до суворої +корпоративної NDA (угоди про нерозголошення), але навіть це не +гарантується. Навіть ODM та IBV не можуть отримати джерельний код від Intel, в +більшості випадків (вони просто інтегрують блоки, надані Intel). + +Новіші графічні чіпсети Intel [вимагають блобів +прошивки](https://01.org/linuxgraphics/intel-linux-graphics-firmwares?langredirect=1). + +Проект `libreboot` *надає* деяку підтримку для новіших платформ Intel, але +вам варто знати про ці проблемні питання, якщо ви вибираєте використовувати ці машини. + +Підводні камені свободи, які слід враховувати на апаратному забезпеченні AMD {#amd} +---------------------------------------------------------------------------- + +AMD має більш-менш ту саму проблему, що й Intel, коли справа +стосується свободи програмного забезпечення. + +### AMD Platform Security Processor (PSP) + +По суті, це власна версія [Intel Management +Engine](#intelme) від AMD. Він має ті самі базові проблеми безпеки та свободи, +хоча реалізація кардинально відрізняється. + +Процесор безпеки платформи (Platform Security Processor, PSP) вбудовано в процесори AMD, +[архітектура](https://en.wikipedia.org/wiki/List_of_AMD_CPU_microarchitectures) яких пізня родини 16h (Puma), Zen 17h або пізніше (а також у +графічні процесори AMD GCN 5-го покоління (Vega) або пізніше). На процесорах PSP +контролює запуск основного ядра x86. Прошивка PSP має криптографічний підпис +надійним ключем, подібно до Intel ME. Якщо вбудована прошивка PSP +відсутня або ключ підпису AMD відсутній, ядра x86 не +будуть відпущені з перезавантаження, що призведе до непрацездатності системи. + +PSP - це ядро ARM із технологією TrustZone, вбудоване в головний +процесор. Таким чином, він має можливість приховувати власний програмний код, +скидати оперативну пам'ять і будь-які дані, які він міг взяти та зберегти з +менш привілейованої системної оперативної пам'яті x86 (ключі шифрування ядра, дані входу, +історія перегляду, натискання клавіш, хто знає!). Що ще гірше, +PSP теоретично має доступ до всього простору системної пам'яті (AMD +або не буде, або не зможе заперечити це, і це, здається, потрібно, +щоб "функції" DRM могли працювати належним чином), що означає, що він має +принаймні доступ на основі MMIO до мережевих контролерів та будь-яких інших +периферійних пристроїв PCI/PCIe, встановлених у системі. + +Теоретично будь-який зловмисник, який має доступ до ключа підпису AMD міг +би встановити стійке зловмисне програмне забезпечення, яке не можливо було би викорінити +без обладнання для зовнішньої прошивки та завідомо справного образу PSP. Крім того, +у мікропрограмному забезпеченні AMD у минулому було продемонстровано численні вразливості системи безпеки, +і є всі підстави припускати, що одна або декілька вразливостей нульового дня +ховаються в мікропрограмному забезпеченні PSP. Враховуючи надзвичайний рівень +привілеїв (кільце -2 або кільце -3) PSP, зазначені уразливості матимуть +можливість віддалено відстежувати та контролювати будь-яку машину з підтримкою PSP +абсолютно поза знаннями користувача. + +Подібно до Intel Boot Guard (додаток Intel +Management Engine), PSP від AMD також може діяти як тиран, перевіряючи +підписи будь-якої завантажувальної мікропрограми, яку ви прошиваєте, унеможливлюючи заміну +завантажувальної мікропрограми (наприклад, libreboot, coreboot) на деяких платах. Ранні +неофіційні повідомлення свідчать про те, що аналог AMD boot guard буде використовуватися +на більшості апаратного забезпечення OEM, відключений лише на так званих процесорах +"ентузіастів". + +### Прошивка AMD IMC + +Прочитайте . + +ПРИМІТКА: Ця секція є застарілою, та потребує очищення. + +### Прошивка AMD SMU + +ПРИМІТКА: Ця секція є застарілою, та потребує очищення. + +Керує деякими функціями керування живленням для пристроїв PCIe (без цього ваш ноутбук +не працюватиме належним чином) і кількома іншими функціями, +пов'язаними з керуванням живлення. + +Мікропрограма підписана, хоча на старішому апаратному забезпеченні AMD це симетричний +ключ, що означає, що з доступом до ключа (у разі витоку) ви можете підписати +свою власну модифіковану версію та запустити її. Рудольф Марек (хакер coreboot) +дізнався, як видобути цей ключ [у цій відео +демонстрації](https://media.ccc.de/v/31c3_-_6103_-_en_-_saal_2_-_201412272145_-_amd_x86_smu_firmware_analysis_-_rudolf_marek), +і на основі цієї роботи, Демієн Замміт (інший хакер coreboot) +[частково замінив її](https://github.com/zamaudio/smutool/) вільною +прошивкою, але у відповідній системі (ASUS F2A85-M) все ще були присутні +інші блоби (Відео BIOS та інші). + +### Прошивка AMD AGESA + +ПРИМІТКА: Більше має бути написано про це, щоб відобразити сучасну реальність. +Ситуація з AMD в останні роки змінилась. Інформація на цій сторінці поширених +запитань застаріла кілька років тому. + +Це відповідає практично за всю ініціалізацію основного обладнання в +сучасних системах AMD. У 2011 році AMD почала співпрацювати з проектом coreboot, +випустивши це як джерельний код під вільною ліцензією. В 2014 році +вони припинили випускати джерельний код і замість цього почали випускати AGESA у вигляді +бінарних блобів. Це робить AGESA еквівалентом [Intel FSP](#fsp). + +### Оновлення мікрокоду ЦП AMD + +Прочитайте розділ Intel +практично так само, хоча було виявлено, що з набагато пізнішим апаратним забезпеченням +AMD можна працювати без оновлень мікрокоду. Невідомо, чи потрібні оновлення на всіх +платах AMD (залежить від ЦП). + +### AMD не співпрацює + +Здавалося, що AMD була на правильному шляху в 2011 році, коли вони почала +співпрацювати та випускати джерельний код для кількох критичних +компонентів для проекту coreboot. Цьому не було бути. З так званих +економічних причин вони вирішили, що більше не варто витрачати час на інвестування +в проект coreboot. На жаль, вони навіть не поділилися джерельним +кодом бібліотеки AGESA для архітектур сімейства 15h Steamroller/Excavator +(які, як і попередні fam15h Bulldozer/Piledriver, не +мають PSP) і випустили його для проекту coreboot лише як двійковий файл. + +Перехід компанії від такої хорошої до такої поганої лише за 3 роки +свідчить, що з AMD щось серйозно не так. Подібно Intel, вони +не заслуговують ваших грошей. + +Враховуючи поточний стан апаратного забезпечення Intel з Management Engine, ми +вважаємо, що все продуктивне апаратне забезпечення x86, новіше, ніж ЦП AMD +Family 15h (на стороні AMD) або будь-яке інше, випущене після 2009 року на стороні Intel +є дефектним за своєю конструкцією і не може бути безпечно використаним для зберігання, передачі +або обробки конфіденційних даних. Конфіденційні дані - це будь-які дані, у яких +порушення може завдати значної економічної шкоди суб'єкту, який створив +або був відповідальний за збереження цих даних, тому це включатиме банки, +компанії, що видають кредитні картки, або роздрібних продавців (записи рахунків клієнтів), в +додаток до "звичайних" інжинірингових фірм та фірм з розробки програмного забезпечення. +Це також стосується викривачів або будь-кого, кому потрібна справжня конфіденційність та +безпека. + +Привіт, у мене <вставте сюди випадкову систему>, чи підтримується вона? +-------------------------------------------------------------------------------------------------------- + +Якщо в coreboot бракує підтримки для вашого апаратного забезпечення, ви мусите додати підтримку для нього. +Будь-ласка, проконсультуйтесь з проектом coreboot для наставництва. + +Загальні питання +================= + +Як встановити libreboot? +------------------------------------------------------- + +Подивіться [посібник з встановлення](docs/install/) + +Як запрограмувати флеш-чіп SPI? +--------------------------------------------------------------------------------- + +Зверніться до:\ +[Зовнішній перезапис 25xx NOR flash через протокол SPI](docs/install/spi.md) + +Можна використовувати 16-контактний затискач SOIC на 8-контактній мікросхемі SOIC, якщо +правильно впорядкувати контакти. Як правило, з'єднання більш міцне. + +Як захистити флеш-чіп від запису? +---------------------------------------------------------------------------- + +За замовчуванням немає захисту від запису на системі libreboot. Це +з міркувань зручності використання, оскільки більшість людей не мають легкого доступу до зовнішнього +програматора для перепрошивання їх мікропрограми, або вони знаходять +незручним використання зовнішнього програматора. + +У деяких системах можна захистити мікропрограму від запису, щоб вона +була доступна лише для читання на рівні ОС (зовнішнє перепрошивання все ще +можливе за допомогою спеціального обладнання). Наприклад, на сучасних ноутбуках GM45 +(таких як, ThinkPad X200, T400) можна захистити від запису (див. +[утиліту ICH9 gen](docs/install/ich9utils.md#ich9gen)). + +Захист від запису можна встановити на всіх системах libreboot, але інструкції +потрібно написати. Документація знаходиться в основному репозиторії git, тому ви можете +надсилати виправлення, додаючи ці інструкції. + +ЗРОБИТИ: Задокументувати захист флеш-пам'яті на основі PRx на платформах Intel і дослідити інші +методи на системах AMD. + +Як змінити налаштування BIOS? +------------------------------------------------------------------------ + +Більшість налаштувань libreboot насправді використовує [корисне навантаження +GRUB](http://www.coreboot.org/GRUB2). Більше інформації про корисні навантаження +може бути знайдено на +[coreboot.org/Payloads](http://www.coreboot.org/Payloads). SeaBIOS також +доступний. Конфігурацію *CMOS* жорстко закодовано в libreboot. + +Проект libreboot успадковує модульну концепцію корисного навантаження від coreboot, що +означає, що програми *налаштування BIOS* не дуже +практичні. Coreboot (та libreboot) включає утиліту, названу +*nvramtool*, яка може бути використана для зміни деяких налаштувань. Ви можете знайти +nvramtool у *coreboot/util/nvramtool/*, в архівах джерельного коду +libreboot. + +Параметр *-a* у nvramtool покаже список доступних параметрів, і *-w* +може бути використано для їх зміни. Зверніться до документації nvramtool на +coreboot вікі для більшої інформації. + +На практиці, у більшості випадків, вам не потрібно змінювати жодні з цих +налаштувань. + +Налаштування libreboot за замовчуванням блокують таблицю CMOS, щоб забезпечити узгоджену функціональність +для всіх користувачів. Ви можете використовувати: + + nvramtool -C вашаROM.rom -w деякеналаштування=деякезначення + +Щоб отримати повний список доступних опцій, зробіть це: + + nvramtool -C вашаROM.rom -a + +Це змінить за замовчуванням всередині образа ROM, і потім ви можете +перепрошити його. + +Як заповнити ROM перед перепрошивкою? +-------------------------------------- + +Бажано просто використовувати більший образ ROM. Цей розділ був написаний здебільшого для +материнських плат ASUS KCMA-D8 та KGPE-D16, де раніше ми надавали +тільки образи ROM розміром 2 MБ у libreboot, але тепер ми надаємо образи ROM розміром 16 МБ. +Інші розміри не надаються, оскільки на практиці хтось, оновлюючи один із +цих чіпів, використовуватиме лише 16 МБ. Доступні більші розміри, але 16 МБ +це максимум, який ви можете використати на всіх підтримуваних системах libreboot, які +використовують флеш-пам'ять SPI. + +Необхідно для ROM, де образ ROM менший за флеш-чіп +(наприклад, запис 2 МБ ROM на флеш-чіп 16 МБ). + +Створіть порожній (00 байти) файл із різницею розміру між +ROM та флеш-чіпом. Випадок вище, наприклад: + + truncate -s +14MiB pad.bin + +Для бездескрипторних x86 образів потрібно додавати *з початку* ROM: + + cat pad.bin вашrom.rom > вашrom.rom.new + +Для ARM та x86 з intel flash descriptor, вам потрібно додавати після образу: + + cat вашrom.rom pad.bin > вашrom.rom.new + +Прошийте отриманий файл. Зауважте, що cbfstool не зможе працювати +з образами, доповненими таким чином, тому обов'язково внесіть усі зміни до образу, включаючи +конфігурацію середовища виконання, перед доповненням. + +Щоб видалити заповнення, наприклад, після зчитування його з флеш-чіпа, +просто скористайтеся dd(1), щоб вилучити лише незаповнену частину. Продовжуючи +наведені вище приклади, щоб видобути ROM без дескрипторів 2 МБ x86 із доповненого +образа 16 МБ, виконайте наступне: + + dd if=flashromread.rom of=вашrom.rom ibs=14MiB skip=1 + +Після видалення заповнення cbfstool зможе працювати із образом як зазвичай. + +Чи потрібно встановлювати завантажувач під час встановлення дистрибутива? +--------------------------------------------------------------------------------------------------- + +Більшість налаштувань libreboot уже інтегрують завантажувач GRUB як +*[корисне навантаження](http://www.coreboot.org/Payloads)*. Це означає, що завантажувач GRUB +фактично *прошивається* як частина завантажувальної прошивки +(libreboot). Це означає, що вам не потрібно встановлювати завантажувач на +HDD або SSD під час встановлення нового дистрибутива. Ви зможете нормально завантажитися, +використовуючи завантажувач (GRUB), який знаходиться у мікросхемі флеш-пам'яті. + +Це означає, що навіть якщо ви виймете жорсткий диск або твердотільний накопичувач, у вас всеодно +буде встановлено функціонуючий завантажувач, який можна використовувати для завантаження програми +встановлення дистрибутива з флеш-пам'яті USB. Див. +[Як інсталювати Linux у системі libreboot](../docs/linux/grub_boot_installer.md) + +В даний час також передбачені інші корисні навантаження. Якщо ви використовуєте корисне навантаження SeaBIOS, +тоді на вашому HDD або SSD використовується звичайний завантажувальний сектор MBR, як і слід було +очікувати. Отже, наведені вище параграфи стосуються лише корисного навантаження GRUB. + +Чи потрібно мені перепрошивати, коли я перевстановлю дистрибутив? +------------------------------------------------------------------------------------------- + +Більше ні. Останні версії libreboot (з використанням корисного навантаження GRUB) +автоматично переключатимуться на конфігурацію GRUB на HDD або SSD, якщо +існує. Ви також можете завантажити іншу конфігурацію GRUB з будь-якого пристрою, який підтримується +GRUB (наприклад, флеш-накопичувач USB). Для +більшої інформації див. +[Змінення конфігурації GRUB в системах libreboot](../docs/linux/grub_cbfs.md) + +Якщо ви використовуєте корисне навантаження SeaBIOS, це ще простіше. Це працює так, як ви +очікували. SeaBIOS реалізує звичайний інтерфейс x86 BIOS. + +Як виглядає флеш-чіп? +----------------------------------------------------------------- + +Ви можете знайти фотографії різних видів чипів на наступній сторінці:\ +[Керівництво зовнішньої прошивки 25xx NOR](docs/install/spi.md) + +Неможливість виконати modprobe thinkpad\_acpi на Haswell +=============================================== + +Про це повідомив користувач, який використовує Debian 11 з +ядром `5.19.0-0.deb11.2-amd64`. Модуль `thinkpad_acpi` не завантажувався +з таким повідомленням: + +``` +modprobe: ERROR: could not insert 'thinkpad_acpi': "No such device" +``` + +Інформація про батарею в `/sys` була відсутньою, по цій причині. Користувач повідомив, що +наступний обхідний шлях був ефективним (в Debian). + +Додайте цей рядок до `/etc/modprobe.d/thinkpad_acpi.conf`: + +``` +options thinkpad_acpi force_load=1 +``` + +tlp +--- + +Ви можете встановити пакет `tlp` та розпочати той сервіс. Наприклад, на +Debian: + +``` +apt-get install tlp tlp-rdw +systemctl enable tlp +systemctl start tlp +``` + +Тепер прочитайте документацію: + +``` +man tlp-stat +``` + +Від імені root, ви можете зробити: + +``` +tlp-stat -b +``` + +Це надасть інформацію про батарею. + +Яке ще мікропрограмне забезпечення існує за межами libreboot? +================================================== + +### Зовнішні графічні карти + +Відео BIOS наявний на більшості графічних карт. Для інтегрованої графіки +VBIOS (спеціальний вид OptionROM) зазвичай вбудовано +в основну завантажувальну прошивку. Для зовнішньої графічної карти VBIOS зазвичай +на самій графічній карті. Він зазвичай пропрієтарний; єдина +різниця в тому, що SeaBIOS може виконати це (як варіант, ви вбудовуєте це +в образ ROM coreboot і coreboot виконує його, якщо у вас +інше корисне навантаження, таке як GRUB). + +*Проект coreboot* надає вільний код ініціалізації, на багатьох платах, і +libreboot буде використовувати цей код, коли він наявний, в залежності від конфігурації. + +В конфігураціях, де SeaBIOS і власна ініціалізація GPU використовуються разом, +додається спеціальна прокладка VBIOS, яка використовує лінійний кадровий буфер coreboot. + +### Прошивка EC (вбудований контролер) + +Це є у більшості (всіх?) ноутбуків. EC (вбудований контролер) - це невеликий, +окремий процесор, який в основному обробляє вхідні/вихідні дані, характерні +для ноутбуків. Наприклад: + +- Коли ви натискаєте перемикач увімкнення/вимкнення радіо, EC увімкне/вимкне + бездротові пристрої (wifi, bluetooth і так далі) і ввімкне/вимкне + світлодіод, який вказує, чи це увімкнено, чи ні. +- Слухає іншу мікросхему, яка виконує вимірювання показників температури, налаштовуючи + швидкість вентилятора відповідним чином (або вмикає/вимикає вентилятор). +- Отримує певні введення з клавіатури, напр. збільшення/зменшення яскравості, + збільшення/зменшення гучності. +- Визначати, коли кришка закрита або відкрита, і надсилати сигнал, що + вказує на це. +- Тощо. + +EC присутній ледь не на всіх ноутбуках. Інші пристрої використовують, залежно від складності, +або EC, або варіант із прошивкою в Mask ROM - SuperIO. + +### Прошивка HDD/SSD + +Жорсткі диски та твердотільні накопичувачі містять вбудоване програмне забезпечення, +призначене для обробки внутрішньої роботи пристрою, водночас відкриваючи простий, стандартний інтерфейс (наприклад, +AHCI/SATA), який програмне забезпечення ОС може використовувати, як правило. Ця прошивка є невидимою +для користувача накопичувача. + +Жорсткі диски та твердотільні накопичувачі є досить складними, і сьогодні містять досить складне +обладнання, яке навіть здатне запускати цілу операційну систему (під цим ми маємо +на увазі, що сам диск здатний запускати свою власну вбудовану ОС), навіть +Linux або BusyBox/Linux. + +SSD та HDD є особливим випадком, оскільки вони є постійними пристроями зберігання, +а також комп'ютерами. + +Приклад атаки, яку може здійснити зловмисне програмне забезпечення: заміна ваших ключів SSH, +що дозволяє невідомому зловмиснику неавторизований віддалений доступ. Або, можливо, +підміна ваших ключів GPG. Диски SATA також можуть мати DMA (через +контролер), що означає, що вони можуть читать з системної пам'яті; +теоретично диск може мати власне приховане сховище, де він міг би читати ваші ключі +LUKS і зберігати їх у незашифрованому вигляді для майбутнього вилучення +загрозою. + +З належним IOMMU та використанням USB замість SATA можна було б пом'якшити +будь-які проблеми, пов'язані з DMA, які можуть виникнути. + +Було продемонстровано деякі докази концепцій. Для HDD: + Для SSD: + + +Про існування життєздатної вільної заміни прошивки наразі невідомо. Для +SSD проект +[OpenSSD](https://web.archive.org/web/20220425071606/http://www.openssd-project.org/wiki/The_OpenSSD_Project) +може бути цікавим. + +Очевидно, диски SATA самі по собі не мають DMA, але можуть використовувати його +через контролер. Це + +(сторінки 388-414, 420-421, 427, 446-465, 492-522, 631-638) і це + +(сторінки 59, 67, 94, 99). + +Наступне засновано на дискусії з Пітером Стьюджем (CareBear\\) в +каналі IRC coreboot в п'ятницу, 18 вересня 2015 року, під час +дослідження того, чи може сам диск SATA використовувати DMA. Наступне +базується на таблицях даних, посилання на які наведено вище: + +Згідно з цими приведеними документами, тип FIS 39h - це *"DMA Activate FIS +- Device to Host"*. У ньому згадується *"передача даних від хоста до +пристрою, і далі сказано: після отримання DMA Activate, +якщо контролер DMA адаптера хоста було запрограмовано та увімкнено, адаптер +хоста ініціює передачу Data FIS і передасть +в цьому FIS дані, які відповідають регіонам пам'яті хоста, вказані +контекстом контролера DMA."* FIS - це одиниця протоколу (Інформаційна +структура кадру, Frame Information Structure). Базуючись на цьому, здається, що накопичувач може повідомити +контролеру хоста, що він хоче, щоб відбувся DMA, але допоки програмне забезпечення хоста +не налаштувало або не хотітиме в майбутньому налаштувати передачу DMA, +нічого не відбудеться. **Диск також може відправити DMA Setup**. Якщо DMA +Setup FIS відправлено першим, з встановленим бітом Auto-Activate, тоді це +вже налаштовано, і диск може ініціювати DMA. Далі в документі йдеться +*"Отримавши DMA Setup, одержувач FIS повинен +перевірити отриманий запит на DMA Setup."* - іншими словами, хост +повинен перевірити; але, можливо, тут є помилка. Далі в документі +сказано *"Конкретна реалізація ідентифікатора буфера +та перевірки буфера/адреси не визначена"* - тому ніхто +насправді не буде турбуватися. *"отримувач FIS"* - у випадку, який ми +розглядаємо, це обладнання хост-контроллера в чіпсеті та/або +драйвер ядра (швидше за все, драйвер ядра). Всі пристрої SATA мають +мікропрограму, з можливістю оновлення флеш-пам'яті, +яку зазвичай можна оновити, запустивши програмне забезпечення у вашій ОС; **зловмисне ПЗ, запущене від імені root, +може оновити цю мікропрограму, або мікропрограма +вже може бути шкідливою**. Ваш жорсткий диск або SSD є ідеальним місцем для зловмисника, +щоб встановити зловмисне програмне забезпечення, оскільки це постійний пристрій зберігання даних, +а також комп'ютер. + +Виходячи з цього, можна з упевненістю сказати, що використання USB замість SATA є +доцільним, якщо питання безпеки викликає занепокоєння. USB 2.0 має достатню пропускну здатність +багатьох жорстких дисків (декілька високоякісних дисків можуть використовувати більшу пропускну здатність, ніж USB 2.0), +але для SSD це може бути проблематично (якщо ви не використовуєте +USB 3.0, який ще не можна використовувати в свободі. Подивіться + +Використання USB також не є абсолютною гарантією безпеки, тому будьте обережні. +Поверхня для атаки стає набагато меншою, але шкідливий накопичувач все одно може +спробувати здійснити "фуззингову" атаку (наприклад, надсилання некоректних USB- +дескрипторів, завдяки чому було зламано DRM тиранію Playstation 3, +щоб користувачі могли запускати власну операційну систему та запускати +непідписаний код). (Ви, мабуть, у безпеці, якщо немає недоліку безпеки +в USB-бібліотеці/драйвері, який використовує ваша ОС. USB зазвичай вважається +одним із найбезпечніших протоколів, саме тому, що USB-пристрої не мають DMA) + +Інші посилання: + +- + +Рекомендовано використовувати повне шифрування диска на жорстких дисках, +підключених через USB. У мережі є кілька адаптерів, які дозволяють підключати жорсткі диски +SATA через USB, і проект Libreboot здатний завантажуватись з них +звичайним чином. Проконсультуйтесь з документацією для вашої операційної системи Linux/BSD, +щоб знати те, як встановити їх з *повнодисковим шифруванням*: + + +Поточна теорія (недоведена) полягає в тому, що це принаймні запобіжить +зловмисним дискам неправильно маніпулювати даними, які зчитуються з диска +або записуються на диск, оскільки він не може отримати доступ до вашого ключа LUKS, +якщо він знаходиться лише в оперативній пам'яті, за умови що жорсткий диск не має DMA (USB-пристрої не +мають DMA). Найгірше, що він може зробити в цьому випадку, це знищити ваші дані. +Звичайно, ви повинні переконатися, що ніколи не розміщуєте ключові файли в заголовку LUKS. +**Сприймайте сказане в цьому абзаці з дрібкою солі. Це все ще обговорюється +і нічого з цього не доведено.** + +### NIC (контролер ethernet) + +Мережеві карти Ethernet зазвичай запускають вбудоване програмне забезпечення, яке відповідає +за внутрішню ініціалізацію пристрою. Теоретично його можна налаштувати +на відкидання пакетів або навіть їх модифікацію. + +З належним IOMMU можна було би пом'якшити проблеми, пов'язані з DMA. +Також можна використовувати мережевий адаптер USB, який не має DMA. + +### Мікрокод процесора + +Мікрокод налаштовує масиви логічних вентилів у мікропроцесорі для реалізації +архітектури набору інструкцій. Спеціальні *декодери* в мікропроцесорі налаштують +схему на основі цього мікрокоду. + +### Звукова карта + +Звукове обладнання (інтегроване чи дискретне) зазвичай має вбудоване програмне забезпечення +(DSP) для обробки введення/виведення. Знову ж таки, USB DAC є хорошим +обхідним шляхом. + +### Веб-камера + +Веб-камери мають вбудоване програмне забезпечення, яке обробляє зображення, що вводиться +в камеру; налаштування фокуса, балансу білого тощо. Можна використовувати апаратне забезпечення +веб-камери USB, щоб вирішити можливі проблеми DMA; інтегровані веб-камери +(наприклад, на ноутбуках) не рекомендовані проектом libreboot з +міркувань безпеки. + +### Хост-контролер USB + +Хост-контролери USB потребують мікропрограми. Іноді це потрібно надати +самому coreboot. + +### Прошивка WWAN + +Деякі ноутбуки можуть мати пристрій для зчитування SIM-карт із карткою для роботи з +WWAN, підключення до мережі 3g/4g (наприклад, GSM). Це та +сама технологія, яка використовується в мобільних телефонах для віддаленого доступу до мережі (наприклад, +інтернет). + +ПРИМІТКА: не плутати з wifi. Wifi - це інша технологія, яка +абсолютно не пов'язана з нею. + +Процесор базової смуги всередині мікросхеми WWAN матиме власну вбудовану +операційну систему, швидше за все, пропрієтарну. Використання цієї технології також +передбачає ті ж проблеми конфіденційності, що й у випадку з мобільними телефонами (віддалене відстеження +за допомогою мережі GSM, шляхом тріангуляції сигналу). + +На деяких ноутбуках ці карти використовують USB (внутрішньо), тому не матимуть DMA, +але це все одно є великою проблемою свободи та конфіденційності. Якщо у вас є +внутрішній чіп/карта WWAN, проект libreboot рекомендує вимкнути та +(в ідеалі, якщо можливо) фізично видалити апаратне забезпечення. Якщо вам абсолютно +необхідно використовувати цю технологію, зовнішній USB-адаптер набагато +кращий, оскільки його можна легко вийняти, коли він вам не потрібен, тим самим +вимикаючи будь-які зовнішні об'єкти від відстеження вашого місцезнаходження. + +Рекомендується використовувати ethernet або wifi, на відміну від мобільних мереж, +оскільки вони, як правило, набагато безпечніші. + +Операційні системи +================= + +Чи я можу використовувати Linux? +-------------------------------------------------- + +Абсолютно! Він добре перевірений в libreboot, та дуже рекомендований. Подивіться +[встановлення Linux](../docs/linux/grub_boot_installer.md) та +[запуск Linux](../docs/linux/grub_cbfs.md). + +Будь-який сучасний дистрибутив має працювати, допоки він використовує KMS (kernel mode +setting) для графіки. + +Fedora не завантажується? (також може бути застосовано до Redhat/CentOS) +----------------------------------------------------------- + +У Fedora типово grub.cfg намагається завантажити linux в 16-розрядному режимі. +Вам просто потрібно змінити конфігурацію GRUB Fedora. +Зверніться до [сторінки Linux](docs/linux/). + +Чи я можу використовувати BSD? +---------------------------------- + +Абсолютно! Прошивка libreboot має добру підтримку для FreeBSD, NetBSD та +OpenBSD. Інші системи не перевірені, але мають працювти нормально. + +Дивіться: +[docs/bsd/](docs/bsd/) + +Чи підтримуються інші операційні системи? +------------------------------------------------------------------- + +Невідомо. Можливо, але неможливо сказати без подальшого випробовування. + +Який рівень програмної свободи дає мені libreboot? +=================================================== + +Прошивка libreboot надає ініціалізацію апаратного забезпечення хоста всередині файлів ROM, +що може бути записано на флеш NOR, але на багатьох системах існує +набагато більше маленьких комп'ютерів на материнській платі, виконуючих двійкові прошивки. +Деякі з них неможливо замінити через те, що вони розташовані на Mask ROM. +Наприклад, більшість ноутбуків мають вбудоване програмне забезпечення EC (вбудований контролер). + +Крім самого програмного забезпечення (вбудованого в ROM чи ні), більшість апаратного забезпечення +(від мікросхем до друкованих плат) не випускається за ліцензіями з відкритим джерелом. +У нас немає жодного пристрою, який можна вважати на "100% вільним", +і таких абсолютів майже неможливо досягти. + +Відомі пропрієтарні блоби (неповний список): + +* Всі пристрої + * Прошивка жорсткого диска SATA/PATA/оптичного дисковода + ([часто має потужний, заснований на ARM комп'ютер]( + http://spritesmods.com/?art=hddhack&page=1)) + * Флеш-накопичувачі та будь-які периферійні USB-пристрої - вони містять комп'ютер + із запущеним кодом, щонайменше, для обробки протоколу USB +* ThinkPad: + * Прошивка EC (H8S до включаючи Sandy Bridge, пізніше заснований на ARC MEC16xx) + * Прошивка TrackPoint (8051) + * Пристрої Penabled містять мікроконтролер µPD78F0514 на підплаті wacom, + і Atmega (AVR) на світлодіодному індикаторі/платі кнопок + * BMS акумулятора, bq8030 (CoolRISC C816) +* Хромбуки C201PA/C100PA: + * BMS акумулятора, bq30z55 + * Тачпад Elan + * Прошивка [контролера флеш-пам'яті](https://en.wikipedia.org/wiki/Flash_memory_controller) eMMC + +Одного дня ми житимемо у світі, де будь-хто зможе виготовити власні чіпи, включаючи +процесори, а також будь-які інші типи мікросхем. Зусилля зробити домашнє виробництво чіпів реальністю +зараз знаходяться в зародковому стані, але такі зусилля +існують, наприклад, робота, виконана Семом Зелофом і проектом Libre Silicon: + +* +* +* + +(Сем буквально робить процесори в своєму гаражі) + +Де я можу вивчати більше про електроніку +========================================== + +* Основи пайки та переробки від PACE + Обидві серії відео є обов'язковими незалежно від ваших навичок паяння. + * [Базове паяння](https://yewtu.be/playlist?list=PL926EC0F1F93C1837) + * [Переробка та ремонт](https://yewtu.be/playlist?list=PL958FF32927823D12) + Наведені вище серії PACE охоплюють класичні методи, але не стосуються + *сучасної* електроніки. Для цього дивіться: + * [Уроки мікропайки iFixit із Джессою + Джонс](https://yewtu.be/playlist?list=PL4INaL5vWobD_CltiZXr7K46oJ33KvwBt) + * Також перегляньте посилання на youtube нижче, особливо відео Луї Россмана, щоб дізнатися + (набагато) більше. +* [Курс edX з основ електроніки](https://www.edx.org/course/circuits-and-electronics-1-basic-circuit-analysi-2) + У більшості країн зміст цього курсу розглядається в середній та старшій + школі. Це також добре послужить, щоб освіжити вашу пам'ять, + якщо ви з тих пір не користувались цими знаннями. +* Вступ до імпедансу + * [Подібності в поведінці хвиль](https://yewtu.be/watch?v=DovunOxlY1k) + * [Відбиття в лінії передачі](https://yewtu.be/watch?v=y8GMH7vMAsQ) + * Заглушки: + * [Стаття на Вікіпедії про заглушки](https://en.wikipedia.org/wiki/Stub_(electronics)) + * [Стаття Polar Instruments про заглушки](http://www.polarinstruments.com/support/si/AP8166.html) + З зовнішньої прошивкою SPI ми дбаємо лише про заглушки непередбачених друкованих плат +* [Як точно виміряти крок конектора](https://www.microcontrollertips.com/accurately-measure-headerconnector-pitch/) +* Інші YouTube-канали з корисним контентом про електроніку + * [EEVblog](https://yewtu.be/channel/UC2DjFE7Xf11URZqWBigcVOQ) + (загалом про електроніку, огляди обладнання і так далі, деякі + відео ремонту) + * [Луї Россман](https://yewtu.be/channel/UCl2mFZoRqjw_ELax4Yisf6w) + (пропаганда права на ремонт, багато відео про ремонт macbook) + * [mikeselectricstuff](https://yewtu.be/channel/UCcs0ZkP_as4PpHDhFcmCHyA) + * [bigclive](https://yewtu.be/channel/UCtM5z2gkrGRuWd0JQMx76qA) + * [ElectroBOOM](https://yewtu.be/channel/UCJ0-OtVpF0wOKEqT2Z1HEtA) + (він підриває речі та показує, як цього не робити) + * [Jeri Ellsworth](https://yewtu.be/user/jeriellsworth/playlists) + (має відео, що показує як виготовити *транзистор* самостійно) + * [Sam Zeloof](https://yewtu.be/channel/UC7E8-0Ou69hwScPW1_fQApA) + (Сем буквально робить процесори в своєму гаражі, натхненний роботою Джері Еллсуорт + з транзисторами) + * [iPad Rehab with Jessa Jones](https://yewtu.be/channel/UCPjp41qeXe1o_lp1US9TpWA) + (дуже точна пайка. вона займається ремонтом мобільних телефонів і подібного, про що + також йдеться в серії iFixit про ремонт компонентів) +* Файли Boardview може бути відкрито в [OpenBoardview](https://github.com/OpenBoardView/OpenBoardView), +що є вільним програмним забезпеченням під ліцензією MIT. + +Використання `yt-dlp` (покращеного відгалудження `youtube-dl`) рекомендовано для посилань +на `youtube.com`. Дивіться: + +Нарешті найважливіше повідомлення для всіх, хто починає це чудове нове хобі - [Секрет вивчення електроніки](https://yewtu.be/watch?v=xhQ7d3BK3KQ) diff --git a/site/favicon.ico b/site/favicon.ico new file mode 100644 index 0000000..212bb32 Binary files /dev/null and b/site/favicon.ico differ diff --git a/site/footer.de.include b/site/footer.de.include new file mode 100644 index 0000000..b2a1cd1 --- /dev/null +++ b/site/footer.de.include @@ -0,0 +1,12 @@ + +------------------------------------------------------------------------------- + +* [Diese Seite bearbeiten](/git.de.md) +* [Wer entwickelt Libreboot?](/who.de.md) +* [Lizenz](/license.md) +* [Vorlage](/template-license.md) +* [Logo](/logo-license.md) +* [Autoren](/contrib.md) + +------------------------------------------------------------------------------- + diff --git a/site/footer.include b/site/footer.include new file mode 100644 index 0000000..c7fa65b --- /dev/null +++ b/site/footer.include @@ -0,0 +1,12 @@ + +------------------------------------------------------------------------------- + +* [Edit this page](/git.md) +* [Who develops Libreboot?](/who.md) +* [License](/license.md) +* [Template](/template-license.md) +* [Logo](/logo-license.md) +* [Authors](/contrib.md) + +------------------------------------------------------------------------------- + diff --git a/site/footer.uk.include b/site/footer.uk.include new file mode 100644 index 0000000..e216534 --- /dev/null +++ b/site/footer.uk.include @@ -0,0 +1,12 @@ + +------------------------------------------------------------------------------- + +* [Редагувати цю сторінку](/git.md) +* [Хто розробляє Libreboot?](/who.uk.md) +* [Ліцензія](/license.md) +* [Шаблон](/template-license.uk.md) +* [Логотип](/logo-license.uk.md) +* [Автори](/contrib.uk.md) + +------------------------------------------------------------------------------- + diff --git a/site/footer.zh-cn.include b/site/footer.zh-cn.include new file mode 100644 index 0000000..3d107d5 --- /dev/null +++ b/site/footer.zh-cn.include @@ -0,0 +1,12 @@ + +------------------------------------------------------------------------------- + +* [编辑本页面](/git.md) +* [谁在开发 Libreboot?](/who.md) +* [许可证](/license.md) +* [模板](/template-license.md) +* [图标](/logo-license.md) +* [作者](/contrib.md) + +------------------------------------------------------------------------------- + diff --git a/site/git.de.md b/site/git.de.md new file mode 100644 index 0000000..eab0673 --- /dev/null +++ b/site/git.de.md @@ -0,0 +1,297 @@ +--- +title: Code review +x-toc-enable: true +... + +Libreboot Repositories +=================== + +Informationen darüber wer an Libreboot arbeitet und wer das Projekt betreibt +sind unter [who.de.md](who.de.md) zu finden. + +Das `libreboot` Projekt hat hauptsächlich 3 Git Repositories: + +* Build system: +* Webseite (+Anleitungen): +* Bilder (für die Webseite): + +Du kannst dir lbmk auch auf Libreboot's eigener cgit Instanz *ansehen*, +allerdings ist dies nicht für die Entwicklung gedacht (benutze hierfür bitte codeberg):\ + + +Weiter unten auf dieser Seite sind Mirror von `lbmk` und `lbwww` aufgelistet, +sofern die Haupt Git Repositories nicht erreichbar sein sollten. + +Zuvor hat Libreboot NotABug verwendet, aber es gab regelmässig +Probleme mit der der Zuverlässigkeit aufgrund von HTTP Error 500, +hauptsächlich in den Abendstunden, höchstwahrscheinlich weil zu viele Leute +darauf zugegriffen haben; daher wurde beschlossen, das Libreboot eine +stabilere Lösung benötigt, daher verwendet Libreboot nun codeberg. Siehe +[Ankündigung des Wechsels zu codeberg, 8. April 2023](news/codeberg.md) + +Zudem gibt es noch diese vom Libreboot Projekt gehosteten Programme, welche +von libreboot entweder empfohlen oder verwendet werden: + +Das `ich9utils` Projekt ist nun unter `util/ich9utils` in lbmk verfügbar, +und lbmk verdendet *dies*, aber das alte standalone Repository ist nach +wie vor verfügbar unter notabug (bucts is also there): + +* Bucts (Utility): +* ich9utils (Utility): + +Du kannst diese Repositories herunterladen, sie nach deinen Wünschen ändern, +und dann deine Änderungen zur Verfügung stellen mithilfe der folgenden +Anleitungen. + +Es wird empfohlen den libreboot build (alle zugehörigen Teile) in einer +Linux Umgebung herzustellen. Unter BSD Systemen ist das build system (lbmk) +beispielsweise nicht getestet. +Installiere `git` auf deinem Linux System und lade eines der Repositories +herunter. + +Die Entwicklung von Libreboot findet mithilfe der Versionskontrolle von +Git statt. Sieh in der [offiziellen Git Dokumentation](https://git-scm.com/doc) +nach, sofern Du nicht weisst wie man Git verwendet. + +Das `bucts` Repository wird auch vom Libreboot Projekt gehostet, da das +Original Repository auf `stuge.se` nicht mehr verfügbar ist, seit wie dies +zuletzt geprüft haben. Das `bucts` Programm wurde von Peter Stuge geschrieben. +Du benötigst `bucts` sofern Du ein Libreboot ROM intern auf ein Thinkpad X60 +oder T60 flashen möchtest, welches (derzeit) noch ein nicht-freies Lenovo +BIOS verwendet. Anleitungen hierfür findest Du hier:\ +[Libreboot Installations Anleitungen](docs/install/) + +Das `ich9utils` Repository wird erheblich vom `lbmk` build system verwendet. +Du kannst `ich9utils` allerdings auch separat herunterladen und verwenden. +Es erzeugt ICH9M descriptor+GbE Images für GM45 ThinkPads welche die ICH9M +Southbridge verwenden. Es könnte auch für andere Systeme funktionieren, +welche dieselbe Platform bzw. denselben Chipsatz verwenden. +Dokumentation für `ich9utils` ist hier verfügbar:\ +[ich9utils Dokumentation](docs/install/ich9utils.md) + +lbmk (libreboot-make) +--------------------- + +Dies ist das zentrale build system in Libreboot. Man könnte auch sagen `lbmk` *ist* +Libreboot! Das Git repository herunterladen: + + git clone https://codeberg.org/libreboot/lbmk + +Der oben dargestellte `git` Befehl, wird das Libreboot build system `lbmk` +herunterladen. +Du kannst dann folgendermassen in das Verzeichnis wechseln: + + cd lbmk + +Ändere dies nach deinen Vorstellungen oder erstelle einfach einen build. +Für Anleitungen bzgl. `lbmk` build, siehe [build Anleitungen](docs/build/). + +Informationen über das build system selbst und wie es funktioniert, sind +verfügbar unter dem [lbmk maintenance guide](docs/maintain/). + +lbwww and lbwww-img +------------------- + +Die *gesamte* Libreboot Website sowie Dokumentation befindet sich in einem +Git Repository. +Du kannst es folgendermassen herunterladen: + + git clone https://codeberg.org/libreboot/lbwww + +Bilder befinden sich unter und sind verfügbar +in einem separaten Git Repository: + + git clone https://codeberg.org/libreboot/lbwww-img + +Du kannst alles nach deinen Vorstellungen ändern. Beachte die nachfolgenden +Informationen wie Du deine Änderungen zur Verfügung stellen kannst. + +Die gesamte Website ist in Markdown geschrieben, insbesondere die Pandoc Version. +Die statischen HTML Seiten werden mit [Untitled](https://untitled.vimuser.org/) +generiert. Leah Rowe, die Gründerin von Libreboot, ist auch die Gründerin des Untitled static +site generator Projekts. + +Wenn Du möchtest, kannst Du einen lokalen HTTP Server einrichten und eine +lokale Version der Website herstellen. Bitte bedenke, dass alle Bilder nach +wie vor mit den Bildern auf verknüpft werden, +daher werden jegliche Bilder die Du `lbwww-img` hinzugefügt hast nicht auf +deiner lokalen `lbwww` Seite dargestellt, sofern Du die Bilder (die Du +hinzugefügt hast) mit `av.libreboot.org` verknüpfst. Es ist jedoch erforderlich, +dass sich diese Bilder auf av.libreboot.org befinden. + +Sofern Du der Webseite Bilder hinzufügen möchtest, füge diese ebenso +dem `lbwww-img` Repository hinzu, indem Du diese dann jeweils mit diesem Link verknüpfst +. +Wenn dein Patch der Libreboot Webseite hinzugefügt wird, werden erscheinen deine Bilder live. + +Zu Entwicklungszwecken, könntest Du deine Bilder auch lokal verknüpfen, und +anschliesend die URLs anpassen sobald Du deine Patches für die Dokumentation/Webseite schickst. + +Eine Anleitung wie Du eine lokale Version der Webseite herstellen kannst, +befinden sich auf der Untitled Webseite. Lade untitled +herunter, und erstelle in dem `untitled` Verzeichnis ein Verzeichnis mit +dem Namen `www/` dann wechsle in dieses Verzeichnis und klone das `lbwww` +Repository dorthin. Konfiguriere deinen lokalen HTTP Server entsprechend. + +Nochmal, Anleitungen hierfür findest Du auf der Untitled Webseite. + +Name nicht erforderlich +----------------- + +Beiträge die Du hinzufügst, werden in einem für jeden zugänglichen Git +Repository öffentlich aufgezeichnet. Dies betrifft ebenso den Namen sowie +die email Adresse des Mitwirkenden. + +Du musst bei Git keinen Autoren Namen bzw. keine email Addresse verwenden, +mithilfe derer Du identifizierbar bist. Du kannst `libreboot Contributor` +verwenden und deine email Addresse könnte als contributor@libreboot.org +spezifiert werden. Es ist Dir gestattet dies zu tun, sofern Du deine Privatsphäre +wahren möchtest. Wir glauben an Privatsphäre. Sofern Du anonym bleiben möchtest +werden wir dies respektieren. + +Natürlich kannst Du jeglichen Namen und/oder jegliche email Adresse verwenden +die Du möchtest. + +Rechtlich gesprochen, jegliches Urheberrecht fällt automatisch unter die +Berner Übereinkunft zum Schutz von Werken der Literatur und Kunst. Es spielt +keine Rolle welchen Namen, oder ob Du tatsächlich überhaupt ein Urheberrecht +deklariert hast (aber wir setzen voraus das bestimmte Lizenzen für das +Urheberrecht verwndet werden - lies mehr darüber auf dieser Seite). + +Sofern Du einen anderen Namen sowie eine andere email Adresse für deine +Commits/Patches verwendest dann solltest Du anonym sein. Verwende +[git log](https://git-scm.com/book/en/v2/Git-Basics-Viewing-the-Commit-History) +und [git show](https://git-scm.com/docs/git-show) um dies zu überprüfen +bevor Du einem öffentlichen Git Repository Änderungen hinzufügst. + +Lizenzen (für Mitwirkende) +-------- + +Stelle sicher, dass deine Beiträge mit einer libre Lizenz frei lizensiert +sind. Libreboot schreibt nicht mehr vor, welche Lizenzen akzeptiert werden, +und es existieren einige Lizenzen. Wir werden deinen Beitrag prüfen und +dir mitteilen sofern es ein Problem damit gibt (z.B. keine Lizenz). + +Gib *immer* eine Lizenz an für deine Arbeit! Keine Lizenz anzugeben bedeutet +das deine Arbeit unter die Standard Urheberrechte fällt, was deine Arbeit +proprietär macht und somit von denselben Einschränkungen betroffen ist. + +Die MIT Lizenz ist ein guter Start, und sie ist die bevorzugte Lizenz +für sämtliche Arbeit an Libreboot, aber wir sind nicht pingelig. Libreboot +hat in der Vergangenheit GNU Lizenzen so wie GPL verwendet; vieles davon +besteht nach wie vor und wird auch weiterhin bestehen. +Es ist deine Arbeit; sofern deine Arbeit auf der Arbeit eines anderen basiert, +ist es aufgrund der Lizenz-Kompatibilität ggfs. naheliegend diesselbe Lizenz zu +verwenden. + +[Hier](https://opensource.org/licenses) findest Du übliche Beispiele für Lizenzen. + +*Wenn* deine Arbeit auf bestehender Arbeit basiert, dann ist es wichtig +(für deinen Beitrag) das die Lizenz deiner Arbeit kompatibel ist mit der +Lizenz der Arbeit auf der sie beruht. Die MIT Lizenz ist hierfür gut geeignet, +weil sie mit vielen anderen Lizenen kompatibel ist, und Freiheit zulässt +(wie zum Beispiel die Freiheit einer SubLizenz) was bei vielen anderen +Lizenzen nicht der Fall ist: + + + +Patches senden +------------ + +Erstelle einen Account unter und navigiere (während +Du eingeloggt bist) zu dem Repository das Du bearbeiten möchtest. Klicke +auf *Fork* und Du wirst ein eigenes Libreboot Repository in deinem Account +erhalten. Erstelle einen Clone dieses Repository, füge alle gewünschten Änderungen hinzu +und führe anschliessend einen Push in dein Repository in deinem Account +auf Codeberg durch. Du kannst dies auch in einem neuen Branch erledigen, +sofern Du magst. + +In deinem Codeberg Account kannst Du nun zum offiziellen Libreboot +Repository navigieren und dort einen Pull Request erstellen. Die Art und +Weise wie dies funktioniert ist vergleichbar mit anderen populären Web basierten +Git Plattformen die heutzutage verwendet werden. + +Du kannst dort deine Patches bereitstellen. Alternativ kannst Du dich in +den Libreboot IRC Kanal einloggen und dort bekannt geben welche deiner Patches +geprüft werden sollen, sofern Du ein eigenes Git repository mit den Patches +hast. + +Sobald Du einen Pull Request erstellt hast, werden die Libreboot Maintainer +per email informiert. Sofern Du nicht schnell genug eine Antwort erhälst, +kannst Du das Projekt ebenso mithilfe des `#libreboot` Kanals auf Libera +Chat kontaktieren. + +Ein weiterer Weg Patches zu senden ist Leah Rowe direkt eine email zu senden: +[info@minifree.org](mailto:info@minifree.org) ist Leah's Projekt email Addresse. + +Um den Prozess der Quelltext Überprüfung transparent zu gestalten, +wird jedoch empfohlen künftig Codeberg zu verwenden. + +Mirrors für lbmk.git +=================== + +Das `lbmk` Repository enthält Libreboot's automatischess build system, welches +Libreboot Veröffentlichungen herstellt (inklusive kompilierter ROM Images). + +Du kannst `git clone` für alle diese Links ausführen (die Links können auch +angeklickt werden, um Änderungen in deinem Web Browser anzusehen): + +* +* +* +* +* +* +* +* + +lbwww.git Mirror +---------------- + +Das `lbwww` Repository enthält Markdown Dateien (Pandoc Variant), für die +Verwendung mit dem [Untitled Static Site Generator](https://untitled.vimuser.org/); +dies wird von Libreboot verwendet um HTML Web Seiten bereitzustellen, *inklusive* +der Seite die Du gerade liest! + +Du kannst `git clone` für diese Links ausführen und/oder die Links +anklicken um Änderungen in deinem Web Browser anzusehen). Siehe: + +* +* +* +* +* +* +* + +HINWEIS: Das `lbwww-img` Repository wird generell nicht auf einem Mirror +zur Verfügung gestellt, weil dies lediglich Bilder sind die Du unter + finden kannst und es ist nicht die Intention +des Libreboot Projektes *Mirror* mit zusätzlichen Datenverkehr durch +Bilder zu belasten. + +Notabug Repositories +==================== + +Commits die zu codeberg gepusht werden, werden ebenso zu notabug gepusht, +zusätzlich zu den anderen Mirrors. +Notabug wird seit dem 8. April 2023 als *Mirror* betrachtet, seitdem +Libreboot's Haupt Entwicklung zu *Codeberg* gewechselt hat. + +In die ALTEN notabug Repositories wird zu Backup Zwecken nach wie vor gepusht, +aber der codeberg mirror wird nun als der hauptsächliche/offizielle betrachtet, +wie in dieser [Ankündigung vom 8. April 2023](news/codeberg.md). Siehe: + +* Build system: +* Webseite (+Dokumentation): +* Bilder (für die Webseite): + +Um Patches zu senden, wird nun bevorzugt wenn Du *codeberg* verwendest. +Technisch gesehen sind pull requests via Notabug nach wie vor möglich. +Während Notabug nach wie vor existiert, werden Libreboot Patches nach wie +vor dorthin gepushed, als Mirror für Änderungen die auf Notabug gepushed werden. + +Weil pull requests und issues in der Vergangenheit auf notabug verfügbar waren, +macht es Sinn diese offen zu lassen, dennoch würden wir dich bitten an codeberg +zu schicken. Sofern diese auf notabug geschlossen werden, dann werden diese PRs +und issues ohnehin nicht mehr sichtbar, daher sollten diese offen bleiben. diff --git a/site/git.md b/site/git.md new file mode 100644 index 0000000..7a1477c --- /dev/null +++ b/site/git.md @@ -0,0 +1,275 @@ +--- +title: Code review +x-toc-enable: true +... + +libreboot repositories +=================== + +Information about who works on libreboot and who runs the project can be +found on [who.md](who.md) + +The `libreboot` project has 3 main Git repositories: + +* Build system: +* Website (+docs): +* Images (for website): + +You can also *browse* lbmk on Libreboot's own cgit instance, though it is not +intended for development (use codeberg for that):\ + + +If the main Git repositories are down, mirrors of `lbmk` and `lbwww` are listed +further down in this page + +Libreboot was previously using NotABug, but it had continued reliability +issues due to HTTP 500 errors being returned, largely in the evenings, most +likely because too many people were on it; it was decided that Libreboot +needed something more stable, so now Libreboot is hosted on codeberg. See: +[announcement of move to codeberg, 8 April 2023](news/codeberg.md) + +There are also these programs, hosted by the Libreboot project, and libreboot +either recommends them or makes use of them: + +The `ich9utils` project is now available under `util/ich9utils` in lbmk, and +lbmk uses *that*, but the old standalone repository is still available on +notabug (bucts is also there): + +* Bucts (utility): +* ich9utils (utility): + +You can download any of these repositories, make whatever changes you like, and +then submit your changes using the instructions below. + +It is recommended that you build libreboot (all parts of it) in a Linux +distribution. For example, the build system (lbmk) is untested on BSD systems. +Install `git` in your Linux system, and download one of the repositories. + +Development of libreboot is done using the Git version control system. +Refer to the [official Git documentation](https://git-scm.com/doc) if you don't +know how to use Git. + +The `bucts` repository is hosted by the libreboot project, because the original +repository on `stuge.se` is no longer available, last time we checked. The +`bucts` program was written by Peter Stuge. You need `bucts` if you're flashing +internally an libreboot ROM onto a ThinkPad X60 or T60 that is currently running +the non-free Lenovo BIOS. Instructions for that are available here:\ +[libreboot installation guides](docs/install/) + +The `ich9utils` repository is used heavily, by the `lbmk` build system. However, +you can also download `ich9utils` on its own and use it. It generates ICH9M +descriptor+GbE images for GM45 ThinkPads that use the ICH9M southbridge. It may +also work for other systems using the same platform/chipset. +Documentation for `ich9utils` is available here:\ +[ich9utils documentation](docs/install/ich9utils.md) + +lbmk (libreboot-make) +--------------------- + +This is the core build system in libreboot. You could say that `lbmk` *is* +libreboot! Download the Git repository: + + git clone https://codeberg.org/libreboot/lbmk + +The `git` command, seen above, will download the libreboot build system `lbmk`. +You can then go into it like so: + + cd lbmk + +Make whatever changes you like, or simply build it. For instructions on how to +build `lbmk`, refer to the [build instructions](docs/build/). + +Information about the build system itself, and how it works, is available in +the [lbmk maintenance guide](docs/maintain/). + +lbwww and lbwww-img +------------------- + +The *entire* libreboot website and documentation is hosted in a Git repository. +Download it like so: + + git clone https://codeberg.org/libreboot/lbwww + +Images are hosted on and available in a separate +repository: + + git clone https://codeberg.org/libreboot/lbwww-img + +Make whatever changes you like. See notes below about how to send patches. + +The entire website is written in Markdown, specifically the Pandoc version of +it. The static HTML pages are generated with [Untitled](https://untitled.vimuser.org/). +Leah Rowe, the founder of libreboot, is also the founder of the Untitled static +site generator project. + +If you like, you can set up a local HTTP server and build your own local +version of the website. Please note that images will still link to the ones +hosted on , so any images that you add to `lbwww-img` +will not show up on your local `lbwww` site if you make the image links (for +images that you add) link to `av.libreboot.org`. However, it is required that such +images be hosted on av.libreboot.org. + +Therefore, if you wish to add images to the website, please also submit to the +`lbwww-img` repository, with the links to them being + for each one. +When it is merged on the libreboot website, your images will appear live. + +For development purposes, you might make your images local links first, and +then adjust the URLs when you submit your documentation/website patches. + +Instructions are on the Untitled website, for how to set up your local version +of the website. Download untitled, and inside your `untitled` directory, create +a directory named `www/` then go inside the www directory, and clone the `lbwww` +repository there. Configure your local HTTP server accordingly. + +Again, instructions are available on the Untitled website for this purpose. + +Name not required +----------------- + +Contributions that you make are publicly recorded, in a Git repository which +everyone can access. This includes the name and email address of the +contributor. + +In Git, for author name and email address, you do not have to use identifying +data. You can use `libreboot Contributor` and your email address could be +specified as contributor@libreboot.org. You are permitted to do this, if +you wish to maintain privacy. We believe in privacy. If you choose to remain +anonymous, we will honour this. + +Of course, you can use whichever name and/or email address you like. + +Legally speaking, all copyright is automatic under the Berne Convention of +international copyright law. It does not matter which name, or indeed whether +you even declare a copyright (but we do require that certain copyright +licenses are used - read more about that on this same page). + +If you use a different name and email address on your commits/patches, then you +should be fairly anonymous. Use +[git log](https://git-scm.com/book/en/v2/Git-Basics-Viewing-the-Commit-History) +and [git show](https://git-scm.com/docs/git-show) to confirm that before you +push changes to a public Git repository. + +Licenses (for contributors) +-------- + +Make sure to freely license your work, under a libre license. Libreboot no +longer sets arbitrary restrictions on what licenses are accepted, and many +licenses out there already exist. We will audit your contribution and tell +you if there are problems with it (e.g. no license). + +*Always* declare a license on your work! Not declaring a license means that +the default, restrictive copyright laws apply, which would make your work +proprietary, subject to all of the same restrictions. + +The MIT license is a good one to start with, and it is the preferred license +for all new works in Libreboot, but we're not picky. Libreboot has historically +used GNU licensing such as GPL; much of that remains, and is likely to remain. +It's your work; obviously, if you're deriving from an existing work, +it may make sense to use the same license on your contribution, for license +compatibility. + +You can find common examples of licenses +[here](https://opensource.org/licenses). + +If you *are* deriving from an existing work, it's important that your license +(for your contribution) be compatible with the licensing of the work from which +yours was derived. The MIT license is good because it's widely compatible +with many other licenses, and permits many freedoms (such as the freedom to +sublicense) that other licenses do not: + + + +Send patches +------------ + +Make an account on and navigate (while logged in) to the +repository that you wish to work on. Click *Fork* and in your account, +you will have your own repository of libreboot. Clone your repository, make +whatever changes you like to it and then push to your repository, in your +account on Codeberg. You can also do this on a new branch, if you wish. + +In your Codeberg account, you can then navigate to the official libreboot +repository and submit a Pull Request. The way it works is similar to other +popular web-based Git platforms that people use these days. + +You can submit your patches there. Alternative, you can log onto the libreboot +IRC channel and notify the channel of which patches you want reviewed, if you +have your own Git repository with the patches. + +Once you have issued a Pull Request, the libreboot maintainers will be notified +via email. If you do not receive a fast enough response from the project, then +you could also notify the project via the `#libreboot` channel on Libera Chat. + +Another way to submit patches is to email Leah Rowe directly: +[info@minifree.org](mailto:info@minifree.org) is Leah's project email address. + +However, for transparency of the code review process, it's recommended that you +use Codeberg, for the time being. + +Mirrors of lbmk.git +=================== + +The `lbmk` repository contains Libreboot's automated build system, which +produces Libreboot releases (including compiled ROM images). + +You can run `git clone` on any of these links (the links are also clickable, +to view changes in your Web browser): + +* +* +* +* +* +* +* +* + +lbwww.git mirror +---------------- + +The `lbwww` repository contains Markdown files (pandoc variant), for use +with the [Untitled Static Site Generator](https://untitled.vimuser.org/); this +is what Libreboot uses to provide HTML web pages, *including* the page that +you are reading right now! + +You can run `git clone` on these links, and/or click to view changes in your +Web browser. See: + +* +* +* +* +* +* +* + +NOTE: The `lbwww-img` repository is not generally provided, on mirrors, as +those are just image files which you can find on +and it is not the intention of the Libreboot project to bog down *mirrors* +with additional traffic by hosting images. + +Notabug repositories +==================== + +Commits that go to codeberg are also still pushed to notabug, in addition to +the other mirrors. Notabug is considered a *mirror* since 8 April 2023, when +Libreboot's main development site moved to *Codeberg*. + +OLD notabug repos are still pushed to as backup, but the codeberg mirror is +considered to be main/official now, as of the [announcement on 8 +April 2023](news/codeberg.md). See: + +* Build system: +* Website (+docs): +* Images (for website): + +For sending patches, it is now preferred that you use *codeberg*. Technically, +pull requests are still possible via Notabug. While Notabug still exists, +Libreboot patches will continue be pushed there, mirroring what gets pushed +on Notabug. + +Because pull requests and issues were available on notabug in the past, it +makes sense to keep them open, though we ask that you send to codeberg. If +they were to be closed on notabug, existing PRs and issues won't be visible +anymore either, so they have to stay open. diff --git a/site/git.uk.md b/site/git.uk.md new file mode 100644 index 0000000..ca03667 --- /dev/null +++ b/site/git.uk.md @@ -0,0 +1,275 @@ +--- +title: Огляд коду +x-toc-enable: true +... + +репозиторії libreboot +=================== + +Інформацію про те, хто працює над libreboot і хто керує проектом, можна +знайти на [who.uk.md](who.uk.md) + +Проект `libreboot` має 3 основні сховища Git: + +* Система побудови: +* Веб-сайт (+документація): +* Зображення (для веб-сайта): + +You can also *browse* lbmk on Libreboot's own cgit instance, though it is not +intended for development (use codeberg for that):\ + + +If the main Git repositories are down, mirrors of `lbmk` and `lbwww` are listed +further down in this page + +Libreboot was previously using NotABug, but it had continued reliability +issues due to HTTP 500 errors being returned, largely in the evenings, most +likely because too many people were on it; it was decided that Libreboot +needed something more stable, so now Libreboot is hosted on codeberg. See: +[announcement of move to codeberg, 8 April 2023](news/codeberg.md) + +Є також ці програми, розміщені в проекті Libreboot, і libreboot +або рекомендує їх, або використовує їх: + +The `ich9utils` project is now available under `util/ich9utils` in lbmk, and +lbmk uses *that*, but the old standalone repository is still available on +notabug (bucts is also there): + +* Bucts (утиліта): +* ich9utils (утиліта): + +Ви можете завантажити будь-яке з цих сховищ, внести будь-які зміни, і +потім надіслати свої зміни, дотримуючись інструкцій нижче. + +Рекомендовано створювати libreboot (усі його частини) у дистрибутиві +Linux. Наприклад, система збірки (lbmk) не перевірена на системах BSD. +Встановіть `git` у вашій системі Linux, і завантажте одне із сховищ. + +Розробка libreboot виконується за допомогою системи контролю версій Git. +Зверніться до [офіційної документації Git](https://git-scm.com/doc), якщо ви не +знаєте, як користуватися Git. + +Репозиторій `bucts` розміщено в проекті libreboot, оскільки оригінальний +репозиторій на `stuge.se` більше не доступний, коли ми перевіряли останній раз. +Програма `bucts` була написана Пітером Стьюджем. Вам знадобляться `bucts`, якщо ви прошиваєте +внутрішньо libreboot ROM на ThinkPad X60 або T60, на якому зараз працює +невільний Lenovo BIOS. Інструкції щодо цього доступні тут:\ +[посібники зі встановлення libreboot](docs/install/) + +Репозиторій `ich9utils` активно використовується системою збирання `lbmk`. Однак +ви також можете завантажити `ich9utils` самостійно та використовувати його. Він генерує ICH9M +дескриптор+GbE образи для GM45 ThinkPad, які використовують південний міст ICH9M. Він +також може працювати з іншими системами, що використовують ту саму платформу/чіпсет. +Документація для `ich9utils` доступна тут:\ +[документація ich9utils](docs/install/ich9utils.md) + +lbmk (libreboot-make) +--------------------- + +Це основна система збирання в libreboot. Можна сказати, що `lbmk` *це* +libreboot! Завантажте репозиторій Git: + + git clone https://codeberg.org/libreboot/lbmk + +Команда `git`, показана вище, завантажить систему збірки libreboot `lbmk`. +Потім ви можете перейти до цього так: + + cd lbmk + +Внесіть будь-які зміни, які забажаєте, або просто побудуйте. Щоб отримати вказівки щодо +збирання `lbmk`, зверніться до [інструкцій зі збирання](docs/build/). + +Інформація про саму систему збірки та про те, як вона працює, доступна в +[посібнику обслуговування lbmk](docs/maintain/). + +lbwww та lbwww-img +------------------- + +*Весь* веб-сайт і документація libreboot розміщені в репозиторії Git. +Завантажте так: + + git clone https://codeberg.org/libreboot/lbwww + +Зображення розміщені на і доступні в окремому +сховищі: + + git clone https://codeberg.org/libreboot/lbwww-img + +Вносьте будь-які зміни, які забажаєте. Дивіться нотатки нижче про те, як надсилати виправлення. + +Весь веб-сайт написаний у Markdown, зокрема його версія Pandoc. +Статичні сторінки HTML створюються за допомогою [Untitled](https://untitled.vimuser.org/). +Лія Роу, засновниця libreboot, також є засновницею проекту генератор статичних сайтів +Untitled. + +Якщо хочете, ви можете налаштувати локальний HTTP-сервер і створити власну локальну +версію веб-сайту. Зауважте, що зображення все одно будуть посилатися на ті, що +розміщені на , тому будь-які зображення, які ви додаєте до `lbwww-img` +не відображатимуться на вашому локальному сайті `lbwww`, якщо ви зробите, щоб посилання на зображення (для +зображень, які ви додаєте) посилались на `av.libreboot.org`. Однак необхідно, щоб такі +зображення розміщувалися на av.libreboot.org. + +Тому, якщо ви бажаєте додати зображення на веб-сайт, надішліть їх також до +репозиторія `lbwww-img`, із посиланням на них + для кожного з них. +Коли його буде поєднано на веб-сайті libreboot, ваші зображення з'являться в реальному часі. + +Для цілей розробки ви можете спочатку створити локальні посилання на зображення, а +потім налаштувати URL-адреси, коли надсилатимете документацію/патчі веб-сайту. + +На веб-сайті Untitled є інструкції щодо налаштування локальної версії +веб-сайту. Завантажте untitled, і в своєму каталозі `untitled` створіть каталог +під назвою `www/`, потім увійдіть у каталог www і клонуйте сховище `lbwww` +там. Налаштуйте локальний HTTP-сервер відповідним чином. + +Знову ж таки, інструкції для цього доступні на веб-сайті Untitled. + +Ім'я не вимагається +----------------- + +Внески, які ви робите, реєструються публічно в репозиторії Git, доступ +до якого мають всі. Це включає ім'я та електронну адресу +учасника. + +У Git для імені автора та електронної адреси вам не потрібно використовувати +ідентифікаційні дані. Ви можете використовувати `libreboot Contributor`, а свою електронну адресу можна +вказати як contributor@libreboot.org. Вам дозволено це робити, якщо +ви бажаєте зберегти конфіденційність. Ми віримо в конфіденційність. Якщо ви вирішите залишитися +анонімними, ми врахуємо це. + +Звичайно, ви можете використовувати будь-яке ім'я та/або адресу електронної пошти. + +З юридичної точки зору всі авторські права є автоматичними відповідно до Бернської конвенції +міжнародного авторського права. Немає значення, яке ім'я, чи дійсно ви навіть +заявляєте про авторське право (але ми вимагаємо наявності певного +ліцензування авторського права - докладніше про це на цій же сторінці). + +Якщо ви використовуєте інше ім'я та адресу електронної пошти у своїх комітах/патчах, то +маєте бути досить анонімним. використовуйте +[git log](https://git-scm.com/book/en/v2/Git-Basics-Viewing-the-Commit-History) +та [git show](https://git-scm.com/docs/git-show), щоб підтвердити це перед тим, як ви +надсилаєте зміни до загальнодоступного сховища Git. + +Ліцензії (для учасників) +-------- + +Обов'язково вільно ліцензуйте свою роботу, за вільною ліцензією. Libreboot більше не +встановлює довільні обмеження на те, які ліцензії приймаються, і багато +інших ліцензій вже існує. Ми перевіримо ваш внесок і розкажемо вам, якщо з ним +виникли проблеми (наприклад, немає ліцензії). + +*Завжди* декларуйте ліцензію на свою роботу! Недекларування ліцензії означає, що +за замовчуванням застосовуються обмежувальні закони про авторське право, які зроблять вашу роботу +захищеною власністю, підпадаючи під усі ті самі обмеження. + +Ліцензія MIT є хорошою для початку, і вона є бажаною ліцензією +для всіх нових робіт у Libreboot, але ми не вибагливі. Libreboot історично +використовував ліцензування GNU, таке як GPL; багато з цього залишилося, і, ймовірно, залишиться. +Це ваша робота; очевидно, якщо ви використовуєте існуючу роботу, +може мати сенс використовувати ту саму ліцензію для вашого внеску, для сумісності +ліцензії. + +Ви можете знайти типові приклади ліцензій +[тут](https://opensource.org/licenses). + +Якщо ви *виходите* на основі існуючого твору, важливо, щоб ваша ліцензія (на ваш внесок) +була сумісна з ліцензуванням твору, з якого +ваш був отриманий. Ліцензія MIT хороша, оскільки вона широко сумісна +з багатьма іншими ліцензіями та надає багато свобод (наприклад, свободу +субліцензування), яких немає в інших ліцензіях: + + + +Надсилайте виправлення +------------ + +Створіть обліковий запис на і перейдіть (увійшовши в систему) до +репозиторію, над яким ви хочете працювати. Натисніть *Fork*, і у вашому обліковому записі, +ви матимете власне сховище libreboot. Клонуйте свій репозиторій, внесіть у нього +будь-які зміни, а потім надішліть їх у свій репозиторій у своєму обліковому +записі на NotABug. Ви також можете зробити це на новій гілці, якщо хочете. + +У своєму обліковому записі Codeberg, ви можете перейти до офіційного репозиторія libreboot +і надіслати запит на отримання. Принцип роботи подібний до інших популярних веб-платформ +Git, якими люди користуються сьогодні. + +Ви можете відправити свої патчі туди. Крім того, ви можете увійти на +IRC-канал libreboot і повідомити канал, які виправлення ви хочете бути переглянутими, якщо у вас +є власне сховище Git з виправленнями. + +Після того, як ви подасте Pull Request, розробники libreboot отримають сповіщення +електронною поштою. Якщо ви не отримаєте достатньо швидкої відповіді від проекту, ви +також можете повідомити проект через канал `#libreboot` на Libera Chat. + +Інший спосіб подати виправлення - це напряму надіслати Лії Роу електронною поштою: +[leah@libreboot.org](mailto:leah@libreboot.org) - це адреса електронної пошти проекту Лії. + +Однак, для прозорості процесу перевірки коду, ми рекомендуємо на даний момент +використовувати Codeberg. + +Mirrors of lbmk.git +=================== + +The `lbmk` repository contains Libreboot's automated build system, which +produces Libreboot releases (including compiled ROM images). + +You can run `git clone` on any of these links (the links are also clickable, +to view changes in your Web browser): + +* +* +* +* +* +* +* +* + +lbwww.git mirror +---------------- + +The `lbwww` repository contains Markdown files (pandoc variant), for use +with the [Untitled Static Site Generator](https://untitled.vimuser.org/); this +is what Libreboot uses to provide HTML web pages, *including* the page that +you are reading right now! + +You can run `git clone` on these links, and/or click to view changes in your +Web browser. See: + +* +* +* +* +* +* +* + +NOTE: The `lbwww-img` repository is not generally provided, on mirrors, as +those are just image files which you can find on +and it is not the intention of the Libreboot project to bog down *mirrors* +with additional traffic by hosting images. + +Notabug repositories +==================== + +Commits that go to codeberg are also still pushed to notabug, in addition to +the other mirrors. Notabug is considered a *mirror* since 8 April 2023, when +Libreboot's main development site moved to *Codeberg*. + +OLD notabug repos are still pushed to as backup, but the codeberg mirror is +considered to be main/official now, as of the [announcement on 8 +April 2023](news/codeberg.md). See: + +* Build system: +* Website (+docs): +* Images (for website): + +For sending patches, it is now preferred that you use *codeberg*. Technically, +pull requests are still possible via Notabug. While Notabug still exists, +Libreboot patches will continue be pushed there, mirroring what gets pushed +on Notabug. + +Because pull requests and issues were available on notabug in the past, it +makes sense to keep them open, though we ask that you send to codeberg. If +they were to be closed on notabug, existing PRs and issues won't be visible +anymore either, so they have to stay open. diff --git a/site/global.css b/site/global.css new file mode 100644 index 0000000..dbabe1b --- /dev/null +++ b/site/global.css @@ -0,0 +1,144 @@ +/* + * This CSS is released under Creative Commons Zero 1.0 Universal license: + * https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt + */ +.specs +{ + float: right; +} + +:not(p) +{ + max-width: 85em; + margin: 0 auto; +} + + +@media (max-width:89em) +{ + html + { + font-size: 0.95em; + } +} +@media (min-width:90em) +{ + html + { + font-size: 1.05em; + } +} + +html +{ + background: #280b22; + color: #eee; + font-family: sans-serif; + line-height: 1.4; + text-shadow: 1px 1px #000; +} + +code,pre, #TOC, a:hover +{ + background: #4e324e; +} + +a +{ + color: #fcc; +} + +img,video,iframe,pre +{ + max-width: 100%; + overflow: auto; +} + +.title>*, header ul>li, .nav ul>li, +#footer ul>li, .h:hover>* +{ + display: inline; + margin: 0.7%; + text-align :center; +} + +.title>*, span.date +{ + display: block; +} + +html, ul, #TOC +{ + padding: 1em; +} + +.date, .author, .h a +{ + display: none; +} + +@media (min-width:60em) +{ + .title-logo{display:none} + div.title,h1.title { + background:url("/favicon.ico") no-repeat; + background-size:auto 99%; + min-height:2em + } + div.title {background-position:right} + h1.title {padding:0 4em} + #TOC + { + float: left; + margin: 1em; + min-width: 25%; + } +} + +.f, .f * +{ + position: fixed; + max-width: 100%; + max-height: 100%; + top: 50%; + left: 50%; +} + +.f * +{ + transform: translate(-50%, -50%); +} + +.f +{ + display: none; + top: 0; + left: 0; + width: 100%; + height: 100%; + background: rgba(0, 0, 0, 0.8); +} + +*:focus + .f +{ + display: block; +} + +img +{ + cursor: pointer; +} + +.l,.r { + max-width:40%; + margin:1em; +} +.r { + float: right; +} +.l { + float: left; +} +.p { + max-width: 13em; +} diff --git a/site/index.de.md b/site/index.de.md new file mode 100644 index 0000000..f2202af --- /dev/null +++ b/site/index.de.md @@ -0,0 +1,80 @@ +--- +title: Libreboot projekt +x-toc-enable: true +... + +Das *Libreboot* Projekt bietet +eine [freie](https://writefreesoftware.org/) *Boot +Firmware* welche auf [bestimmten Intel/AMD x86 und ARM Geräten](docs/hardware/) +die Hardware initialisiert (z.b. Speicher-Controller, CPU, Peripherie), +und dann einen Bootloader für dein Betriebssystem startet. [Linux](docs/linux/) +sowie [BSD](docs/bsd/) werden gut unterstützt. Es ersetzt proprietäre BIOS/UEFI +Firmware. Hilfe ist verfügbar +via [\#libreboot](https://web.libera.chat/#libreboot) +und [Libera](https://libera.chat/) IRC. + + + +**NEUESTE VERSION: Die neueste Version von Censored Libreboot ist c20230710, veröffentlicht am +10. July 2023. +Siehe auch: [Censored Libreboot c20230710 release announcement](news/censored-libreboot20230710.md).** + +Warum solltest Du *Libreboot* verwenden? +---------------------------- + +Libreboot gibt dir [Freiheit](https://writefreesoftware.org/) welche +Du mit den meisten Boot Firmwares nicht hast, und zusätzlich schnellere Boot +Geschwindigkeiten sowie [höhere Sicherheit](docs/linux/grub_hardening.md). +Es ist extrem leistungsfähig und für viele Einsatzzwecke [konfigurierbar](docs/maintain/). + +Du hast Rechte. Das Recht auf Privatsphäre, Gedankenfreiheit, Meinungsäußerungsfreiheit, +und Informationsfreiheit. In diesem Zusammenhang, Libreboot gibt dir diese Rechte. +Deine Freiheit ist wichtig. +[Das Recht auf Reparatur](https://yewtu.be/watch?v=Npd_xDuNi9k) ist wichtig. +Viele Menschen verwenden proprietäre (non-libre) +Boot Firmware, sogar wenn Sie ein [Libre OS](https://www.openbsd.org/) verwenden. +Proprietäre Firmware [enthält](faq.html#intel) häufig [Hintertüren](faq.html#amd), +und kann fehlerhaft sein. Das Libreboot Projekt wurde im Dezember 2013 gegründet, +mit dem Ziel, Coreboot Firmware auch für technisch unerfahrene Nutzer verfügbar +zu machen. + +Das Libreboot Projekt verwendet [Coreboot](https://www.coreboot.org/) für +[die Initialiserung der Hardware](https://doc.coreboot.org/getting_started/architecture.html). +Die Coreboot Installation ist für unerfahrene Benutzer überaus schwierig; sie +übernimmt lediglich die Basis Initialisierung und springt dann zu einem separaten +[payload](https://doc.coreboot.org/payloads.html) Programm (z.B. +[GRUB](https://www.gnu.org/software/grub/), +[Tianocore](https://www.tianocore.org/)), welche zusätzlich konfiguriert werden muss. +*Libreboot löst dieses Problem*; es ist eine *Coreboot Distribution* mit +einem [automatisierten Build System](docs/build/) welches vollständige *ROM images* +für eine robustere Installation erstellt. +Dokumentation ist verfügbar. + +Libreboot ist kein Coreboot Fork +----------------------------------- + + + +Tatsächlich versucht Libreboot so nah am regulären Coreboot zu bleiben wie möglich, +für jedes Board, aber mit vielen automatisch durch das Libreboot Build System zur +Verfügung gestellten verschiedenen Konfigurationstypen. + +Ebenso wie *Alpine Linux* eine *Linux Distribution* ist, ist Libreboot eine +*Coreboot Distribution*. Sofern Du ein ROM Image von Grund auf herstellen möchtest, +musst Du zunächst Konfigurationen auf Experten Level durchführen, +und zwar für Coreboot, GRUB sowie sämtliche Software die Du sonst noch verwenden +möchtest um das ROM Image vorzubereiten. Mithilfe von *Libreboot* kannst Du +sprichwörtlich von Git oder einem anderen Quell-Archiv herunterladen, anschliessend +`make` ausführen, und es wird komplette ROM Images herstellen, ohne das Benutzer +Eingaben oder Eingreifen von Nöten sind. Die Konfiguration wurde bereits im +Vorfeld erledigt. + +Sofern Du das reguläre Coreboot herstellen wollen würdest, ohne hierfür das automatisierte +Libreboot Build System zu verwenden, würde dies deutlich mehr Eingreifen und ein +sehr tiefgreifendes technisches Verständnis voraussetzen um eine funktionsfähige +Konfiguration herzustellen. + +Reguläre Binär Veröffentlichungen bieten diese ROM Images vor-kompiliert, +und Du kannst dies einfach installieren ohne spezielle technische +Kenntnisse oder Fertigkeiten abgesehen von der Fähigkeit einer +[vereinfachten Anleitung, geschrieben für technisch unerfahrene Benutzer](docs/install/) zu folgen. diff --git a/site/index.fr.md b/site/index.fr.md new file mode 100644 index 0000000..dc7a405 --- /dev/null +++ b/site/index.fr.md @@ -0,0 +1,76 @@ +--- +title: Projet Libreboot +x-toc-enable: true +... + +Libreboot est un micrologiciel de démarrage [libéré](https://writefreesoftware.org/) +qui initialise le matériel (càd le contrôleur mémoire, CPU, +périphériques) sur [des ordinateurs x86/ARM spécifiques](docs/hardware/) +et lance un chargeur d'amorçage pour votre système d'exploitation. [Linux](docs/linux/) et [BSD](docs/bsd/) sont bien supportés. C'est un +remplacement pour le micrologiciel UEFI/BIOS propriétaire. +Des canaux d'aide sont disponibles +dans le canal [\#libreboot](https://web.libera.chat/#libreboot) sur le serveur IRC [Libera](https://libera.chat/). + + + +**NOUVELLE VERSION: La dernière version est [Censored Libreboot c20230710](news/censored-libreboot20230710.md), sortie +le 10 Juillet 2023.** + +Pourquoi devriez-vous utiliser *Libreboot*? +----------------------------------- + +Libreboot vous donne des [libertés](https://writefreesoftware.org/) +que nous n'auriez pas autrement avec d'autre micrologiciel de démarrage. Il est +extremement [puissant](docs/linux/grub_hardening.md) +et [configurable](docs/maintain) pour plein de cas d'utilisations. + +Vous avez des droits. Un droit à la vie privée, liberté de pensée, liberté d'espression et le droit de lire. Dans ce contexte là, Libreboot vous permet d'avoir ces droits. +Votre liberté compte. +Le [Droit à la réparation](https://yewtu.be/watch?v=Npd_xDuNi9k) est important. +Beaucoup de personnes utilisent un micrologiciel de +démarrage propriétare (non libre), même +si ils utilisent [un système d'exploitation libre](https://www.openbsd.org/). +Les micrologiciels propriétaires [contiennent](faq.html#intel) souvent +des [portes dérobées](faq.html#amd) et peuvent être instable. Libreboot +a été fondé en Décembre 2013 avec le but de rendre le libre +au niveau du micrologiciel accessible pour les utilisateurs non-techniques. + +Libreboot utilise [coreboot](https://www.coreboot.org) pour +[l'initialisation matérielle](https://doc.coreboot.org/getting_started/architecture.html) +Coreboot est renommé comme être difficilement installable par des utilisateurs +non technique; il se charge seulement de l'initialisation basique +puis bascule sur un programme de [charge utile](https://doc.coreboot.org/payloads.html) +(par ex. [GRUB](https://www.gnu.org/software/grub/), +[Tianocore](https://www.tianocore.org/)), qui doit lui aussi être configuré. +*Libreboot règle ce problème*; c'est une *distribution de coreboot* avec +un [système de compilation automatisé](docs/builds/), crééant des +*images ROM* complètes pour une installation plus robuste. De la documentation est disponible. + +De quelle façon Libreboot diffère de Coreboot? +------------------------------------------------ + + + +Contrairement à l'opinion populaire, le but principal de Libreboot n'est +pas de fournir un Coreboot déblobbé; ceci n'est simplement qu'une +des politiques de Libreboot, une importante certes, mais qui n'est qu'un +aspect mineur de Libreboot. + +De la même façon que *Alpine Linux* est une distribution Linux, Libreboot +est une *distribution coreboot*. Si vous voulez compilé une image ROM +en partant des bases, vous devez alors effectuer une configuration experte +de Coreboot, GRUB et n'importe quel autre logiciel dont vous avez besoin +afin de préparer la ROM. Avec *Libreboot*, +vous pouvez télécharger la source depuis Git ou une archive, exécuter +`make` etça compilera une image ROM entières. Le système de compilation +automatisé de Libreboot nommé `lbmk` (Libreboot MaKe), compile ces images +ROM automatiquement, sans besoin d'entrées utilisateur or intervention +requise. La configuration est faite à l'avance. + +Si vous devriez compiler du coreboot classique sans utiliser le système +de build automatisé de Libreboot, ça demanderait bien plus d'effort et +de connaissances techniques décente pour écrire une configuration qui marche. + +Les versions de Libreboot fournissent ces images ROM pré-compilés et vous +pouvez les installez simplement, sans connaissance ou compétence particulière +à savoir, sauf [suivre des instructions simplifiés écrite pour des utilisateurs non techniques](docs/install/). diff --git a/site/index.md b/site/index.md new file mode 100644 index 0000000..bc16f55 --- /dev/null +++ b/site/index.md @@ -0,0 +1,77 @@ +--- +title: Libreboot project +x-toc-enable: true +... + +The *Libreboot* project provides +[free, open source](https://writefreesoftware.org/) (*libre*) boot +firmware based on coreboot, replacing proprietary BIOS/UEFI firmware +on [specific Intel/AMD x86 and ARM based motherboards](docs/hardware/), +including laptop and desktop computers. It initialises the hardware (e.g. memory +controller, CPU, peripherals) and starts a bootloader for your operating +system. [Linux](docs/linux/) and [BSD](docs/bsd/) are well-supported. Help is +available via [\#libreboot](https://web.libera.chat/#libreboot) +on [Libera](https://libera.chat/) IRC. + + + +**NEW RELEASE: The latest release is Censored Libreboot c20230710, released on +10 July 2023. +See: [Censored Libreboot c20230710 release announcement](news/censored-libreboot20230710.md).** + +Why should you use *Libreboot*? +---------------------------- + +Libreboot gives you [freedoms](https://writefreesoftware.org/) that +you otherwise can't get with most other boot firmware, plus faster boot speeds +and [better security](docs/linux/grub_hardening.md). It's extremely powerful +and [configurable](docs/maintain/) for many use cases. + +You have rights. The right to privacy, freedom of thought, freedom of speech +and the right to read. In this context, Libreboot gives you these rights. +Your freedom matters. +[Right to repair](https://yewtu.be/watch?v=Npd_xDuNi9k) matters. +Many people use proprietary (non-libre) +boot firmware, even if they use [a libre OS](https://www.openbsd.org/). +Proprietary firmware often [contains](faq.html#intel) [backdoors](faq.html#amd), +and can be buggy. The Libreboot project was founded in December 2013, with the +express purpose of making coreboot firmware accessible for non-technical users. + +The Libreboot project uses [coreboot](https://www.coreboot.org/) for [hardware +initialisation](https://doc.coreboot.org/getting_started/architecture.html). +Coreboot is notoriously difficult to install for most non-technical users; it +handles only basic initialization and jumps to a separate +[payload](https://doc.coreboot.org/payloads.html) program (e.g. +[GRUB](https://www.gnu.org/software/grub/), +[Tianocore](https://www.tianocore.org/)), which must also be configured. +*Libreboot solves this problem*; it is a *coreboot distribution* with +an [automated build system](docs/build/) that builds complete *ROM images*, for +more robust installation. Documentation is provided. + +Libreboot is not a fork of coreboot +----------------------------------- + + + +In fact, Libreboot tries to stay as close to *stock* coreboot as possible, +for each board, but with many different types of configuration provided +automatically by the Libreboot build system. + +In the same way that *Alpine Linux* is a *Linux distribution*, Libreboot is +a *coreboot distribution*. If you want to build a ROM image from scratch, you +otherwise have to perform expert-level configuration of coreboot, GRUB and +whatever other software you need, to prepare the ROM image. With *Libreboot*, +you can literally download from Git or a source archive, and run `make`, and it +will build entire ROM images. An automated build system, named `lbmk` +(Libreboot MaKe), builds these ROM images automatically, without any user input +or intervention required. Configuration has already been performed in advance. + +If you were to build regular coreboot, without using Libreboot's automated +build system, it would require a lot more intervention and decent technical +knowledge to produce a working configuration. + +Regular binary releases of Libreboot provide these +ROM images pre-compiled, and you can simply install them, with no special +knowledge or skill except the ability to +follow [simplified instructions, written for non-technical +users](docs/install/). diff --git a/site/index.uk.md b/site/index.uk.md new file mode 100644 index 0000000..ee2873e --- /dev/null +++ b/site/index.uk.md @@ -0,0 +1,71 @@ +--- +title: Проект Libreboot +x-toc-enable: true +... + +Проект *Libreboot* надає +[вільну](https://writefreesoftware.org/) *завантажувальну +прошивку*, яка ініціалізує апаратне забезпечення (наприклад, контролер пам'яті, ЦП, +периферію) на [конкретних цілях Intel/AMD x86 та ARM](docs/hardware/), що +потім розпочинає завантажувач для вашої операційної системи. [Linux](docs/linux/) +та [BSD](docs/bsd/) добре підтримуються. Це заміняє пропрієтарну BIOS/UEFI +прошивку. Допомога доступна +через [\#libreboot](https://web.libera.chat/#libreboot) +на [Libera](https://libera.chat/) IRC. + + + +**НОВИЙ ВИПУСК: Останній випуск Censored Libreboot c20230710, випущено 10 липня 2023. +Дивіться: [Оголошення про випуск Censored Libreboot c20230710](news/censored-libreboot20230710.md).** + +Чому вам варто використовувати *Libreboot*? +---------------------------- + +Libreboot надає вам [свободи](https://writefreesoftware.org/), які в +іншому випадку ви не можете отримати з більшістю інших завантажувальних +прошивок. Він надзвичайно [потужний](docs/linux/grub_hardening.md) +та [налаштовується](docs/maintain/) для багатьох випадків використання. + +У вас є права. Право на конфіденційність, свобода мислення, свобода висловлювання +та право читати. В цьому контексті, Libreboot надає вам ці права. +Ваша свобода має значення. +[Право на ремонт](https://yewtu.be/watch?v=Npd_xDuNi9k) має значення. +Багато людей використовують пропрієтарну (невільну) +завантажувальну прошивку, навіть якщо вони використовують [вільну операційну систему](https://www.openbsd.org/). +Пропрієтарна прошивка часто [містить](faq.uk.html#intel) [лазівки](faq.uk.html#amd), +та може бути глючною. Проект Libreboot було засновано в грудні 2013 року, з +явною метою зробити прошивку coreboot доступною для нетехнічних користувачів. + +Проект Libreboot використовує [coreboot](https://www.coreboot.org/) для [ініціалізації апаратного забезпечення](https://doc.coreboot.org/getting_started/architecture.html). +Coreboot помітно складний для встановлення для більшості нетехнічних користувачів; він +виконує тільки базову ініціалізацію та перестрибує до окремої програми +[корисного навантаження](https://doc.coreboot.org/payloads.html) (наприклад, +[GRUB](https://www.gnu.org/software/grub/), +[Tianocore](https://www.tianocore.org/)), які також мають бути налаштованими. +*Програмне забезпечення Libreboot вирішує цю проблему*; це *дистрибутив coreboot* з +[автоматизованою системою побудови](docs/build/index.uk.md), яка збирає завершені *образи ROM*, для +більш надійної установки. Документація надається. + +Чим Libreboot відрізняється від звичайного coreboot? +--------------------------------------------- + + + +Таким же самим чином, як *Debian* це дистрибутив Linux, Libreboot це +*дистрибутив coreboot*. Якщо ви хочете зібрати образ ROM з нуля, вам +інакше довелось би виконати налаштування експертного рівня coreboot, GRUB та +будь-якого іншого потрібного програмного забезпечення, для підготування образа ROM. З *Libreboot*, +ви можете буквально завантажити з Git або архіву джерельного коду, та запустити `make`, і це +побудує всі образи ROM. Автоматизована система побудови, названа `lbmk` +(Libreboot MaKe), збирає ці образи ROM автоматично, без будь-якого вводу користувача +або потрібного втручання. Налаштування вже виконано заздалегідь. + +Якщо би ви збирали звичайний coreboot, не використовуючи автоматизовану систему побудови Libreboot, +це вимагало би набагато більше втручання та гідних технічних +знань для створення робочої конфігурації. + +Звичайні бінарні випуски Libreboot надають ці +образи ROM попередньо зібраними, і ви можете просто встановити їх, не маючи спеціальних +знань або навичок, окрім можливості +слідувати [спрощеним інструкціям, написаним для нетехнічних +користувачів](docs/install/). diff --git a/site/index.zh-cn.md b/site/index.zh-cn.md new file mode 100644 index 0000000..443a774 --- /dev/null +++ b/site/index.zh-cn.md @@ -0,0 +1,35 @@ +--- +title: Libreboot 项目 +x-toc-enable: true +... + +*Libreboot* 项目提供了[自由](https://writefreesoftware.org/)的*引导固件*，能够在[特定的 Intel/AMD x86 以及 ARM 目标机](docs/hardware/)上对硬件（如内存控制器、CPU、外设）进行初始化，进而为操作系统启动 bootloader。本项目对 [Linux](docs/linux/) 和 [BSD](docs/bsd/) 支持良好，并替代了专有的 BIOS/UEFI 固件。寻求帮助，可以前往 [Libera](https://libera.chat/) IRC 上的 [\#libreboot](https://web.libera.chat/#libreboot) 频道。 + + + +**新版发布: 最新版本 Censored Libreboot c20230710 已在 2023 年 7 月 10 日发布。 +详见: [Censored Libreboot c20230710 发布公告](news/censored-libreboot20230710.md).** + +为什么要使用 *Libreboot*? +---------------------------- + +Libreboot 赋予了你[自由](https://writefreesoftware.org/)，而这等自由，是你用其他引导固件得不到的。同时，它的启动速度更加快，[安全性也更加高](docs/linux/grub_hardening.md)。在各种情况下使用，它都十分强大，具有高度[可配置性](docs/maintain/)。 + +权利在你手上。你拥有隐私权、思想自由、言论自由、阅读权。这时，Libreboot 赋予了你这些权利。你的自由是宝贵的。 +[修理权](https://yewtu.be/watch?v=Npd_xDuNi9k)是宝贵的。 +尽管许多人在用[自由的操作系统](https://www.openbsd.org/)，但他们用的引导固件却是专有（非自由）的。专有固件常常[包含](faq.html#intel)了[后门](faq.html#amd)，并且也可能出问题。2013 年 12 月，我们建立了 Libreboot 项目，目的是让不懂技术的用户能使用 coreboot 固件。 + +Libreboot 项目使用 [coreboot](https://www.coreboot.org/) 来[初始化硬件](https://doc.coreboot.org/getting_started/architecture.html)。对大部分不懂技术的用户来说，coreboot 是出了名地难安装；它只处理了基础的初始化，然后跳转进入单独的 [payload](https://doc.coreboot.org/payloads.html) 程序（例如 [GRUB](https://www.gnu.org/software/grub/)、[Tianocore](https://www.tianocore.org/)），而后者也需要进行配置。*Libreboot 解决了这样的问题*；他是一个 *coreboot 发行版*，配有[自动构建系统](docs/build/)，能够构建完整的 *ROM 镜像*，从而让安装更加稳定。另有文档可参考。 + +Libreboot 不是 coreboot 的分支 +----------------------------------- + + + +事实上，Libreboot 对每一块主板，都尽可能保持与*标准*的 coreboot 接近，但 Libreboot 构建系统也自动提供了许多不同类型的配置。 + +Libreboot 是一个 *coreboot 发行版*，就好比 *Alpine Linux* 是一个 *Linux 发行版*。如果你想要从零开始构建 ROM 镜像，那你需要对 coreboot、GRUB 以及其他所需软件进行专业级别的配置，才能准备好 ROM 镜像。有了 *Libreboot*，你只需要下载 Git 仓库或者源代码归档，然后运行 `make`，接着就能构建整个 ROM 镜像。一套自动构建系统，名为 `lbmk`（Libreboot Make），将自动构建 ROM 镜像，而无需任何用户输入或干预。配置已经提前完成。 + +如果你要构建常规的 coreboot，而不使用 Libreboot 的自动构建系统，那么需要有很多的干预以及相当的技术知识，才能写出一份能工作的配置。 + +Libreboot 的常规二进制版本，提供了这些预编译的 ROM 镜像。你可以轻松安装它们，而无需特别的知识和技能，只要能遵循[写给非技术用户的简单指南](docs/install/)。 diff --git a/site/lbkey.asc b/site/lbkey.asc new file mode 100644 index 0000000..be7d1f1 --- /dev/null +++ b/site/lbkey.asc @@ -0,0 +1,54 @@ +-----BEGIN PGP PUBLIC KEY BLOCK----- + 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the Free Software +Foundation, with no Invariant Sections, no Front Cover +Texts and no Back Cover +Texts. + +The *logo* for libreboot is Copyright (C) 2014 Marcus Moeller, released under +Creative Common Zero license, version 1.0: + + +The original logo files are here: + +You can download the logo files from `lbwww-img.git`. See: + + +These pages are static HTML, generated from Markdown files, which you can find +a link to at the bottom of each HTML page, for the corresponding Markdown file. + +The terms of this license are written below, unmodified, except to change the +formatting so that the text would integrate nicely on this website. + +You can also find the license here: + + +The markdown version, hosted by the GNU project, can be found here: + + +The *unmodified* license text is as follows: + +GNU Free Documentation License +============================== + +Version 1.3, 3 November 2008 + +Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, +Inc. + +Everyone is permitted to copy and distribute verbatim copies of this +license document, but changing it is not allowed. + +0. PREAMBLE +----------- + +The purpose of this License is to make a manual, textbook, or other +functional and useful document "free" in the sense of freedom: to +assure everyone the effective freedom to copy and redistribute it, +with or without modifying it, either commercially or noncommercially. +Secondarily, this License preserves for the author and publisher a way +to get credit for their work, while not being considered responsible +for modifications made by others. + +This License is a kind of "copyleft", which means that derivative +works of the document must themselves be free in the same sense. It +complements the GNU General Public License, which is a copyleft +license designed for free software. + +We have designed this License in order to use it for manuals for free +software, because free software needs free documentation: a free +program should come with manuals providing the same freedoms that the +software does. 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Now you see the generic footer +generated for every page on this website: + diff --git a/site/logo-license.md b/site/logo-license.md new file mode 100644 index 0000000..572c8b9 --- /dev/null +++ b/site/logo-license.md @@ -0,0 +1,18 @@ +--- +title: Libreboot logo license +... + +The Libreboot logo is copyright 2014 Marcus Moeller, and it was also created by +that person. It is released under the terms of the Creative Commons Zero +license, version 1.0. + +The sticker files, based on that logo, are made by Patrick McDermott in 2015, +released under the same license. + +A copy of this license (CC-0 1.0) can be found at: + + +The font on the sticker designs is `lato`. Install this, otherwise the vectors +won't look correct for the text. + +You can see the logo files here: diff --git a/site/logo-license.uk.md b/site/logo-license.uk.md new file mode 100644 index 0000000..b97fa5b --- /dev/null +++ b/site/logo-license.uk.md @@ -0,0 +1,18 @@ +--- +title: Ліцензія на логотип Libreboot +... + +Логотип Libreboot захищений авторським правом у 2014 році Маркусом Моллером, його також було створено +цією особою. Він випущений згідно з умовами Creative Commons Zero license, +version 1.0. + +Файли наклейок, на основі цього логотипу, створені Патріком МакДермоттом у 2015 році, +випущені за тією ж ліцензією. + +A copy of this license (CC-0 1.0) can be found at: + + +Шрифт на дизайні стікерів `lato`. Встановіть його, інакше вектори +не виглядатимуть правильно для тексту. + +Ви можете переглянути файли логотипів тут: diff --git a/site/news/MANIFEST b/site/news/MANIFEST new file mode 100644 index 0000000..e6b5685 --- /dev/null +++ b/site/news/MANIFEST @@ -0,0 +1,37 @@ +censored-libreboot20230710.md +audit.md +e6400.md +mirrors.md +codeberg.md +kgpe-d16.md +usa-libre-part3.md +usa-libre-part2.md +fedfree.md +libreboot20220710.md +usa-libre.md +translations.md +libreboot20211122.md +libreboot20210522.md +libreboot20160907.md +libreboot20160902.md +libreboot20160818.md +libreboot20150518.md +libreboot20150208.md +libreboot20150126.md +libreboot20150124.md +libreboot20141015.md +libreboot20140911.md +libreboot20140903.md +libreboot20140811.md +libreboot20140729.md +libreboot20140720.md +libreboot20140716.md +libreboot20140711.md +libreboot20140622.md +libreboot20140611.md +libreboot20140605.md +libreboot20140309.md +libreboot20140221.md +libreboot20131214.md +libreboot20131213.md +libreboot20131212.md diff --git a/site/news/audit.md b/site/news/audit.md new file mode 100644 index 0000000..d690804 --- /dev/null +++ b/site/news/audit.md @@ -0,0 +1,354 @@ +% Libreboot build system audit +% Leah Rowe +% 13 June 2023 + +Introduction +============ + +In recent weeks, Libreboot's build system has gone through an intense audit and +until recent *days* has undergone extensive testing. There are still a few more +things to be done. The purpose of this audit has been to: + +* Look for and fix bugs +* Improve code quality (nicer coding style) +* Reduce code repetition + +This concerns only *lbmk*, the [automated build system](../docs/maintain/) that +Libreboot uses. This is what Libreboot uses to build coreboot, payloads, +utilities, ROM images and, ultimately, Libreboot releases, so one could argue +that lbmk *is* Libreboot. It automatically downloads, patches, pre-configures +and compiles everything from scratch, but in a way that is simplified from the +perspective of the end user (almost everything is just a single command, where +users are typically not required to edit any files unless they want to). + +Brief summary of changes +------------------------ + +In short, the following work has been performed: + +* [OpenBSD coding style](https://man.openbsd.org/style.9) more rigorously + adopted, on some C utilities included in lbmk; though this was already the + case for some of them. +* That same BSD coding style has been *adapted* for use with shell scripts. +* Vastly improved error handling, on some scripts (in many cases, errors that + were previously unhandled are now handled fully). + +Example of build system cleanup recently performed: all scripts in the main +directory of lbmk are now consolidated into a *single* shell script. Similar +cleanup is underway for other parts of the build system. + +Libreboot's build system is already very efficient. It's *only* a few thousand +source lines (about 2200, at the last count). Libreboot's build system provides +the minimal glue necessary to download, patch, configure and build ROM images +for end users. The mentality behind is is that every codebase on average +probably has the same percentage of bugs, so *less code* means less bugs, so +*less code* is *good*. Many people ask *how* but the most important question +is usually *why* (or *when*). Libreboot's build system tries to avoid bloat +and *feature creep* when possible, intentionally refusing to implement certain +features that are considered superfluous. + +Example of BSD coding style on shell scripts +-------------------------------------------- + +One of the most common practises in BSD style in *top-down* logic, which +makes programs much easier to read (in my opinion). Here is an example +of the BSD coding style in use within *lbmk*. Here is the *old* coreboot +download script in lbmk: + + + +And here is that same script, after auditing and cleanup with the BSD style +adapted: + + + +The trick is to have a `main()` at top, and add this line at the bottom of +the script: + + main $@ + +This will pass all arguments on the shell, to the `main()` function. Where +possible, only *global* variables are written outside functions, with no +other logic written (all logic is to be written inside functions). + +Where feasible, and desirable, this style will now be used for all new scripts +in the Libreboot build system, with existing scripts modified accordingly. This +and other work is ongoing. + +Auditing of utilities +===================== + +This process has *also* been applied to some of the utilities (written in C) +that Libreboot includes as part of lbmk. The following utilities have been +audited: + +* `spkmodem-recv` (more on this in a moment) +* `e6400-flash-unlock` (minor cleanup, basically removing one unused function) +* `nvmutil` (massive code size reduction, minor fixes here and there) + +Pledge +------ + +The `nvmutil` program was already pledged, when compiled on OpenBSD, but it was +not handled well. It is now handled correctly (correct ifdef rule), and it +has been *hardened* greatly. + +The code has also been unveiled. See manpages: + + + + + +spkmodem-recv +------------- + +This utility was *added* to the build system. It was imported from coreboot, +which in turn previously forked it from GNU GRUB. It is a receiving client for +spkmodem, to provide a serial console via pulses on the standard *PC speaker*. + +Libreboot's version is *heavily* re-factored, doing away with the GNU coding +style and replacing it with a BSD coding style (the licensing is unchanged). + +For reference, here is the original version from GRUB: + + + +And here is the version coreboot had, which Libreboot forked: + + + +And here is the *Libreboot* version, as of today, 13 June 2023: + + + +In addition to code style changes, certain variables are renamed for clarity, +and certain redundant variables removed. Logic split into functions, and the +code is conditionally *pledged* if you compile it on OpenBSD (for OpenBSD), +see: + +FULL list of changes resulting from the audit +============================================== + +Not all patches are listed below, if they are patches not relevant, or patches +not currently pushed to upstream Libreboot git mirrors. The following patches +are available, live: + +(time references such as "36 minutes ago" are relative to ~1.30am UK time +on 13 June 2023) + +``` +* dee8f44b - util/spkmodem-recv: fix regression (5 days ago) +* f2822db9 - util/spkmodem-recv: make ringpos a global variable (7 days ago) +* 334bfedf - util/spkmodem-recv: simplify sample_cnt/char reset (8 days ago) +* 4a6b5827 - util/spkmodem-recv: print stats in other function (8 days ago) +* 2652a1dd - util/spkmodem-recv: only print unhandled err on -d (8 days ago) +* 3fb99a01 - util/spkmodem-recv: make debug a runtime option (8 days ago) +* 264a31b9 - util/spkmodem-recv: always disable line buffering (8 days ago) +* 118bb19f - util/spkmodem-recv: simplify stdout flush logic (8 days ago) +* af36cc7f - util/spkmodem-recv: rename variables for clarity (8 days ago) +* f7fccb59 - util/spkmodem-recv: split print_char() up (8 days ago) +* b40a30b1 - util/spkmodem-recv: reduce indent in print_char() (8 days ago) +* b21c1dd5 - util/spkmodem-recv: squash a few code lines (8 days ago) +* 3401f287 - util/spkmodem-recv: bsd-style indent (8 days ago) +* 2a6ad971 - util/spkmodem-recv: order prototypes per function (8 days ago) +* 212ce3a8 - util/spkmodem-recv: warn on unhandled exit error (8 days ago) +* 9a6d2908 - util/spkmodem-recv: another minor code cleanup (8 days ago) +* a61ab37b - util/spkmodem-recv: always set errno on err() (8 days ago) +* e8889fd1 - util/spkmodem-recv: minor code cleanup (8 days ago) +* 3c2a287e - util/spkmodem-recv: handle sample errors correctly (8 days ago) +* 979db74c - util/spkmodem-recv: simplify pulse check (8 days ago) +* 94aa43d8 - util/nvmutil: call unveil earlier, and harden (9 days ago) +* db63fcff - util/nvmutil: hardening: reduce pledges earlier (9 days ago) +* dbd6defe - util/nvmutil: fix faulty arg check (9 days ago) +* 270693fc - util/nvmutil: cleanup: move logic out of main() (10 days ago) +* 46a9eea0 - util/nvmutil: major cleanup. simpler arg handling. (10 days ago) +* c9fdfce3 - util/nvmutil: simplify writeGbeFile() (11 days ago) +* bdccd7cb - util/nvmutil: don't call writeGbeFile if O_RDONLY (11 days ago) +* 99258a38 - util/nvmutil: code cleanup (pledge/unveil calls) (11 days ago) +* 69fa333e - util/nvmutil: harden pledge/unveil calls (OpenBSD) (12 days ago) +* adf3aece - util/nvmutil: fix faulty fd check (12 days ago) +* b49da12d - util/nvmutil: only swap/copy if checksum is valid (12 days ago) +* 9aa34f1e - util/nvmutil: use bsd-style indentation (12 days ago) +* 18f39ab6 - util/nvmutil: clean up rhex() (12 days ago) +* 4d91bcc2 - util/nvmutil: check correct return value on close() (12 days ago) +* c2c31677 - util/nvmutil: massive code cleanup (12 days ago) +* f0846134 - util/nvmutil: move includes to nvmutil.h (12 days ago) +* 2dabafe6 - util/nvmutil: move xpledge/xunveil to nvmutil.h (12 days ago) +* 9a3e6516 - util/nvmutil: use SPDX license headers (12 days ago) +* 5d6af06a - util/nvmutil: move non-functions to nvmutil.h (12 days ago) +* a2136933 - util/nvmutil: use even more macros (code cleanup) (12 days ago) +* 5a9fac2a - util/nvmutil: remove unnecessary parentheses (12 days ago) +* 6885200c - util/nvmutil: simplify setWord() with word() macro (12 days ago) +* 7ab209d5 - util/nvmutil: do xor swap in a macro (12 days ago) +* 293ca0fc - util/nvmutil pledge,unveil: use correct err string (12 days ago) +* a1df8fd1 - util/nvmutil: ensure that errno is set on err() (12 days ago) +* 1f548604 - util/nvmutil: minor code cleanup (12 days ago) +* 8f1e6d79 - util/nvmutil: simplified error handling in main (13 days ago) +* 78fc8935 - util/nvmutil: Use unveil, and harden pledges (13 days ago) +* c2cd1916 - util/nvmutil: Harden pledge promises (13 days ago) +* c759a7a0 - util/nvmutil: Simplify use of pledge (on OpenBSD) (13 days ago) +* f37bd759 - util/nvmutil: Use correct pledge promise (OpenBSD) (13 days ago) +* 83ecf268 - util/*: Properly detect OpenBSD for pledge() call (13 days ago) +* 8df2f809 - util/e6400-flash-unlock: clean up commented code (2 weeks ago) +* ff954c5b - unify download/build scripts (2 weeks ago) +* 092600d1 - unify these scripts: build, modify and update (2 weeks ago) +* 6344b196 - build/payload/seabios: reduced indentation (2 weeks ago) +* 2be1a8ea - download/coreboot: fix error handling in subshell (3 weeks ago) +* d0171eef - download/coreboot: don't needlessly re-download (3 weeks ago) +* c616930b - download/coreboot: remove unnecessary bloat (3 weeks ago) +* d1935c05 - build/clean/u-boot: remove unnecesssary check (3 weeks ago) +* 676efbb0 - build/clean/u-boot: improved coding style (3 weeks ago) +* 06a92f61 - build/clean/ich9utils: don't use subshell (3 weeks ago) +* 43e2dfe2 - build/u-boot: top-down, split-function code style (3 weeks ago) +* a8f0721a - build/payload/u-boot: 79 chars or less per line (3 weeks ago) +* 89ac1ea5 - build/payload/u-boot: fix wrong attributions (3 weeks ago) +* c973b959 - build/payload/grub: rename functions for clarity (3 weeks ago) +* 51e0e401 - build/payload/grub: remove unnecessary check (3 weeks ago) +* 8e206be7 - build/payload/grub: split logic into functions (3 weeks ago) +* db7e8161 - build/payload/grub: 79 chars or less per line (3 weeks ago) +* 92bd18c4 - build/release/roms: minor cleanup (3 weeks ago) +* ec3d1006 - build/release/roms: handle argument properly (3 weeks ago) +* e0b97660 - build/release/roms: remove superfluous comments (3 weeks ago) +* 681538a2 - build/release/roms: handle errors inside subshell (3 weeks ago) +* a9bd5442 - build/release/roms: split logic into functions (3 weeks ago) +* 29833090 - build/release/roms: use tabs for indentation (3 weeks ago) +* fff5fa53 - build/release/src: 79 chars or less per code line (3 weeks ago) +* 1cdf1c7c - build/release/src: handle errors in subshells (3 weeks ago) +* 16f878e8 - build/release/src: split logic into functions (3 weeks ago) +* 4e2ee58a - build/ich9utils: simplify, fix error handling (3 weeks ago) +* 93ec91e8 - build/memtest86plus: use tabs for indentation (3 weeks ago) +* 4b80f250 - build/clean/crossgcc: better code style (3 weeks ago) +* 187d5fa4 - build/descriptors: simplify and fix error handling (3 weeks ago) +* a05be169 - build/grub: fix inconsistent indentation (3 weeks ago) +* 02919c47 - build/grub: implement error handling (3 weeks ago) +* 5bab3bbc - build/grub: introduce main(), split it up (3 weeks ago) +* 277e1df0 - build/cbutils: remove unnecessary directory check (3 weeks ago) +* ed9eb462 - build/cbutils: rename function for clarity (3 weeks ago) +* b12dced4 - build/cbutil: avoid frivilous use of subshells (3 weeks ago) +* 355a45b4 - build/cbutils: top-down coding style, main on top (3 weeks ago) +* 9f58d4e4 - build/cbutils: 79 chars or less per line (3 weeks ago) +* 691f2664 - build/cbutils: use tabs for indendation (3 weeks ago) +* 3cbcfce9 - gitclone: add my copyright for recent changes (4 weeks ago) +* 01a2ab37 - use env in shell scripts (4 weeks ago) +* 1e8f2cc1 - gitclone: only rm the old directory at the end (4 weeks ago) +* 3da8d20c - gitclone: stricter error handling (4 weeks ago) +* e8048494 - gitclone: minor cleanup (4 weeks ago) +* fd2ca12e - gitclone: split logic out of main() (4 weeks ago) +* 08ad9eb1 - download/coreboot: minor cleanup (4 weeks ago) +* 8d9570b6 - gitclone: cleaner coding style (4 weeks ago) +* 9fb489ac - modify: clean up duplicated code (4 weeks ago) +* f7f3aef1 - modify: cleaner coding style (4 weeks ago) +* 34df727c - build: cleaner coding style (4 weeks ago) +* 1a062bb6 - build: reduce code to less than 80 chars per line (4 weeks ago) +* c08e3258 - .gitcheck: exit 1 if unsupported argument given (4 weeks ago) +* c5122557 - .gitcheck: use subshells where appropriate (4 weeks ago) +* dd8fb524 - .gitcheck: re-add redirection to /dev/null (4 weeks ago) +* 82c4d7b2 - .gitcheck clean: clean coreboot directories too (4 weeks ago) +* 0f3c3ca6 - .gitcheck: reduce indentation level for loop (4 weeks ago) +* ecd7f1d1 - .gitcheck: move logic out of main() (4 weeks ago) +* 829bc02b - .gitcheck: *actually* check coreboot directories (4 weeks ago) +* 52bc07bc - .gitcheck: improved coding style (4 weeks ago) +* 83235fb9 - .gitcheck: check argv when running gitcheck-clean (4 weeks ago) +* 6ce77652 - .gitcheck: actually *run* gitcheck-clean (4 weeks ago) +* 8782bff8 - download: code cleanup (4 weeks ago) +* a232f9c5 - download: check for non-existent script in loop (4 weeks ago) +* b4f1804e - download script: bugfix: gitcheck clean didn't run (4 weeks ago) +* 62c88dfb - download script: improved coding style (4 weeks ago) +* 5b594909 - util/spkmodem_recv: Use pledge but only on OpenBSD (4 weeks ago) +* 25241ae2 - util/spkmodem_recv: Add -u flag (no line buffer) (4 weeks ago) +* 01fdfa3a - util/spkmodem_recv: Tidy up global variables (4 weeks ago) +* 50b35939 - util/spkmodem_recv: Make pulse variable global (4 weeks ago) +* 14190de9 - util/spkmodem_recv: Use parentheses on comparisons (4 weeks ago) +* c0f2bf30 - util/spkmodem_recv: Move global variable: pulse (4 weeks ago) +* 5d03598b - util/spkmodem_recv: Purge unused global: amplitude (4 weeks ago) +* 63e43819 - util/spkmodem_recv: Remove unused variable: pos (4 weeks ago) +* a0abcb9f - util/spkmodem_recv: Re-order functions for clarity (4 weeks ago) +* 93cc6642 - util/spkmodem_recv: Handle output in new function (4 weeks ago) +* 27866e65 - util/spkmodem_recv: Re-order prototypes (4 weeks ago) +* 8b851258 - util/spkmodem_recv: Rename functions for clarity (4 weeks ago) +* 6c1bf756 - util/spkmodem_recv: Return errno in main (4 weeks ago) +* c23806e1 - util/spkmodem_recv: Use correct printf specifier (4 weeks ago) +* 0cc23b23 - util/spkmodem_recv: Add error handling (4 weeks ago) +* 17932381 - util/spkmodem_recv: Move logic out of main (4 weeks ago) +* 3d554294 - util/spkmodem_recv: Rename variable for clarity (4 weeks ago) +* 697ae5e2 - util/spkmodem_recv: Remove use of static keyword (4 weeks ago) +* 2c12e70c - util/spkmodem_recv: Rename variable for clarity (4 weeks ago) +* 5b6f5cb0 - util/spkmodem_recv: Remove space in function calls (4 weeks ago) +* abc5cfd3 - util/spkmodem_recv: Say frame in English (4 weeks ago) +* e2864704 - util/spkmodem_recv: Top-down logic (main on top) (4 weeks ago) +* 3722c1e6 - util/spkmodem_recv: simplified pulse check (4 weeks ago) +* 88683b76 - util/spkmodem_recv: Define argc/argv in main (4 weeks ago) +* 83b34e2f - util/spkmodem_recv: Reduced indentation in loop (4 weeks ago) +* 22633e0d - util/spkmodem_recv: Use tabs for indentation (4 weeks ago) +* 9152d0f9 - util/spkmodem_recv: Add clean to the Makefile (4 weeks ago) +* 754410f2 - util/spkmodem_recv: Define CC in the Makefile (4 weeks ago) +* f2887e9b - util/spkmodem_recv: Add strict CFLAGS (4 weeks ago) +* b496ead7 - util/spkmodem_recv: Import from coreboot (4 weeks ago) +* 52d87f5f - download/coreboot: minor code cleanup (4 weeks ago) +* 7bd206b9 - download/coreboot: remove errant code (4 weeks ago) +* bd82d90f - download/coreboot: tidy up variable names (4 weeks ago) +* 66d06afd - download/coreboot: run extra.sh from cbtree (4 weeks ago) +* c4b0825c - download/coreboot: avoid variable conflict (4 weeks ago) +* 0e1e9c17 - download/coreboot: fix downloads without argument (4 weeks ago) +* bea67353 - download/coreboot: much cleaner coding style (4 weeks ago) +* 2d69072a - download/coreboot: clone upstream via ./gitclone (4 weeks ago) +* c17423e4 - download/coreboot: simplify check (4 weeks ago) +* 00cafd70 - download/coreboot: fix misnamed function (4 weeks ago) +* 86512e84 - download/coreboot: simplify small if statements (4 weeks ago) +* d28584f3 - download/coreboot: fetch config in new function (4 weeks ago) +* 162f4bf5 - download/coreboot: use global variables (4 weeks ago) +* 56b80c0a - download/coreboot: rename function for clarity (4 weeks ago) +* ee79d8ba - download/coreboot: reduce indentation in loop (4 weeks ago) +* f858baea - download/coreboot allow downloading specific trees (4 weeks ago) +* a33e5c67 - download/coreboot: split config check to function (4 weeks ago) +* 62038f1d - download/coreboot: fix misnamed variable (4 weeks ago) +* 342e846f - download/coreboot: consistent function declaration (4 weeks ago) +* c32ae597 - download/coreboot: rename function for clarity (4 weeks ago) +* e47aaa8f - download/coreboot: prune errant comments (4 weeks ago) +* 31d8fcd3 - download/coreboot: split main() (4 weeks ago) +* 4c2cff5e - download/coreboot functions: rename board variable (4 weeks ago) +* 7a6f40fc - download/coreboot: top-down re-ordering (4 weeks ago) +* fd8b8084 - download/coreboot: simplified for loops (4 weeks ago) +* b24fbc74 - download/coreboot: move initial logic to main() (4 weeks ago) +* 2871db15 - download/coreboot: RFC 2646 compliance (4 weeks ago) +* 8b4c1c16 - download/coreboot: consistent tab indentation (4 weeks ago) +* 1388cccb - build/seabios: cleaner coding style (4 weeks ago) +* ddad8f00 - build/seabios: simplify. stricter error handling (4 weeks ago) +* 557272fa - download/mrc: stricter error handling (4 weeks ago) +* 7b36ffc1 - download/mrc: handle exit status within subshell (4 weeks ago) +* 963b5247 - download/mrc: use cleaner coding style (4 weeks ago) +* d89585fb - gitclone: check for invalid patch filename (4 weeks ago) +* db3c1d9c - download/grub: delete grub if gnulib cloning fails (4 weeks ago) +* d90dfb0a - build/dependencies/*: RFC 2646 compliance (4 weeks ago) +* 48bda9e0 - update/coreboot: top-down coding style (4 weeks ago) +* 17429788 - remove errant code lines from last commit (4 weeks ago) +* fdc9e444 - Remove warning for coreboot images build without a payload (4 weeks ago) +* f2e31767 - modify/u-boot: cleaner coding style (4 weeks ago) +* 71cac866 - modify/coreboot: cleaner coding style (4 weeks ago) +* 174d3af7 - modify/seabios: cleaner coding style (4 weeks ago) +* c8dfc3cc - build/build/roms: simplify mkCoreboot() arguments (4 weeks ago) +* d8a8a1c6 - build/boot/roms: don't use subshells frivilously (4 weeks ago) +* 834be77c - build/boot/roms: remove errant debug line (4 weeks ago) +* 39c14398 - build/boot/roms: simplify build_rom_images() (4 weeks ago) +* 65dfdd56 - build/boot/roms: use fast dd command for ich9m ifd (4 weeks ago) +* 6a4ce66f - build/boot/roms: don't run ich9gen twice (4 weeks ago) +* 1e9ed989 - build/boot/roms: simplify moverom() (4 weeks ago) +* 5811e53e - build/boot/roms: remove unused legacy code (4 weeks ago) +* 3bd82b76 - build/boot/roms: reduced code indentation (4 weeks ago) +* 9eee0fb4 - build/boot/roms: split main() to topdown functions (4 weeks ago) +* bceb5f2e - build/roms_helper: move logic into main() (4 weeks ago) +* df611f9b - remove ga-g41m-es2l board for now (5 weeks ago) +* 3da0ee4f - remove python3 patches (5 weeks ago) +* 6290f999 - build/boot/roms_helper: further cleanup (5 weeks ago) +* 722c844e - build/boot/roms: top-down function order (5 weeks ago) +* 5f44556f - build/roms: general code style cleanup (5 weeks ago) +* d521fca7 - build/roms: fix faulty keymap list expansion (5 weeks ago) +* 67a607b8 - build/boot/roms*: RFC 2646 compliance (5 weeks ago) +* 79939f2f - Add devicetree patch for E6400 with Nvidia GPU (5 weeks ago) +* 3f1ee015 - seabios: do normal config, disable oprom in vgarom (5 weeks ago) +* ee46c042 - update the makefile (5 weeks ago) +* f5150f26 - remove e6400_8mb and e6400_16mb (keep e6400_4mb) (5 weeks ago) +* f820e304 - add e6400_flash_unlock binary to .gitignore (5 weeks ago) +* f49eccee - util/e6400-flash-unlock: do void on ec_fdo_command (6 weeks ago) +* 6588be67 - don't force console mode in grub (7 weeks ago) +``` diff --git a/site/news/censored-libreboot20230710.md b/site/news/censored-libreboot20230710.md new file mode 100644 index 0000000..2ef9a69 --- /dev/null +++ b/site/news/censored-libreboot20230710.md @@ -0,0 +1,229 @@ +% Censored Libreboot c20230710 released! +% Leah Rowe +% 10 July 2023 + +**[Click here for the uncensored version of this page](https://libreboot.org/news/censored-libreboot20230710.html)** - +it shows what was removed from regular Libreboot, in order to make this release. + +This version of the release announcement is provided as an illustration of what +such an announcement *would* have looked like, under previous Libreboot policy. + +Introduction +============ + +Libreboot provides boot firmware for supported x86/ARM machines, starting a +bootloader that then loads your operating system. It replaces proprietary +BIOS/UEFI firmware on x86 machines, and provides an *improved* configuration +on [ARM-based chromebooks](../docs/install/chromebooks.html) supported +(U-Boot bootloader, instead of Google's depthcharge bootloader). On x86 +machines, the GRUB and SeaBIOS coreboot +payloads are officially supported, provided in varying configurations per +machine. It provides an [automated build system](../docs/maintain/) for the +[configuration](../docs/build/) and [installation](../docs/install/) of coreboot +ROM images, making coreboot easier to use for non-technical people. You can find +the [list of supported hardware](../docs/hardware/) in Libreboot documentation. + +Libreboot's main benefit is *higher boot speed*, +[better](../docs/linux/encryption.md) +[security](../docs/linux/grub_hardening.md) and more +customisation options compared to most proprietary firmware. As a +[libre](https://writefreesoftware.org/) software project, the code can be audited, and coreboot does +regularly audit code. The other main benefit is [*freedom* to study, adapt and +share the code](https://writefreesoftware.org/), a freedom denied by most boot +firmware, but not Libreboot! Booting Linux/BSD is also [well](../docs/linux/) +[supported](../docs/bsd/). + +Build from source +----------------- + +*This* release was build-tested on Debian *Sid*, as of 9 July 2023. Your +mileage may vary, with other distros. Refer to Libreboot documentation. + +KFSN4-DRE, KCMA-D8, KGPE-D16 re-added +------------------------------------- + +FUN FACT: This includes building of ASUS KFSN4-DRE, KCMA-D8 and KGPE-D16 +boards, which were re-added based on coreboot `4.11_branch`. ROM images are +provided for these boards, in this Libreboot release. The toolchain in +this coreboot version would not build on modern Linux, so I spent time patching +it. I want to use coreboot `4.11_branch` to study code differences between the +D8 and D16 boards, which are mostly otherwise identical code-wise, so that I +can port KCMA-D8 to Dasharo, and then use that for D8/D16 in Libreboot. Dasharo +is based on a much newer coreboot version, with many new fixes/features. + +Coreboot, GRUB, U-Boot and SeaBIOS revisions +------------------------------------ + +In Censored Libreboot c20230710: + +* Coreboot (default): commit ID `e70bc423f9a2e1d13827f2703efe1f9c72549f20`, 17 February 2023 +* Coreboot (cros): commit ID `8da4bfe5b573f395057fbfb5a9d99b376e25c2a4` 2 June 2022 +* Coreboot (fam15h\_udimm): commit ID `1c13f8d85c7306213cd525308ee8973e5663a3f8`, 16 June 2021 +* GRUB: commit ID `f7564844f82b57078d601befadc438b5bc1fa01b`, 14 February 2023 +* SeaBIOS: commit ID `ea1b7a0733906b8425d948ae94fba63c32b1d425`, 20 January 2023 +* U-Boot (for coreboot/cros): commit ID `890233ca5569e5787d8407596a12b9fca80952bf`, 9 January 2023 + +In Libreboot 20220710: + +* Coreboot (default): commit ID `b2e8bd83647f664260120fdfc7d07cba694dd89e`, 17 November 2021 +* Coreboot (cros): **did not exist** (no ARM/U-Boot support in Libreboot 20220710) +* Coreboot (fam15h\_udimm): commit ID `ad983eeec76ecdb2aff4fb47baeee95ade012225`, 20 November 2019 +* GRUB: commit ID `f7564844f82b57078d601befadc438b5bc1fa01b`, 25 October 2021 +* SeaBIOS: commit ID `1281e340ad1d90c0cc8e8d902bb34f1871eb48cf`, 24 September 2021 +* U-Boot: **did not exist** (no ARM/U-Boot support in Libreboot 20220710) + +List of changes relative to Libreboot 20220710 +============================================== + +New mainboards supported +------------------------ + +These mainboards are now supported: + +* [Dell Latitude E6400](../docs/hardware/e6400.md) +* [ASUS Chromebook Flip C101 (gru-bob)](../docs/install/chromebooks.md) +* [Samsung Chromebook Plus (v1) (gru-kevin)](../docs/install/chromebooks.md) + +Build system changes +-------------------- + +A main focus has indeed been on build system auditing, utilities and +general polishing: + +* [MASSIVE build system audit](audit.md) - the entire build system was + re-written in a much cleaner coding style, with much stricter error handling + and clear separation of logic. A *lot* of bugs were fixed. A *LOT* of bugs. + Build system auditing has been the *main* focus, in these past 12 months. +* `cros`: Disable coreboot-related BL31 features. This fixes poweroff on gru + chromebooks. Patch courtesy of Alper Nebi Yasak. +* `u-boot`: Increase EFI variable buffer size. This fixes an error where + Debian's signed shim allocates too many EFI variables to fit in the space + provided, breaking the boot process in Debian. Patch courtesy Alper Nebi Yasak +* Coreboot build system: don't warn about no-payload configuration. Libreboot + compiles ROM images *without* using coreboot's payload support, instead it + builds most payloads by itself and inserts them (via cbfstool) afterwards. + This is more flexible, allowing greater configuration; even U-Boot is + handled this way, though U-Boot at least still uses coreboot's crossgcc + toolchain collection to compile it. Patch courtesy Nicholas Chin. +* `util/spkmodem-recv`: New utility, forked from GNU's implementation, then + re-written to use OpenBSD style(9) programming style instead of the + originally used GNU programming style, and it is uses + OpenBSD `pledge()` when compiled on OpenBSD. Generally much cleaner coding + style, with better error handling than the original GNU version (it is forked + from coreboot, who forked it from GNU GRUB, with few changes made). This + is a receiving client for spkmodem, which is a method coreboot provides to + get a serial console via pulses on the PC speaker. +* download/coreboot: Run `extra.sh` directly from given coreboot tree. Unused + by any boards, but could allow expanding upon patching capabilities in lbmk + for specific mainboards, e.g. apply coreboot gerrit patches in a specific + order that is not easy to otherwise guarantee in more generalised logic of + the Libreboot build system. +* `util/e6400-flash-unlock`: New utility, that disables flashing protections + on Dell's own BIOS firmware, for Dell Latitude E6400. This enables Libreboot + installation *without* disassembling the machine (external flashing equipment + is *not required*). Courtesy Nicholas Chin. +* Build dependencies scripts updated for more modern distros. As of this day's + release, Libreboot compiles perfectly in bleeding edge distros e.g. Arch + Linux, whereas the previous 20220710 required using old distros e.g. + Debian 10. +* `cbutils`: New concept, which implements: build coreboot utilities like + cbfstool and include the binaries in a directory inside lbmk, to be re-used. + Previously, they would be compiled in-place within the coreboot build system, + often re-compiled needlessly, and the checks for whether a given util are + needed were very ad-hoc: now these checks are much more robust. + Very centralised approach, per coreboot tree, rather than selectively + compiling specific coreboot utilities, and makes the build system logic in + Libreboot much cleaner. +* GRUB config: 30s timeout by default, which is friendlier on some desktops + that have delayed keyboard input in GRUB. +* ICH9M/GM45 laptops: 256MB VRAM by default, instead of 352MB. This fixes + certain performance issues, for some people, as 352MB can be very unstable. +* U-Boot patches: for `gru_bob` and `gru_kevin` chromebooks, U-Boot is used + instead of Google's own *depthcharge* bootloader. It has been heavily + modified to avoid certain initialisation that is replaced by coreboot, in + such a way that U-Boot is mainly used as a bootloader providing UEFI for + compliant Linux distros and BSDs. Courtesy Alper Nebi Yasak. +* lbmk: The entire Libreboot build system has, for the most part, been made + portable; a lot of scripts now work perfectly, on POSIX-only implementations + of `sh` (though, many dependencies still use GNU extensions, such as GNU + Make, so this portability is not directly useful yet, but a stepping stone. + Libreboot eventually wants to be buildable on non-GNU, non-Linux systems, + e.g. BSD systems) +* nvmutil: Lots of improvements to code quality, features, error handling. This + utility was originally its own project, started by Leah Rowe, and later + imported into the Libreboot build system. +* build/boot/roms: Support cross-compiling coreboot toolchains for ARM platforms, + in addition to regular x86 that was already supported. This is used for + compiling U-boot as a payload, on mainboards. +* U-boot integration: at first, it was just downloading U-Boot. Board integration + for ARM platforms (from coreboot) came later, e.g. ASUS Chromebook Flip C101 + as mentioned above. The logic for this is forked largely from the handling + of coreboot, because the interface for dealing with their build systems is + largely similar, and they are largely similar projects. Courtesy Denis Carikli + and Alper Nebi Yasak. +* New utility: `nvmutil` - can randomise the MAC address on Intel GbE NICs, for + systems that use an Intel Flash Descriptor +* General build system fixes: better (and stricter) error handling +* Fixed race condition when building SeaBIOS in some setups. +* GRUB configs: only scan ATA, AHCI or both, depending on config per board. + This mitigates performance issues in GRUB on certain mainboards, when + scanning for `grub.cfg` files on the HDD/SSD. +* GRUB configs: speed optimisations by avoiding slow device enumeration in + GRUB. + +The number of changes are vast, too big to be readable on a release +announcement. Again, I say: check log in `lbmk.git`. + +Hardware supported in Censored Libreboot c20230710 +================================================== + +All of the following are believed to *boot*, but if you have any issues, +please contact the Libreboot project. They are: + +Servers (AMD, x86) +------------------ + +- [ASUS KGPE-D16 motherboard](../docs/hardware/kgpe-d16.md) +- [ASUS KFSN4-DRE motherboard](../docs/hardware/kfsn4-dre.md) + +Desktops (AMD, Intel, x86) +----------------------- + +- [ASUS KCMA-D8 motherboard](../docs/hardware/kcma-d8.md) +- [Gigabyte GA-G41M-ES2L motherboard](../docs/hardware/ga-g41m-es2l.md) +- [Acer G43T-AM3](../docs/hardware/acer_g43t-am3.md) +- [Intel D510MO and D410PT motherboards](../docs/hardware/d510mo.md) +- [Apple iMac 5,2](../docs/hardware/imac52.md) + +### Laptops (Intel, x86) + +- **[Dell Latitude E6400](../docs/hardware/e6400.md) (easy to flash, no disassembly, similar + hardware to X200/T400)** +- ThinkPad X60 / X60S / X60 Tablet +- ThinkPad T60 (with Intel GPU) +- [Lenovo ThinkPad X200 / X200S / X200 Tablet](../docs/hardware/x200.md) +- Lenovo ThinkPad X301 +- [Lenovo ThinkPad R400](../docs/hardware/r400.md) +- [Lenovo ThinkPad T400 / T400S](../docs/hardware/t400.md) +- [Lenovo ThinkPad T500](../docs/hardware/t500.md) +- [Lenovo ThinkPad W500](../docs/hardware/t500.md) +- [Lenovo ThinkPad R500](../docs/hardware/r500.md) +- [Apple MacBook1,1 and MacBook2,1](../docs/hardware/macbook21.md) + +### Laptops (ARM, with U-Boot payload) + +- [ASUS Chromebook Flip C101 (gru-bob)](../docs/install/chromebooks.md) +- [Samsung Chromebook Plus (v1) (gru-kevin)](../docs/install/chromebooks.md) + +Downloads +========= + +You can find this release on the downloads page. At the time of this +announcement, some of the rsync mirrors may not have it yet, so please check +another one if your favourite one doesn't have it. + +This censored version is in the directory named `censored`, on Librbeoot rsync +and https mirrors. For example: + + + diff --git a/site/news/codeberg.md b/site/news/codeberg.md new file mode 100644 index 0000000..9eb08e1 --- /dev/null +++ b/site/news/codeberg.md @@ -0,0 +1,99 @@ +% Libreboot Git repositories now on Codeberg (RIP Notabug) +% Leah Rowe +% 8 April 2023 + +RIP Notabug +=========== + +Git repositories provided by Libreboot are still available via Notabug, but +the Notabug site has been quite unreliable for some time now. I notice it +mostly in the evenings, when more people are likely using it. Essentially, the +service is overloaded all the time and this results in regular HTTP 500 errors, +causing pull requests, git clone, issue reports and other things to go +offline at random times. + +I kept Libreboot on Notabug for as long as possible, because I hoped that the +admin (single) would fix issues, but I can't keep waiting. + +Libreboot was originally a member of the Peers Community, which hosts Notabug. +So I had an affinity for Notabug. + +Libreboot repos now hosted by Codeberg +-------------------------------------- + +I've decided to set up an account on Codeberg. You can find it here: + +* + +On this day, 8 April 2023, the following repositories are available via +Codeberg: + +* Build system: +* Website (markdown files): +* Images (av.libreboot.org): + +The `ich9utils` repository is now part of lbmk, +under `util/ich9utils`, so the ich9utils repository was not +needed on Codeberg (it still exists on Notabug). I'll add bucts +to Libreboot's lbmk repo too (under `util/bucts/`). + +Codeberg has nicer features +--------------------------- + +Codeberg runs on forgejo, itself a fork of Gitea, which *itself* is a fork +of Gogs. *Notabug* runs on an older, modified version of Gogs, which lacks a +lot of nicer features like issue search. + +Codeberg's forgejo instance has issue search, and it has a nice CI built in, +namely *woodpecker*. All of this and more could be useful to Libreboot, and +is being looked into. + +The interface is virtually identical to that of Notabug, since it's based +upon the same original codebase. Links on libreboot.org have been updated. +You can send issue reports and pull requests in much the same way as before, +but you will need to make a new account on codeberg.org if you don't already +have one. + +Notabug still available +----------------------- + +The notabug repositories are *still* available, and I'll still push new code +to them. I push to several repositories, not just codeberg/notabug, but those +are the ones that I openly advertise. + +Notabug is *usually* available, but it is often overloaded in the evenings, +so it's no longer viable for production use, but it's still viable as a backup. +If codeberg is ever down, at least you'd be able to download from Notabug. + +Why not self-host? +================== + +Forgejo, based on Gitea, is what runs on Codeberg. They host the project, on +behalf of the developers. Forgejo is working on federating the git forge, so +that mastodon-like features are available (pull requests, issues and such). + +Until federated collaboration is possible in Git (via the web), it's simply +not viable for a small project like Libreboot to provide a self-hosted +instance, because it would mean that people have to make an account on the +site *just* for Libreboot. This seems unreasonable as a request. Lots of +people are on codeberg, and already have accounts. + +Codeberg is run by a non-profit organisation that seems pretty solid, with +donations infrastructure too, so they'll probably always have the resources +to manage the service effectively. + +When federation becomes available, I assume Codeberg's forgejo instance will +become part of that, so it just makes practical sense for Libreboot to +use Codeberg. + +Why not sourcehut? +------------------ + +I considered sourcehut. I like the concept of it (mailing lists made easier, +email-based collaboration) but I don't think most people will want to use that. + +Forgejo provides a web-based interface in a style that most people are used to. + +Libreboot is *not* hosted on sourcehut, officially, in any capacity. + +That is all. diff --git a/site/news/e6400.md b/site/news/e6400.md new file mode 100644 index 0000000..b459142 --- /dev/null +++ b/site/news/e6400.md @@ -0,0 +1,75 @@ +% Dell Latitude E6400 added (blob-free, no disassembly) +% Leah Rowe +% 19 April 2023 + +NOTE: This pertains to the Intel GPU variant. Nvidia GPU variants are +unsupported, for this class of machine. + +Introduction +============ + +Today, Libreboot gained the Dell Latitude E6400 laptop port. This is a +blob-less port, courtesy of Nicholas Chin (`nic3-14159` on Libreboot IRC). +Nicholas has worked extensively on this port, for several years, and it's in +a ready state for entry to Libreboot. + +The hardware platform is GM45, similar to ThinkPad X200, T400 and so on that +Libreboot already supports. + +You can learn more on the E6400 [installation page](../docs/install/e6400.md) +and the [hardware info page](../docs/hardware/e6400.md). + +100% libre, blob-free +--------------------- + +This is a *blob-free* board in the boot flash. No Intel ME firmware needed, +and it boots without CPU microcode. + +*But wait.* There's more. A lot more of *them*, that is. + +Readily available on eBay etc, and cheap +----------------------------- + +Dells were much more popular than those ThinkPads, and more commonly used, +so there are still *several* of these available on sites like eBay. Enough to +keep people with an affinity for GM45 machines happy for a while longer (older +GM45 ThinkPad X200, T400 etc are very hard to find nowadays). + +This could very well replace X200, T400 etc, in terms of what certain people +want to use - nice enough screen/keyboard, and easy of installation just makes +this a very nice machine indeed. + +But wait.... It gets better: + +Software flashing possible! (no disassembly) +--------------------------- + +tl;dr Nicholas is a genius, but he spent time studying the board, finding that +the EC is hooked up to GPIO33 which allows for flash descriptor override. He +successfully reverse engineered a command that can be used to disable IFD +protections, and discovered that the SMM BIOS lock protection could be +bypassed, allowing installation of Libreboot. + +This is without needing to disassemble. No clip required. + +**That is to say, you can install Libreboot on this board without +taking it apart, and you can install it easily within 5 minutes.** + +This is done with the following utility from Nicholas Chin, which I merged +into lbmk: + + + +The original util, before Nicholas sent it to lbmk, is here (same util): + + + +It merges some code changes that I made myself, after Nicholas published it, +tidying up the code a bit (OpenBSD-like coding style adopted, for fun). See: + + + +Libreboot users should use the one in `util/` on Libreboot proper. + + +That is all! Read the manuals to know more about this machine. Thank you! diff --git a/site/news/e6400.uk.md b/site/news/e6400.uk.md new file mode 100644 index 0000000..30a0b97 --- /dev/null +++ b/site/news/e6400.uk.md @@ -0,0 +1,72 @@ +% Dell Latitude E6400 додано (вільна від блобів конфігурація) +% Лія Роу +% 19 квітня 2023 року + +Вступ +============ + +Сьогодні, Libreboot отримав порт ноутбука Dell Latitude E6400. Цей порт +є вільним від блобів, увічливість Ніколаса Чін (`nic3-14159` на Libreboot IRC). +Ніколас працював розгорнуто над цим портом, протягом декількох років, і він в +готовому стані для вступу до Libreboot. + +Платформа апаратного забезпечення GM45, схоже на ThinkPad X200, T400 і так далі, +що Libreboot вже підтримує. + +Ви можете вивчити більше на [сторінці встановлення](../docs/install/e6400.md) +E6400 та [сторінці інформації про апаратне забезпечення](../docs/hardware/e6400.md). + +вільна від блобів конфігурація +------------------------------ + +Це є *вільною від блобів* платою в завантажувальній флеш-пам'яті. Прошивка Intel ME +не потрібна, та [мікрокод може бути видалено, якщо ви бажаєте]. + +*Але почекайте.* Є більше. Набагато більше *цього*, так ось. + +Доступно на eBay і так далі, а також дешево +----------------------------- + +Dell були набагато більш популярні, ніж ті ThinkPad, та більш звичайно +використовувались, тому існує досі *багато* цих в доступності на сайтах, подібних +eBay. Достатньо, щоб тримати людей з симпатією до машин GM45 щасливими дещо довше +(старіші GM45 ThinkPad X200, T400 і так далі є дуже складними для пошуку в ці дні). + +Це могло би дуже добре замінити X200, T400 і так далі, стосовно того, що +деякі люди хочуть використовувати - досить добрий екран/клавіатура, та легке +встановлення просто робить це дуже доброю машиною звісно. + +Але почекайте.... Стає ще краще: + +Прошивка програмним забезпеченням можлива! (без розбору) +--------------------------- + +tl;dr Ніколас геній, але він витратив час, вивчаючи плату, шукаючи, що +EC з'єднана з GPIO33, що дозволяє пройти через flash descriptor. Він +успішно провів зворотню розробку команди, яка може бути використана для вимкнення +захистів, дозволяючи встановлення Libreboot. + +Це без потреби розбирати. Кліпса не потрібна. + +**Це означає, що ви можете встановити Libreboot на цій платі без +розбору на запчастини, і ви можете встановити його легко протягом 5 хвилин.** + +Це робиться з наступною утилітою від Ніколаса Чін, яку я злила +в lbmk: + + + +Оригінальна утиліта, перед тим, як Ніколас відправив її в lbmk, тут (та сама утиліта): + + + +Це поглинає деякі кодові зміни, які я зробила самостійно, після того, як Ніколас +опублікував її, наводячи порядок в коді трохи (OpenBSD-подібний стиль коду взято, +заради веселощів). Дивіться: + + + +Користувачам Libreboot варто використовувати той, що в `util/` на власне Libreboot. + + +Це все! Читайте керівництва, щоб дізнатись більше про цю машину. Дякую! diff --git a/site/news/fedfree.md b/site/news/fedfree.md new file mode 100644 index 0000000..a875385 --- /dev/null +++ b/site/news/fedfree.md @@ -0,0 +1,44 @@ +% How libreboot.org is hosted +% Leah Rowe +% 8 January 2023 + +I've recently started a new project, which I call the *Federation of Freedom*. +It is a website that teaches people how to self-host their own servers on the +internet, on all libre software. You could actually do it all on Libreboot +hardware. + +When I say recently, I mean it; Fedfree launched on 25 December 2022. Today +is 8 January 2023. Thus, Fedfree is just about two weeks old, on this day. + +**This is the website: [fedfree.org](https://fedfree.org/)** + +I'm basically starting out with it, documenting each part of libreboot.org in +terms of hosting, but it will later expand. On that first part, it's still not +complete; it lacks a mail server guide (libreboot.org has mail), rsync +guide (ditto) and cgit guide (ditto) - I'm planning to host +a [forgejo instance](https://forgejo.org/) for git, and that'll be yet +another guide for Fedfree. + +The guides it does currently have are: + +* [L2TP tunnel router, with redundant + routing](https://fedfree.org/docs/router/debian-l2tp-aaisp.html) +* [Nginx web server on Debian with LetsEncrypt HTTPS and + Certbot](https://fedfree.org/docs/http/debian-nginx.html) +* [BIND9 authoritative name + server](https://fedfree.org/docs/dns/debian-bind.html) + +The setups described in those guides is exactly how libreboot.org is hosted, +for the types of services described. + +Help is greatly appreciated, if people want to submit their own guides. The +basic premise behind it is this: hardware and software freedom are all well and +good, but most people with good ideas don't know how to do hosting, so they +default to using proprietary services like GitHub. I want to change that! + +Basically, I want every website on the internet to be hosted in someone's +living room. I'm only half-joking when I say that. That is literally how +libreboot.org was hosted, for many years; the setup is still self-hosted, but +it's not currently hosted in a *living room*. + +More information is available on the [Fedfree website](https://fedfree.org/) diff --git a/site/news/kgpe-d16.md b/site/news/kgpe-d16.md new file mode 100644 index 0000000..aad4de9 --- /dev/null +++ b/site/news/kgpe-d16.md @@ -0,0 +1,59 @@ +% ASUS KGPE-D16 hardware donation needed +% Leah Rowe +% 30 March 2023 + +**UPDATE: As of 25 April 2023, I've now ordered one myself. The issue was +finding one with a decent cooler, which is rare, but I found one. 2 CPUs, +some RAM, the cooler - and I'll get a case+PSU to put it in. Expect D16 in +the next Libreboot release. Expect it.** + +Please donate a D16 machine if you can +====================================== + +If someone can donate one to me, that would be a great service to the Libreboot +project. Preferably assembled, with CPU, cooler, working RAM (in coreboot), in +a case with PSU... throw in a graphics card if you can. + +ASUS KGPE-D16 support was removed from Libreboot a while ago, because I didn't +have enough testers to be confident in providing ROM images for it. + +I would like to re-add support for ASUS KGPE-D16 in a future Libreboot release, +but this time I'd like to be able to test it myself. + +I don't currently have a KGPE-D16 set up at my lab, because finding parts +and (especially) the coolers is a challenge, to say the least. + +If you would like to help, and have a machine to spare, please can you contact +me at my email address: [info@minifree.org](mailto:info@minifree.org) + +KCMA-D8 also needed +------------------- + +I'm also arranging for an assembled machine with KCMA-D8 in it to be sent to +me - though I'm not yet sure if that will go through, so if you have one of +those aswell, I'd be interested too. + +How I plan to re-add +==================== + +Dasharo produces updated coreboot images for KGPE-D16, with source code. They +took coreboot from release 4.11 and updated the code. I plan to add support in +lbmk (Libreboot's build system) for using other coreboot repositories besides +the official one, when downloading, patching and compiling for each board. + +In other words, I would integrate Dasharo's coreboot repository in Libreboot, +alongside the default one on coreboot.org. + +As far as I know, Dasharo does not yet work on KCMA-D8 (that was the case, +last time I checked), but I could inspect code differences between D8/D16 in +coreboot's branch `4.11_branch` and try to port those to Dasharo, to then put +in Libreboot. + +Failing that (for KCMA-D8), I would just use `4.11_branch` from coreboot. +D8/D16 support was dropped in coreboot after release 4.11, but updated code +mostly fixing compiler issues and such, is available in a branch off +of 4.11 called `4.11_branch`. + +When Libreboot dropped support for D8/D16, it wasn't using `4.11_branch`. +Instead, it was using the normal 4.11 tag in coreboot.git, with some extra +patches on top provided by Libreboot. diff --git a/site/news/libreboot20131212.md b/site/news/libreboot20131212.md new file mode 100644 index 0000000..e27ac54 --- /dev/null +++ b/site/news/libreboot20131212.md @@ -0,0 +1,20 @@ +% Libreboot 20131212 +% Leah Rowe +% 12 December 2013 + +r20131212 (1st release) {#release20131212} +======================= + +- 12th December 2013 + +Supported: +---------- + +- ThinkPad X60 +- ThinkPad X60s + +Development notes +----------------- + +- initial release +- source code deblobbed diff --git a/site/news/libreboot20131213.md b/site/news/libreboot20131213.md new file mode 100644 index 0000000..6cfa6d3 --- /dev/null +++ b/site/news/libreboot20131213.md @@ -0,0 +1,23 @@ +% Libreboot 20131213 +% Leah Rowe +% 13 December 2013 + +r20131213 (2nd release) {#release20131213} +======================= + +- 13th December 2013 + +Supported: +---------- + +- ThinkPad X60 +- ThinkPad X60s + +Development notes +----------------- + +- added background image to GRUB2 +- added memtest86+ payload to grub2 +- improvements to the documentation +- new grub.cfg + diff --git a/site/news/libreboot20131214.md b/site/news/libreboot20131214.md new file mode 100644 index 0000000..826ff4e --- /dev/null +++ b/site/news/libreboot20131214.md @@ -0,0 +1,21 @@ +% Libreboot 20131214 release +% Leah Rowe +% 14 December 2013 + +r20131214 (3rd release) {#release20131214} +======================= + +- 14th December 2013 + +Supported: +---------- + +- ThinkPad X60 +- ThinkPad X60s + +Development notes +----------------- + +- Added SeaBIOS payload to GRUB2 (for booting USB drives) +- new grub.cfg + diff --git a/site/news/libreboot20140221.md b/site/news/libreboot20140221.md new file mode 100644 index 0000000..48c5c9e --- /dev/null +++ b/site/news/libreboot20140221.md @@ -0,0 +1,36 @@ +% Libreboot 20140221 release +% Leah Rowe +% 21 February 2014 + +Release 20140221 (4th release) {#release20140221} +============================== + +- 21st February 2014 + +Officially supported +-------------------- + +- ThinkPad X60 +- ThinkPad X60s + +Development notes +----------------- + +- Removed SeaBIOS (redundant) +- New GRUB version (2.02\~beta2) + - Fixes some USB issues + - Includes ISOLINUX/SYSLINUX parser +- New grub.cfg +- Removed useless options: + - options for booting sda 2/3/4 + - seabios boot option +- Added new menu entries: + - Parse ISOLINUX config (USB) + - Parse ISOLINUX config (CD) + - Added 'cat' module for use on GRUB command line. +- "set pager=1" is set in grub.cfg, for less-like functionality + +The "Parse" options read ./isolinux/isolinux.cfg on a CD or USB, and +automatically converts it to a grub config and switches to the boot menu +of that distro. This makes booting ISOs \*much\* easier than before. + diff --git a/site/news/libreboot20140309.md b/site/news/libreboot20140309.md new file mode 100644 index 0000000..03e96bb --- /dev/null +++ b/site/news/libreboot20140309.md @@ -0,0 +1,41 @@ +% Libreboot 20140309 release +% Leah Rowe +% 9 March 2014 + +Revision notes (9th March 2014): +-------------------------------- + +- recreated coreboot config from scratch +- GRUB loads even faster now (less than 2 seconds). +- Total boot time reduced by further \~5 seconds. +- Added crypto and cryptodisk modules to GRUB +- cbfstool now included in the binary archives + +Development notes +----------------- + +- Binary archive now have 2 images: + - With serial output enabled and memtest86+ included (debug level + 8 in coreboot) + - With serial output disabled and memtest86+ excluded (faster boot + speeds) (debugging disabled) +- Reduced impact on battery life: + - 'processor.max\_cstate=2' instead of 'idle=halt' for booting + default kernel +- coreboot.rom (faster boot speeds, debugging disabled): + - Disabled coreboot serial output (Console-> in "make + menuconfig") + - Set coreboot debug level to 0 instead of 8 (Console-> in + "make menuconfig") + - Changed GRUB timeout to 1 second instead of 2 (in grub.cfg + - Removed background image in GRUB. + - Removed memtest86+ payload (since it relies on serial output) +- coreboot\_serial.rom (slower boot speeds, debugging enabled): + - Boot time still reduced, but only by \~2 seconds + - has the memtest86+ payload included in the ROM + - has serial port enabled. How this is achieved (from + X60\_source): Turn on debugging level to 8, and enable serial + output +- (in Console-> in coreboot "make menuconfig") +- (and build with grub\_serial.cfg and grub\_memdisk\_serial.cfg) + diff --git a/site/news/libreboot20140605.md b/site/news/libreboot20140605.md new file mode 100644 index 0000000..fe60d4b --- /dev/null +++ b/site/news/libreboot20140605.md @@ -0,0 +1,10 @@ +% Libreboot 20140605 release +% Leah Rowe +% 5 June 2014 + +Revision notes (5th June 2014): +------------------------------- + +- added backlight support (Fn+Home and Fn+End) on X60 +- fixed broken/unstable 3D when using kernel 3.12 or higher +- (see 'BACKPORT' file) diff --git a/site/news/libreboot20140611.md b/site/news/libreboot20140611.md new file mode 100644 index 0000000..9adbdd2 --- /dev/null +++ b/site/news/libreboot20140611.md @@ -0,0 +1,10 @@ +% Libreboot 20140611 release +% Leah Rowe +% 11 June 2014 + +Revision notes (11th June 2014): +-------------------------------- + +- removed 'CD' boot option from coreboot.rom (not needed) +- removed 'processor.max\_cstate=2' and 'idle=halt' options (see + README.powertop file) diff --git a/site/news/libreboot20140622.md b/site/news/libreboot20140622.md new file mode 100644 index 0000000..df37946 --- /dev/null +++ b/site/news/libreboot20140622.md @@ -0,0 +1,67 @@ +% Libreboot 20140622 release +% Leah Rowe +% 22 June 2014 + +Release 20140622 (5th release) +============================== + +- 7th March 2014 +- revised 22nd June 2014 + +Officially supported +-------------------- + +- ThinkPad X60 +- ThinkPad X60s + +Revision (22nd June 2014 - extra) +--------------------------------- + +- Documentation: added X60 Unbricking tutorial +- Documentation: added info about enabling or disabling wifi +- Documentation: added info about enabling or disabling trackpoint + +Revision (22nd June 2014 - extra) +--------------------------------- + +- Documentation: Improved the instructions for using flashrom +- Documentation: Improved the instructions for using cbfstool (to + change the default GRUB menu) +- Documentation: Numerous small fixes. + +Revision notes (22nd June 2014) +------------------------------- + +- updated GRUB (git 4b8b9135f1676924a8458da528d264bbc7bbb301, 20th + April 2014) +- Made "DeJavu Sans Mono" the default font in GRUB (fixes border + corruption). +- added 6 more images: + - coreboot\_ukqwerty.rom (UK Qwerty keyboard layout in GRUB) + - coreboot\_serial\_ukqwerty.rom (UK Qwerty keyboard layout in + GRUB) + - coreboot\_dvorak.rom (US Dvorak keyboard layout in GRUB) + - coreboot\_serial\_dvorak.rom (US Dvorak keyboard layout in GRUB) + - coreboot\_ukdvorak.rom (UK Dvorak keyboard layout in GRUB) + - coreboot\_serial\_ukdvorak.rom (UK Dvorak keyboard layout in + GRUB) + - (coreboot.rom and coreboot\_serial.rom have US Qwerty keyboard + layout in GRUB, as usual) +- improved the documentation: + - removed FLASH\_INSTRUCTION and README.powertop and merged them + with README + - removed obsolete info from README and tidied it up + - deleted README (replaced with docs/) +- tidied up the menu entries in GRUB +- tidied up the root directory of X60\_source/, sorted more files into + subdirectories +- improved the commenting inside the 'build' script (should make + modifying it easier) +- Renamed X60\_binary.tar.gz and X60\_source.tar.gz to + libreboot\_bin.tar.gz and libreboot\_src.tar.gz, respectively. +- Replaced GRUB version with "FREE AS IN FREEDOM" on the GRUB start screen. +- Added sha512.txt files in libreboot\_src and libreboot\_bin. (inside + the archives) +- Added libreboot\_bin.tar.gz.sha512.txt and + libreboot\_src.tar.gz.sha512.txt files (outside of the archives) + diff --git a/site/news/libreboot20140711.md b/site/news/libreboot20140711.md new file mode 100644 index 0000000..1146b91 --- /dev/null +++ b/site/news/libreboot20140711.md @@ -0,0 +1,229 @@ +% Libreboot 20140711 release +% Leah Rowe +% 11 July 2014 + +Revisions for r20140711 (1st beta) (11th July 2014) +--------------------------------------------------- + +- Initial release (new coreboot base, dated 1st June 2014. See + 'getcb' script for reference) +- DEBLOBBED coreboot +- Removed the part from memtest86+ 'make' where it tried to connect + to some scp server while compiling. (commented out line 24 in the + Makefile) +- X60 now uses a single .config (for coreboot) +- X60 now uses a single grub.cfg (for grub memdisk) +- X60 now uses a single grub.elf (payload) +- Added new native graphics code for X60 (replaces the old 'replay' + code) from Vladimir Serbinenko: 5320/9 from review.coreboot.org +- T60 is now supported, with native graphics. (5345/4 from + review.coreboot.org, cherry-picked on top of 5320/9 checkout) +- Added macbook2,1 support (from Mono Moosbart and Vladimir + Serbinenko) from review.coreboot.org (see 'getcb' script to know + how that was done) + - Documentation: added information linking to correct page and + talking about which models are supported. + - Added resources/libreboot/config/macbook21config + - macbook21: Added 'build-macbook21' script and linked to it in + 'build' (ROMs included under bin/macbook21/) + - macbook21: Removed dd instructions from build-macbook21 script + (macbook21 does not need bucts when flashing libreboot while + Apple EFI firmware is running) + - Documentation: Added macbook21 ROMs to the list of ROMs in + docs/\#rom + - Documentation: Write documentation linking to Mono Moosbart's + macbook21 and parabola page (and include a copy) +- Documentation: added a copy of Mono's Parabola install guide (for + macbook21 with Apple EFI firmware) and linked in in main index. +- Documentation: added a copy of Mono's Coreboot page (for macbook21) + and linked it in main index. +- T60: Copy CD option from the grub.cfg files for T60 \*serial\*.rom + images into the grub configs for non-serial images. (T60 laptops have + CD/DVD drive on main laptop) +- macbook21: remove options in build-macbook21 for \*serial\*.rom + (there is no dock or serial port available for macbook21) +- Added patches for backlight controls on X60 and T60 with help from + Denis Carikli (see ./resources/libreboot/patch/gitdiff and ./getcb + and docs/i945\_backlight.md) + - Documentation: added docs/i945\_backlight.html showing how + backlight controls were made to work on X60/T60 +- Documentation: Added info about getting LCD panel name based on EDID + data. + - Documentation: Added a link to this from the list of supported + T60 laptopss and LCD panels for T60 (so that the user can check + what LCD panel they have). +- X60/T60: Merged patches for 3D fix (from Paul Menzel) when using + kernel 3.12 or higher (see ./resources/libreboot/patch/gitdiff and + ./getcb) + - based on 5927/11 and 5932/5 from review.coreboot.org +- Improved thinkpad\_acpi support (from coreboot ): xsensors shows + more information. + - From 4650/29 in review.coreboot.org (merged in coreboot + 'master' on June 1st 2014) +- Merged changes for digitizer (X60 Tablet) and IR (X60 and T60) based + on 5243/17, 5242/17 and 5239/19 from review.coreboot.org + - (see ./resources/libreboot/patch/gitdiff and ./getcb) +- Documentation: added information about building flashrom using + 'builddeps-flashrom' script. +- Re-created resources/libreboot/config/x60config +- Re-created resources/libreboot/config/t60config +- Added 'x60tconfig' in resources/libreboot/config (because X60 + Tablet has different information about serial/model/version in + 'dmidecode') + - Added 'build-x60t' script + - Updated 'build' script to use 'build-x60t' + - Documentation: added to \#config section the section + \#config\_x60t (libreboot configuration and dmidecode info) + - Documentation: added x60t ROMs to the list of ROMs +- Tidied up the 'builddeps' script (easier to read) +- Tidied up the 'cleandeps' script (easier to read) +- Annotated the 'buildall' script +- Added 'getcb' script for getting coreboot revision used from git, + and patching it. +- Added 'getgrub' script for getting the GRUB revision used from + git, and patching it. +- Added 'getmt86' script for getting the memtest86+ version used, + and patching it. +- Added 'getbucts' script for getting the bucts version used. +- Added 'getflashrom' script for getting the flashrom version used, + and patching it +- Added 'getall' script which runs all of the other 'get' scripts. +- Add instructions to the 'build' script to prepare + libreboot\_meta.tar.gz + - New archive: libreboot\_meta.tar.gz - minimal archive, using the + 'get' scripts to download all the dependencies (coreboot, + memtest, grub and so on). +- Documentation: added information about where 'build' script + prepares the libreboot\_meta.tar.gz archive. +- Documentation: added information about how to use the 'get' + scripts in libreboot\_meta.tar.gz (to generate + libreboot\_src.tar.gz) + - Documentation: mention that meta doesn't create libreboot\_src/ + directory, but that libreboot\_meta itself becomes the same. + - Documentation: advise to rename libreboot\_meta to + libreboot\_src after running 'getall'. +- Annotated the 'builddeb' script, to say what each set of + dependencies are for. +- Separated bucts/flashrom builddeb sections into separate scripts: + builddeb-flashrom, builddeb-bucts. +- Documentation: Updated relevant parts based on the above. +- Added instructions to 'build' script for including builddeb-bucts + and builddeb-flashrom in libreboot\_bin +- Updated flashrom checkout (r1822 2014-06-16) from SVN + (http://flashrom.org/Downloads). + - Updated flashing instructions in docs/ for new commands needed + (Macronix chip on X60/T60) + - For X60/T60 (flashrom): Patched + flashchips.c\_lenovobios\_macronix and + flashchips.c\_lenovobios\_sst executables for SST/macronix + (included in resources/flashrom/patch) + - Updated builddeps to build flashrom\_lenovobios\_sst and + flashrom\_lenovobios\_macronix, for X60/T60 users with Lenovo + BIOS + - moved the flashrom build instructions from 'builddeps' and put + them in 'builddeps-flashrom', excecuting that from + 'builddeps'. + - Added builddeps-flashrom to libreboot\_bin.tar.gz +- flashrom: added patched flashchips.c to resources/flashrom/patch + (automatically use correct macronix chip on libreboot, without using + '-c' switch) + - removed 'MX25L1605' and 'MX25L1605A/MX25L1606E' entries in + flashchips.c for the patched version of flashchips.c + - added instructions to 'builddeps-flashrom' to automatically + use this modified flashchips.c in the default build +- Added builddeb to libreboot\_bin.tar.gz +- Moved 'bucts' build instructions from builddeps to builddeps-bucts + - builddeps now runs 'builddeps-bucts' instead + - Added 'builddeps-bucts' to libreboot\_bin.tar.gz + - Documentation: Added information about using 'builddep-bucts' + to build the BUC.TS utility. +- Added 'lenovobios\_firstflash' and 'lenovobios\_secondflash' + scripts + - Added instructions to 'build' script for including those files + in libreboot\_bin + - Documentation: Add tutorial for flashing while Lenovo BIOS is + running (on X60/T60) +- Added 'flash' script (make sure to run builddeps-flashrom first) + which (while libreboot is already running) can use flashrom to flash + a ROM + - eg: "sudo ./flash bin/x60/coreboot\_serial\_ukdvorak.rom" + equivalent to "sudo ./flashrom/flashrom -p internal -w + bin/x60/coreboot\_uk\_dvorak.rom" + - updated 'build' script to include the 'flash' script in + libreboot\_bin.tar.gz +- Documentation: replaced default flashrom tutorial to recommend the + 'flash' script instead. +- Re-add cbfstool source code back into libreboot\_bin.tar.gz, as + cbfstool\_standalone + - Patched that version to work (able to be built and used) without + requiring the entire coreboot source code. + - Created patched version of the relevant source files and added + it into resources/cbfstool/patch + - see coreboot/util/cbfstool/rmodule.c and then the patched + version in resources/cbfstool/patch/rmodule.c + - see coreboot/src/include/rmodule-defs.h and the rule in + 'build' for including this in + ../libreboot\_bin/cbfstool\_standalone + - Added instructions to 'build' script for applying this patch + to the cbfstool\_standalone source in libreboot\_bin + - Added instructions to 'build' script for then re-compiling + cbfstool\_standalone in libreboot\_bin after applying the patch + - Added a 'builddeps-cbfstool' script (in src, but only used in + bin and put in bin by 'build') that compiles + cbfstool\_standalone in libreboot\_bin (make), moves the + cbfstool and rmodtool binaries into libreboot\_bin/ and then + does 'make clean' in libreboot\_bin/cbfstool\_standalone + - Updated the 'build' script to put 'builddeps-cbfstool' in + libreboot\_bin + - Updated the 'build' script in the cbfstool (standalone) part + to accomodate the above. + - Documentation: added notes about cbfstool (standalone) in + libreboot\_bin +- Documentation: made docs/linux/grub\_cbfs.html slightly easier to + follow. +- Annotate the 'build\*' scripts with 'echo' commands, to help the + user understand what it actually happening during the build process. +- Documentation: added information about how 'dmidecode' data was + put in the coreboot configs + - Documentation: In fact, document how the 'config' files in + resources/libreboot/config/ were created +- Documentation: Added information about which ThinkPad T60 laptops are + supported, and which are not. +- Documentation: added information about LCD inverters (for upgrading + the LCD panel on a T60 14.1' XGA or 15.1' XGA) + - it's FRU P/N 41W1478 (on T60 14.1") so this was added to the + docs. + - it's P/N 42T0078 FRU 42T0079 or P/N 41W1338 (on T60 15.1") so + this was added to the docs. +- Documentation: added information about names of LCD panels for T60 + to the relevant parts of the documentation. +- Documentation: added information (with pictures) about the + differences between T60 with Intel GPU and T60 with ATI GPU. +- Documentation: added pictures of keyboard layouts (US/UK + Qwerty/Dvorak) to the ROM list, to let the user compare with their + own keyboard. +- Move the coreboot build instructions in 'builddeps' into + 'builddeps-coreboot' and link it in 'builddeps' + - Link to 'builddeps-coreboot' in final stage of 'getcb' +- Move GRUB build instructions from 'builddeps' into + 'builddeps-grub', link from 'builddeps' + - Link to 'builddeps-grub' in final stage of 'getgrub' +- Move MemTest86+ build instructions from 'builddeps' into + 'builddeps-memtest86', link from 'builddeps' + - Link to 'builddeps-memtest86' in final stage of 'getmt86' +- made 'build' script put resources/ directory in libreboot\_bin, to + make builddeps-flashrom work in libreboot\_bin +- Removed instructions for building source code in the 'get' script + (they don't really belong there) +- Added libfuse-dev and liblzma-dev to the list of GRUB dependencies + in 'builddeb' script. +- Converted the 'RELEASE' file to 'docs/RELEASE.html' +- Added those dependencies to builddeb script (for GRUB part): gawk + libdevmapper-dev libtool libfreetype6-dev +- Added to build script the instruction at the end to create a + sha512sum.txt with a file manifest plus checksums. +- Deleted the RELEASE and BACKPORT files (no longer needed) +- Documentation: added information about X60/T60 dock (ultrabase x6 + and advanced mini dock) to relevant sections. + - Added to docs/\#serial + diff --git a/site/news/libreboot20140716.md b/site/news/libreboot20140716.md new file mode 100644 index 0000000..6d8575a --- /dev/null +++ b/site/news/libreboot20140716.md @@ -0,0 +1,11 @@ +% Libreboot 20140716 release +% Leah Rowe +% 16 July 2014 + +Revisions for r20140716 (2nd beta) (16th July 2014) +--------------------------------------------------- + +- Deleted all git-related files from the coreboot directory. This was + necessary because with those it is possible to run 'git diff' + which shows the changes made in the form of a patch (diff format); + this includes the blobs that were deleted during deblobbing. diff --git a/site/news/libreboot20140720.md b/site/news/libreboot20140720.md new file mode 100644 index 0000000..7f603e8 --- /dev/null +++ b/site/news/libreboot20140720.md @@ -0,0 +1,53 @@ +% Libreboot 20140720 release +% Leah Rowe +% 20 July 2014 + +Revisions for r20140720 (3rd beta) (20th July 2014) +--------------------------------------------------- + +- Fixed typo that existed in 2nd beta where the release date of the + 2nd beta was listed as being in year 2016, when in actual fact it + was 2014. +- Documentation: added (preliminary) details about (rare) buggy CPUs + on the ThinkPad T60 that were found to fail (instability, kernel + panics, etc) without the microcode updates. +- Documentation: added docs/hardware/x60\_heatsink.html for showing + how to change the heatsink on the Thinkpad X60 +- Added ROM images for Azerty (French) keyboard layout in GRUB + (courtesy of Olivier Mondoloni) +- Tidied up some scripts: + - ~~Re-factored those scripts (made easier to read/maintain): + build-x60, build-x60t, build-t60, build-macbook21~~ + - ~~Reduced the number of grub configs to 2 (or 1, for macbook21), + the build scripts now generate the other configs at build + time.~~ + - Deleted build-x60, build-x60t, build-t60, build-macbook21 and + replaced with intelligent (generic) buildrom-withgrub script + - Updated build to use buildrom-withgrub script for building the + ROM images. + - coreboot.rom and coreboot\_serial.rom renamed to + coreboot\_usqwerty.rom and coreboot\_serial\_usqwerty.rom + - coreboot\_dvorak and coreboot\_serial\_dvorak.rom renamed to + coreboot\_usdvorak.rom and coreboot\_serial\_usdvorak.rom + - Renamed coreboot\*rom to libreboot\*rom + - Made flash, lenovobios\_firstflash and lenovobios\_secondflash + scripts fail if the specified file does not exist. + - Updated all relevant parts of the documentation to reflect the + above. +- Replaced background.png with background.jpg. added gnulove.jpg. + (resources/grub/background/) +- Updated buildrom-withgrub to use background.jpg instead of + background.png +- Updated buildrom-withgrub to use gnulove.jpg aswell +- Updated resources/grub/config/macbook21/grub\*cfg to use gnulove.jpg + background. +- Updated resources/grub/config/{x60,t60,x60t}/grub\*cfg to use + background.jpg background. +- Documentation: updated docs/\#grub\_custom\_keyboard to be more + generally useful. +- nvramtool: + - Updated builddeps-coreboot script to build it + - Updated build script to include it in libreboot\_bin +- Documentation: added docs/security/x60\_security.html (security + hardening for X60) + diff --git a/site/news/libreboot20140729.md b/site/news/libreboot20140729.md new file mode 100644 index 0000000..8c31ebc --- /dev/null +++ b/site/news/libreboot20140729.md @@ -0,0 +1,30 @@ +% Libreboot 20140729 release +% Leah Rowe +% 29 July 2014 + +Revisions for r20140729 (4th beta) (29th July 2014) +--------------------------------------------------- + +- Documentation: improved (more explanations, background info) in + docs/security/x60\_security.html (courtesy of Denis Carikli) +- MacBook2,1 tested (confirmed) +- macbook21: Added script 'macbook21\_firstflash' for flashing + libreboot while Apple EFI firmware is running. +- Documentation: macbook21: added software-based flashing instructions + for flashing libreboot while Apple EFI firmware is running. +- Reduced size of libreboot\_src.tar.gz: + - Removed .git and .gitignore from grub directory + (libreboot\_src); not needed. Removing them reduces the size of + the archive (by a lot). GRUB development should be upstream. + - Removed .git and .gitignore from bucts directory + (libreboot\_src); not needed. Removing them reduces the size of + the archive. bucts development should be upstream. + - Removed .svn from flashrom directory (libreboot\_src); not + needed. Removing it reduces the size of the archive. flashrom + development should be upstream. +- Added ROMs with Qwerty (Italian) layout in GRUB + (libreboot\*itqwerty.rom) +- Added resources/utilities/i945gpu/intel-regs.py for debugging issues + related to LCD panel compatibility on X60 Tablet and T60. (courtesy + of [Michał Masłowski](http://mtjm.eu)) + diff --git a/site/news/libreboot20140811.md b/site/news/libreboot20140811.md new file mode 100644 index 0000000..6ff3814 --- /dev/null +++ b/site/news/libreboot20140811.md @@ -0,0 +1,55 @@ +% Libreboot 20140811 release +% Leah Rowe +% 11 August 2014 + +Corrections to r20140811 (5th beta) (11th August 2014) +------------------------------------------------------ + +- Fixed typo where revision list for 5th beta was listed as March 11th + 2014, when in fact it was August 11th 2014 +- Fixed incorrect grub.cfg that was actually placed in + resources/grub/config/x60/grub\_usqwerty.cfg which broke the default + GRUB menu entry on X60 + +Revisions for r20140811 (5th beta) (11th August 2014) +----------------------------------------------------- + +- build: added 'luks', 'lvm', 'cmosdump' and 'cmostest' to the + list of modules for grub.elf +- Documentation: added pics showing T60 unbricking (still need to + write a tutorial) +- build: include cmos.layout + (coreboot/src/mainboard/manufacturer/model/cmos.layout) files in + libreboot\_bin +- Documentation: added **install/x60tablet\_unbrick.html** +- Documentation: added **install/t60\_unbrick.html** +- Documentation: added **install/t60\_lcd\_15.html** +- Documentation: added **install/t60\_security.html** +- Documentation: added **install/t60\_heatsink.html** +- Documentation: Renamed RELEASE.html to release.html +- Documentation: removed pcmcia reference in x60\_security.html (it's + cardbus) +- Documentation: added preliminary information about randomized seal + (for physical intrusion detection) in x60\_security.html and + t60\_security.html +- Documentation: added preliminary information about + preventing/mitigating cold-boot attack in x60\_security.html and + t60\_security.html +- Documentation: added info to \#macbook21 warning about issues with + macbook21 +- Documentation: X60/T60: added information about checking custom ROMs + using dd to see whether or not the top 64K region is duplicated + below top or not. Advise caution about this in the tutorial that + deals with flashing on top of Lenovo BIOS, citing the correct dd + commands necessary if it is confirmed that the ROM has not been + applied with dd yet. (in the case that the user compiled their own + ROMs from libreboot, without using the build scripts, or if they + forgot to use dd, etc). +- Split resources/libreboot/patch/gitdiff into separate patch files + (getcb script updated to accomodate this change). +- Re-added .git files to bucts +- Fixed the oversight where macbook21\_firstflash wasn't included in + binary archives +- Release archives are now compressed using .tar.xz for better + compression + diff --git a/site/news/libreboot20140903.md b/site/news/libreboot20140903.md new file mode 100644 index 0000000..7244a94 --- /dev/null +++ b/site/news/libreboot20140903.md @@ -0,0 +1,149 @@ +% Libreboot 20140903 release +% Leah Rowe +% 3 September 2014 + +Revisions for r20140903 (6th beta) (3rd September 2014) +------------------------------------------------------- + +- Added modified builddeb\* scripts for Arch-based distros: + buildpac, buildpac-flashrom, buildpac-bucts (courtesy of Noah + Vesely) +- Documentation: updated all relevant areas to mention use of + buildpac\* scripts for Parabola users. +- Documentation: added information showing how to enable or disable + bluetooth on the X60 +- MacBook1,1 tested! See **hardware/\#macbook11** +- Documentation: fixed typo in \#get\_edid\_panelname (get-edit + changed to get-edid) +- Documentation: added images/x60\_lcd\_change/ (pics only for now) +- Added gcry\_serpent and gcry\_whirlpool to the GRUB module list in + the 'build' script (for luks users) +- **Libreboot is now based on a new coreboot version from August 23rd, + 2014:\ + Merged commits (relates to boards that were already supported in + libreboot):** + - + - (merged already) + - (merged already) + - (merged already) + - (merged already) + - ** (merged already)** + - (merged already) + - (merged already) + - (merged already) + (text-mode patch, might enable memtest. macbook21) + - (MERGED) (remove useless + ps/2 keyboard delay from macbook21. already merged) +- These were also merged in coreboot (relates to boards that libreboot + already supported): + - (merged) + - (merged) + - (merged) + - (merged) + - (merged) + - (merged) +- Documentation: removed the section about tft\_brightness on X60 (new + code makes it obsolete) +- Removed all patches from resources/libreboot/patch/ and added new + patch: 0000\_t60\_textmode.git.diff +- Updated getcb script and DEBLOB script. +- Updated configuration files under resources/libreboot/config/ to + accomodate new coreboot version. +- Removed grub\_serial\*.cfg and libreboot\_serial\*.rom, all + configs/rom files are now unified (containing same configuration as + serial rom files from before). + - Documentation: updated \#rom to reflect the above. +- Updated GRUB to new version from August 14th, 2014. +- Unified all grub configurations for all systems to a single grub.cfg + under resources/grub/config/ +- Updated flashrom to new version from August 20th, 2014 +- Added getseabios and builddeps-seabios (builddeps and getall were + also updated) + - Added instructions to 'buildrom-withgrub' to include + bios.bin.elf and vgaroms/vgabios.bin from SeaBIOS inside the + ROM. +- Added seabios (and sgavgabios) to grub as payload option in menu +- Disabled serial output in Memtest86+ (no longer needed) to speed up + tests. + - MemTest86+ now works properly, it can output on the laptop + screen (no serial port needed anymore). +- Added getgrubinvaders, builddeps-grubinvaders scripts. Added these + to getall and builddeps. + - Added [GRUB Invaders](http://www.coreboot.org/GRUB_invaders) + menu entry in resources/grub/config/grub.cfg +- Added rules to builddeps-coreboot to build libpayload with + TinyCurses. (added appropriate instructions to cleandeps script). +- Commented out lines in resources/grub/config/grub.cfg for loading + font/background (not useful anymore, now that GRUB is in text-mode). +- Commented out lines in buildrom-withgrub that included + backgrounds/fonts (not useful anymore, now that GRUB is in + text-mode). +- Added resources/utilities/i945-pwm/ (from + git://git.mtjm.eu/i945-pwm), for debugging acpi brightness on i945 + systems. + - Added instructions for it in builddeps, builddeps-i945pwm, + builddeb and cleandeps +- 'build' script: removed the parts that generated sha512sum + manifests (not needed, since release tarballs are GPG-signed) +- 'build' script: removed the parts that generated libreboot\_meta + directory (not needed anymore, since \_meta will be hosted in git) + - Updated \#build\_meta (and other parts of documentation) to + accomodate this change. +- Documentation: simplified (refactored) the notes in \#rom +- 'build' script: removed the parts that generated libreboot\_bin + and added them to a new script: 'build-release' + - Documentation: \#build updated to reflect the above. +- ~~Added all gcry\_\* modules to grub (luks/cryptomount): + gcry\_arcfour gcry\_camellia gcry\_crc gcry\_dsa gcry\_md4 + gcry\_rfc2268 gcry\_rmd160 gcry\_seed gcry\_sha1 gcry\_sha512 + gcry\_twofish gcry\_blowfish gcry\_cast5 gcry\_des gcry\_idea + gcry\_md5 gcry\_rijndael gcry\_rsa gcry\_serpent gcry\_sha256 + gcry\_tiger gcry\_whirlpool~~ +- Added GNUtoo's list of GRUB modules (includes all of the gcry\_\* + modules above), cryptomount should be working now. +- Removed builddeb-bucts and builddeb-flashrom, merged them with + builddeb ( updated accordingly) +- Removed buildpac-bucts and buildpac-flashrom, merged them with + buildpac ( updated accordingly) +- Renamed buildpac to deps-parabola ( updated accordingly) +- Documentation: removed all parts talking about build dependencies, + replaced them with links to \#build\_dependencies +- Documentation: emphasized more strongly on the documentation, the + need to re-build bucts and/or flashrom before flashing a ROM image. +- build-release: flashrom, nvramtool, cbfstool and bucts are no longer + provided pre-compiled in binary archives, and are now in source form + only. (to maximize distro compatibility). +- 'build' script: replaced grub.elf assembly instructons, it is now + handled by a utility added under resources/utilities/grub-assemble +- Moved resources/grub/keymap to + resources/utilities/grub-assemble/keymap, and updated that utility + to use it +- Documentation: removed useless links to pictures of keyboard layouts + and unmodified layouts. +- Removed all unused fonts from dejavu-fonts-ttf-2.34/ directory +- 'buildrom-withgrub' script: updated it to create 2 sets of ROMs + for each system: one with text-mode, one with coreboot framebuffer. +- Documentation: updated \#rom to reflect the above +- Deleted unused README and COPYING file from main directory +- Removed some rm -Rf .git\* instructions from the get\* scripts and + moved them to build-release script +- Split up default grub.cfg into 6 parts: + extra/{common.cfg,txtmode.cfg,vesafb.cfg} and + menuentries/{common.cfg,txtmode.cfg,vesafb.cfg} + - buildrom-withgrub script uses these to generate the correct + grub.cfg for each type of configuration. +- grub\_memdisk.cfg (used inside grub.elf) now only loads grub.cfg + from cbfs. It no longer enables serial output or sets prefix. + (menuentries/common.cfg does instead) +- resources/grub/config/extra/common.cfg, added: + - insmod instructions to load those modules: nativedisk, ehci, + ohci, uhci, usb, usbserial\_pl2303, usbserial\_ftdi, + usbserial\_usbdebug + - set prefix=(memdisk)/boot/grub + - For native graphics (recommended by coreboot wiki):\ + gfxpayload=keep\ + terminal\_output \--append gfxterm + - Play a beep on startup:\ + play 480 440 1 +- Documentation: updated linux/grub\_cbfs.html to make it safer + (and easier) to follow. diff --git a/site/news/libreboot20140911.md b/site/news/libreboot20140911.md new file mode 100644 index 0000000..496d8ad --- /dev/null +++ b/site/news/libreboot20140911.md @@ -0,0 +1,72 @@ +% Libreboot 20140911 release +% Leah Rowe +% 11 September 2014 + +6th release (pre-release, 7th beta) +=================================== + +- Released 11th July 2014 (pre-release) 1st beta +- Revised (pre-release, 2nd beta) 16th July 2014 +- Revised (pre-release, 3rd beta) 20th July 2014 +- Revised (pre-release, 4th beta) 29th July 2014 +- Revised (pre-release, 5th beta) 11th August 2014 (corrected 11th + August 2014) +- Revised (pre-release, 6th beta) 3rd September 2014 +- Revised (pre-release, 7th beta) 11th September 2014 + +Machines still supported (compared to previous release): +-------------------------------------------------------- + +- **Lenovo ThinkPad X60/X60s** + - You can also remove the motherboard from an X61/X61s and replace + it with an X60/X60s motherboard. + +New systems supported in this release: +-------------------------------------- + +- **Lenovo ThinkPad X60 Tablet** (1024x768 and 1400x1050) with + digitizer support + - See **hardware/\#supported\_x60t\_list** for list of supported LCD + panels + - It is unknown whether an X61 Tablet can have its mainboard + replaced with an X60 Tablet motherboard. +- **Lenovo ThinkPad T60** (Intel GPU) (there are issues; see below) + - See notes below for exceptions, and + **hardware/\#supported\_t60\_list** for known working LCD panels. + - It is unknown whether a T61 can have its mainboard replaced with + a T60 motherboard. + - T60p (and T60 variants with ATI GPU) will likely never be supported: + **hardware/\#t60\_ati\_intel** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - See **hardware/\#macbook11**. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - See **hardware/\#macbook21**. + +Machines no longer supported (compared to previous release): +------------------------------------------------------------ + +- **All previous systems still supported!** + +Revisions for r20140911 (7th beta) (11th September 2014) +-------------------------------------------------------- + +- The changes below were made in a git repository, unlike in previous + releases. Descriptions below are copied from 'git log'. +- Update .gitignore for new dependencies. +- Use a submodule for i945-pwm. +- Don't clean packages that fail or don't need cleaning. +- Don't clean i945-pwm, it's not needed. +- Regression fix: Parabola live ISO boot issues +- Re-enable background images in ISOLINUX/SYSLINUX GRUB parser menus +- Regression fix: Re-add CD-ROM (ata0) in GRUB +- Documentation: add notes about performance penalty when using + ecryptfs. +- Documentation: Fixed spelling and grammatical errors. +- Documentation: macbook21: add new system as tested +- Documentation: macbook21: add info about improving touchpad + sensitivity +- Documentation: X60 Tablet: add more information about finger input +- Documentation: release.html: Add information about recently merged + commit in coreboot + diff --git a/site/news/libreboot20141015.md b/site/news/libreboot20141015.md new file mode 100644 index 0000000..3aa133f --- /dev/null +++ b/site/news/libreboot20141015.md @@ -0,0 +1,64 @@ +% Libreboot 20141015 release +% Leah Rowe +% 15 October 2014 + +Machines supported in this release: +=================================== + +- **Lenovo ThinkPad X60/X60s** + - You can also remove the motherboard from an X61/X61s and replace + it with an X60/X60s motherboard. An X60 Tablet motherboard will + also fit inside an X60/X60s. +- **Lenovo ThinkPad X60 Tablet** (1024x768 and 1400x1050) with + digitizer support + - See **hardware/\#supported\_x60t\_list** for list of supported LCD + panels + - It is unknown whether an X61 Tablet can have its mainboard + replaced with an X60 Tablet motherboard. +- **Lenovo ThinkPad T60** (Intel GPU) (there are issues; see below): + - See notes below for exceptions, and + **hardware/\#supported\_t60\_list** for known working LCD panels. + - It is unknown whether a T61 can have its mainboard replaced with + a T60 motherboard. + - See **future/\#t60\_cpu\_microcode**. + - T60p (and T60 variants with ATI GPU) will likely never be supported: + **hardware/\#t60\_ati\_intel** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - See **hardware/\#macbook11**. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - See **hardware/\#macbook21**. + +Changes for this release (latest changes first, earliest changes last) +---------------------------------------------------------------------- + +- Updated coreboot (git commit + 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e), the latest at the time of + writing. +- Updated SeaBIOS (git commit + 67d1fbef0f630e1e823f137d1bae7fa5790bcf4e), the latest at the time of + writing. +- Updated Flashrom (svn revision 1850), the latest at the time of + writing. +- Updated GRUB (git commit 9a67e1ac8e92cd0b7521c75a734fcaf2e58523ad), + the latest at the time of writing. +- Cleaned up the documentation, removed unneeded files. +- ec/lenovo/h8 (x60/x60s/x60t/t60): Enable + wifi/bluetooth/wwan/touchpad/trackpoint by default. +- Documentation: Updated list of T60 LCDs (Samsung LTN150XG 15" XGA + listed as non-working). +- builddeps-coreboot: Don't build libpayload (not needed. This was + leftover by mistake, when trying out the TINT payload). +- Replaced most diff files (patches) for coreboot with gerrit + checkouts (cherry-pick). +- Documentation: x60\_security.html and t60\_security.html: added + links to info about the ethernet controller (Intel 82573). +- Documentation: x60\_security.html and t60\_security.html: added + notes about DMA and the docking station. +- builddeps-coreboot: use 'make crossgcc-i386' instead of 'make + crossgcc'. Libreboot only targets x86 at the time of writing. +- ROM images no longer include SeaBIOS. Instead, the user adds it + afterwards. Documentation and scripts updated. +- docs/images/encrypted\_parabola.html: Notes about linux-libre-grsec +- Documentation: added more info about wifi chipsets + diff --git a/site/news/libreboot20150124.md b/site/news/libreboot20150124.md new file mode 100644 index 0000000..b4144b1 --- /dev/null +++ b/site/news/libreboot20150124.md @@ -0,0 +1,159 @@ +% Libreboot 20150124 release +% Leah Rowe +% 24 January 2015 + +Machines supported in this release: +=================================== + +- **Lenovo ThinkPad X60/X60s** + - You can also remove the motherboard from an X61/X61s and replace + it with an X60/X60s motherboard. An X60 Tablet motherboard will + also fit inside an X60/X60s. +- **Lenovo ThinkPad X60 Tablet** (1024x768 and 1400x1050) with + digitizer support + - See **hardware/\#supported\_x60t\_list** for list of supported LCD + panels + - It is unknown whether an X61 Tablet can have it's mainboard + replaced with an X60 Tablet motherboard. +- **Lenovo ThinkPad T60** (Intel GPU) (there are + issuesinstall/x200\_external.html; see below): + - See notes below for exceptions, and + **hardware/\#supported\_t60\_list** for known working LCD panels. + - It is unknown whether a T61 can have it's mainboard replaced + with a T60 motherboard. + - See **future/\#t60\_cpu\_microcode**. + - T60p (and T60 laptops with ATI GPU) will likely never be + supported: **hardware/\#t60\_ati\_intel** +- **Lenovo ThinkPad X200** + - X200S and X200 Tablet are also supported, conditionally; see + **hardware/x200.html\#x200s** + - **ME/AMT**: libreboot removes this, permanently. + **hardware/gm45\_remove\_me.html** +- **Lenovo ThinkPad R400** (r20150208 and later, only) + - **ME/AMT**: libreboot removes this, permanently. + **hardware/gm45\_remove\_me.html** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - See **hardware/\#macbook11**. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - See **hardware/\#macbook21**. + +Changes for this release (latest changes first, earliest changes last) +---------------------------------------------------------------------- + +- grub.cfg: Added (ahci1) to list of devices for ISOLINUX parser + (CD/DVD) (this is needed for the X200 docking station). +- grub.cfg: ISOLINUX parsing is now done on all USB partitions. +- grub.cfg: Automatically switched to /boot/grub/libreboot\_grub.cfg + on a partition, if it exists. +- libreboot\_bin: added static ARM binaries for flashrom, cbfstool, + ich9gen and ich9deblob (tested on beaglebone black). +- Flashrom: removed redundant Macronix flashchip definitions (for X200 + owners). +- Flashrom: added whitelist for ThinkPad X200. +- X200: fixed uneven backlight (at low levels) +- ich9macchange (new script, uses ich9gen): for changing the default + MAC address on X200 ROM images. +- ich9gen: added capability to change the default MAC address (and + update the checksum) +- ich9deblob: added new utility ich9gen: this can generate a + descriptor+gbe image without a factory.rom dump present. +- Modified ich9deblob to use a struct for Gbe, documenting everything. +- Massively updated the ich9deblob utility: re-factored everything + completely. +- Enabled cstates 1 and 2 on macbook21. This reduces idle heat / power + consumption. +- buildrom-withgrub: disabled creation of \*txtmode\*.rom for X200 + (only framebuffer graphics work) +- Updated SeaBIOS (again) +- docs/install/\#flashrom\_x200: improve instructions +- Updated flashrom (again) - patches updated +- Updated GRUB (again) +- Updated coreboot (again) +- build-release: not all files were copied to libreboot\_src. fix + that. +- build-release: include cbmem (statically compiled) in libreboot\_bin +- Documentation (X200): added software-based flashing instructions +- Documentation: remove all references to the bus pirate (replaced + with BBB flashing tutorials) +- **New board:** ThinkPad X200S and X200 Tablet support added to + libreboot +- build: automatically find board names (configs) to build for +- **New board:** ThinkPad X200 support added to libreboot +- coreboot-libre config (all boards): enable USB dongle log output + (for BeagleBone Black) +- cleandeps: actually clean grubinvaders +- .gitignore: add powertop directory +- cleandeps: clean i945-pwm utility +- scripts (all): fix typos +- Documentation: general cleanup. +- builddeps-flashrom: reduce build commands to a single for loop +- scripts (all): replace unnecessary rm -Rf with rm -f +- docs/release.html: add lenovo g505s to the list of candidates +- .gitignore: add libreboot\_bin.tar.xz and libreboot\_src.tar.xz +- libreboot\_bin.tar.xz: Include utils as statically linked binaries + - This means that the user does not have to install build + dependency or build from source anymore. +- deps-parabola (removed) Remove Parabola dependencies script. Will + re-add later (properly tested) +- grub.cfg: Add more path checks to isolinux parser (more ISOs should + work now) +- Update SeaBIOS +- x60flashfrom5 (new), for X60 users upgrading from 5th/early release +- Update flashrom +- Update GRUB +- Updated coreboot-libre + - i945: permanently set tft\_brightness to 0xff (fixes bug on X60 + where turning up brightness at max would make it loop back to + low brightness) +- getcb: Revert X60/T60 to legacy backlight controls + - The ACPI brightness patches were abandoned and obsolete. +- grub.cfg: Only load initrd.img if it exists. Add rw to linux line + (for ProteanOS) +- build: Only generate the GRUB configurations once (re-use on all + images) +- Only build 2 GRUB payload executables, re-use on all boards. +- resources/utilities/grub-assemble/gen.txtmode.sh: Use BASH\ + resources/utilities/grub-assemble/gen.vesafb.sh: Use BASH +- scripts (error handling): Replace exit with exit 1 (make debugging + easier) +- Move most files in CBFS to GRUB memdisk, except grub.cfg and + grubtest.cfg +- docs/release.html Add DMP vortex86ex to list of candidates. +- docs/release.html Add ThinkPad X201 to list of candidates. +- New links added to docs/security/x60\_security and + docs/security/t60\_security +- lenovobios\_secondflash: Warn if BUCTS is not present. (not a + dealbreaker. Can just pull out nvram battery/coin). +- lenovobios\_firstflash: Fail if BUCTS fails. (anti-bricking + precaution) +- Removed obnoxious warnings from flashing scripts, improved + documentation instead. +- scripts (all): add proper error checking (fail fast, fail early. Do + not continue if there are errors) +- buildrom-withgrub: rename image to boardname\_layout\_romtype.rom +- buildrom-withgrub: don't move cbfstool, execute directly +- resources/utilities/grub-assemble: add French Dvorak (BEPO) keyboard + layout. +- Documentation: add docs/hardware/x60\_keyboard.html (show how to + replace keyboard on X60/X60T) +- Documentation: major cleanup (better structure, easier to find + things) +- docs/release.html: Remove Acer CB5 from list of future candidates. + - Too many issues. Chromebooks are crippled (soldered + RAM/storage/wifi) and have too many usability issues for the + libreboot project. +- docs/linux/grub\_cbfs.html Major cleanup. Usability improvements. +- flash (flashrom script): remove boardmismatch=force + - This was put there before for users upgrading from libreboot r5 + to r6, but also allows the user to flash the wrong image. For + example, the user could flash a T60 image on an X60, thus + bricking the system. It's almost certain that most people have + upgraded by now, so remove this potentially dangerous option. +- Documentation: update compatibility list for X60T LCD panels. +- docs/release.html: add note about X60 Tablet board in X60/X60s +- docs/howtos/grub\_boot\_installer.html: small corrections +- docs/howtos/grub\_boot\_installer.html: improved readability, fixed + html errors +- Documentation (macbook21 related): clean up + diff --git a/site/news/libreboot20150126.md b/site/news/libreboot20150126.md new file mode 100644 index 0000000..3729125 --- /dev/null +++ b/site/news/libreboot20150126.md @@ -0,0 +1,57 @@ +% Libreboot 20150126 release +% Leah Rowe +% 26 January 2015 + +Machines supported in this release: +=================================== + +- **Lenovo ThinkPad X60/X60s** + - You can also remove the motherboard from an X61/X61s and replace + it with an X60/X60s motherboard. An X60 Tablet motherboard will + also fit inside an X60/X60s. +- **Lenovo ThinkPad X60 Tablet** (1024x768 and 1400x1050) with + digitizer support + - See **hardware/\#supported\_x60t\_list** for list of supported LCD + panels + - It is unknown whether an X61 Tablet can have it's mainboard + replaced with an X60 Tablet motherboard. +- **Lenovo ThinkPad T60** (Intel GPU) (there are + issuesinstall/x200\_external.html; see below): + - See notes below for exceptions, and + **hardware/\#supported\_t60\_list** for known working LCD panels. + - It is unknown whether a T61 can have it's mainboard replaced + with a T60 motherboard. + - See **future/\#t60\_cpu\_microcode**. + - T60p (and T60 laptops with ATI GPU) will likely never be + supported: **hardware/\#t60\_ati\_intel** +- **Lenovo ThinkPad X200** + - X200S and X200 Tablet are also supported, conditionally; see + **hardware/x200.html\#x200s** + - **ME/AMT**: libreboot removes this, permanently. + **hardware/gm45\_remove\_me.html** +- **Lenovo ThinkPad R400** (r20150208 and later, only) + - **ME/AMT**: libreboot removes this, permanently. + **hardware/gm45\_remove\_me.html** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - See **hardware/\#macbook11**. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - See **hardware/\#macbook21**. + +Revisions for r20150126 (relative to r20150124) +----------------------------------------------- + +This is a bug fix release based on r20150124. It contains a few small +changes: + +- grub.cfg: hardcode the list of partitions to search (speeds up + booting considerably. GRUB regexp isn't very well optimized) +- Docs (x200.html hcl): Remove incorrect information +- Documentation (bbb\_setup.md): Fix typos +- build-release: delete ich9fdgbe\_{4m,8m}.bin files from ich9gen + - These were accidentically included in the r20150124 release. + They are generated from ich9gen so it's ok, but they don't + need to be in the archive. +- Documentation (grub\_cbfs.md): Looping in libreboot\_grub.cfg (Add + notes about it if the user copied from grub.cfg in CBFS.) + diff --git a/site/news/libreboot20150208.md b/site/news/libreboot20150208.md new file mode 100644 index 0000000..a65fa37 --- /dev/null +++ b/site/news/libreboot20150208.md @@ -0,0 +1,74 @@ +% Libreboot 20150208 release +% Leah Rowe +% 8 February 2015 + +Machines supported in this release: +=================================== + +- **Lenovo ThinkPad X60/X60s** + - You can also remove the motherboard from an X61/X61s and replace + it with an X60/X60s motherboard. An X60 Tablet motherboard will + also fit inside an X60/X60s. +- **Lenovo ThinkPad X60 Tablet** (1024x768 and 1400x1050) with + digitizer support + - See **hardware/\#supported\_x60t\_list** for list of supported LCD + panels + - It is unknown whether an X61 Tablet can have it's mainboard + replaced with an X60 Tablet motherboard. +- **Lenovo ThinkPad T60** (Intel GPU) (there are + issuesinstall/x200\_external.html; see below): + - See notes below for exceptions, and + **hardware/\#supported\_t60\_list** for known working LCD panels. + - It is unknown whether a T61 can have it's mainboard replaced + with a T60 motherboard. + - See **future/\#t60\_cpu\_microcode**. + - T60p (and T60 laptops with ATI GPU) will likely never be + supported: **hardware/\#t60\_ati\_intel** +- **Lenovo ThinkPad X200** + - X200S and X200 Tablet are also supported, conditionally; see + **hardware/x200.html\#x200s** + - **ME/AMT**: libreboot removes this, permanently. + **hardware/gm45\_remove\_me.html** +- **Lenovo ThinkPad R400** (r20150208 and later, only) + - **ME/AMT**: libreboot removes this, permanently. + **hardware/gm45\_remove\_me.html** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - See **hardware/\#macbook11**. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - See **hardware/\#macbook21**. + +Revisions for r20150208 (relative to r20150126) +----------------------------------------------- + +This is a maintenance release (polishing) based on r20150126. Users who +installed r20150126 don't really need to update to this release. + +- buildrom-withgrub: use gnulove.jpg background on 16:10 laptops + (MacBook2,1 and X200) +- build-release: include grub-background script in libreboot\_bin +- grub-background (new): lets user change GRUB background image +- grub-assemble: Add link to original utility. +- buildrom-withgrub: Put background.jpg in CBFS, not GRUB memdisk +- grub-assemble: merge scripts into a single script gen.sh +- Documentation: implement theme, drastically improve readability +- docs/hardware/: update list of compatible T60 LCD panels +- docs/: more clarification of libreboot's stated purpose. +- build-release: include the commitid file in the release archives +- docs/: Further emphasize the Linux requirement. +- lenovobios\_firstflash: fix BASH errors +- lenovobios\_secondflash: fix BASH errors +- docs/install/x200\_external.html: Tell user to switch MAC address. +- docs/git/: Add to the list of x86\_64 compatible hosts. +- docs/install/: Remove old (obsolete) information. +- docs/git/: Say that the build dependencies are for src (and not + nedeed for libreboot\_bin) +- build: re-factor the descriptor/gbe generating loop for GM45/ICH9M +- X60, X60S and X60 Tablet now the same ROM images. +- Add QEMU (q35/ich9) support to libreboot. +- Add QEMU (i440fx/piix4) support to libreboot +- docs/: Re-write the description of what libreboot is. +- docs/release.html: Add notes about how to use GPG. +- build-release: delete the commitid file from release archives +- build-release: create file named commitid after build-release + diff --git a/site/news/libreboot20150518.md b/site/news/libreboot20150518.md new file mode 100644 index 0000000..dfc10ba --- /dev/null +++ b/site/news/libreboot20150518.md @@ -0,0 +1,224 @@ +% Libreboot 20150518 release +% Leah Rowe +% 18 May 2015 + +Installation instructions can be found at ***docs/install/***. Building +instructions (for source code) can be found at ***docs/git/\#build***. + +Machines supported in this release: +----------------------------------- + +- **ThinkPad X60/X60s** + - You can also remove the motherboard from an X61/X61s and replace + it with an X60/X60s motherboard. An X60 Tablet motherboard will + also fit inside an X60/X60s. +- **ThinkPad X60 Tablet** (1024x768 and 1400x1050) with digitizer + support + - See ***docs/hardware/\#supported\_x60t\_list*** for list of supported + LCD panels + - It is unknown whether an X61 Tablet can have it's mainboard + replaced with an X60 Tablet motherboard. +- **ThinkPad T60** (Intel GPU) (there are issues; see below): + - See notes below for exceptions, and + ***docs/hardware/\#supported\_t60\_list*** for known working LCD + panels. + - It is unknown whether a T61 can have it's mainboard replaced + with a T60 motherboard. + - See ***docs/future/\#t60\_cpu\_microcode***. + - T60p (and T60 laptops with ATI GPU) will likely never be + supported: ***docs/hardware/\#t60\_ati\_intel*** +- **ThinkPad X200** + - X200S and X200 Tablet are also supported, conditionally; see + ***docs/hardware/x200.html\#x200s*** + - **ME/AMT**: libreboot removes this, permanently. + ***docs/hardware/gm45\_remove\_me.html*** +- **ThinkPad R400** + - See ***docs/hardware/r400.html*** + - **ME/AMT**: libreboot removes this, permanently. + ***docs/hardware/gm45\_remove\_me.html*** +- **ThinkPad T400** + - See ***docs/hardware/t400.html*** + - **ME/AMT**: libreboot removes this, permanently. + ***docs/hardware/gm45\_remove\_me.html*** +- **ThinkPad T500** + - See ***docs/hardware/t500.html*** + - **ME/AMT**: libreboot removes this, permanently. + ***docs/hardware/gm45\_remove\_me.html*** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - See ***docs/hardware/\#macbook11***. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - See ***docs/hardware/\#macbook21***. + +Changes for this release, relative to r20150208 (earliest changes last, recent changes first) +--------------------------------------------------------------------------------------------- + +- Add a whitelist entry to board\_enable.c in flashrom, for the + ThinkPad R400, T400 and T500 +- Updated flashrom (to SVN revision 1889) + - X200 whitelist patch removed (merged upstream) + - X200 whitelist modified to include X200S and X200 Tablet +- libreboot\_util: don't include cmos layout files (not needed + anymore) +- **coreboot-libre: backport patches for X200 Tablet digitizer + support** +- build/release/archives: create SHA512 sum manifest file of the + release archives +- build/release/archives: separate crossgcc into a new archive +- disabled generation of txtmode ROM images for now (they will be back + again in the next release) +- coreboot-libre: delete unused code (reduce size of src archive) +- Flashing guides: make them more friendly to colourblind people +- docs/linux/encrypted\_\*.html: Remove mention of password + length - it was arbitrary and pointless. +- docs/maintain/: Finish the guide +- scripts/download/coreboot: use diffs included in libreboot, not + external gerrit cherry-picks - review.coreboot.org (gerrit) being + down no longer kills libreboot (backup mirrors of the master + repository exist) +- docs/install/bbb\_setup.html: Add info about wp/hold and pinouts +- docs/: improve the description of libreboot +- docs/hardware/gm45\_remove\_me.html: notes about the demefactory utility +- docs/install/bbb\_setup.html: EHCI debug: recommend linux-libre +- docs/install/bbb\_setup.html: EHCI Debug logging setup guide +- docs/hardware/t500.html: Add screen compatibility report (TODO: fix + incompatible screens) +- Update coreboot(again) + merge GM45 hybrid GPU patches - means that + T400/T500 with the ATI+Intel hybrid GPU setup will work (ATI + disabled, Intel permanently enabled). power\_on\_after\_fail nvram + option added to all GM45 boards, defaulting to No, so that plugging + it AC doesn't boot up the system against the users will. Net20DC is + now the default debug dongle on all boards (compatible with BBB). +- demefactory (new utility): create GM45 factory.rom without the ME +- ich9deblob: re-factor descriptor.c functions +- docs/hardware/t500.html: add hardware logs +- docs/linux/encrypted\_\*.html: No password for default entry +- docs/git/: Add more details about BUC.TS +- grub.cfg: Also scan for grub2/grub.cfg, not just grub/grub.cfg +- docs/maintain/ (new section. WIP!): Maintaining libreboot +- docs/linux/grub\_boot\_installer.html: Fix hazardous instruction +- docs/tasks.html: Better categorization between intel/amd/arm +- docs/install/bbb\_setup.html: notes about SPI flashing stability +- docs/install/bbb\_setup.html: more names for the 0.1" cables +- docs/install/\*\_external.html: add disclaimer about thermal paste +- docs/install/bbb\_setup.html: Fix broken links +- docs/install/bbb\_setup.html: preliminary notes about EHCI debug +- docs/hardware/gm45\_remove\_me.html: Link to websites talking about the + ME +- docs/install/{t400,t500,r400}\_external.html: Notes about CPU + compatibility +- Delete the ich9macchange script. It's useless, and confuses people +- docs/hardware/gm45\_remove\_me.html: prioritize ich9gen executable path +- docs/hardware/gm45\_remove\_me.html: prioritize changing mac address +- docs/hardware/gm45\_remove\_me.html: less confusing notes about ich9gen +- build/dependencies/parabola: Add dependencies for x86\_64 +- scripts/dependencies/paraboladependencies: build dependencies + (32-bit Parabola) +- **New board**: ThinkPad T500 +- Add diffs for descriptor/gbe differences between T500 and X200 +- coreboot-libre: provide better blob categorization +- docs/hardware/gm45\_remove\_me.html: add notes about flash write protect +- **New board**: ThinkPad T400 +- GRUB: add partial vesamenu.c32 support (fixes tails ISOLINUX menu) +- Update GRUB (to revision fa07d919d1ff868b18d8a42276d094b63a58e299) +- Update coreboot (to revision + 83b05eb0a85d7b7ac0837cece67afabbdb46ea65) + - Intel CPU microcode (most of it) no longer deleted, because it + was deleted upstream (moved to a 3rd party repository). + - MacBook2,1 cstate patch is no longer cherry picked (merged + upstream) + - Patch to disable use of timestamps in coreboot no longer + included (merged upstream) +- coreboot-libre: don't list vortex86ex kbd firmware as microcode + (list it separately) +- coreboot-libre: don't rm \*/early\_setup\_ss.h (these are not + blobs) +- coreboot-libre: add GPLv3 license to the findblobs script +- coreboot-libreboot: don't rm raminit\_tables (nahelem/sandybridge) + (they are not blobs) +- coreboot-libre: don't delete the .spd.hex files (they are not + blobs) +- build/release/archives: don't put rmodtool in libreboot\_util +- docs/install/x200\_external.html: recommend installing Linux at + the end +- docs/install/x200\_external.html: add more photos, improve + instructions +- build/clean/grub: use distclean instead of clean +- grub-assemble: Add the *bsd* and *part\_bsd* modules +- build/roms/withgrub: Only run ich9gen if gm45/gs45 images exist +- docs/git/: Add notes about building for specific boards +- build/roms/withgrub: Allow building for a custom range of boards +- grub-assemble: Disable verbose output +- Add documentation on how to unlock root encrypted fs with key in + initramfs in Parabola Linux +- docs/linux/grub\_cbfs.html: Improve structure (easier to use) +- grub.cfg: Disable the beep on startup +- docs/install/bbb\_setup.html: Make the guide easier to use +- docs/linux/grub\_cbfs.html: Remove redundant instructions +- docs/install/x200\_external.html: Mark pins in the images +- docs/install/bbb\_setup.html: Replace 3.3V PSU photo with ATX PSU +- docs/hardware/x200.html: Add dumps from 4-MiB X200 with Lenovo BIOS 3.22 +- docs/hardware/x200.html: Add dumps from 4-MiB X200 with Lenovo BIOS 3.18 +- grub.cfg: add syslinux\_configfile menuentry for ahci0 +- grub.cfg: Add more paths for syslinux\_configfile +- docs/future.html: T60: Add EDID dump from LG-Philips LP150E05-A2K1 +- docs/install/bbb\_setup.html: Further clarify which clip is needed +- bash scripts: Make script output more user-friendly in general +- bash scripts: Only enable verbose output if DEBUG= is used +- build: Support multiple extra options - now possible to build + multiple images for arbitrary boards (configs), but without building + the entire collection. +- Deleted the signing archive key - the finger print and ID is given + instead, so that the user can download it from a key server +- scripts/helpers/build/release: Move docs to separate archive - + reduces the size of the other archives considerably +- Move DEBLOB to resources/utilities/coreboot-libre/deblob +- scripts/helpers/build/release: Delete DEBLOB from libreboot\_src/ - + not needed in libreboot\_src (release archive) because it contains a + coreboot revision that has already been deblobbed. +- flash (script): Use *build* instead of *DEBLOB* to know if in src +- docs/install/r400\_external.html: Show images, don't link. +- docs/install/x200\_external.html: Show images, don't link. +- docs/install/bbb\_setup.html: Show images, instead of linking +- Documentation: optimize all images (reduce file sizes) +- Remove download links from the release page (and the archive page) - + release archives are hosted differently following this release, + which means that the old methods are no longer viable. +- Moved ich9macchange to resources/scripts/misc/ich9macchange +- ich9macchange: assume that the script is being run from \_util (act + only on one ROM image, defined by a user-provided path) +- Move grub-background to resources/scripts/misc/grub-background +- grub-background: assume that it is being run from libreboot\_util +- grub-background: change only one ROM image, specified by path +- build (release archives): Add the commitid file to release/ +- build-release: Move the release archives to release/ +- Merge all build scripts into a single generic script, with helpers + in resources/scripts/helpers/build/ +- Replace *getall* with *download*, which takes as input an argument + specifying which program the user wants to download. +- Moved the get scripts to resources/scripts/helpers/download/ +- build-release: Remove the powertop entries +- Documentation: general improvements to the flashing instructions +- Merged all flashing scripts into a single script +- Updated GRUB +- bucts: Make it build without git +- Moved dejavu-fonts-ttf-2.34/AUTHORS to resources/grub/font/ +- Deleted GRUB Invaders from libreboot +- Deleted SeaBIOS from libreboot +- build-release: optimize use of tar (reduced file sizes) +- grub.cfg: add another SYSLINUX config location + (/syslinux/syslinux.cfg) +- build-release: remove the bin/ directory from libreboot\_util +- cleandeps: delete the bin/ directory +- buildrom-withgrub: create the bin directory if it does not exist +- coreboot-libre: don't use git for version timestamp +- i945-pwm: add clean command to Makefile +- i945-pwm: add -lz to Makefile +- docs/install/x200\_external: Mention GPIO33 non-descriptor mode +- docs/hardware/: Remove redundant links +- ich9macchange: Add R400 +- build-release: Separate ROM images into individual archives +- build-release: rename libreboot\_bin to libreboot\_util +- **New board:** ThinkPad R400 support added to libreboot. +- bbb\_setup.html: tell user to use libreboot's own flashrom + diff --git a/site/news/libreboot20160818.md b/site/news/libreboot20160818.md new file mode 100644 index 0000000..a41175b --- /dev/null +++ b/site/news/libreboot20160818.md @@ -0,0 +1,169 @@ +% Libreboot 20160818 release +% Leah Rowe +% 18 August 2016 + +This is in comparison to the Libreboot 20150518 release. + +Installation instructions can be found at `docs/install/`. Building +instructions (for source code) can be found at `docs/git/\#build`. + +Machines supported in this release: +----------------------------------- + +- **ASUS Chromebook C201** + - Check notes in ***docs/hardware/c201.html*** +- **Gigabyte GA-G41M-ES2L desktop motherboard** + - Check notes in ***docs/hardware/ga-g41m-es2l.html*** +- **Intel D510MO desktop motherboard** + - Check notes in ***docs/hardware/d510mo.html*** +- **Intel D945GCLF desktop motherboard** + - Check notes in ***docs/hardware/d945gclf.html*** +- **Apple iMac 5,2** + - Check notes in ***docs/hardware/imac52.html*** +- **ASUS KFSN4-DRE server board** + - PCB revision 1.05G is the best version (can use 6-core CPUs) + - Check notes in ***docs/hardware/kfsn4-dre.html*** +- **ASUS KGPE-D16 server board** + - Check notes in ***docs/hardware/kgpe-d16.html*** +- **ASUS KCMA-D8 desktop/workstation board** + - Check notes in ***docs/hardware/kcma-d8.html*** +- **ThinkPad X60/X60s** + - You can also remove the motherboard from an X61/X61s and replace + it with an X60/X60s motherboard. An X60 Tablet motherboard will + also fit inside an X60/X60s. +- **ThinkPad X60 Tablet** (1024x768 and 1400x1050) with digitizer + support + - See ***docs/hardware/\#supported\_x60t\_list*** for list of supported + LCD panels + - It is unknown whether an X61 Tablet can have it's mainboard + replaced with an X60 Tablet motherboard. +- **ThinkPad T60** (Intel GPU) (there are issues; see below): + - See notes below for exceptions, and + ***docs/hardware/\#supported\_t60\_list*** for known working LCD + panels. + - It is unknown whether a T61 can have it's mainboard replaced + with a T60 motherboard. + - See ***docs/future/\#t60\_cpu\_microcode***. + - T60p (and T60 laptops with ATI GPU) will likely never be + supported: ***docs/hardware/\#t60\_ati\_intel*** +- **ThinkPad X200** + - X200S and X200 Tablet are also supported, conditionally; see + ***docs/hardware/x200.html\#x200s*** + - **ME/AMT**: libreboot removes this, permanently. + ***docs/hardware/gm45\_remove\_me.html*** +- **ThinkPad R400** + - See ***docs/hardware/r400.html*** + - **ME/AMT**: libreboot removes this, permanently. + ***docs/hardware/gm45\_remove\_me.html*** +- **ThinkPad T400** + - See ***docs/hardware/t400.html*** + - **ME/AMT**: libreboot removes this, permanently. + ***docs/hardware/gm45\_remove\_me.html*** +- **ThinkPad T500** + - See ***docs/hardware/t500.html*** + - **ME/AMT**: libreboot removes this, permanently. + ***docs/hardware/gm45\_remove\_me.html*** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - See ***docs/hardware/\#macbook11***. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - See ***docs/hardware/\#macbook21***. + +Changes for this release of Libreboot, relative to Libreboot version 20150518 (earliest changes are shown last and the most recent changes are shown first first) +--------------------------------------------------------------------------------------------- + +- NEW BOARDS ADDED: + - ASUS Chromebook C201 (ARM laptop) (thanks to Paul Kocialkowski) + - Gigabyte GA-G41M-ES2L motherboard (desktop) (thanks to Damien + Zammit) + - Intel D510MO motherboard (desktop) (thanks to Damien Zammit) + - ASUS KCMA-D8 motherboard (desktop) (thanks to Timothy Pearson) + - ASUS KFSN4-DRE motherboard (server) (thanks to Timothy Pearson) + - ASUS KGPE-D16 motherboard (server) (thanks to Timothy Pearson) + +For details development history on these boards, refer to the git log +and documentation. + +For boards previously supported, many fixes from upstream have been +merged. + +Other changes (compared to libreboot 20150518), for libreboot in general +or for previously supported systems: (this is a summary. For more +detailed change list, refer to the git log) + +256MiB VRAM allocated on GM45 (X200, T400, T500, R400) instead of 32MiB. +This is an improvement over both Lenovo BIOS and Libreboot 20150518, +allowing video decoding at 1080p to be smoother. (thanks Arthur Heymans) +To clarify, GM45 video performance in libreboot 20160818 is better than +on the original BIOS and the previous libreboot release. + +64MiB VRAM on i945 (X60, T60, MacBook2,1) now supported in +coreboot-libre, and used by default (in the previous release, it was +8MiB allocated). Thanks to Arthur Heymans. + +Higher battery life on GM45 (X200, T400, T500, R400) due to higher +cstates now being supported (thanks Arthur Heymans). C4 power states +also supported. + +Higher battery life on i945 (X60, T60, MacBook2,1) due to better CPU +C-state settings. (Deep C4, Dynamic L2 shrinking, C2E). + +Text mode on GM45 (X200, T400, T500, R400) now works, making it possible +to use MemTest86+ comfortably. (thanks to Nick High from coreboot) + +Dual channel LVDS displays on GM45 (T400, T500) are now automatically +detected in coreboot-libre. (thanks Vladimir Serbinenko from coreboot) + +Partial fix in coreboot-libre for GRUB display on GM45, for dual channel +LVDS higher resolution LCD panels (T400, T500). (thanks Arthur Heymans) + +Massively improved GRUB configuration, making it easier to boot more +encrypted systems automatically, and generally a more useful menu for +booting the system (thanks go to Klemens Nanni of the autoboot project). +Libreboot now uses the grub.cfg provided by the installed Linux +distribution automatically, if present, switching to that configuration. +This is done across many partitions, where libreboot actively searches +for a configuration file (also on LVM volumes and encrypted volumes). +This should make libreboot more easy to use for non-technical users, +without having to modify the GRUB configuration used in libreboot. + +Utilities archives is now source only. You will need to compile the +packages in there (build scripts included, and a script for installing +build dependencies). (binary utility archives are planned again in the +next release, when the new build system is merged) + +SeaGRUB is now the default payload on all x86 boards. (SeaBIOS +configured to load a compressed GRUB payload from CBFS immediately, +without providing an interface in SeaBIOS. This way, GRUB is still used +but now BIOS services are available, so you get the best of both +worlds). Thanks go to Timothy Pearson of coreboot for this idea. + +crossgcc is now downloaded and built as a separate module to +coreboot-libre, with a universal revision used to build all boards. + +Individual boards now have their own coreboot revision and patches, +independently of each other board. This makes maintenance easier. + +Updated all utilities, and modules (coreboot, GRUB, etc) to newer +versions, with various bugfixes and improvements upstream. + +RTC century byte issue now fixed on GM45 in coreboot-libre, so the date +should now be correctly displayed when running the latest linux kernel, +instead of seeing 1970-01-01 when you boot (thanks to Alexander Couzens +from coreboot) + +Build system now uses multiple CPU cores when building, speeding up +building for some people. Manually specifying how many cores are needed +is also possible, for those using the build system in a chroot +environment. (thanks go to Timothy Pearson from coreboot) + +In the build system (git repository), https:// is now used when cloning +coreboot. http:// is used as a fallback for GRUB, if git:// fails. + +New payload, the depthcharge bootloader (free bootloader maintained by +Google) for use on the ASUS Chromebook C201. (thanks go to Paul +Kocialkowski) + +Various fixes to the ich9gen utility (e.g. flash component density is +now set correctly in the descriptor, gbe-less descriptors now supported) + diff --git a/site/news/libreboot20160902.md b/site/news/libreboot20160902.md new file mode 100644 index 0000000..2015fac --- /dev/null +++ b/site/news/libreboot20160902.md @@ -0,0 +1,5 @@ +% Libreboot 20160902 release +% Leah Rowe +% 2 September 2016. + +This fixes build issues in the previous 20160818 release diff --git a/site/news/libreboot20160907.md b/site/news/libreboot20160907.md new file mode 100644 index 0000000..fa3ba03 --- /dev/null +++ b/site/news/libreboot20160907.md @@ -0,0 +1,17 @@ +% Libreboot 20160907 release +% Leah Rowe +% 7 September 2016 + +In comparison to Libreboot 20160902: + +For existing boards, there are no new board specific changes. + +This release adds one new mainboard to libreboot: + +- Intel D945GCLF desktop motherboard (thanks to Arthur Heymans) + +Other bugfixes: + +- Various improvements to the documentation +- re-added "unset superusers" to the grub.cfg, which was needed for + some users depending on the distros that they used diff --git a/site/news/libreboot20210522.md b/site/news/libreboot20210522.md new file mode 100644 index 0000000..6539cbe --- /dev/null +++ b/site/news/libreboot20210522.md @@ -0,0 +1,2252 @@ +% Libreboot 20210522 released! +% Leah Rowe +% 22 May 2021 + +Join us now and flash the firmware! +=================================== + +You'll be free! +--------------- + +Libreboot is [free](https://writefreesoftware.org/) (as in freedom) boot +firmware, which initializes the hardware +(e.g. memory controller, CPU, peripherals) in your computer so that software +can run. Libreboot then starts a bootloader to load your operating system. It +replaces the proprietary BIOS/UEFI firmware typically found on a computer. +Libreboot is compatible with specifical computer models that use the Intel/AMD +x86 architecture. Libreboot works well with Linux and BSD operating systems. + +The last Libreboot release, version 20160907, was released on September 7th +in 2016. *This* new release, Libreboot 20210522, is being released today on May +22nd, 2021. This is a *testing* release, so expect there to be some bugs. Every +effort has been made to ensure reliability on all boards, however. + +You can find this release in the `testing` directory on Libreboot release +mirrors. If you check in the `stable` directory, you'll still only find +the 20160907 release in there, so please ensure that you check the `testing` +directory! + +Tested boards +------------- + +More testing is needed, for this release. Frequent update releases are planned +after this release, fixing any issues that people may come across. + +GM45 laptops (e.g. ThinkPad X200, T400) are well-tested and should work fine. +X4X platforms (e.g. Gigabyte GA-G41M-ES2L) should also work. A few people have +tested the KCMA-D8 and KGPE-D16 ROM images too, and those should work fine. +The ASUS KFSN4-DRE is *untested* for this release. Intel i945 platforms such +as ThinkPad X60/T60 and Macbook2,1 have been tested, and should work fine. +Intel D510MO and D945GCLF boards are untested! Acer G43T-AM3 is untested! + +New boards +========== + +Desktops +-------- + +### Acer G43T-AM3 + +This is a desktop mainboard, with similar hardware to the already supported +Gigabyte GA-G41M-ES2L + +Laptops +------- + +### Lenovo ThinkPad R500 + +This is another Intel GM45 target, similar to the ThinkPad T500 that Libreboot +already supports. + +### Lenovo ThinkPad X301 + +This is another Intel GM45 target, similar to the ThinkPad X200 that Libreboot +already supports. + +List of supported boards +------------------------ + +This release has focused on the build system, and updating to the latest +coreboot release. This Libreboot release uses coreboot 4.14. Only a few boards +have been added, but existing ones have been updated heavily. Another new +release is planned soon, specifically an update release with ROM images in it +for more boards, while being built from the Libreboot 20210522 source code. +Visit the [tasks page](/tasks/) to know which machines are on the TODO list. + +### Desktops (AMD, Intel, x86) + +- Gigabyte GA-G41M-ES2L motherboard +- Intel D510MO and D410PT motherboards +- Intel D945GCLF +- Apple iMac 5,2 +- Acer G43T-AM3 + +### Servers/workstations (AMD, x86) + +- ASUS KCMA-D8 motherboard +- ASUS KGPE-D16 motherboard +- ASUS KFSN4-DRE motherboard + +### Laptops (Intel, x86) + +- ThinkPad X60 / X60S / X60 Tablet +- ThinkPad T60 (with Intel GPU) +- Lenovo ThinkPad X200 / X200S / X200 Tablet +- Lenovo ThinkPad R400 +- Lenovo ThinkPad T400 / T400S +- Lenovo ThinkPad T500 +- Lenovo ThinkPad W500 +- Lenovo ThinkPad R500 +- Lenovo ThinkPad X301 +- Apple MacBook1,1 and MacBook2,1 + +Dropped boards +-------------- + +ASUS Chromebook C201 was dropped. It will be re-added at a later date, when +the build system in Libreboot has better integration for ARM hardware. + +More boards coming soon! +------------------------ + +I had planned to add a lot more boards before doing a new release, but the +existing boards are greatly improved already (lots of new fixes and features +in coreboot), and there already are a few boards added. + +The next Libreboot release will likely just be a few more ROM images, but while +referencing this release (Libreboot 20210522) for the source code. See the +tasks page on libreboot.org for a list of the boards I plan to add. + +lbmk +==== + +The build system in libreboot is called `lbmk`, short for Libreboot Make. In +the previous Libreboot release, this build system had no name. It was simply +called "the build system" or just "libreboot". It was scrapped, shortly after +the 20160907 release and an ambitious new re-write began. + +The build system in Libreboot 20160907 was very conservative, focusing on +stability rather than features. That build system was designed to be easily +maintained, but it was highly monolithic and not very configurable. Also, that +build system was largely centered around x86 hardware (Intel/AMD). + +The intention behind the re-write was to create a much more configurable, and +highly advanced build system, with many new features. However, that re-write +failed and the result was that there were no more regular Libreboot releases. +I scrapped the re-write in December 2020, and continued with my development on +the Libreboot 20160907 build system. + +Fundamental design flaws were fixed, and it is much more configurable these +days. + +Moving forward, ideas/features that were implemented (whether on not they were +completed) in the re-write will be implemented in lbmk. The design of lbmk is +intentionally much simpler. The focus of lbmk is purely to provide releases of +pre-compiled ROM images that the user can easily flash on their machine, with +simple and clear guidance provided on the Libreboot website. + +Here is a summary of the improvements made in lbmk (based on osbmk-libre), when +compared to the Libreboot 20160907 build system: + +* Generally it is much more cleanly written, and more modular +* The way coreboot boards are added is greatly simplified. It has reverted to + using a directory per coreboot board, *but* a coreboot board can simply link + to another board, while using its own configs. The other board doesn't need + to have any configs either, so in this release there are 3 "boards" that aren't + actually boards, but specify a coreboot revision and patches, for other boards + to use: + * `default` (most boards use this one) (uses coreboot 4.14 in this release) + * `fam15h_udimm` (fam10h and 15h targets with UDIMM modules use this) + * `fam15h_rdimm` (fam10h and 15h targets with RDIMM modules use this. it + uses a raminit patch that fixes RDIMM training but breaks a lot of UDIMM + modules. The udimm version doesn't have this patch) + * the fam15h branches use coreboot 4.11, with some custom patches applied. + a full fork of coreboot 4.11 is planned, with newer coreboot features + backported to it, and it will be maintained over time (e.g. ensure that + it continues to build using modern toolchains, and fix bugs that appear) +* Coreboot configs are much more flexible. The build system can now generate + many more types of configurations. For example, desktop boards now load PCI + ROMs automatically, if found (on add-on cards, such as graphics cards). + Separate options are provided, for coreboot configs where loading of PCI ROMs + is disabled. This was done because Libreboot now supports a lot more desktop + hardware than the previous release; the build system has historically been + optimized towards building coreboot configs for laptops. It is now much more + flexible in this regard, creating perfectly usable ROM images for more types + of hardware. +* Multiple crossgcc revisions are now used, if multiple coreboot revisions are + also used. In Libreboot 20160907, the same crossgcc revision was always used, + from an arbitrarily selected coreboot revision. This worked because at the + time, all boards used more or less the same coreboot version, give or take a + few commits. There were more revisions used, but they were closer together. + In *this* release, coreboot 4.11 and 4.14 are the versions used, and these + revisions are quite far apart from each other. +* You no longer have to manually run individual commands within lbmk: + each command checks if previous commands + required were run, and runs them if not. **This means you can just type a + single command to build a ROM image if you wish!** +* Makefile included, making the build system even easier to use. The Makefile + contains no logic, it just runs lbmk commands. +* The GRUB payload is now handled by a completely separate command. The + command `./build payload grub` generates the GRUB payload executables, and + puts them in `payload/grub/`, in a completely modular way. +* Same thing for SeaBIOS. SeaBIOS is handled by the `./build payload seabios` + command in lbmk, and the payloads appear under `payload/seabios/` when built. + In the Libreboot 20160907 release, SeaBIOS and GRUB were always built precisely + while building the ROM images, so the logic for payload building and coreboot + ROM building was shoehorned into a single script. Now it is a separate script +* The commands `./build roms withgrub` and `./build roms withseabios` are + scrapped. Instead, a single command `./build boot roms` is used. Each board + defined in `resources/coreboot/` (in 20160907 it was `resources/libreboot`), + a file named `board.cfg` defines, among other things, what payloads are to be + used. The config files for coreboot boards are specified as having *no* + payload, and lbmk inserts the payload externally, using `cbfstool`. +* Vastly improved `grub.cfg`: un-hardcodes a lot of functionality, improved + usability on i945 targets such as X60/T60/macbook21, USB HDD support out of + the box +* SeaBIOS now included as standard, on all ROM images; on images with the GRUB + payload, SeaBIOS is an option in the boot menu. +* The build system is *much* easier to use when adding new board configs +* Each `board.cfg` for each board defines what payloads it is to use, what + architecture, etc. Coreboot trees are now handled on a directory basis, + instead of creating multiple branches in a newly initialized Git repository; + this is less efficient on disk space, but it is simpler to maintain, so now + the priority is to minimize how ever many coreboot revisions are used. +* Boards can link to other boards; for example, X200 could use the same setup + as T400. However, in this case the specific board would still have it's own + specific coreboot configuration files. Basically similar in spirit to the + variants concept in the coreboot build system, but for the purposes of + integrating various coreboot configs and revisions together, for several + boards. +* Build system highly optimized; unnecessary steps are skipped. If you just + want to build for 1 board, you can! Only the things necessary for that board + will be compiled by osbmk, at least automatically that is! +* In general, it is a *much more automated* automated build system! + It's better documented, and easier for the average person to maintain. + +Documentation +============= + +Generally, the documentation is much improved. In particular, the "maintain" +page has been reintroduced, which describes every aspect of the build system +in great detail. + +Build system documentation was absent for the last few years, due to the +rewrite. The rewrite had a very over-inflated scope in its agenda and it was +extremely complex considering what Libreboot is supposed to be: a coreboot +distro. + +The installation guides for Libreboot are greatly improved. In particular, the +external flashing guides now have a lot more information; for example, there is +now a single page that clearly defines each type of flash IC you'll likely +encounter. It also has information about flashing new chips in a breadboard, +and replacing WSON8 ICs with SOIC8 ICs (useful for ThinkPad X200 Tablet and +X200S owners who wish to install Libreboot). + +The documentation is not fundamentally different from the last release, mostly +because the documentation wasn't worked on much over the last few years. Rather, +the documentation has been *tweaked* over the years. We didn't focus as much on +adding new hardware to Libreboot, because of the re-write that occured. + +Ever since the re-write was scrapped, the focus is now once again on hardware +support, rather than build system changes. As such, the installation guides +are greatly improved and there are *more* systems documented now. + +GRUB +==== + +In GRUB payloads, a much more recent version is used. The difference is +literally: the GRUB version that Libreboot 20160907 uses was released 5 years +ago. The version that this new Libreboot release uses is from *a few days ago*. + +In Libreboot 20160907, only a limited subset of GRUB modules were included. In +this new Libreboot list, all modules (from `moddeps.lst` when building GRUB) are +used. One consequence of this is that there are no longer errors in the GRUB +payload complaining about missing modules. + +In particular, GRUB now supports LUKSv2. In the Libreboot 20160907 release, it +was necessary to downgrade LUKSv2 to LUKSv1 if you were doing a fully encrypted +Linux installation (where the GRUB payload was expected to decrypt the /boot +directory). + +Keymaps are mostly the same, but now Colemak keyboard layout is supported. It +is possible to add any keymap to GRUB, if you follow the notes in the Libreboot +documentation and then re-build the ROM from source. + +The default GRUB configuration in Libreboot is much more automated now, with +less hardcoded functionality. It's more optimized in general, especially on +ICH7 platforms (e.g. ThinkPad X60, T60). Other features are implemented, such +as automatically booting an installed Linux distro from an external USB +HDD or SSD (or flash drive!) + +In GRUB payloads, SeaBIOS is no longer used to start GRUB, on any platform in +Libreboot. Instead, GRUB is always loaded directly (by coreboot). The effort to +produce a so-called "SeaGRUB" payload has been abandoned. We simply use a +standard SeaBIOS setup now. SeaBIOS is available in the GRUB menu (GRUB can +load and execute any other coreboot payload). + +One could argue that it's a GRUB setup! + +Anyway, Libreboot 20160907 used GRUB at git commit ID +7f2a856faec951b7ab816880bd26e1e10b17a596 March 2016. + +This new Libreboot releases used GRUB c0e647eb0e2bd09315612446cb4d90f7f75cb44c +from May 10th, 2021. + +Download GRUB from the upstream repository and check every commit +since then. + +GM45/X4X now set 352MiB VRAM by default +======================================= + +In the previous Libreboot release, PCI MMIO size was set to 1GiB. It is now +set to 2GiB, allowing for 352MiB VRAM to be allocated when using the onboard +Intel GPUs. It used to be tht 352MiB VRAM was unstable, so the previous +Libreboot release set it to 256MiB. It is now 352MiB, by default. + +The following patch in coreboot allowed that (shortly after the Libreboot +20160907 release in fact!): + + + +Quad-core CPU mod on ThinkPad T500 etc +======================================= + +NOTE: The actual modification (to the hardware) is only documented for T500, +but it should be possible to adapt those instructions for similar GM45 laptops +that have a socketed CPU. + +NOTE: Hardware modifications are required to make quad-core CPUs work. You have +to cut/disable a few signals and solder 1 wire. Look online for ThinkPad T500 +quad core mod. Alongside this hardware mod, the boot firmware also must be +configured to allow for quad core CPUs. This new Libreboot release has such +configuration already enabled, so if you've already performed the modifications +to your hardware then it should Just Work. + +The option `MAX_CPUS=4` is now the default, on these machines in coreboot: + +* ThinkPad R400 +* ThinkPad T400 +* ThinkPad T500 +* ThinkPad R500 +* ThinkPad W500 + +This is necessary, for a special mod that is possible on these machines, to +enable quad-core CPUs (core2quad). + +libgfxinit +========== + +In Libreboot 20160907, *native graphics initialization* was C code implemented +on each platform, and it was very messy, but it *worked*. + +Since that release, coreboot re-wrote the core of its native video +initialization code in Ada and put it in a 3rdparty submodule +called `libgfxinit`. When downloading the `default` coreboot version in +Libreboot (using `./download coreboot default`) you can check the code for +libgfxinit in `coreboot/default/3rdparty/libgfxinit/`, and this is also in the +source code release archive of this Libreboot release. + +The new code is much better, and more reliable. For example, during testing, +some screens on ThinkPad T400 that didn't work in Libreboot 20160907 work +perfectly with libgfxinit in recent coreboot revisions and on the new +coreboot 4.14 release. Other features like VBT are much improved + +The following platforms in Libreboot are now handled by `libgfxinit` for video +initialialization: + +* Intel GM45 (ThinkPad X200, T400, T500, W500, R400, R500, T400S, X200S, + X200T, X301) +* Intel X4X (Gigabyte GA-G41M-ES2L, Acer G43T-AMT3, Intel DG43GT etc) + +From looking at the coreboot source code, it seems that the following platforms +are not yet migrated over to libgfxinit: + +* Intel pineview (Intel D510MO, Gigabyte GA-D510UD, Foxconn D41S) +* Intel i945 (ThinkPad X60, T60, Macbook2,1, Macbook1,1 etc) +* AMD Fam10h / Fam15h (ASpeed AST2050 framebuffer chip used on ASUS KCMA-D8 + and KGPE-D16 - NOTE: these and other AMD boards in Libreboot are currently + stuck on coreboot 4.11) + +The code is much cleaner. Much of the code in coreboot is still written in C, +for *interfacing* with the Ada code. The actual video initialization is handled +with the Ada code, in the libgfxinit submodule. + +Right now there aren't many commits in that repository, so we will just list +them here. You can run `git log` in `3rdparty/libgfxinit` when +running `git submodule update --init` in a coreboot git clone: + +```` +* 8d5c24d (origin/master, origin/HEAD, master) Add support to switch LSPCON modes +* 0a8174b gfx dp_aux: Add I2C_{Read,Write}_Byte procedures +* ae186bd gfx gma skylake: Implement some workarounds +* bc0588e (HEAD) gma: Export backlight control interface +* 994971a gma: actually enable/disable backlight with new backlight control +* dde0630 gma: Add `Cannon_Point` PCH +* e79babd gma: Introduce `PCH_Type` +* c9ad9de gma: Fix setting of `Raw Clock` scratchpad +* 3318bf2 Drop generation suffix from `Power_And_Clocks` +* 450c24c haswell: Make VGA on FDI work +* 3f86b0b Move `PSR_Off` out of `Power_And_Clocks_Haswell` +* c0db994 common/Makefile.inc: Factor out generation TLAs +* 8fc8e49 common/Makefile.inc: eliminate duplicate substitutions +* 2a3dbba gma config: allow override of presence straps +* 2e87c0d gma: Map dummy PTEs for buggy VT-d +* cdbfce2 gma config: Add Comet Lake PCI IDs +* 5dbaf4b gma bxt panel: Allow to use secondary panel control logic +* 1f63d51 gma bxt panel: Correct panel backlight handling +* 3ea5d60 gma bxt panel: Correct power-cycle delay programming +* 7050d2d gma bxt: Add panel power and backlight register definitions +* 2bbd6e7 gma panel: Introduce `Panel_Control` type +* 8a6e7bd gma panel config: Turn `internal display type` into a `panel port` +* 8beafd7 gma: Split `Internal` port type into `eDP` & `LVDS` +* fe7985f gma: Fix GTT size reading for Gen8+ +* a563ec2 gfx_test: Refactor animation loop and handle hotplug events +* 92de9c4 gma display_probing: Add Hotplug_Events() +* b0bbdbc gma: Automatically update CDClk and dot clocks +* 8469b00 gma bxt: Implement CDClk switching +* 6b4678d gma skl: Implement CDClk switching +* d0f84b9 gma hsw: Implement CDClk switching +* 1eb5faa gma ilk: Handle CDClk and calculate dot-clock limits +* b47a5c4 gma g45: Read CDClk and calculate dot-clock limits +* 07ff1b9 gma config: Allow to cache CDClk in variable config state +* 3d3452f dp_info: read eDP 1.4+ DPCD link rates +* 04c1d01 gma ilk hdmi: Add workaround for enable-bit quirk +* f6a2d18 gma ilk: Handle Ibex Peak DP correctly +* 6c10d36 Increase range of our main Frequency_Type +* 530651b gma g45 config: Limit HDMI rate to 165MHz +* a4e7f25 gma i2c: Increase timeout, again +* e317e9c gma: Merge `Config_State` into `State` +* c5c66ec gma: Allow private sub-packages to access PCI config +* 7f3e280 gma: Give GM45 its own designation (separate from G45) +* 9a4c4c3 gma: Refactor Update_Outputs() +* 88da05e gma config_helpers: Add dot-clock helper functions +* 9e96a45 gma config_helpers: Introduce Valid_FB() +* 312433c gma pcode: Move and revise mailbox handling +* 82ca09f gma registers: Implement `Success` parameter for Wait*() +* efa3ca8 gma i2c: Rework GMBUS reset procedure +* 4fc6dc2 gma display_probing: End probing after all ports failed +* 75a707f gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge +* d8282b6 gfx_test: Refactor to allow Restrictions (No_Elaboration_Code) +* a815704 gma bdw+ transcoder: Use always-on path for primary pipe on eDP +* 94fb916 dp training: Write correct training data when switching patterns +* f80c3e4 dp training: Always end with normal output +* 68f439d gma i2c: Increase timeout to >100ms +* c1d2030 gma i2c: Try to clear NAK indicator +* 040d9b6 gma: Publish Read_EDID() +* 2c92794 gma: Add more PCI IDs for Coffee/Whiskey/Amber Lake +* 88badbe gma: Add Kaby Lake support +* 25fdb15 gma: Add support for ULX variants +* d49b56b gma pipe setup: Refactor calculation to ease proof +* b3b9fa3 gma: Fix Ironlake panel fitting, revisited +* 8a9062a gma config: Enable Restrictions (No_Elaboration_Code) +* 6a996dc gma: Implement automatic CPU detection +* adfe11f gma config: Make Config.CPU and Config.CPU_Var variable +* d936561 gma config: Tag constants depending on generation or CPU +* 27088aa gma config: Initialize stateful configs late +* 30e8408 gma config: Group mutable state into a record +* 86445f3 gma pipe setup: Drop explicit Global and Depends contracts +* 63ec836 gma: Give constants depending on Config.CPU* a type +* 63dc919 gma: Turn constants depending on Config.CPU* into functions +* d7809ab gma config: Limit types of CPU and CPU_Var +* 998ee2b gma config: Introduce per CPU booleans +* 6621a14 gma: Introduce Generation type +* c76749d gfx_test: Use GMA.Read_GTT() instead of own GTT mapping +* ceda17d gma registers: Add Read_GTT() procedure +* 0b2329a gma registers: Separate 32- and 64-bit GTT access +* d0d8b79 gma registers: Draw usage of Config.Fence_Count into the code +* 1ee5714 gma broxton power/clocks: Turn pre-condition into code +* ef3b093 gma config: Introduce Has_New_FDI_(Sink|Source) +* 117db37 gma config: Introduce Have_HDMI_Buf_Override +* 318bca1 gma config, port detection: Scatter Valid_Port initialization +* cf88f3d gma: Provide `Global` contracts for public procedures +* 67cf6d8 gma config: Introduce Is_ULT +* f70edda gma pipe_setup: Work around a PFIT_CONTROL quirk on G45 +* d58de7d gma config: Introduce Has_Tertiary_Pipe +* eb4e8f9 gma config: Fix CPU range for Has_PCH_DAC +* 7ba7bd6 gma pipe setup: Add missing `pragma Debug` +* 865f1fa gfx: Introduce Size_Type for framebuffer size in bytes +* c5c767a Use (Width|Height)_Type for modeline sizes +* da1185e gfx, gma pipe_setup: Rewrite Scale_Keep_Aspect +* db68441 gma skylake power/clocks: Refactor to allow proof without inlining +* 57bebc7 gma panel: Refactor to allow proof without inlining +* 8a5a3b5 gma: Add contract to Enable_Output() to rely less on proof inlining +* 5a3191f gma display probing: Use expression functions for less proof inlining +* 7eb1350 edid: Use expression functions to rely less on proof inlining +* 565f33b gma broxton: Tighten types to rely less on proof inlining +* b679013 gfx: Increase range of Frequency_Type +* 718c79b g45/hw-gfx-gma-gmch-hdmi.adb: Use GMCH_HDMI_MODE_SELECT_DVI +* f361ec8 gma: Introduce Pipe_Config.Scaler_Available() +* 958c564 gma: Revise scaling on G45 +* b217ece gfx, gma: Add helper to decide scaling aspect +* 7167746 gfx, gma: Move Requires_Scaling() up into GFX +* 3299ad5 gfx, gma: Move inline functions into private package parts +* ab69e36 gma ironlake..broadwell: Enable X-tiling +* a63e833 gfx_test: Move Cursors +* 7bb10c6 gfx_test: Draw cursors +* 15ffc4f gma: Add interface functions to update/place/move cursor +* 4dc4c61 gma: Configure cursor plane +* a02b2c6 gma: Add cursor infrastructure +* 7a74043 Rename Pos_Type --> Position_Type +* abb16d9 gma hsw transcoder: Choose PDW path for scaling on DDI A +* 3d06de8 gma hsw: Enable Power Down Well for scaling on DDI A +* 73ea032 gma: Add G45 support +* d519844 gma: Add flag to set up GMCH Panel Fitter +* fdb0df1 gma: Fix Ironlake panel fitting +* a455f0e gfx_test: Add loop that shows cuttings of the test image +* f7f537e gma pipe_setup: Replace Update_Offset() with Setup_FB() +* 8fd92a1 gma pipe_setup: Write DSPSURF register last +* cbbaade gma config_helpers: Pass only the modeline to Validate_Config() +* b4b7279 gma pipe_setup: Explicitly disable panel fitter if unused +* 5ef4d60 Add Start_X and Start_Y offsets for framebuffer panning +* 34be654 gma: Reverse meaning of GTT_Rotation_Offset +* 98a673d gma ddi: Move conditionally used Program_Buffer_Translations() +* 60d0e5f gma: Add Pipe_Index to the Connectors.Post_On method +* e87d0d1 gma: Add flag to use GMCH PP registers +* 5d08a93 gma: Add GPU_Port types that are convenient for GMCH to use +* 636390c gma: Add a flag to use GMCH transcoder registers +* 229ed1c gma: Add flag to use GMCH GMBUS registers +* dfcdd77 gma: Add flag to allow use of VGACNTRL on GMCH +* d1988d1 gma: Make Raw_Clock a variable +* 7628493 gfx_test: Update i915 binding in wrapper script +* 9ca69f1 gfx_test: Add top marker for rotated framebuffers +* 88f3c98 gfx_test: Add rotation parameter +* 244ea7e gfx_test: Add corner markers to test screen +* 9b47941 gma: Add support for rotated framebuffers +* b747049 Add Rotation setting to Framebuffer +* 0164b02 gma: Set tiled framebuffers up through Plane_Control +* b03c8f1 gma registers: Add procedures to set fence registers +* 51375ad Add Tiling setting to Framebuffer +* e7ac6eb gma: Implement PCI Id based generation check +* 208857d gma hsw+: Treat DDI E and PCH DAC disabling separately +* 907e415 gma hsw+: Don't use DDI E if DDI A uses all lanes +* 19729a7 gma hsw+: Revise Has_DDI_D flag +* 5fd9a31 gma: Fix decoding the size of Stolen Memory on Gen4 +* 3b654a0 gfx_test: Set our own framebuffers up, update README +* 42fb2d0 gma: Add procedure to power up legacy VGA block +* 3a0e2a0 gma skl: Disable DDI clocks on reset path +* 8540805 gma skl: Prevent race by late timeout check +* 234e772 dp training: Allow to adjust pre-emphasis during clock recovery +* 41b18ca dp training: Fix channel equalization phase +* 1bc496f gma-display_probing: Only check display type on DVI-I +* c3f66f6 gma: Add Map_Linear_FB() +* eedde88 gma: Check that framebuffer fits stolen memory and aperture +* 5374c3a gma: Add Setup_Default_FB() +* 194e57e gma: Allow offsets /= 0 in Setup_Default_GTT() +* bebca13 gma: Move a warning justification to spec +* e015e82 gma: Fix refined contract of Initialize() +* 17d64b6 gma: Clear "fence" registers during initialization +* 2b6f699 gma: Add a HW.PCI.Dev for dynamic MMIO setup +* b8ae618 gma: Move GTT constants into GMA.Config +* fda2d6e gfx_test: Update to use *libhwbase* new PCI interface +* 58afc20 gma skl: Add I_boost configuration +* 18ff0c1 gma skl: Add DDI buffer translations +* 730f17c gma hsw bdw: Add DDI buffer translations +* 01b680f gma hsw+: Add boilerplate for DDI buffer translations +* 247adf3 gma hsw+: Add default value for HDMI buffer levels +* 0923b79 gma-connectors: Add Initialize() procedure +* fb4f8ce Add a README describing libgfxinit and the build process +* 1d0abe4 Add linux user-space app `gfx_test` +* 3586101 gma: Juggle with types of a precondition +* 1c3b928 gma broxton: Add final glue +* fdd9365 gma broxton: Add signal level control for DDI PHYs +* afadcac gma broxton: Implement pre-PLL setup for DDI PHYs +* 4b0239f gma broxton: Fill in port PLL configuration +* f626600 gma broxton: Implement DDI PHY power handling +* 4082044 gma broxton: Start off with power domains and CDClk +* 21da574 gma: Add config plus stubs for Broxton SoC +* b83107c common/hw-gfx-gma: Remove trailing space in debug output +* 799752f configs: Escape hash characters +* ac455ad gma ddi: Don't try to disable non-existent DDI D +* bcb2c47 gma registers: Add generic Wait() procedure +* 31a5217 gma: Justify some use-visibility warnings +* 8fb0f31 gma: Do not check for hot-plug events on analog port +* 4c7356d gma: Add option to keep port power after Scan_Ports() +* 4798c66 gma: Always clear hot-plug events before enabling a pipe +* 564103f gma: Rework power handling in Update_Outputs() +* b56b9c5 gma: Disable all stale pipes before enabling any new +* 3be61d4 gma: Refactor Hotplug_Detect() interface and usage +* 43370ba gma: Factor enabling of a single pipe out of Update_Outputs() +* 1a712d3 gma: Drop state tracking of active `DP_Links` +* af9cc9e dp_info: Refactor debug output for DP settings +* 6e327c9 gma: Get rid of Get_Pipe_Hint() +* 7ad2d65 gma: Move transcoder setup into own package +* 113a14b gma pipe_setup: Untangle pipe and transcoder config +* 33912aa gma: Move Legacy_VGA_Off() into Pipe_Setup +* f3e2366 gma: Move pipe/transcoder register selection into Pipe_Setup +* 02cfbb3 gma: Choose FDI-link settings after mode determination +* d6d6f6b gma config: Fix framebuffer alignment check +* 793a8d4 gma: Make cleaning the hardware state optional +* 6a4dfc8 gma skl: Use framebuffer size as plane source size +* 7892ff6 gma ironlake: Reorder panel power handling +* 6f9a50d gma-display_probing: Enable panel power early +* 8c45bcf gma: Split out config derivation and port probing +* 3c544ee gma: Refactor Port_Config derivation +* 6b7a40b gma: Probe sibling ports for improper connected displays +* 845de36 gma: Do not probe EDID if a port's sibling is configured +* 1b2c9a3 gma: Refactor Scan_Ports() +* 995436b gma: Get rid of Port_Config in Read_EDID() +* dca242d gma: Drop Auto_Configure() +* 0d454cd gma: Rename ports Digital[123] => HDMI[123] +* 99f10f3 gma: Rename Config_Type => Pipe_Config +* 43cf8d5 gma haswell: Turn comment into sane code +* 88a7f17 edid: Sanitize bad EDID header patterns +* aa91bb5 gma: Add parameter to Scan_Ports to limit number of pipes +* 74ec962 gma: Limit HDMI pixel rate +* fbb4220 gma: Implement Ivy Bridge VGA plane workaround +* 3675db5 gma: Add option for VGA plane on the primary pipe +* 4916e34 gma: Configure panel fitter / pipe scaler +* 770fe4a gma: Use framebuffer size as pipe source size +* 47ff069 gma: Show that we never try to downscale the image +* dcd274b gma: Validate maximum scalable width +* c7a4fee gma: Validate pipe configurations +* 6a35667 gma: Fix loop logic in Scan_Ports() +* d55afeb gma i2c: Make I2C port for VGA displays a config option +* 393aa8a gma edid: Check expected display type +* abe3de2 gma dp aux: Program 2x bit clock divider +* f54d096 gma: Program PCH_RAWCLK_FREQ register +* 125a29e Relicense libgfxinit under GPL v2+ +* be4eadd gma pch lvds: Fully initialize port register +* 16f3dec edid: Correctly initialize BPC if it's unset in EDID +* 2600c36 common/Makefile: Avoid double slashes in generated paths +* 3e50827 Strip quotes from config variables to be Kconfig compatible +* eeb5a39 gma: Expect zero Audio_VID_DID on Ibex Peak +* 83693c8 Initial upstream commit +```` + +coreboot release logs +===================== + +The following is a page linking to release logs for coreboot, upstream:\ + + +In this section, we will explore the entries (from coreboot release logs) that +are most relevant to Libreboot. Roughly speaking, Libreboot 20160907 (the +previous release, 4 years and 8 months ago) used revisions of coreboot near or +around coreboot version 4.4 and 4.5, depending on the board. + +coreboot 4.14 +------------- + +Lots of random fixes, too many to list. Instead, see git logs on this page for +specific boards/platforms. + +This release of coreboot focused mostly on adding new boards, and none of them +are suitable for Libreboot at the present time. (except for Pine64 Rockpro64, +which is a candidate for Libreboot, but more research is needed on it) + +However, the following fixes were made for Lenovo X200 recently: + +* +* + +coreboot 4.13 +------------- + +* Mostly re-factoring and minor bug fixes, but it has some interesting fixes + that benefit libreboot +* Acer G43T-AM3 mainboard added. This is also in the Libreboot release. This + board was also present in Libreboot, prior to it updating to use coreboot + 4.14, but now it is in the latest coreboot stable release +* Initial support for x86\_64. Not yet used by Libreboot, but it might be + interesting in the future on x86 targets +* New resource allocator: enables more efficient use of memory during bootup + +coreboot 4.12 +------------- + +* SMMSTORE is now a thing. See: . + This is relevant for Tianocore, a UEFI payload, which libreboot currently + does not integrate for any boards, but Tianocore integration is planned in + the future. Tianocore provides the option to use any UEFI-compliant operating + system, and this benefits Linux distributions aswell (it Just Works). + SMMSTORE is basically UEFI's answer to CMOS "NVRAM". it is a way to store + configurations, in SPI flash. it's handled via SMM interrupts (SMIs). NOTE: + SMMSTOREv2 is also becoming a thing now + +coreboot 4.11 +------------- + +* C\_ENVIRONMENTAL\_BOOTBLOCK is now preferred, instead of the old romcc + bootblocks. i945, x4x and gm45 platforms have been adapted to use this (this + affects almost every libreboot target) +* vboot support for gm45 (but libreboot currently doesn't do anything with it) +* Generally, this was another "code cleanup release" of coreboot. A lot of code + in coreboot was re-factored + +coreboot 4.10 +------------- + +* nothing noteworthy to libreboot, this was mainly a "code cleanup" release in + coreboot + +coreboot 4.9 +------------ + +* Less repetition in the codebase, for similar boards. For example, X200 + thinkpad is its own codebase, and similar boards are "variants" where only + the differences are implemented (e.g. X301 thinkpad support). similar for + T400 thinkpad: T500, W500, R500 etc are implemented as variants nowadays +* Intel X4X platform: Add DDR3 support (raminit) +* + +coreboot 4.8 +------------ + +* Improved VBT implementations in libgfxinit +* i945 (X60/T60/macbook21 etc): native video initialization is now skipped + during resume from S3 (sleep mode). This means that the OS needs to handle it + now. The i915 video driver in the linux kernel can handle it, but at the time + of this coreboot release, the framebuffer driver couldn't. this will need to + be tested! + +coreboot 4.7 +------------ + +* GM45 laptops: set display backlight PWM correctly +* Add romstage timings +* raminit: improved compatibility with mixed DIMMs +* Intel X4X: fix booting with FSB800 DDR667 combination +* Intel X4X: Rework ram DQZ receiver enable training sequence +* Intel X4X: Rework and fixSPD reading and decoding +* Intel X4X: Allow external GPU to take VGA cycles + +coreboot 4.6 +------------ + +* fix buggy S3 suspend/resume on Gigabyte GA-G41M-ES2L mainboard, and fix bugs + in raminit +* intel x4x/gm45/i945 boards: improvements/fixes to raminit and native video + initialization +* all platforms: video init re-written. old code was in C, new code is in Ada, + with many improvements in general +* nb/i945/raminit: Add fixes for 800MHz & 1067MHz FSB CPUs +* nb/intel/gm45: Fix panel-power-sequence clock divisor + + +Detailed coreboot git logs +========================== + +The following are lists of changes in coreboot 4.14, versus coreboot revisions +used in various platforms/mainboards from Libreboot 20160907. These lists are +mostly pulled directly from the coreboot git log. + +These logs are made by copying the coreboot git log, on specific directories +such as directories for mainboards, or entire platforms, in the git log of +coreboot. + +These changes will be split into distinct categories: + +* Northbridge changes +* Southbridge changes +* Board-specific changes + +There are many other aspects of coreboot that can be shown here, but it's not +useful to list all of them. Listing just the platform/board changes gives an +excellent picture overall. + +Northbridge changes +------------------- + +For all intents and purposes, the northbridge and southbridge code *is* the +platform for a given board, and then you have board specific code. + +### git log src/northbridge/intel/i945/ + +This mainly benefits the ThinkPad X60, T60, Macbook2,1, Macbook1,1 and other +i945 hardware that Libreboot supports. + +```` +* 88dcb3179b src: Retype option API to use unsigned integers +* c8116f6ea0 nb/intel: Don't select VBOOT_SEPARATE_VERSTAGE +* f9c939029b nb/intel: Use get_int_option() +* 1d4044ae88 nb/intel/i945: Use new fixed BAR accessors +* e97a66d371 nb/intel/i945/raminit.c: Replace `DIMM0` +* a60b42a26a nb/intel/i945: Refactor `dump_spd_registers` function +* b238caaaca device/device.c: Rename .disable to .vga_disable +* 98f7d60d97 nb/intel/i945: Use UPMC4 macro +* 030d338bb2 nb/intel: Add missing +* 8f20b12c95 nb/i945/raminit.c: Don't hard code 'bool integrated_graphics' +* 6f35c53bbb src/nb: Remove unused +* 4299cb4829 nb/intel/i945: Use common {DMI,EP,MCH}BAR accessors +* b70ff52b83 intel: Define `RCBA_LENGTH` in Kconfig and use it +* 6e732d34a0 intel: Turn `DEFAULT_RCBA` into a Kconfig symbol +* 37cae54034 nb/intel/x/bootblock.c Revert `include ` +* 00b5f53361 treewide [Kconfig]: Remove useless comment +* 487c1a24f5 nb/intel/i945/bootblock.c: include +* 9b04f56d4a nb/intel/i945: Drop casts from DEFAULT_{MCH,DMI}BAR +* a6b0922aa1 nb/intel/i945: Define and use MMCONF_BUS_NUMBER +* 7d638784a2 device/Kconfig: Declare MMCONF symbols' type once +* 15ef9b6513 nb/intel/i945/northbridge.c: Reserve upper part of lower memory +* a6e4afc1cb nb/intel/i945/northbridge.c: Improve readability +* c6589aefc1 drivers/intel/gma: Include gfx.asl by default for all platforms... +* 8b56c8c6b2 drivers: Replace set_vbe_mode_info_valid +* 02a23b510c nb/intel/i945: Introduce memmap.h +* 92f46aaac7 src: Include when appropriate +* e298391337 nb/intel/i945/acpi: Convert i945.asl to ASL 2.0 syntax +* dddd1cc691 src/northbridge: Drop unneeded empty lines +* 4a2f08c846 nb/intel/i945: Deduplicate PCIEXBAR decoding +* cff4d1649f nb/intel/i945: Refactor `get_pcie_bar` +* c96292492c nb/intel/i945/gma.c: Remove extra indentation +* f48acbda7b src: Change BOOL CONFIG_ to CONFIG() in comments & strings +* 3580d816e6 nb/intel/i945: Put names to northbridge PCI devices +* 81c9c275e6 nb/intel/i945: Drop dead code +* f67bf49ead nb/intel/i945: Use ASL 2.0 syntax +* 837141fa56 nb/intel/i945/acpi: Tidy up comments and cosmetics +* 1a1b04ea51 device/smbus_host: Declare common early SMBus prototypes +* f3973bd4cf i945 boards: Factor out MAX_CPUS +* 22aeed307d nb/intel/i945/rcven.c: Correct comment +* 304925714d nb/intel/i945: Clean up raminit coding style +* e3c68d2e1b nb/intel/i945: Use PCI bitwise ops +* 1fc0edd9fe src: Use pci_dev_ops_pci where applicable +* dd59762729 intel/gma: Only enable bus mastering if we are going to use it +* dfdf102000 intel/gma: Don't bluntly enable I/O +* f2a0be235c drivers/intel/gma: Move IGD OpRegion to CBMEM +* 7cf96aeeb7 northbridge/intel/i945: Mark legacy VGA memory as reserved +* c4b70276ed src: Remove leading blank lines from SPDX header +* 6b5bc77c9b treewide: Remove "this file is part of" lines +* c49d7a3e63 src/: Replace GPL boilerplate with SPDX headers +* 36787b0e7b northbridge/*/Kconfig: Replace GPLv2 long form headers with SPDX header +* f49f4d48ba nb/intel/i945/memmap: Convert to 96 characters line length +* 76cedd2c29 acpi: Move ACPI table support out of arch/x86 (3/5) +* 7536a398e9 device: Constify struct device * parameter to acpi_fill_ssdt() +* 0f007d8ceb device: Constify struct device * parameter to write_acpi_tables +* 48d5b8d463 nb/intel/i945: Add vboot support +* 3dff32c804 nb/i945: Improve code formatting +* 2f8ba69b0e Replace DEVICE_NOOP with noop_(set|read)_resources +* a461b694a6 Drop unnecessary DEVICE_NOOP entries +* 961658f3dc nb/intel/i945: Use 'const' to set pci_devfn_t statically +* 4b42983c7a src/northbridge: Use SPDX for GPL-2.0-only files +* deeccbf4e9 Drop explicit NULL initializations from `device_operations` +* fd054bc7d4 nb/intel/i945: Simplify GMA SSDT generator +* 68680dd7cd Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator` +* 95cdd9f21b nb/intel/i945: Make some cosmetic changes +* f3f36faf35 src (minus soc and mainboard): Remove copyright notices +* b4d9f229d4 nb/intel/i945/raminit: Simplify if condition +* d789b658f7 nb/intel/i945/raminit: Use boolean type for helper variables +* 842dd3328d nb/intel/i945/raminit: Remove space for correct alignment +* 8273e13a11 intel/i945: Call fixup_i945_errata() only for mobile version +* 3cd4327ad9 src/nb: Use 'print("%s...", __func__)' +* 8247cc3328 northbridge: Remove unused include +* 2119d0ba43 treewide: Capitalize 'CMOS' +* ef90609cbb src: capitalize 'RAM' +* e0cd2eb6d3 nb/intel/i945: Use boot path macros +* 7adc370dc7 intel/{i945,pineview},i82801gx: Move enable_smbus() call +* 0c9630eeff nb/intel/{i945,sandybridge}/bootblock.c: Fix typo +* bd65985a63 nb/intel/{i945,x4x,pineview}: Remove wrapper spd_read_byte() +* cbf9571588 drivers/pc80/rtc: Separate {get|set}_option() prototypes +* dc987fecce src/northbridge: Remove unused +* de64078102 bootblock: Provide some common prototypes +* 442fb05acf nb/{haswell,i945,sandybridge}: Drop outdated comment +* 13746076e9 mainboard/(i945,ich7): Remove commented RCBA32(0x341c) code +* 8cb5ea7879 nb/i945: Fix typo +* c05b1a66b3 Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbol +* c583920a74 nb/intel/i945: Initialize console in bootblock +* e27c013f39 nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCK +* dc584c3f22 nb/intel/i945: Move boilerplate romstage to a common location +* 399b6c11ef sb/intel/i82801gx: Add common early code +* b236352281 sb/intel/i82801gx: Add a function to set up BAR +* 4ec67fc82c nb/intel: Use defined DEFAULT_RCBA +* 340e4b8090 lib/cbmem_top: Add a common cbmem_top implementation +* c7783a39f8 nb/intel: Remove unused 'barrier()' +* fcdb03358d acpi: Drop wrong _ADR objects for PCI host bridges +* f9891c8b46 kontron/986lcd-m,roda/rk886ex: Drop secondary PCI reset +* ad787e18e0 intel/i945,i82801gx: Refactor early PCI bridge reset +* 2647b6f9ba intel/i945: Define peg_plugin for potential add-on PCIe card +* 9137cbd5e4 intel/i945: Delay bridge VGA IO enable to ramstage +* 444d2af9a9 intel/i945: Define p2peg for PCIe x16 slot +* df128a55b1 intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL +* e39becf521 intel/cpu: Switch older models to TSC_MONOTONIC_TIMER +* 10348399a6 {i945,i82801gx}: Remove unneeded include +* 1e3d16e8d1 nb/i945: Remove unused include +* d53fd704f2 intel/smm/gen1: Use smm_subregion() +* cd7a70f487 soc/intel: Use common romstage code +* a963acdcc7 arch/x86: Add +* f091f4daf7 intel/smm/gen1: Rename header file +* 544878b563 arch/x86: Add postcar_frame_common_mtrrs() +* 5bc641afeb cpu/intel: Refactor platform_enter_postcar() +* b3267e002e cpu/intel: Replace bsp_init_and_start_aps() +* 0f5e01a962 arch/x86: Flip option NO_CAR_GLOBAL_MIGRATION +* 9fc12e0d4e arch/x86: Enable POSTCAR_CONSOLE by default +* 0a4457ff44 lib/stage_cache: Refactor Kconfig options +* fe481eb3e5 northbridge/intel: Rename ram_calc.c to memmap.c +* bccd2b6c49 intel/i945,gm45,pineview,x4x: Fix stage cache location +* aba8fb1158 intel/i945,gm45,pineview,x4x: Move stage cache support function +* 8881d57531 nb/i945/gma: Store vga_disable if MAINBOARD_DO_NATIVE_VGA_INIT +* 4593d66a20 nb/i945: Fix gate graphics hardware for frequency change +* 7fbed223c7 intel/i945: Fix udelay() prototypes +* 8abf66e4e0 cpu/x86: Flip SMM_TSEG default +* 6e2d0c1b90 arch/x86: Adjust size of postcar stack +* 3bf4e28fb8 nb/i945: Drop CHANNEL_XOR_RANDOMIZATION selection +* 51401c3050 src/northbridge: Add missing 'include ' +* 686b539949 i945: Add device identification D2:F1 +* 274dabd7a0 src/northbridge: Remove unneeded include +* 32b9a99e16 nb/intel/i945: Use macro instead of magic number +* 45b824d694 src: Remove unused include +* 5db9871a5e ich7/i945: Use system_reset() +* 01912201a4 nb/intel/i945: Check if interleaved even if rank #4 size is zero +* 420d7e009d ich7/i945: Use full_reset() +* b217baa4ee nb/intel/i945: Fix ich7_setup_root_complex_topology +* f74f6cbde5 nb/intel/{gm45,i945,x4x}: Correct array bounds checks +* 5d1f9a0096 Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX) +* 346d201d73 nb/intel/i945: Use DEBUG_RAM_SETUP +* 4a0f07166f {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem() +* a1e22b8192 src: Use 'include ' when appropriate +* 3449fafec3 nb/intel/i945: Remove 2nd write on SLOTCAP (R/WO) +* e183429bd2 nb/intel/stage_cache.c: Drop unnecessary includes +* cd49cce7b7 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) +* 89989cf61f src: Drop unused include +* 503d3247e4 Remove DEFAULT_PCIEXBAR alias +* 13f66507af device/mmio.h: Add include file for MMIO ops +* 065857ee7f arch/io.h: Drop unnecessary include +* 2796b242b2 nb/intel/i945: Remove redundant use of ACPI offset operator +* f1b58b7835 device/pci: Fix PCI accessor headers +* c01a505282 sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read() +* d3fa7fa5d8 nb/intel/i945: Fix typo on DMIBAR32(0x334) +* 3452eca26d nb/intel/i945: Remove initialization already done at bootblock +* dce3927f20 nb/intel/i945: Put stage cache in TSEG +* 1a9034cca6 i945,ICH7: Write on RPFN only once +* f266932836 nb/intel/i945: Use parallel MP init +* b31aee9973 nb/intel/{i945,pineview}: Remove unused function +* c2c1dc9c76 {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem() +* 4e008c699b nb/intel/i945: Reduce pcidev_on_root() calls +* c70eed1e62 device: Use pcidev_on_root() +* 1f4cb326fa northbridge: Remove useless include +* cf3076eff1 nb/intel/i945: Use common SMM_TSEG code +* a6634f1f78 nb/intel/i945: Add and use defines for registers of device 0:01.0 +* a9068aa4e0 nb/intel/i945/early_init.c: Correct the PEG_LC address of DEV(0:01.0) +* 68aed91eb9 intel/i945: Fix booting on a dual channel configuration +* 8a5283ab1b src: Remove unneeded include +* f765d4f275 src: Remove unneeded include +* e9a0130879 src: Remove unneeded include +* ead574ed02 src: Get rid of duplicated includes +* d2b9ec1362 src: Remove unneeded include "{arch,cpu}/cpu.h" +* 771328f7df intel/i945: add timestamps in romstage +* 2a1c4302d1 nb/intel/i945: Remove irrelevant conditional statement +* d522db048b nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware +* 17ad4598e9 nb/intel/*: Account for cbmem_top alignment +* 794f56bdf5 nb/intel/i945: Fix domain resources +* d44221f9c8 Move compiler.h to commonlib +* ef20ecc92b nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address +* e6c8f7ec20 nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled +* 1faa11ed39 Fix PCI ACPI _OSC methods +* 64f6b71af5 src/northbridge: Fix typo +* a4fc7bef7f nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMs +* a8a9f34e9b sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables +* fe2510764d nb/intel/i945: Remove dead code +* e07df9d783 nb/intel/i945: Enable and allocate 8M for TSEG +* f6d14773b2 nb/intel/i945: Add a common function to compute TSEG size +* 730df3cc43 arch/x86: Make RELOCATABLE_RAMSTAGE the default +* 2dcc3a5c68 nb/intel/i945: Switch to POSTCAR_STAGE +* 089b9089c1 nb/intel: Use postcar_frame_add_romcache() +* f369e60329 northbridge/intel: Remove unneeded includes +* 654cc2fe10 {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate +* 5474eb15ef src/northbridge: Add and update license headers +* 9749a85cb0 nb/intel/i945/raminit.c: Remove not necessary braces {} +* 96184e9f2d nb/intel/i945/bootblock.c: Correct comment +* 3de303179a {mb,nb,soc}: Remove references to pci_bus_default_ops() +* 658a9348f0 nb/intel/i945: Get rid of device_t +* 5e7ad65f6f nb/intel/i945/gma: Skip native VGA init for ACPI S3 resume +* b23833fb29 nb/intel/i945/gma: Factor out code to new `gma_ngi()` +* c8412ed1f9 nb/intel/i945/gma: Log native graphics init in level INFO +* 82683c0d6d nb/intel/i945/gma: Fix aligment of equal sign +* bcf9a0a7ab nb/intel/i945/gma: Log configured VGA mode +* fc31e44e47 device/ddr2,ddr3: Rename and move a few things +* 8324d87bf4 nb/intel/i945: Use ESMRAMC instead of 0x9e +* 242ea84b01 intel: Replace msr(0x198) with msr(IA32_PERF_STATUS) +* f6aa7d94c8 nb/intel/*/gma: Port ACPI opregion to older platforms +* 5661945c3b nb/i945/raminit: Don't fall back to smbus read on failed SPD decode +* 105e368247 nb/intel/i945: Add space after comma in log message +* 0ab4904481 nb/i945/raminit: Use common ddr2 decode functions +* 5c84f87fcf nb/intel/i945/early_init.c: Replace numbers with macros +* 5613b175de nb/intel/i945/raminit.c: Replace numbers with macros +* 0b80bd1cf4 nb/intel/i945: Clear timeout bits after disabling watchdog +* 250272340b nb/intel/i945/raminit.c: Refactor tRD selection +* 8da2286885 nb/intel/*/gma.c: Use macros for GMBUS numbers +* 6a00113de8 Rename __attribute__((packed)) --> __packed +* 8868fc616c nb/intel/i945/gma.c: Remove redefined "DISPPLANE_BGRX888" +* 692e7df6c1 nb/intel/i945/gma.c: Add whitespace around '<<' +* 33232604a7 nb/intel: add IS_ENABLED() around Kconfig symbol references +* 6d8266b91d Kconfig: Add choice of framebuffer mode +* 7971582ec4 Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFER +* ce642f08b9 Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG +* c5fba2c17c nb/intel/i945: Define and use a default MMCONF_BASE_ADDRESS +* 2f6b52e3a0 nb/intel/i945: Fix PEG port on 945gc +* 46cf5c29b3 nb/intel/i945: Move INTEL_EDID +* b45bbb253f nb/intel/i945: Fix SPD dumps +* 70a8e34853 nb/intel/i945: Fix errors found by checkpatch.pl +* 8e079000dc nb/i945/gma.c: Refactor panel setup +* 44a3066015 nb/i945: Clean "Programming DLL Timings" function +* 308aefffc6 nb/intel/i945: Fix sdram_enhanced_addressing_mode for channel1 +* bce7e33f23 intel/i945: Fix up whitespace and indentation +* 39bfc6cb13 nb/i945/raminit.c: Fix dll timings on 945GC +* 75da1fb2ba nb/i945/raminit: sdram_set_channel_mode Test if DIMM slot 3 is populated +* d81078d944 nb/i945/gma.c: Remove writes to FIFO Watermark registers +* 85cfddb4b4 nb/i945/gma.c: Change name and type of mmiobase in functions argument +* 561bebfbaa drivers/intel/gma/vbt: Add Kconfig symbol for SSC ref +* 186e9c4313 nb/i945/raminit.c: Use Makefile.inc instead of '#include rcven.c' +* 1853781748 nb/intel/945gc: Hardcode the integrated graphic frequencies +* 6d0c65ebc6 nb/intel/*/northbridge.c: Remove #include +* 62902ca45d sb/ich7: Use common/gpio.h to set up GPIOs +* f7acdf82cb nb/i945/early_init.c: Add FSB800 and 1067 to Egress Port Virtual Channel +* 885c289bba nb/intel/i945: Make pci_mmio_size a devicetree parameter +* 122e5bc6b1 intel i945 gm45 x4x: Switch to RELOCATABLE_RAMSTAGE +* 8183025be9 intel/i945: Use romstage_handoff for S3 +* 823020d56b intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup +* 811932a614 intel i945 gm45 x4x: Apply cbmem_top() alignment +* 27198ac2e3 MMCONF_SUPPORT: Drop redundant logging +* e25b5ef39f MMCONF_SUPPORT: Consolidate resource registration +* 3d15e10aef MMCONF_SUPPORT: Flip default to enabled +* 6f66f414a0 PCI ops: MMCONF_SUPPORT_DEFAULT is required +* d9e654321c nb/i945/raminit.h: Fix fsb_frequency's comment +* 533a3859c8 nb/intel/i945/gma: Declare count variable outside 'for' loop +* bac0fad408 Remove explicit select MMCONF_SUPPORT +* 128c104c4d nb/intel: Fix some spelling mistakes in comments and strings +* a4ffe9dda0 intel post-car: Separate files for setup_stack_and_mtrrs() +* 5db945062c nb/intel/i945/early_init.c: Add DDR2-667 detection for 945GC +* 6372a0eef1 nb/intel/i945/early_init.c: Use "IS_ENABLED(CONFIG_ ....)" +* f3f4bea6b5 nb/i945/gma.c: use an if else statement for use of native init +* d0e0118be8 nb/i945/gma.c: Do not try to load vbios when selecting native init +* a299345f4a nb/intel/i945/gma.c: Homogenize code for PCI IDs. +* 04be6b5949 nb/intel/i945: Add PCI id for I945GC +* c057a0611b nb/i945/gma.c: Set the MSAC register correctly +* a6b0fc9d7c nb/i945/Kconfig: select the correct VGA_BIOS_ID for 945GC +* 9c5fc62f96 nb/i945/gma.c: use IS_ENABLED instead of #if, #endif +* 8b6df62fc2 nb/i945/raminit: Add fix for clock crossing for 800MHz FSB CPU +* e189761603 nb/i945/raminit: Add fix for 1067MHz FSB CPUs +* 75f9131453 nb/i945,gm45,x4x/gma.c: fix unsigned arithmetics +* c8c73a68be nb/i945/gma.c: correct VSYNC end offset +* 62f4dad88d i945/gma.c: Only init LVDS if it is detected +* 7141ff3b9f nb/intel/*/graphic_init: use sizeof instead of hardcoding edid size +* 626f8c8440 i945/raminit.c: correctly write CLKCFG for 945GC +* c9848a82e2 intel/i945: Use "IS_ENABLED" for fsbclk & memclk +* 7db506c3dd src/northbridge: Remove unnecessary whitespace +* 0b9ecb5831 mb/intel/d945gclf: Allow use of native graphic init +* b59bcb2d5f i945/gma.c: add native VGA init +* 7dfc8a5ebd i945/gma.c: use linux code to calculate divisors +* 333176e5d3 i945/gma.c: Generate fake VBT +* 0a15fe9299 northbridge/intel/i945: Add space around operators +* a1e1e5c7e3 i945.h: fix #include path +* 6e8b3c1110 src/northbridge: Improve code formatting +* 70f5b825c6 northbridge/intel/i945: transition away from device_t +* 12df950583 northbridge/intel: Add required space before opening parenthesis '(' +* 874a8f961f i945: Enable changing VRAM size +* 38424987c6 src/northbridge: Remove unnecessary whitespace before "\n" and "\t" +* 15279a9696 src/northbridge: Capitalize CPU, RAM and ROM +* e6b5a4f5f0 intel/i945: Use common ACPI S3 recovery +* a969ed34db Move definitions of HIGH_MEMORY_SAVE +* c7a1a3e994 northbridge/i945/gma: Re-enable NVRAM tft_brightness +```` + +### git log src/northbridge/intel/pineview/ + +This benefits the Intel D510MO / D410PT mainboards, and any other pineview +board that Libreboot has added or will add. + +```` +* 88dcb3179b src: Retype option API to use unsigned integers +* f9c939029b nb/intel: Use get_int_option() +* 11cabea60d nb/intel/pineview: Replace remaining BAR accessors +* 0aeaee7d9d nb/intel/pineview: Use new fixed BAR accessors +* 7720f1da36 nb/intel: Factor out remaining MCHBAR macros +* 07ccc8d9cd nb/intel/pineview: Correct COMP register write +* e7a68ec05a nb/intel/pineview/raminit.c: Correct clkset1 programming +* 7ee1c47cba nb/intel/pineview: Correct HICLKGTCTL write +* 7383318856 nb/intel/pineview: Drop MCHBAR macro from DMIBAR access +* ff254ea60b nb/intel/pineview: Drop unused `GPIO32` macro +* 030d338bb2 nb/intel: Add missing +* 24b1d8af06 nb/intel/pineview: Use common {DMI,EP,MCH}BAR accessors +* 94eea6fe16 nb/intel/pineview: Rewrite hex values in lowercase +* 896a1f7609 nb/intel/pineview: Delete rude and useless comment +* 12d3768ec5 nb/intel/pineview: Clean up FIXMEs in raminit +* f1f560568b nb/intel/pineview: Guard {MCH,DMI,EP}BAR macros +* b70ff52b83 intel: Define `RCBA_LENGTH` in Kconfig and use it +* 6e732d34a0 intel: Turn `DEFAULT_RCBA` into a Kconfig symbol +* 00b5f53361 treewide [Kconfig]: Remove useless comment +* 1318ab475d nb/intel/pineview: Define and use MMCONF_BUS_NUMBER +* 7d638784a2 device/Kconfig: Declare MMCONF symbols' type once +* 4338ae3194 nb/intel/pineview/northbridge.c: Fix overlapping resources +* 95a1142019 nb/intel/pineview/northbridge.c: Improve readability +* eef4343a9f nb/intel/pineview: Extract HPET setup and delay function +* c6589aefc1 drivers/intel/gma: Include gfx.asl by default for all platforms... +* baf27dbaeb cbfs: Enable CBFS mcache on most chipsets +* ac12976f0c nb/intel/pineview: Fix clearing memory +* 8f0b3e546a nb/intel/pineview: Place raminit definitions in raminit.h +* dddd1cc691 src/northbridge: Drop unneeded empty lines +* 6549661b9c nb/intel/pineview: Guard DMIBAR/EPBAR macro parameters +* d25e2f6c80 nb/intel/pineview/iomap.h: Rename to memmap.h +* a4dd33cc8b src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers +* 90de10c17a nb/intel/pineview: Refactor `decode_pcie_bar` +* 653d8717ba nb/intel/pineview: Change signature of `decode_pciebar` +* 69356489fe nb/intel/pineview: Use `MiB` definition +* aaf5b09a5a nb/intel/pineview: Remove dead assignments +* 0a760cd05b nb/intel/pineview/hostbridge_regs.h: Clean up registers +* 0ddc2459bc nb/intel/pineview: Put host bridge registers into its own file +* 5f201ef866 nb/intel/pineview/acpi: Remove unmatched comment start +* bfc80098da nb/intel/pineview: Convert to ASL 2.0 syntax +* 4d962b2ecf nb/intel/pineview: Tidy up comments and cosmetics +* ec5b71ae30 nb/intel/pineview: Drop undefined function declaration +* 1a1b04ea51 device/smbus_host: Declare common early SMBus prototypes +* 26766fd85d nb/intel/pineview: Use PCI bitwise ops +* 1fc0edd9fe src: Use pci_dev_ops_pci where applicable +* dd59762729 intel/gma: Only enable bus mastering if we are going to use it +* dfdf102000 intel/gma: Don't bluntly enable I/O +* f2a0be235c drivers/intel/gma: Move IGD OpRegion to CBMEM +* 5ac723e5a4 nb/intel: Fix 16-bit read/write PCI_COMMAND register +* c4b70276ed src: Remove leading blank lines from SPDX header +* 6b5bc77c9b treewide: Remove "this file is part of" lines +* c49d7a3e63 src/: Replace GPL boilerplate with SPDX headers +* 36787b0e7b northbridge/*/Kconfig: Replace GPLv2 long form headers with SPDX header +* ac9590395e treewide: replace GPLv2 long form headers with SPDX header +* 02363b5e46 treewide: Move "is part of the coreboot project" line in its own comment +* 76cedd2c29 acpi: Move ACPI table support out of arch/x86 (3/5) +* 2d7173d462 src: Remove unused 'include ' +* 0f007d8ceb device: Constify struct device * parameter to write_acpi_tables +* 2f8ba69b0e Replace DEVICE_NOOP with noop_(set|read)_resources +* a461b694a6 Drop unnecessary DEVICE_NOOP entries +* 4b42983c7a src/northbridge: Use SPDX for GPL-2.0-only files +* deeccbf4e9 Drop explicit NULL initializations from `device_operations` +* affd771ba3 nb/intel/pineview: drop intel_gma_get_controller_info() +* 68680dd7cd Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator` +* f3f36faf35 src (minus soc and mainboard): Remove copyright notices +* 39ff703aa9 nb/intel/pineview: Clean up code and comments +* 8247cc3328 northbridge: Remove unused include +* 2119d0ba43 treewide: Capitalize 'CMOS' +* ef90609cbb src: capitalize 'RAM' +* 7adc370dc7 intel/{i945,pineview},i82801gx: Move enable_smbus() call +* bd65985a63 nb/intel/{i945,x4x,pineview}: Remove wrapper spd_read_byte() +* cbf9571588 drivers/pc80/rtc: Separate {get|set}_option() prototypes +* 1f66809111 src: Remove unneeded 'include ' +* 748caed022 northbridge: Add missing include +* f97c1c9d86 {nb,soc}: Replace min/max() with MIN/MAX() +* dc987fecce src/northbridge: Remove unused +* de64078102 bootblock: Provide some common prototypes +* c05b1a66b3 Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbol +* 399b6c11ef sb/intel/i82801gx: Add common early code +* b236352281 sb/intel/i82801gx: Add a function to set up BAR +* 4ec67fc82c nb/intel: Use defined DEFAULT_RCBA +* 340e4b8090 lib/cbmem_top: Add a common cbmem_top implementation +* 34715df801 src: Remove unused '#include ' +* fcdb03358d acpi: Drop wrong _ADR objects for PCI host bridges +* 2437fe9dfa sb/intel/i82801gx: Move CIR init to a common place +* 246334390b nb/intel/pineview/Kconfig: Remove romcc leftover +* c73c92368f sb/intel/nm10: Fix enabling HPET +* df128a55b1 intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL +* e39becf521 intel/cpu: Switch older models to TSC_MONOTONIC_TIMER +* d53fd704f2 intel/smm/gen1: Use smm_subregion() +* cd7a70f487 soc/intel: Use common romstage code +* a963acdcc7 arch/x86: Add +* 157b189f6b cpu/intel: Enter romstage without BIST +* f091f4daf7 intel/smm/gen1: Rename header file +* 544878b563 arch/x86: Add postcar_frame_common_mtrrs() +* 5bc641afeb cpu/intel: Refactor platform_enter_postcar() +* b3267e002e cpu/intel: Replace bsp_init_and_start_aps() +* 0f5e01a962 arch/x86: Flip option NO_CAR_GLOBAL_MIGRATION +* 9fc12e0d4e arch/x86: Enable POSTCAR_CONSOLE by default +* 0a4457ff44 lib/stage_cache: Refactor Kconfig options +* fe481eb3e5 northbridge/intel: Rename ram_calc.c to memmap.c +* bccd2b6c49 intel/i945,gm45,pineview,x4x: Fix stage cache location +* aba8fb1158 intel/i945,gm45,pineview,x4x: Move stage cache support function +* 78107939de nb/intel/pineview: Remove dead code in switch +* 8abf66e4e0 cpu/x86: Flip SMM_TSEG default +* 6e2d0c1b90 arch/x86: Adjust size of postcar stack +* d10680bbbf nb/intel/pineview: Remove unused code +* af159d4416 nb/intel/pineview/raminit.c: Remove variable set but not used +* 51401c3050 src/northbridge: Add missing 'include ' +* 82882288c9 nb/intel/pineview: Use MTRR as a proxy for proper reset +* 99e578e3c1 nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK +* f00d37342c nb/intel/pineview/early_init.c: Remove variable set but not used +* 274dabd7a0 src/northbridge: Remove unneeded include +* 1bc7b6e135 {gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function +* 45b824d694 src: Remove unused include +* 363b77177e nb/intel/pineview: Use system_reset() +* 0f49dd26ad src/northbridge/intel: Remove unused variables +* 425e75a2db sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB +* b70c77691b nb/intel/pineview: Correct lsbpos(0) and msbpos(0) +* f5cf60f25b Move calls to quick_ram_check() before CBMEM init +* 4a0f07166f {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem() +* a1e22b8192 src: Use 'include ' when appropriate +* 74aa99a543 src: Drop unused '#include ' +* e183429bd2 nb/intel/stage_cache.c: Drop unnecessary includes +* 484efffa58 {mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.h +* cd49cce7b7 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) +* 503d3247e4 Remove DEFAULT_PCIEXBAR alias +* 13f66507af device/mmio.h: Add include file for MMIO ops +* 065857ee7f arch/io.h: Drop unnecessary include +* bdaec07a85 arch/io.h: Add missing includes +* f1b58b7835 device/pci: Fix PCI accessor headers +* c01a505282 sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read() +* 20f71369d9 nb/intel/pineview: Put stage cache in TSEG +* 84fdda3812 nb/intel/pineview: Use parallel MP init +* da44e34743 nb/intel/pineview: Select 1M TSEG +* c6ff1ac29e nb/intel/pineview: Move the boilerplate mainboard_romstage_entry +* b31aee9973 nb/intel/{i945,pineview}: Remove unused function +* c70eed1e62 device: Use pcidev_on_root() +* 66b462dd4f nb/intel/pineview/raminit.c: Remove unused variable +* 1f4cb326fa northbridge: Remove useless include +* 586f24dab4 northbridge: Remove unneeded include +* de6bda63d9 nb/intel/pineview: Use common code for SMM in TSEG +* d522db048b nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware +* 17ad4598e9 nb/intel/*: Account for cbmem_top alignment +* a342f3937e src: Remove unneeded whitespace +* ef20ecc92b nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address +* b60920df52 northbridge: Use 'unsigned int' to bare use of 'unsigned' +* e6c8f7ec20 nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled +* eb6f2f55ff nb/intel/pineview: Use a common MMCONF_BASE_ADDRESS +* 015339fbf0 nb/intel/pineview: Use the correct address for the RCVEN strobe +* 1f6369e333 nb/intel/pineview: Use i2c block read to fetch SPD +* 3d45000c9c src: Fix typo +* 64f6b71af5 src/northbridge: Fix typo +* 15e1b39e6e nb/intel/pineview: Don't use PCI operations on the pci_domain device +* fd051dc018 src/northbridge: Use "foo *bar" instead of "foo* bar" +* a8a9f34e9b sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables +* 4bdfebd4d8 nb/intel/pineview: Enable and allocate 8M for TSEG +* 730df3cc43 arch/x86: Make RELOCATABLE_RAMSTAGE the default +* aa7cf5597b nb/intel/pineview: Switch to POSTCAR_STAGE +* 089b9089c1 nb/intel: Use postcar_frame_add_romcache() +* f369e60329 northbridge/intel: Remove unneeded includes +* 654cc2fe10 {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate +* 5474eb15ef src/northbridge: Add and update license headers +* 3de303179a {mb,nb,soc}: Remove references to pci_bus_default_ops() +* 6275360d56 nb/intel/pineview: Get rid of device_t +* bb98b38b93 nb/intel/pineview: Port ACPI opregion to pineview +* aaebb415d7 nb/intel/pineview: Enable dram remapping +* 5bb27b7815 nb/intel/pineview: Fix typo in DRAM timing computation +* 12a4e98cea nb/intel/pineview/raminit: Refactor timings selection +* 3b633bbf1d cpu/intel/pineview: Include speedstep +* 33232604a7 nb/intel: add IS_ENABLED() around Kconfig symbol references +* 53815e1561 nb/intel/pineview/raminit: Remove very long delays +* 6bf13012c1 nb/intel/pineview/raminit.c: Use static const for lookup tables +* d4ebeaf475 device/Kconfig: Put gfx init methods into a `choice` +* ce642f08b9 Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG +* d2ca9d12dc nb/pineview/raminit: Don't do Jedec init on resume from S3 +* f6cf3a8f0d nb/intel/pineview: Select RELOCATABLE_RAMSTAGE +* 62e784bd8a nb/intel/pineview: Move to early cbmem +* 00fd3ff507 nb/pineview/raminit: Fix raminit failing on hot reset path +* 097d753980 nb/intel/pineview/raminit: Fix CONFIG_DEBUG_RAM_SETUP=y not compiling +* 2a0e998ec2 nb/intel/pineview: Make preallocated igd memory a cmos parameter +* 6d0c65ebc6 nb/intel/*/northbridge.c: Remove #include +* 530f677cdc buildsystem: Drop explicit (k)config.h includes +* 3d15e10aef MMCONF_SUPPORT: Flip default to enabled +* bac0fad408 Remove explicit select MMCONF_SUPPORT +* 128c104c4d nb/intel: Fix some spelling mistakes in comments and strings +* d3284a6977 nb/intel/*/gma.c: remove spaces at the fake vbt generation +* 6e8b3c1110 src/northbridge: Improve code formatting +* 12df950583 northbridge/intel: Add required space before opening parenthesis '(' +* 32a38ee85b intel/pineview: Do not use scratchpad register for ACPI S3 +* 4dc680aaf1 nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declaration +* 66fbeaec98 intel/pineview: Don't try to store 34 bits in 32 +```` + +### git log src/northbridge/intel/gm45/ + +This benefits GM45 ThinkPads in Libreboot e.g. X200, T400, T500, R500, W500 etc + +```` +* 88dcb3179b src: Retype option API to use unsigned integers +* c8116f6ea0 nb/intel: Don't select VBOOT_SEPARATE_VERSTAGE +* f9c939029b nb/intel: Use get_int_option() +* 3f1f8ef931 nb/intel/gm45: Use new fixed BAR accessors +* 677ac69868 nb/intel/gm45/gm45.h: Guard `CxDRC1_NOTPOP` macro parameters +* 030d338bb2 nb/intel: Add missing +* f462b3d379 nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors +* b70ff52b83 intel: Define `RCBA_LENGTH` in Kconfig and use it +* 6e732d34a0 intel: Turn `DEFAULT_RCBA` into a Kconfig symbol +* 37cae54034 nb/intel/x/bootblock.c Revert `include ` +* 00b5f53361 treewide [Kconfig]: Remove useless comment +* c4d1b47ad9 nb/intel/gm45/bootblock.c: include +* 1ac6f8b804 nb/intel/gm45: Define and use MMCONF_BUS_NUMBER +* 7d638784a2 device/Kconfig: Declare MMCONF symbols' type once +* 58ba83fe74 nb/intel/gm45: Reserve MMIO and firmware memory below 1MiB +* 8e400f0cca Revert "nb/intel/gm45/gm45.h: Remove duplicated include" +* 4537332d64 northbridge/intel/gm45/bootblock.c: Remove repeated word +* 27af8a7e5d nb/intel/gm45/gm45.h: Remove duplicated include +* a93cb11ed6 nb/intel/gm45: Guard macro parameters +* 08ba81b6e4 nb/intel/gm45: Guard `CxDRBy_BOUND_SHIFT` macro parameters +* c6589aefc1 drivers/intel/gma: Include gfx.asl by default for all platforms... +* 2f30e8ca03 nb/intel/gm45: Clean up header handling +* ae2a522827 nb/intel/gm45: Introduce memmap.h +* 3e33be2e69 nb/intel/gm45: Add more DMIBAR/EPBAR registers +* c88a4794c8 nb/intel/gm45: Answer question about conversion stepping A1 +* ac4e4b423f nb/intel/gm45/gm45.h: Clean up cosmetics +* 9c2d15ff7f nb/intel/gm45: Drop unused `DEFAULT_HECIBAR` macro +* 3378de12f6 nb/intel/gm45: Drop casts from DEFAULT_{MCHBAR,DMIBAR} +* dddd1cc691 src/northbridge: Drop unneeded empty lines +* c0c951630a nb/intel/gm45: Deduplicate PCIEXBAR decoding +* b9bbed2c41 nb/intel/gm45/northbridge.c: Use `MiB` definition +* b053583a1c nb/intel/gm45: Use PCI bitwise ops +* f48acbda7b src: Change BOOL CONFIG_ to CONFIG() in comments & strings +* c9e42b98ef nb/intel/gm45/acpi/gm45.asl: Drop dead code +* 29cd350c46 nb/intel/gm45: Use ASL 2.0 syntax +* d85d7e2329 nb/intel/gm45: Tidy up comments and cosmetics +* e1a616cf99 sb/intel/i82801ix: Use pmutil.h definitions +* 1a1b04ea51 device/smbus_host: Declare common early SMBus prototypes +* 8ad0a4c0b8 nb/intel/gm45/iommu.c: Fix regression when updating PCI command +* 1fc0edd9fe src: Use pci_dev_ops_pci where applicable +* dd59762729 intel/gma: Only enable bus mastering if we are going to use it +* dfdf102000 intel/gma: Don't bluntly enable I/O +* f2a0be235c drivers/intel/gma: Move IGD OpRegion to CBMEM +* 5ac723e5a4 nb/intel: Fix 16-bit read/write PCI_COMMAND register +* d13bd05b7a nb/intel: Const'ify pci_devfn_t devices +* c4b70276ed src: Remove leading blank lines from SPDX header +* e30c396ffa src: Remove unused '#include ' +* 6b5bc77c9b treewide: Remove "this file is part of" lines +* c49d7a3e63 src/: Replace GPL boilerplate with SPDX headers +* 36787b0e7b northbridge/*/Kconfig: Replace GPLv2 long form headers with SPDX header +* 76cedd2c29 acpi: Move ACPI table support out of arch/x86 (3/5) +* 7536a398e9 device: Constify struct device * parameter to acpi_fill_ssdt() +* 0f007d8ceb device: Constify struct device * parameter to write_acpi_tables +* 2f8ba69b0e Replace DEVICE_NOOP with noop_(set|read)_resources +* a461b694a6 Drop unnecessary DEVICE_NOOP entries +* 4b42983c7a src/northbridge: Use SPDX for GPL-2.0-only files +* deeccbf4e9 Drop explicit NULL initializations from `device_operations` +* e91883f545 nb/intel/gm45: Simplify GMA SSDT generator +* 68680dd7cd Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator` +* 6343cd846a drivers/intel/gma: fold gma.asl into default_brightness_levels.asl +* 612a867677 drivers/intel/gma/acpi: Add Kconfigs for backlight registers +* f3f36faf35 src (minus soc and mainboard): Remove copyright notices +* 8247cc3328 northbridge: Remove unused include +* 2119d0ba43 treewide: Capitalize 'CMOS' +* ef90609cbb src: capitalize 'RAM' +* c9a717ddb0 nb/intel/gm45: Fix typo in console message +* 1cfafe25e3 intel/{gm45,x4x},i82801{ix|jx}: Move enable_smbus() call +* cbf9571588 drivers/pc80/rtc: Separate {get|set}_option() prototypes +* 4a216475f5 src: Remove some romcc workarounds +* 748caed022 northbridge: Add missing include +* ba9b504ec5 src: Replace min/max() with MIN/MAX() +* dc987fecce src/northbridge: Remove unused +* de64078102 bootblock: Provide some common prototypes +* c05b1a66b3 Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbol +* 4ec67fc82c nb/intel: Use defined DEFAULT_RCBA +* ea2bec2c4b nb/intel/gm45: Add VBOOT support +* 340e4b8090 lib/cbmem_top: Add a common cbmem_top implementation +* be9533aba9 nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support +* 34715df801 src: Remove unused '#include ' +* 468d02cc82 src/[northbridge,security]: change "unsigned" to "unsigned int" +* fcdb03358d acpi: Drop wrong _ADR objects for PCI host bridges +* 29e53582cc nb/intel/gm45: Don't run graphics init on s3 resume +* 9ed0df4c38 sb/intel/i82801ix: Add common code to set up LPC IO decode ranges +* d7205bebd5 nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ use +* e39becf521 intel/cpu: Switch older models to TSC_MONOTONIC_TIMER +* d53fd704f2 intel/smm/gen1: Use smm_subregion() +* cd7a70f487 soc/intel: Use common romstage code +* 4a86b3b036 nb/intel/gm45: Call ddr3_calibrate_zq() only for DDR3 :) +* a963acdcc7 arch/x86: Add +* 157b189f6b cpu/intel: Enter romstage without BIST +* f091f4daf7 intel/smm/gen1: Rename header file +* 544878b563 arch/x86: Add postcar_frame_common_mtrrs() +* 5bc641afeb cpu/intel: Refactor platform_enter_postcar() +* b3267e002e cpu/intel: Replace bsp_init_and_start_aps() +* 08456363f2 nb/intel/gm45: Don't create DMAR tables for disabled IGD +* 15063e8819 nb/intel/gm45/acpi.c: Don't read PCI config to check presence +* 0f5e01a962 arch/x86: Flip option NO_CAR_GLOBAL_MIGRATION +* 9fc12e0d4e arch/x86: Enable POSTCAR_CONSOLE by default +* 0a4457ff44 lib/stage_cache: Refactor Kconfig options +* fe481eb3e5 northbridge/intel: Rename ram_calc.c to memmap.c +* bccd2b6c49 intel/i945,gm45,pineview,x4x: Fix stage cache location +* aba8fb1158 intel/i945,gm45,pineview,x4x: Move stage cache support function +* 8abf66e4e0 cpu/x86: Flip SMM_TSEG default +* 9265f89f4e arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class +* 6e2d0c1b90 arch/x86: Adjust size of postcar stack +* 7f9f3d0cf3 northbridge/gm45: document that raminit doesn't support mirrored ranks +* 51401c3050 src/northbridge: Add missing 'include ' +* 274dabd7a0 src/northbridge: Remove unneeded include +* 1bc7b6e135 {gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function +* ad0b48222f sb/intel/i82801ix: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB +* f74f6cbde5 nb/intel/{gm45,i945,x4x}: Correct array bounds checks +* bf0970e762 src: Use include when appropriate +* 4a0f07166f {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem() +* a1e22b8192 src: Use 'include ' when appropriate +* e183429bd2 nb/intel/stage_cache.c: Drop unnecessary includes +* cd49cce7b7 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) +* 89989cf61f src: Drop unused include +* 503d3247e4 Remove DEFAULT_PCIEXBAR alias +* 13f66507af device/mmio.h: Add include file for MMIO ops +* 065857ee7f arch/io.h: Drop unnecessary include +* f1b58b7835 device/pci: Fix PCI accessor headers +* 0c152cf1bb src: Remove unused include device/pnp_def.h +* 3b0eb602b9 nb/intel/gm45: Use a common romstage +* c3e9ba03b6 nb/intel/gm45: Put stage cache in TSEG +* 6336d4c48d nb/intel/gm45: Use parallel MP init +* 5c29daa150 buildsystem: Promote rules.h to default include +* a6ce5d3faa nb/intel/gm45: Remove the C native graphic init +* e7377556cc device: Use pcidev_path_on_root() +* c70eed1e62 device: Use pcidev_on_root() +* 98a917443e device: Replace ugly cases of dev_find_slot() +* 1f4cb326fa northbridge: Remove useless include +* 4d2d171f02 nb/intel/gm45: Make fetching the blc_pwm freq global +* c679b1f333 nb/intel/gm45: Make fetching the blc_pwm freq its own function +* 009518e79b nb/intel/gm45: Correctly cache TSEG +* 6df3b64c77 src: Remove duplicated round up function +* 48fa9225ca nb/intel/gm45/northbridge.c: Check for NULL pointers +* 8a5283ab1b src: Remove unneeded include +* e9a0130879 src: Remove unneeded include +* ead574ed02 src: Get rid of duplicated includes +* d2b9ec1362 src: Remove unneeded include "{arch,cpu}/cpu.h" +* f33e835a06 nb/intel/gm45: Use macro instead of magic number +* d522db048b nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware +* 17ad4598e9 nb/intel/*: Account for cbmem_top alignment +* ef20ecc92b nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address +* b60920df52 northbridge: Use 'unsigned int' to bare use of 'unsigned' +* e6c8f7ec20 nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled +* 3d45000c9c src: Fix typo +* 64f6b71af5 src/northbridge: Fix typo +* 8908931f1e nb/intel/gm45: Don't use PCI operations on the pci_domain device +* aade90e68d nb/intel/gm45: Use common code for SMM in TSEG +* fd051dc018 src/northbridge: Use "foo *bar" instead of "foo* bar" +* 21b71ce66b src/nb: Fix non-local header treated as local +* 7866d497ad arch/x86/acpi: Add DMAR RMRR helper functions +* e798e6a0b9 sb/intel/i82801ix: Use the common ACPI pirq generator +* f2dd0499b6 libgfxinit: Enable G45 support (for GM45/X4X) +* 730df3cc43 arch/x86: Make RELOCATABLE_RAMSTAGE the default +* 3a4edb6ea8 nb/intel/gm45: Switch to POSTCAR_STAGE +* 089b9089c1 nb/intel: Use postcar_frame_add_romcache() +* f369e60329 northbridge/intel: Remove unneeded includes +* 654cc2fe10 {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate +* 5474eb15ef src/northbridge: Add and update license headers +* 3de303179a {mb,nb,soc}: Remove references to pci_bus_default_ops() +* 6dcdaaf205 nb/intel/gm45: Get rid of device_t +* 2f828ebb59 nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbers +* 8b76605a4a nb/intel/gm45: Allocate a 8M TSEG region +* b31119a348 nb/intel/gm45: Enable LAPIC monotonic timer +* f6aa7d94c8 nb/intel/*/gma: Port ACPI opregion to older platforms +* ca3e121607 nb/intel/gm45: Remove UMA alignment optimization +* 8da2286885 nb/intel/*/gma.c: Use macros for GMBUS numbers +* d65ff22988 nb/intel/gm45: Don't allow too low values for gfx_uma_size +* 049347fee0 nb/intel/gm45: Add romstage timestamps +* 6d8266b91d Kconfig: Add choice of framebuffer mode +* 7971582ec4 Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFER +* ce642f08b9 Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG +* 12e6562289 nb/intel/gm45: Fix raminit with mixed raw card types +* 267d086a08 nb/intel/gm45: Fix some errors/warnings given by checkpatch +* 1dcb2ac199 nb/intel/gm45: Define and use default MMCONF_BASE_ADDRESS +* 20cb85fa98 nb/intel/gm45: Set display backlight according to EDID string +* 53485d2eab nb/intel/gm45/gma.c: Decode EDID before NGI path +* 54235ca1b7 console: Add convenient debug level macros for raminit +* 0624f92118 nb/intel/gm45: Hide some output behind DEBUG_RAM_SETUP +* 561bebfbaa drivers/intel/gma/vbt: Add Kconfig symbol for SSC ref +* bb1af99622 nb/intel/gm45/igd: Hide IGD while disabling +* 1f06028793 nb/gm45/gma.c: Fix reported Pixel clock +* 6d0c65ebc6 nb/intel/*/northbridge.c: Remove #include +* eaebbd10e6 nb/intel/gm45: Use lapic udelay in SMM +* 122e5bc6b1 intel i945 gm45 x4x: Switch to RELOCATABLE_RAMSTAGE +* a6ac187731 intel/gm45: Use romstage_handoff for S3 +* 823020d56b intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup +* 811932a614 intel i945 gm45 x4x: Apply cbmem_top() alignment +* 530f677cdc buildsystem: Drop explicit (k)config.h includes +* 3d15e10aef MMCONF_SUPPORT: Flip default to enabled +* 6f66f414a0 PCI ops: MMCONF_SUPPORT_DEFAULT is required +* 12bed2608f nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency +* d85a71a75c nb/intel/gm45: Fix panel-power-sequence clock divisor +* bac0fad408 Remove explicit select MMCONF_SUPPORT +* 128c104c4d nb/intel: Fix some spelling mistakes in comments and strings +* eeaf9e4687 nb/gm45: Refactor IGD vram decoding +* a4ffe9dda0 intel post-car: Separate files for setup_stack_and_mtrrs() +* c5d972d073 Move select UDELAY_LAPIC from nb/gm45/Kconfig to cpu/model_1067x/Kconfig +* 10141c3006 nb/intel/gm45: Use LAPIC udelay instead of custom version +* 606b8bccb5 nb/gm45/gma.c: Remove writes to DP, FDI registers +* ff1286d500 nb/gm45,x4x/gma.c remove writes to nonexisting FDI registers +* 75f9131453 nb/i945,gm45,x4x/gma.c: fix unsigned arithmetics +* 063cd5f6ee nb/gm45,x4x/gma.c: Compute p2 in VGA init instead of hardcoding it +* fe3eabcaed nb/gm45/gma.c: use linux code to compute LVDS dotclock divisors +* 7141ff3b9f nb/intel/*/graphic_init: use sizeof instead of hardcoding edid size +* 7db506c3dd src/northbridge: Remove unnecessary whitespace +* 58afca4a1a nb/gm45: allow use of 352M preallocated ram for igd +* d3284a6977 nb/intel/*/gma.c: remove spaces at the fake vbt generation +* 9a9c8dba8d northbridge/intel/gm45: Add space around operators +* 0b1a5c259b gm45/gma.c: use correct id string for fake VBT +* c51522f516 nb/gm45/gma.c: enable VESA framebuffer mode on VGA output +* de6ad8369f gm45/gma.c: use screen on vga connector if connected +* 25f75b28e4 northbridge/intel/gm45: transation away from device_t +* 88af372fe8 nb/intel/gm45: Fix DMAR table - IOMMU advertisement for ME interfaces +* 8ba2010d12 gm45/gma.c: clean up some registers +* 0cd338e6e4 Remove non-ascii & unprintable characters +* 15279a9696 src/northbridge: Capitalize CPU, RAM and ROM +```` + +### git log src/northbridge/intel/x4x/ + +This benefits mainly the Gigabyte GA-G41M-ES2L mainboard in Libreboot, and other +x4x boards that have now been added. In Libreboot 20160907, the only x4x board +was the Gigabyte GA-G41M-ES2L + +```` +* 88dcb3179b src: Retype option API to use unsigned integers +* f9c939029b nb/intel: Use get_int_option() +* 2bb361f0f5 nb/intel/x4x: Refactor sync DLL programming (part 2) +* a20a02e82a nb/intel/x4x: Refactor sync DLL programming (part 1) +* b6a2ebe5ef nb/intel/x4x: Sort code in program_dll() +* a5146f3239 nb/intel/x4x: Use new fixed BAR accessors +* 93aab51ec1 nb/intel/x4x: Correct and use macros for CLKCFG +* 70dc0a8cc3 nb/intel/x4x/dq_dqs.c: Avoid breaking strings over multiple lines +* e82191451c nb/intel/x4x: Add missing newlines to log message +* dd7ce4e1d3 nb/intel/x4x: Reflow long lines +* 5c3160ed80 nb/intel/x4x/dq_dqs.c: Fix typo in variable name +* c024c14790 nb/intel/x4x: Correct sync DLL phase search +* 7720f1da36 nb/intel: Factor out remaining MCHBAR macros +* afb3d7e7ec device/dram/ddr3: Get rid of useless typedefs +* b238caaaca device/device.c: Rename .disable to .vga_disable +* 3051a9ecfa nb/intel/x4x: Use a variable for s3resume +* b33c6fbfd5 nb/intel/x4x,sandybridge: Move INITRAM timestamps +* 4ce0a07f06 nb/intel/x4x,sandybridge: Move romstage_handoff_init() call +* 030d338bb2 nb/intel: Add missing +* e88f705946 nb/intel/x4x: Use common {DMI,EP,MCH}BAR accessors +* 06d224f65e nb/intel/x4x: Correct DDR3 turnaround table +* a6daff192f nb/intel/x4x: Constify write leveling arrays +* 9e58afef59 nb/intel/x4x: Update write leveling comment +* b35adab862 nb/intel/x4x: Constify DDR2 ODT table +* 7d3bd6b505 nb/intel/x4x: Clean up RCOMP cosmetics +* a0b97f3743 nb/intel/x4x: Drop unused first array index +* 244391a075 nb/intel/x4x: Unroll programming RCOMP data group +* 6b17794dda nb/intel/x4x: Report if running in async mode +* 43a5e0cc07 nb/intel/x4x: Factor out setting Tx DLL tap and PI +* 22fd0dca17 nb/intel/x4x: Correct ctrlset{2,3} register mask +* b99d592752 nb/intel/x4x: Clean up cosmetics of raminit tables +* 32f9bcaa91 nb/intel/x4x: Drop commented-out statement +* b70ff52b83 intel: Define `RCBA_LENGTH` in Kconfig and use it +* 6e732d34a0 intel: Turn `DEFAULT_RCBA` into a Kconfig symbol +* 37cae54034 nb/intel/x/bootblock.c Revert `include ` +* 00b5f53361 treewide [Kconfig]: Remove useless comment +* 875c21f491 nb/intel/x4x/bootblock.c: include +* bbc80f4405 nb/intel/x4x: Define and use MMCONF_BUS_NUMBER +* 7d638784a2 device/Kconfig: Declare MMCONF symbols' type once +* 985821c4f2 cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE +* f669c81cf4 northbridge/intel/x4x/dq_dqs.c: Remove repeated word +* 6538d91bc3 northbridge/intel/x4x/raminit_ddr23.c: Remove repeated word +* 9d20c84460 nb/intel/x4x: Clean up raminit comments +* bc15e01958 nb/intel/x4x: Reset DQS probe on all channels +* c6589aefc1 drivers/intel/gma: Include gfx.asl by default for all platforms... +* baf27dbaeb cbfs: Enable CBFS mcache on most chipsets +* 41e66ac38f nb/intel/x4x: Place raminit definitions in raminit.h +* fd19075045 nb/intel/x4x: Move register headers into a subfolder +* a5314b62b6 nb/intel/x4x: Clean up DMIBAR/EPBAR definitions +* 6c2568f4f5 drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config +* 6fd9adbecb nb/intel/x4x/x4x.h: Clean up cosmetics +* 2a8ceefb27 nb/intel/x4x/iomap.h: Rename to memmap.h +* dddd1cc691 src/northbridge: Drop unneeded empty lines +* b8b117c7e7 nb/intel/x4x: Clean up TPM-related code +* ad9cd687b8 mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms +* cf0f7ed3ee nb/intel/x4x/raminit_ddr23.c: Remove dead assignment +* 5ba154a597 src: Use space after 'if', 'for' +* 6aa9d66873 src: Use space after switch, while +* d1c590a666 nb/intel/x4x: Define and use `HOST_BRIDGE` macro +* 579ccdf9c9 nb/intel/x4x: Remove dead assignments +* 8f917b1d4b nb/intel/x4x: Refactor `decode_pcie_bar` +* ecec9474d8 nb/intel/x4x: Change signature of `decode_pciebar` +* 6b2be99eb1 nb/intel/x4x/hostbridge_regs.h: Clean up registers +* 3896576a16 nb/intel/x4x: Put host bridge registers into its own file +* 879c4de66f nb/intel/x4x/rcven.c: Rename memory barrier function +* 225be5f7ee src: Remove unused 'include ' +* 7c71f7d15b nb/intel/x4x/acpi: Use ASL 2.0 syntax +* 0b5673dd33 nb/intel/x4x/acpi: Clean up comments +* 1a1b04ea51 device/smbus_host: Declare common early SMBus prototypes +* a1dfce1ce0 x4x boards: Factor out MAX_CPUS +* 306e8930a7 nb/intel/x4x: Drop unused `pci_ops.h` include +* 4a9569a123 nb/intel/x4x: Use PCI bitwise ops +* 1fc0edd9fe src: Use pci_dev_ops_pci where applicable +* 379aab47f9 src: Remove unused 'include ' +* 0c154af217 src: Remove redundant includes +* dd59762729 intel/gma: Only enable bus mastering if we are going to use it +* dfdf102000 intel/gma: Don't bluntly enable I/O +* f2a0be235c drivers/intel/gma: Move IGD OpRegion to CBMEM +* 5ac723e5a4 nb/intel: Fix 16-bit read/write PCI_COMMAND register +* c4b70276ed src: Remove leading blank lines from SPDX header +* 6b5bc77c9b treewide: Remove "this file is part of" lines +* c49d7a3e63 src/: Replace GPL boilerplate with SPDX headers +* 36787b0e7b northbridge/*/Kconfig: Replace GPLv2 long form headers with SPDX header +* ac9590395e treewide: replace GPLv2 long form headers with SPDX header +* 02363b5e46 treewide: Move "is part of the coreboot project" line in its own comment +* 76cedd2c29 acpi: Move ACPI table support out of arch/x86 (3/5) +* 2d7173d462 src: Remove unused 'include ' +* 7536a398e9 device: Constify struct device * parameter to acpi_fill_ssdt() +* 0f007d8ceb device: Constify struct device * parameter to write_acpi_tables +* 2f8ba69b0e Replace DEVICE_NOOP with noop_(set|read)_resources +* a461b694a6 Drop unnecessary DEVICE_NOOP entries +* 4b42983c7a src/northbridge: Use SPDX for GPL-2.0-only files +* 33f89eea9f nb/intel/x4x: Simplify GMA SSDT generator +* 68680dd7cd Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator` +* 6343cd846a drivers/intel/gma: fold gma.asl into default_brightness_levels.asl +* 612a867677 drivers/intel/gma/acpi: Add Kconfigs for backlight registers +* f3f36faf35 src (minus soc and mainboard): Remove copyright notices +* 8247cc3328 northbridge: Remove unused include +* 2119d0ba43 treewide: Capitalize 'CMOS' +* ef90609cbb src: capitalize 'RAM' +* 1cfafe25e3 intel/{gm45,x4x},i82801{ix|jx}: Move enable_smbus() call +* bd65985a63 nb/intel/{i945,x4x,pineview}: Remove wrapper spd_read_byte() +* cbf9571588 drivers/pc80/rtc: Separate {get|set}_option() prototypes +* 1f66809111 src: Remove unneeded 'include ' +* 748caed022 northbridge: Add missing include +* dc987fecce src/northbridge: Remove unused +* de64078102 bootblock: Provide some common prototypes +* 68ec3eb1f0 src: Move 'static' to the beginning of declaration +* a854c9d787 nb/intel/x4x: Factor out hiding PCI devs in pure fn +* c05b1a66b3 Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbol +* 7843bd560e nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK +* bf53acca5e nb/intel/x4x: Move boilerplate romstage to a common location +* 2452afbe04 mb/*/*(ich7/x4x): Use common early southbridge init +* aa990e9289 sb/intel/i82801jx: Move early sb init to a common place +* dc972e17c7 nb/intel/x4x.h: Include stdint.h +* 4ec67fc82c nb/intel: Use defined DEFAULT_RCBA +* 6190d0bfe6 nb/intel/x4x/x4x.h: Include iomap.h +* 340e4b8090 lib/cbmem_top: Add a common cbmem_top implementation +* 44b275e209 nb/intel/{nehalem,x4x}: Remove unused 'include ' +* 34715df801 src: Remove unused '#include ' +* fcdb03358d acpi: Drop wrong _ADR objects for PCI host bridges +* d7205bebd5 nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ use +* 197a3c6cea nb/intel/x4x: Avoid x4x.h header with romcc-bootblock +* e39becf521 intel/cpu: Switch older models to TSC_MONOTONIC_TIMER +* 8bb2bace86 nb/intel/x4x/raminit: Move dummy reads after JEDEC init +* d53fd704f2 intel/smm/gen1: Use smm_subregion() +* cd7a70f487 soc/intel: Use common romstage code +* a963acdcc7 arch/x86: Add +* f091f4daf7 intel/smm/gen1: Rename header file +* 544878b563 arch/x86: Add postcar_frame_common_mtrrs() +* 5bc641afeb cpu/intel: Refactor platform_enter_postcar() +* b3267e002e cpu/intel: Replace bsp_init_and_start_aps() +* 0f5e01a962 arch/x86: Flip option NO_CAR_GLOBAL_MIGRATION +* 9fc12e0d4e arch/x86: Enable POSTCAR_CONSOLE by default +* 0a4457ff44 lib/stage_cache: Refactor Kconfig options +* fe481eb3e5 northbridge/intel: Rename ram_calc.c to memmap.c +* bccd2b6c49 intel/i945,gm45,pineview,x4x: Fix stage cache location +* aba8fb1158 intel/i945,gm45,pineview,x4x: Move stage cache support function +* 5033d6ce51 nb/intel/x4x: Die on invalid memory speeds +* 8abf66e4e0 cpu/x86: Flip SMM_TSEG default +* 6e2d0c1b90 arch/x86: Adjust size of postcar stack +* e951e8ec7f nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps} +* c53665ce55 nb/intel/x4x: Remove variable set but not used +* 2dbc095677 nb/intel/x4x/rcven.c: Remove variable set but not used +* 51401c3050 src/northbridge: Add missing 'include ' +* 502008d5dc nb/northbridge/intel/x4x/acpi.c: Remove variable set but not used +* 0c89c1c05e nb/intel/x4x/early_init.c: Remove variable set but not used +* 274dabd7a0 src/northbridge: Remove unneeded include +* 1bc7b6e135 {gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function +* b559b3c785 nb/x4x: Use system_reset() and full_reset() +* 0f49dd26ad src/northbridge/intel: Remove unused variables +* f74f6cbde5 nb/intel/{gm45,i945,x4x}: Correct array bounds checks +* bf0970e762 src: Use include when appropriate +* f5cf60f25b Move calls to quick_ram_check() before CBMEM init +* 4a0f07166f {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem() +* a1e22b8192 src: Use 'include ' when appropriate +* 74aa99a543 src: Drop unused '#include ' +* e183429bd2 nb/intel/stage_cache.c: Drop unnecessary includes +* cd49cce7b7 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) +* 503d3247e4 Remove DEFAULT_PCIEXBAR alias +* 13f66507af device/mmio.h: Add include file for MMIO ops +* 065857ee7f arch/io.h: Drop unnecessary include +* f1b58b7835 device/pci: Fix PCI accessor headers +* c01a505282 sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read() +* a402a9e7ab nb/intel/x4x: Put stage cache in TSEG +* c82950bf79 nb/intel/x4x: Use parallel MP init +* 15b83da39a nb/intel/x4x: Remove spurious pcidev_on_root() usage +* f5a57a883b mb: Move timestamp_add_now to northbridge x4x +* c70eed1e62 device: Use pcidev_on_root() +* 98a917443e device: Replace ugly cases of dev_find_slot() +* 1f4cb326fa northbridge: Remove useless include +* 586f24dab4 northbridge: Remove unneeded include +* 4c65bfc3e8 nb/intel/x4x: Use common code for SMM in TSEG +* 0ce41f1a11 src: Add required space after "switch" +* 8a5283ab1b src: Remove unneeded include +* f765d4f275 src: Remove unneeded include +* ead574ed02 src: Get rid of duplicated includes +* d2b9ec1362 src: Remove unneeded include "{arch,cpu}/cpu.h" +* 0f14df46aa nb/intel/x4x/raminit: Add missing space +* d522db048b nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware +* 17ad4598e9 nb/intel/*: Account for cbmem_top alignment +* a342f3937e src: Remove unneeded whitespace +* b1ba6624cd nb/intel/x4x: Fix P45 CAPID max frequency +* 8ddd7d1e5e nb/intel/x4x: Program read training results to all ranks +* 88607a4b10 src: Use tabs for indentation +* b0c6cffb09 nb/intel/x4x: Don't use cached settings if CPU FSB has been changed +* 3e3bae03cf nb/intel/x4x/gma.c: fix skipping of native graphics init +* e6c8f7ec20 nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled +* 3d45000c9c src: Fix typo +* 64f6b71af5 src/northbridge: Fix typo +* 3a2f900cfe x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2] +* c6e13b6690 nb/intel/x4x: Don't use PCI operations on the pci_domain device +* 432575c5d3 x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2] +* 6cd2c2f6ff northbridge/x4x: add MCHBAR AND/OR/AND_OR access macros +* a8a9f34e9b sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables +* df946b8696 nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset +* e8093054d3 nb/intel/x4x: Deprecate native graphic init +* 7345a17a43 nb/intel/x4x: Fix a few things in set_enhanced_mode +* 5a9dbde59c nb/intel/x4x: Work around a quirk +* 0602ce67a6 nb/intel/x4x: Add the option for stacked channel map settings +* f2dd0499b6 libgfxinit: Enable G45 support (for GM45/X4X) +* 730df3cc43 arch/x86: Make RELOCATABLE_RAMSTAGE the default +* 4ff675ebd0 nb/intel/x4x: Switch to POSTCAR_STAGE +* 089b9089c1 nb/intel: Use postcar_frame_add_romcache() +* f369e60329 northbridge/intel: Remove unneeded includes +* 654cc2fe10 {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate +* 0d284959dc nb/intel/x4x: Adapt post JEDEC for DDR3 +* 3fa103a602 nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings +* b4a78045d5 nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings +* b5170c3e92 nb/intel/x4x: Implement write leveling +* f1287266ab nb/intel/x4x: Add DDR3 JEDEC init +* e6cc21e262 nb/intel/x4x/raminit: DDR3 specific ODT +* 0d1c9b0e32 nb/intel/x4x: Add DDR3 rcomp +* 638240e98b nb/intel/x4x/raminit: Support programming initials DD3 DLL setting +* 66a0f55c2e nb/intel/x4x/raminit: Support programming DDR3 timings +* 7a3a319e3a nb/intel/x4x/raminit: Make programming launch ddr3 specific +* 840c27ecfc nb/intel/x4x/raminit: Make programming crossclock support DDR3 +* a2cc23169a nb/intel/x4x: Rename a things that are not specific to DDR2 +* 1848ba3b54 nb/x4x/raminit: Decode ddr3 dimms +* 701da39fb7 nb/intel/x4x/raminit: Fix programming dual channel registers +* 3de303179a {mb,nb,soc}: Remove references to pci_bus_default_ops() +* 16a70a48c6 nb/intel/x4x: Change memory layout to improve MTRR +* dfce932cf0 nb/intel/x4x: Fix programming CxDRB +* 95c48cbbb5 nb/intel/x4x: Implement both read and write training +* fea02e1439 nb/x4x: Get rid of device_t +* d4e5762bd7 nb/intel/x4x: Fix computing page_size +* a4e8f67b94 nb/intel/x4x/rcven.c: Change the verbosity of some messages +* 276049f9ee nb/intel/x4x: Add a convenient macro to loop over bytelanes +* 1994e448be nb/intel/x4x: Clarify the raminit memory mapping +* 0bf87de667 nb/intel/x4x: Refactor setting default dll settings +* adc571a54c nb/intel/x4x: Use SPI flash to cache raminit results +* fc31e44e47 device/ddr2,ddr3: Rename and move a few things +* 7be74dbb38 nb/x4x/raminit_ddr2: Refactor clock configuration slightly +* d6f3dd83dc nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout +* 3cf94032bc nb/x4x/raminit: Rewrite SPD decode and timing selection +* f6f4ba9e45 nb/intel/x4x/rcven.c: Fix programming coarse offset +* f6aa7d94c8 nb/intel/*/gma: Port ACPI opregion to older platforms +* 524d497355 nb/intel/x4x: Select LAPIC_MONOTONIC_TIMER +* 24798a1544 nb/intel/x4x: Fix booting with FSB800 DDR667 combination +* 6d7a8c1125 nb/intel/x4x/raminit: Rework receive enable calibration +* c3cbe9433c nb/intel/x4x/gma.c: Probe VGA EDID on DVI-I ports +* 8da2286885 nb/intel/*/gma.c: Use macros for GMBUS numbers +* 3876f24221 nb/intel/x4x: Rework programming DQ and DQS DLL timings +* 349e08535a sb/intel/i82801jx: Add correct PCI ids and change names +* 6d8266b91d Kconfig: Add choice of framebuffer mode +* 7971582ec4 Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFER +* ce642f08b9 Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG +* 37689fae38 nb/intel/x4x/raminit: Initialise async variable +* 27f0ca18bc nb/intel/x4x: Use a struct for dll settings instead of an array +* cfa2eaa4cc nb/intel/x4x: Make raminit less verbose with CONFIG_DEBUG_RAM_SETUP +* e729366d7a nb/intel/x4x/raminit: Remove very long delay +* cfd433b96d nb/intel/x4x: Fix uninitialized variable issue +* 512a2d1c4f nb/intel/x4x: Define and use default MMCONF_BASE_ADDRESS +* 293445ae1f nb/intel/x4x: Add support for second PEG slot +* 5e3cb72a71 nb/x4x: Do not enable IGD when not supported +* 2e7efe65a2 nb/intel/x4x: Don't run NGI if IGD has not been assigned VGA cycles +* c80748c2d0 nb/x4x: Add ramstage IGD disable function +* 4c4f56a6ba nb/x4x/nortbridge.c: Compute TSEG resource allocation dynamically +* ddc8828697 nb/x4x/raminit.c: Remove ME locking code +* 8565c03caf nb/intel/x4x/raminit: Change reset type on incomplete raminit reset +* 4bc9c28811 nb/intel/x4x/Kconfig: Don't fix CBFS_SIZE on i82801gx southbridge +* bb5e77c478 nb/x4x: Move checkreset before SPD reading +* 70a1dda927 nb/intel/x4x: Fix issues found by checkpatch.pl +* ef7e98a2ac nb/intel/x4x: Implement resume from S3 suspend +* 97e13d84c3 nb/intel/x4x: Fix raminit on reset path +* eee4f6b224 nb/x4x/raminit: Fix programming dram timings +* 6d0c65ebc6 nb/intel/*/northbridge.c: Remove #include +* 9e70ce0c3e nb/x4x: Add other Eaglelake IGD PCI DID to list +* 122e5bc6b1 intel i945 gm45 x4x: Switch to RELOCATABLE_RAMSTAGE +* 823020d56b intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup +* 811932a614 intel i945 gm45 x4x: Apply cbmem_top() alignment +* 530f677cdc buildsystem: Drop explicit (k)config.h includes +* 3d15e10aef MMCONF_SUPPORT: Flip default to enabled +* 5b30b823c8 nb/x4x: Fix sticky scratchpad register offset +* 3c20906e42 nb/intel/x4x/raminit: Fix DIMM_IN_CHANNEL calculation +* 696abfcfd3 nb/intel/x4x: Fix and deflate `dimm_config` in raminit +* bac0fad408 Remove explicit select MMCONF_SUPPORT +* 128c104c4d nb/intel: Fix some spelling mistakes in comments and strings +* a4ffe9dda0 intel post-car: Separate files for setup_stack_and_mtrrs() +* 8a3514d0ae nb/x4x/raminit.c: Improve crossclock table cosmetics +* f8a4f41d48 nb/x4x/gma.c: Remove writes to DP, FDI registers +* ff1286d500 nb/gm45,x4x/gma.c remove writes to nonexisting FDI registers +* 75f9131453 nb/i945,gm45,x4x/gma.c: fix unsigned arithmetics +* 063cd5f6ee nb/gm45,x4x/gma.c: Compute p2 in VGA init instead of hardcoding it +* 7141ff3b9f nb/intel/*/graphic_init: use sizeof instead of hardcoding edid size +* de14ea77c3 x4x/gma.c: Add VESA native resolution mode +* 7db506c3dd src/northbridge: Remove unnecessary whitespace +* d3284a6977 nb/intel/*/gma.c: remove spaces at the fake vbt generation +* 6e8b3c1110 src/northbridge: Improve code formatting +* 60a6e153b0 northbridge/intel/x4x: transition away from device_t +* 614ffc60cf nb/intel/x4x: Correct typos in interrupt routing for PEG +* a99c64e129 nb/intel/x4x: Turn on PEG graphics in device enable +* 523e90f9c7 nb/intel/x4x: Increase MMIO PCI space to 2GiB +* 57321db3ca nb/intel/x4x: Fix DMI init +* 12df950583 northbridge/intel: Add required space before opening parenthesis '(' +* eff0c6a99d x4x: make preallocated IGD memory a cmos option +* 27f94eea6c x4x: add non documented vram sizes +* 7c2e5396a3 nb/intel/x4x: Fix CAS latency detection and max memory detection +* b921725b52 nb/intel/x4x: Fix CAS latency detection +* df6eb79a22 intel/x4x: Do not use scratchpad register for ACPI S3 +* 9ae0985328 nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM +* 68e1dcfdd9 nb/intel/x4x: Fix unpopulated value +* a090ae04c2 nb/intel/x4x: Add DMI/EP init +```` + +fam10h / fam15h AMD platform +---------------------------- + +Unlike other boards in this Libreboot release, the AMD fam10h/fam15h boards +are stuck on coreboot 4.11. The other boards use coreboot 4.14. The commits +listed below are since the coreboot revisions used in Libreboot 20160907, right +up to coreboot 4.11. + +### Northbridge changes + +#### fam10h + +Running `git log src/northbridge/amd/amdfam10/` we get these commits: + +```` +* 468d02cc82 src/[northbridge,security]: change "unsigned" to "unsigned int" +* 23d4d9f368 amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE +* c99d3afe3e amdfam10: Remove use of __PRE_RAM__ +* 5cf9ccc57d src: Include instead of +* 04d025cf50 amdfam10: Declare get_sysinfo() +* 8560db6116 amdfam10: Declare empty activate_spd_rom() stub +* f77f7cdf89 device,nb/amd: Deduplicate add_more_links() +* 09c31d557f nb/amd/amdfam10: Use 64 bits in multiplication +* 44245693ec nb/amd/amdfam10/northbridge.c: Remove variable set but not used +* 27ca962058 nb/amd/amdfam10: die() on out of bounds reads +* 51401c3050 src/northbridge: Add missing 'include ' +* 5de93e9011 nb/amd/amdfam10/util.c: Use "CONFIG" only when appropriate +* 5d1f9a0096 Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX) +* a1e22b8192 src: Use 'include ' when appropriate +* d21495549b nb/amd/amdfam10: Remove define macro already done in 'amdfam10.h' +* 6b2e436995 nb/amd/amdfam10: Remove 'IS_ENABLED()' +* cd49cce7b7 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) +* 065857ee7f arch/io.h: Drop unnecessary include +* bdaec07a85 arch/io.h: Add missing includes +* 3e6913b389 arch/io.h: Fix PCI and PNP simple typedefs +* f1b58b7835 device/pci: Fix PCI accessor headers +* 251514d986 src: Don't use a #defines like Kconfig symbols +* c2c1dc9c76 {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem() +* ef62994b94 northbridge/amdfam10: Deal with PCI_ADDR() better +* 20c294884f amdfam10 boards: Simplify early resourcemap +* 2dce923524 mb: Move timestamp_add_now to northbridge/amd/amdfam10 +* e7377556cc device: Use pcidev_path_on_root() +* c70eed1e62 device: Use pcidev_on_root() +* f112f9f912 amdfam10 boards: Use defaults for get_pci1234() +* 21c60fa2b2 amdfam10 boards: Add temporary pirq_router_bus variable +* c0b1be0ba1 amdfam10 boards: Call get_bus_conf() just once +* a2cfe9e900 amdfam10 boards: Add Makefiles and fix resourcemap.c +* 1db4e3a358 amdfam10 boards: Declare get_pci1234() just once +* 9e7ac6b034 amdfam10 boards: Drop AMD_SB_CIMX +* 1f4cb326fa northbridge: Remove useless include +* 586f24dab4 northbridge: Remove unneeded include +* 134da98a51 amd/{nb/amdfam10,cpu/pi}/Kconfig: Remove unused symbols +* 414779db10 src/mainboard: Remove unused "HW_MEM_HOLE_SIZE_AUTO_INC" +* f765d4f275 src: Remove unneeded include +* e9a0130879 src: Remove unneeded include +* d2b9ec1362 src: Remove unneeded include "{arch,cpu}/cpu.h" +* 400ce55566 cpu/amd: Use common AMD's MSR +* 83bd46e5e5 selfboot: remove bounce buffers +* d44221f9c8 Move compiler.h to commonlib +* 88607a4b10 src: Use tabs for indentation +* b60920df52 northbridge: Use 'unsigned int' to bare use of 'unsigned' +* 3d45000c9c src: Fix typo +* 64f6b71af5 src/northbridge: Fix typo +* b0f1988f89 src: Get rid of unneeded whitespace +* c8a649c08f src: Use of device_t is deprecated +* 7904e720d5 arch/x86: Flag platforms without RELOCATABLE_RAMSTAGE +* 448d9fb431 src: Use "foo *bar" instead of "foo* bar" +* 5474eb15ef src/northbridge: Add and update license headers +* 5b3bf4ad27 nb/amd/amdfam10: Get rid of device_t +* 3de303179a {mb,nb,soc}: Remove references to pci_bus_default_ops() +* aa090cb6ea device: acpi_name() should take a const struct device +* b98391c0ee AMD K8 fam10-15: Tidy up CAR disable +* b08d73b845 src/northbridge: Add guards on all header files +* 6a00113de8 Rename __attribute__((packed)) --> __packed +* 77a58b92e8 nb/amd: add IS_ENABLED() around Kconfig symbol references +* 67ed261200 amd/amdfam10: Remove dead code +* 0f3a18ad28 [nb|sb]/amd/[amdfam10|sb700]: Add LPC bridge ACPI names for NB/SB +* 75a3d1fb7c amdfam10: Perform major include ".c" cleanup +* 48f82a9beb AMD fam10 binaryPI: Remove invalid PCI ops on CPU domain +* 27198ac2e3 MMCONF_SUPPORT: Drop redundant logging +* e25b5ef39f MMCONF_SUPPORT: Consolidate resource registration +* 6f66f414a0 PCI ops: MMCONF_SUPPORT_DEFAULT is required +* 425890e59a AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already set +* e0ee4c87e8 northbridge/amd/amdfam10: Remove commented code +* 7db506c3dd src/northbridge: Remove unnecessary whitespace +* 0d4b11a4f8 src/northbridge: Remove whitespace after sizeof +* 04f8fd981f northbridge/amd/amdfam10: Improve code formatting +* f65ccb2cd6 northbridge/amd/amdfam10: transition away from device_t +* 6e8b3c1110 src/northbridge: Improve code formatting +* 5a7e72f1ae northbridge/amd: Add required space before opening parenthesis '(' +* 47f7b0e196 amd/amdfam10: eliminate dead code +* 0cd338e6e4 Remove non-ascii & unprintable characters +* 15279a9696 src/northbridge: Capitalize CPU, RAM and ROM +* 84da72c988 nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure +```` + +#### fam15h + +Running `git log src/northbridge/amd/amdmct/` we get this: + +```` +* 468d02cc82 src/[northbridge,security]: change "unsigned" to "unsigned int" +* 23d4d9f368 amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE +* c99d3afe3e amdfam10: Remove use of __PRE_RAM__ +* 9172b6920c src: Remove variable length arrays +* 5cf9ccc57d src: Include instead of +* 63f98f2304 src: Use CRx_TYPE type for CRx +* 7d881b5189 nb/amd/amdmct/mct_ddr3: Remove unused code +* 31755adc5a nb/amd/amdmct/mct: Remove duplicate if condition +* 19cbe03534 nb/amd/amdmct/mct_ddr3: Remove duplicate conditional +* 86d8c4279d nb/amd/amdmct/mct_ddr3: Remove duplicate code +* e94335e9fd nb/amd/amdmct/mct: Simplify conditional +* 156936b771 nb/amd/amdmct/mct_ddr3/mct_d.c: Remove variable set but not used +* 51401c3050 src/northbridge: Add missing 'include ' +* 3dbfb2bef9 nb/amd/amdmct/mct/mctdqs_d.c: Remove variable set but not used +* f0a576595a nb/amd/amdmct/mct/mctpro_d.c: Remove variable set but not used +* 7a5d4e2b4a nb/amd/amdmct/mct/mctecc_d.c: Remove variable set but not used +* d768e919ae src/northbridge/amd: Remove unused variables +* 351e3e520b src: Use include when appropriate +* 20eaef024c src: Add missing include 'console.h' +* bf0970e762 src: Use include when appropriate +* a1e22b8192 src: Use 'include ' when appropriate +* cd49cce7b7 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) +* bdaec07a85 arch/io.h: Add missing includes +* f1b58b7835 device/pci: Fix PCI accessor headers +* 0f8b8d920c src: Move constant to the right side of comparison +* c70eed1e62 device: Use pcidev_on_root() +* afc63844e2 src/northbridge: Get rid of device_t +* 00d0ddb62b nb/amd/amdmct/{mct,mct_ddr3}: Replace "magic" numbers with macros +* e9a0130879 src: Remove unneeded include +* ead574ed02 src: Get rid of duplicated includes +* d2b9ec1362 src: Remove unneeded include "{arch,cpu}/cpu.h" +* de462804e1 nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macros +* a9473ecbb1 src: Replace common MSR addresses with macros +* d35c7fe1bf amd/mtrr: Fix IORR MTRR +* 718c6faff4 reset: Finalize move to new API +* 8a643703b8 {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros +* dfbe6bd5c3 src: Add missing include +* a342f3937e src: Remove unneeded whitespace +* 400ce55566 cpu/amd: Use common AMD's MSR +* d44221f9c8 Move compiler.h to commonlib +* 3d45000c9c src: Fix typo +* 64f6b71af5 src/northbridge: Fix typo +* bd4a3f8cd9 cpu/amd: Correct number of MCA banks cleared +* fd051dc018 src/northbridge: Use "foo *bar" instead of "foo* bar" +* b0f1988f89 src: Get rid of unneeded whitespace +* 68c851bcd7 src: Get rid of device_t +* 1943f3798d {device,drivers,lib,mb,nb}: Use only one space after 'if' +* b6616ea636 amd/mct/ddr3: Correctly configure CsMux67 +* 0722613563 nb/amd_fam10/mct_ddr3: Use common function to compute crc16 checksum +* 6a00113de8 Rename __attribute__((packed)) --> __packed +* 77a58b92e8 nb/amd: add IS_ENABLED() around Kconfig symbol references +* 30221b45e0 drivers/spi/spi_flash: Pass in flash structure to fill in probe +* 610d1c67b2 Revert "nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h" +* 37e30aa624 nb/amd/amdmct: Remove another currently unused table +* a6b1b258d2 nb/amd/amdmct: Remove two currently unused tables +* 9b4c888f7b nb/amd/ddr3: Make the maximum CDD a signed value +* a19d44d276 amd/mct: Add default values to highest_rank_count for DDR2 +* 17b66c3846 amd/mct/ddr2: Remove orphaned Tab_TrefT_k variable +* 88a2e3b3bf amd/mct/ddr3: Fix unintended sign extension warning +* 590a3e1f6c amd/mct/ddr3: Avoid using uninitialized register address in ECC setup +* a20d0e0f79 amd/mct/ddr3: Free malloced resources in failure branches +* 6f9468f019 amd/mct/ddr3: Rework memory speed to clock value conversion logic +* 8fa624784e amd/mct/ddr3: Correctly program maximum read latency +* 5153cbfeb3 amd/mct/ddr3: Allow critical delay delta to go negative +* cf1cb5b2d4 amd/mct/ddr3: Correctly configure CsMux45 +* aeaabd3fa3 amd/mct/ddr3: Wait for northbridge P-state transitions +* 21b01b80d6 amd/mct/ddr3: Fix incorrect DQ mask calculation +* a4dcdca7ba amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc +* 75a3d1fb7c amdfam10: Perform major include ".c" cleanup +* c28984d9ea spi: Clean up SPI flash driver interface +* bb09f285c3 nb/amd/amdmct/mct: Remove commented code +* 6bc3b96831 northbridge/amd/amdmct/mct_ddr3: Remove commented code +* 7db506c3dd src/northbridge: Remove unnecessary whitespace +* e1606731b6 northbridge/amd/amdmct: Improve code formatting +* 6e8b3c1110 src/northbridge: Improve code formatting +* 5a7e72f1ae northbridge/amd: Add required space before opening parenthesis '(' +* 38424987c6 src/northbridge: Remove unnecessary whitespace before "\n" and "\t" +* 0cd338e6e4 Remove non-ascii & unprintable characters +* 84da72c988 nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure +* d112f46bed nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15h +```` + +### Board changes + +#### ASUS KGPE-D16 + +Running `git log src/mainboard/asus/kgpe-d16/` we get: + +```` +* eb50d9a4fe mb/*: Use common IPMI KCS driver +* cb3e16f287 AMD fam10: Remove HAVE_ACPI_RESUME support +* 04d025cf50 amdfam10: Declare get_sysinfo() +* 8560db6116 amdfam10: Declare empty activate_spd_rom() stub +* e39db681df src/mainboard: Add missing 'include ' +* a1e22b8192 src: Use 'include ' when appropriate +* cd49cce7b7 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) +* 13f66507af device/mmio.h: Add include file for MMIO ops +* 065857ee7f arch/io.h: Drop unnecessary include +* f1b58b7835 device/pci: Fix PCI accessor headers +* 0c152cf1bb src: Remove unused include device/pnp_def.h +* 6b239d8e08 mb/asus/kgpe-d16: Add BMC KCS to ACPI +* 5513c0a216 mb/asus/kgpe-d16: Enable IPMI KCS access +* 20c294884f amdfam10 boards: Simplify early resourcemap +* 22521ab2e6 amdfam10 boards: Drop extern on apicid_sp5100 +* 2dce923524 mb: Move timestamp_add_now to northbridge/amd/amdfam10 +* 9faae2b939 Kconfig: Unify power-after-failure options +* c70eed1e62 device: Use pcidev_on_root() +* 8803b21bbb amdfam10 boards: Use defaults for get_pci1234() +* b30e2bfe34 amdfam10 boards: Drop array bus_sp5100 +* 6bc6c5548e amdfam10 boards: Use PCI_DEVFN() +* 651f4d231c amdfam10 boards: Drop array bus_sr5650 +* 228746b346 amdfam10 boards: Drop const variable sbdn_sp5100 +* af39e0ebc1 amdfam10 boards: Drop variable sbdn_sr5650 +* c9394017db amdfam10 boards: Drop extern on bus_sr5650 and sbdn_sr5650 +* c0b1be0ba1 amdfam10 boards: Call get_bus_conf() just once +* a2cfe9e900 amdfam10 boards: Add Makefiles and fix resourcemap.c +* d482c7dace amdfam10 boards: Drop global bus_isa variable +* 1db4e3a358 amdfam10 boards: Declare get_pci1234() just once +* a79b3f1c63 amdfam10 boards: Drop unused mb_sysconf.h +* a26b02466e drivers/aspeed/ast: Select `MAINBOARD_HAS_NATIVE_VGA_INIT` +* 21c8f9cab3 mainboard: Remove useless include +* 472d68b066 mb/asus/kgpe-d16: Set ASpeed GPIO SPD mux lines during boot +* f0c5be2a4f mb/*/*/Kconfig: Remove useless comment +* 6d19a20f5f mb: Set coreboot as DSDT's manufacturer model ID +* 0cca6e24b7 ACPI: Fix DSDT's revision field +* f765d4f275 src: Remove unneeded include +* ead574ed02 src: Get rid of duplicated includes +* d2b9ec1362 src: Remove unneeded include "{arch,cpu}/cpu.h" +* 1156b35a23 mainboard: Remove unneeded include +* 718c6faff4 reset: Finalize move to new API +* e20dd19dde amdfam10: Convert to `board_reset()` +* 2c5652d72b mb: Fix non-local header treated as local +* 400ce55566 cpu/amd: Use common AMD's MSR +* dd35e2c8a9 mb: Use 'unsigned int' to bare use of 'unsigned' +* 068253c369 mb/*/*/cmos.default: Harmonise CMOS files syntax +* f716f2ac1a mb/*/*/cmos.default: Decrease debug_level to 'Debug' +* 65bb5434f6 src: Get rid of non-local header treated as local +* 08fc8fff25 src/mainboard: Fix typo +* db70f3bb4d drivers/tpm: Add TPM ramstage driver for devices without vboot. +* 95bca33efa src/mb: Use "foo *bar" instead of "foo* bar" +* c07f8fbe6f security/tpm: Unify the coreboot TPM software stack +* e0e1e64855 amdfam10: Drop tests for LATE_CBMEM_INIT +* d54e859ace mb/asus: Get rid of whitespace before tab +* 1bad4ce421 sb/amd/sr5650: Fix invalid function declarations +* 02b05d1f6b mb/asus: Get rid of device_t +* d88fb36e61 security/tpm: Change TPM naming for different layers. +* 64e2d19082 security/tpm: Move tpm TSS and TSPI layer to security section +* 482d16fb0a src/mainboard: Fix various typos +* ec48c749c2 AMD boards: Fix function name (soft_reset) in message +* 74bd2b0e4c mb/asus/kcma-d8,kgde-d16: Don't select SPI_FLASH_WINBOND +* b29078e401 mb/*/*: Remove rtc nvram configurable baud rate +* 8a8386eeb9 asus/kgpe-d16: Add romstage_handoff +* a26377b063 asus/kcma-d8 kgpe/d16: Fix regression for shutdown +* 714709fde6 AMD fam10 ACPI: Use common fixed sleepstates.asl +* 90e07b460c AMD K8 fam10-15: Consolidate post_cache_as_ram call +* f95911ad37 mainboard/[a-e]: add IS_ENABLED() around Kconfig symbol references +* 26ce9af9a0 device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INIT +* e213bf3767 asus/kgpe-d16: Add video card ID for VGA BIOS name +* 00b9f4c4b1 mb/*/*/cmos.layout: Make multibyte options byte aligned +* 2d35809530 mb/asus/kgpe-d16: Enable TPM when selected in Kconfig +* eca093ecfe mainboard/asus/kgpe-d16: Remove obsolete reference to TPM ASL file +* 06a629e4b1 arch/x86: do not define type of SPIN_LOCK_UNLOCKED +* 75a3d1fb7c amdfam10: Perform major include ".c" cleanup +* a8025db49f amd-based mainboards: Fix whitespace in _PTS comments +* 3a0cb458dc cpu/amd/mtrr.h: Drop excessive includes +* 4607cacf30 cpu/x86/msr.h: Drop excessive includes +* 425890e59a AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already set +* f2b8d7cbd6 mb/asus/kcma-d8,kgpe-d16: use MAINBOARD_DO_NATIVE_VGA_INIT +* 3b87812f00 Kconfig: Update default hex values to start with 0x +* b87a734771 mainboard/*/*/dsdt.asl: Use tabs for indents +* 6350a2e43f src/mainboard/a-trend - emulation: Add space around operators +* 7931c6a81d mb/asus/kgpe-d16: Add TPM support +* 64444268e2 mb/asus/[kgpe-d16|kcma-d8]: Fix whitespace errors in devicetree.cb +* d23ee5de22 mainboard: Clean up boot_option/reboot_bits in cmos.layout +* 8ab989e315 src/mainboard: Capitalize ROM, RAM, CPU and APIC +* bb9722bd77 Add newlines at the end of all coreboot files +* 95fe8fb1e0 mainboard: Format irq_tables.c +* 150f476c96 timestamp: Drop duplicate TS_END_ROMSTAGE entries +* ca543396a7 mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header +* 99894127ab mainboard/asus/[kgpe-di6|kcma-d8]: Fix board ROM information +```` + +#### ASUS KCMA-D8 + +Running `git log src/mainboard/asus/kcma-d8/` we get: + +```` +* cb3e16f287 AMD fam10: Remove HAVE_ACPI_RESUME support +* 04d025cf50 amdfam10: Declare get_sysinfo() +* 8560db6116 amdfam10: Declare empty activate_spd_rom() stub +* e39db681df src/mainboard: Add missing 'include ' +* a1e22b8192 src: Use 'include ' when appropriate +* cd49cce7b7 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) +* 13f66507af device/mmio.h: Add include file for MMIO ops +* 065857ee7f arch/io.h: Drop unnecessary include +* f1b58b7835 device/pci: Fix PCI accessor headers +* 0c152cf1bb src: Remove unused include device/pnp_def.h +* 20c294884f amdfam10 boards: Simplify early resourcemap +* 22521ab2e6 amdfam10 boards: Drop extern on apicid_sp5100 +* 2dce923524 mb: Move timestamp_add_now to northbridge/amd/amdfam10 +* 9faae2b939 Kconfig: Unify power-after-failure options +* c70eed1e62 device: Use pcidev_on_root() +* 8803b21bbb amdfam10 boards: Use defaults for get_pci1234() +* b30e2bfe34 amdfam10 boards: Drop array bus_sp5100 +* 6bc6c5548e amdfam10 boards: Use PCI_DEVFN() +* 651f4d231c amdfam10 boards: Drop array bus_sr5650 +* 228746b346 amdfam10 boards: Drop const variable sbdn_sp5100 +* af39e0ebc1 amdfam10 boards: Drop variable sbdn_sr5650 +* c9394017db amdfam10 boards: Drop extern on bus_sr5650 and sbdn_sr5650 +* c0b1be0ba1 amdfam10 boards: Call get_bus_conf() just once +* a2cfe9e900 amdfam10 boards: Add Makefiles and fix resourcemap.c +* d482c7dace amdfam10 boards: Drop global bus_isa variable +* 1db4e3a358 amdfam10 boards: Declare get_pci1234() just once +* a79b3f1c63 amdfam10 boards: Drop unused mb_sysconf.h +* a26b02466e drivers/aspeed/ast: Select `MAINBOARD_HAS_NATIVE_VGA_INIT` +* 21c8f9cab3 mainboard: Remove useless include +* f0c5be2a4f mb/*/*/Kconfig: Remove useless comment +* 6d19a20f5f mb: Set coreboot as DSDT's manufacturer model ID +* 0cca6e24b7 ACPI: Fix DSDT's revision field +* f765d4f275 src: Remove unneeded include +* ead574ed02 src: Get rid of duplicated includes +* d2b9ec1362 src: Remove unneeded include "{arch,cpu}/cpu.h" +* 1156b35a23 mainboard: Remove unneeded include +* 718c6faff4 reset: Finalize move to new API +* e20dd19dde amdfam10: Convert to `board_reset()` +* 2c5652d72b mb: Fix non-local header treated as local +* 400ce55566 cpu/amd: Use common AMD's MSR +* dd35e2c8a9 mb: Use 'unsigned int' to bare use of 'unsigned' +* 068253c369 mb/*/*/cmos.default: Harmonise CMOS files syntax +* f716f2ac1a mb/*/*/cmos.default: Decrease debug_level to 'Debug' +* 65bb5434f6 src: Get rid of non-local header treated as local +* 08fc8fff25 src/mainboard: Fix typo +* 95bca33efa src/mb: Use "foo *bar" instead of "foo* bar" +* e0e1e64855 amdfam10: Drop tests for LATE_CBMEM_INIT +* d54e859ace mb/asus: Get rid of whitespace before tab +* 1bad4ce421 sb/amd/sr5650: Fix invalid function declarations +* 02b05d1f6b mb/asus: Get rid of device_t +* 482d16fb0a src/mainboard: Fix various typos +* ec48c749c2 AMD boards: Fix function name (soft_reset) in message +* 74bd2b0e4c mb/asus/kcma-d8,kgde-d16: Don't select SPI_FLASH_WINBOND +* b29078e401 mb/*/*: Remove rtc nvram configurable baud rate +* c2a921bec1 asus/kcma-d8: Add romstage_handoff +* a26377b063 asus/kcma-d8 kgpe/d16: Fix regression for shutdown +* 714709fde6 AMD fam10 ACPI: Use common fixed sleepstates.asl +* 90e07b460c AMD K8 fam10-15: Consolidate post_cache_as_ram call +* f95911ad37 mainboard/[a-e]: add IS_ENABLED() around Kconfig symbol references +* 26ce9af9a0 device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INIT +* 00b9f4c4b1 mb/*/*/cmos.layout: Make multibyte options byte aligned +* 06a629e4b1 arch/x86: do not define type of SPIN_LOCK_UNLOCKED +* 75a3d1fb7c amdfam10: Perform major include ".c" cleanup +* a8025db49f amd-based mainboards: Fix whitespace in _PTS comments +* 3a0cb458dc cpu/amd/mtrr.h: Drop excessive includes +* 4607cacf30 cpu/x86/msr.h: Drop excessive includes +* 425890e59a AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already set +* f2b8d7cbd6 mb/asus/kcma-d8,kgpe-d16: use MAINBOARD_DO_NATIVE_VGA_INIT +* 3b87812f00 Kconfig: Update default hex values to start with 0x +* b87a734771 mainboard/*/*/dsdt.asl: Use tabs for indents +* 6350a2e43f src/mainboard/a-trend - emulation: Add space around operators +* 64444268e2 mb/asus/[kgpe-d16|kcma-d8]: Fix whitespace errors in devicetree.cb +* d23ee5de22 mainboard: Clean up boot_option/reboot_bits in cmos.layout +* 8ab989e315 src/mainboard: Capitalize ROM, RAM, CPU and APIC +* bb9722bd77 Add newlines at the end of all coreboot files +* 95fe8fb1e0 mainboard: Format irq_tables.c +* 150f476c96 timestamp: Drop duplicate TS_END_ROMSTAGE entries +* ca543396a7 mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header +* 99894127ab mainboard/asus/[kgpe-di6|kcma-d8]: Fix board ROM information +```` + +#### ASUS KFSN4-DRE + +Running `git log src/mainboard/asus/kfsn4-dre/` we get: + +```` +* ad0f485361 src/mainboard: change "unsigned" to "unsigned int" +* 12ef4f2d71 mb/asus/kfsn4-dre: Return early if CK804 not found +* 04d025cf50 amdfam10: Declare get_sysinfo() +* 8560db6116 amdfam10: Declare empty activate_spd_rom() stub +* a1e22b8192 src: Use 'include ' when appropriate +* cd49cce7b7 coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) +* 7362768c50 arch/io.h: Drop includes in fam10 romstages +* 3855c01e0a device/pnp: Add header files for PNP ops +* 065857ee7f arch/io.h: Drop unnecessary include +* bdaec07a85 arch/io.h: Add missing includes +* f1b58b7835 device/pci: Fix PCI accessor headers +* 8b9768effe amd: Remove unused defines +* 0c152cf1bb src: Remove unused include device/pnp_def.h +* 20c294884f amdfam10 boards: Simplify early resourcemap +* 2dce923524 mb: Move timestamp_add_now to northbridge/amd/amdfam10 +* 993bc7098c amdfam10 boards: Use smp_write_pci_intsrc() +* e9fc8fd9b6 amdfam10 boards: Use PCI_DEVFN() +* 9faae2b939 Kconfig: Unify power-after-failure options +* c70eed1e62 device: Use pcidev_on_root() +* f112f9f912 amdfam10 boards: Use defaults for get_pci1234() +* c0b1be0ba1 amdfam10 boards: Call get_bus_conf() just once +* a2cfe9e900 amdfam10 boards: Add Makefiles and fix resourcemap.c +* d482c7dace amdfam10 boards: Drop global bus_isa variable +* 1db4e3a358 amdfam10 boards: Declare get_pci1234() just once +* 21c8f9cab3 mainboard: Remove useless include +* f0c5be2a4f mb/*/*/Kconfig: Remove useless comment +* 6d19a20f5f mb: Set coreboot as DSDT's manufacturer model ID +* f765d4f275 src: Remove unneeded include +* ead574ed02 src: Get rid of duplicated includes +* d2b9ec1362 src: Remove unneeded include "{arch,cpu}/cpu.h" +* 1156b35a23 mainboard: Remove unneeded include +* 718c6faff4 reset: Finalize move to new API +* e20dd19dde amdfam10: Convert to `board_reset()` +* 400ce55566 cpu/amd: Use common AMD's MSR +* dd35e2c8a9 mb: Use 'unsigned int' to bare use of 'unsigned' +* ddcf5a05e3 mb/asus/kfsn4-dre: Use common pnp_{enter,exit} functions +* 068253c369 mb/*/*/cmos.default: Harmonise CMOS files syntax +* f716f2ac1a mb/*/*/cmos.default: Decrease debug_level to 'Debug' +* 65bb5434f6 src: Get rid of non-local header treated as local +* 08fc8fff25 src/mainboard: Fix typo +* b0f1988f89 src: Get rid of unneeded whitespace +* 448d9fb431 src: Use "foo *bar" instead of "foo* bar" +* 7f268eab78 mainboard/asus: Add license headers +* 02b05d1f6b mb/asus: Get rid of device_t +* 963d312e62 mainboard/asus: Add spaces around '==' +* ec48c749c2 AMD boards: Fix function name (soft_reset) in message +* b29078e401 mb/*/*: Remove rtc nvram configurable baud rate +* 90e07b460c AMD K8 fam10-15: Consolidate post_cache_as_ram call +* f95911ad37 mainboard/[a-e]: add IS_ENABLED() around Kconfig symbol references +* d4ebeaf475 device/Kconfig: Put gfx init methods into a `choice` +* 00b9f4c4b1 mb/*/*/cmos.layout: Make multibyte options byte aligned +* ce642f08b9 Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG +* 75a3d1fb7c amdfam10: Perform major include ".c" cleanup +* a8025db49f amd-based mainboards: Fix whitespace in _PTS comments +* 3a0cb458dc cpu/amd/mtrr.h: Drop excessive includes +* 4607cacf30 cpu/x86/msr.h: Drop excessive includes +* 425890e59a AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already set +* 3b87812f00 Kconfig: Update default hex values to start with 0x +* b87a734771 mainboard/*/*/dsdt.asl: Use tabs for indents +* 6350a2e43f src/mainboard/a-trend - emulation: Add space around operators +* 837618bf20 mainboard/asus/*: transition away from device_t +* d23ee5de22 mainboard: Clean up boot_option/reboot_bits in cmos.layout +* 8ab989e315 src/mainboard: Capitalize ROM, RAM, CPU and APIC +* bb9722bd77 Add newlines at the end of all coreboot files +```` + +------------------------------------------------------------------------------- + +I present unto thee: + +The Free Firmware Song! Also known as the Libreboot Theme Song. + +Sing it with me! + +♫\ +♫ + +Join us now and flash free firmware! ♫\ +You’ll be free! Hackers, you’ll be free! ♪ + +Join us now and flash free firmware! ♫\ +You’ll be free! Hackers, you’ll be free! ♪ + +NSA can spy on all of us, that is true. ♫\ +Hackers, that is true. ♪\ +But they cannot touch our firmware! ♫\ +That is good. Hackers, that is good! ♪ + +When we have enough free firmware, at our call, ♫\ +hackers, at our call: ♪\ +We’ll kick out the management engine, evermore, ♫\ +hackers, evermore! ♪ + +Join us now and flash free firmware! ♫\ +You’ll be free! Hackers, you’ll be free! ♪ + +Join us now and flash free firmware! ♫\ +You’ll be free! Hackers, you’ll be free! ♪ + +♫\ +♫ diff --git a/site/news/libreboot20211122.md b/site/news/libreboot20211122.md new file mode 100644 index 0000000..a0d6c67 --- /dev/null +++ b/site/news/libreboot20211122.md @@ -0,0 +1,110 @@ +% Libreboot 20211122 released! +% Leah Rowe +% 22 November 2021 + +Free your BIOS today! +===================== + +Libreboot is [free](https://writefreesoftware.org/) (as in freedom) boot +firmware, which initializes the hardware +(e.g. memory controller, CPU, peripherals) in your computer so that software +can run. Libreboot then starts a bootloader to load your operating system. It +replaces the proprietary BIOS/UEFI firmware typically found on a computer. +Libreboot is compatible with specifical computer models that use the Intel/AMD +x86 architecture. Libreboot works well with Linux and BSD operating systems. + +The last Libreboot release, version 20210522, was released on May 22nd +in 2021. *This* new release, Libreboot 20211122, is released today on November +22nd, 2021. This is yet another *testing* release, so expect there to be some +bugs. Every effort has been made to ensure reliability on all boards, however. + +You can find this release in the `testing` directory on Libreboot release +mirrors. If you check in the `stable` directory, you'll still only find +the 20160907 release in there, so please ensure that you check the `testing` +directory! + +This is a *bug fix* release, relative to 20210522. No new boards or major +features have been added, but several problems that existed in the previous +release have now been fixed. + +Work done since the 20210522 release: +------------------------------------- + +* Updated to newer coreboot, SeaBIOS and GRUB versions. The 20210522 + release was using coreboot 4.14, on most boards, from May 2021. This release + is using a coreboot revision from November 2021. +* Tianocore dropped from the build system. It was planned that this would be + provided in ROM images, but Tianocore is very bloated and buggy, and not + worth maintaining. It was supported in the build system, but not actually + enabled on any boards. Instead, a future release of Libreboot will include + a busybox+linux payload with the u-root bootloader: + +* New upstream used for SeaBIOS: +* Dummy PIKE2008 option ROM now automatically inserted into ASUS KGPE-D16 and + KCMA-D8 ROM images. It is literally an empty file. This disables the option + ROM from being loaded, which is known to hang SeaBIOS on these boards. +* 16MB configs now available, for more boards. For instance, ThinkPad X60 and + T60, ASUS KGPE-D16, etc. It's always possible to upgrade the flash, and + information about this is provided in the documentation. +* `memtest86+` included on more ROMs by default (where text mode startup is used) +* `memtest86+`: Now coreboot's own fork is used, instead of upstream. This fork + works much more reliably on coreboot targets, when running on bare metal. +* More 16MB configs added, for more boards. This will be finished by the time + of the next release. Already, several older laptops such as the ThinkPad X60 + or T60, have these configs in the latest `lbmk.git`. If you upgrade the + default SPI flash to 16MByte / 128MBit (maximum size possible), you can then + easily put an entire busybox+linux system in the flash. +* `coreboot`: Added persmule's 2016 patch to enable more SATA/eSATA ports on + ThinkPad T400. This change benefits T400S users. +* `grub.cfg`: LUKS setups are now detected on mdraid setups. +* `grub.cfg`: Default timeout changed to 10 seconds, instead of 1. This benefit + desktop users, who previously complained about not having time to respond if + they wanted to interact with the boot menu. +* `grub.cfg`: Performance optimization when scanning for encrypted LUKS volumes. + GRUB will stall a lot less often, and feel more responsive, when dealing with + LUKS-encrypted setups. +* `coreboot`: cstate 3 now supported on MacBook2,1 and Macbook1,1. This results + in lower CPU temperatures and higher battery life on idle. Thanks go to + vitali64 on IRC for this fix +* Reset bug fixed, on GM45 platforms (ThinkPad X200/T400/T500 and so on). These + laptops did not reliably reboot, on the Libreboot 20210522 testing release. + They now reboot reliably, with this fix. See: + +* `lbmk`: Use `env` instead of hardcoding the bash path, in bash scripts. This + should make the build system slightly more portable between distros. +* Turkish keyboard layout added on GRUB payloads + +New release schedule under consideration +======================================== + +The 20210522 release happened to coincide with coreboot 4.14's release, more +or less. + +This release also coincides roughly with the coreboot 4.15 release, which came +out on November 5th. See: + + +Coreboot has, since the 4.15 release, decided to release every 3 months instead +of every 6. That means the coreboot 4.16 release is planned for February 2022. + +I'm considering this: 2 releases every 3 months, of Libreboot. A testing release +and then a fork of that is created, to fix bugs ready for a stable release 3 +months later, while simultaneously working (in the lbmk master branch) towards +another testing release. *If no stable release is available at the same time as +a testing release, then delay it if the delay will be minimal, otherwise +cancel and abandon that particular stable branch.* + +So: if I do this, the next stable release of Libreboot could be in February +2022 based on bug fixes of this November 2021 release, using coreboot 4.15. +A testing release could be simultaneously made, with perhaps extra features, +and based on coreboot 4.16. + +I'm considering it. In general, I do want Libreboot to be in sync with the +coreboot project, but coreboot does not guarantee stability in their releases. +Rather, releases are regarded as *milestones* for the coreboot developers to +reflect on current developments, and plan the next few months. + +When Libreboot first started, coreboot did not have a fixed release scheduled. +It was purely rolling release. Coreboot however has been quite reliable with +its own release schedules in the past few years, making it viable for Libreboot +to also have a fixed schedule. diff --git a/site/news/libreboot20220710.md b/site/news/libreboot20220710.md new file mode 100644 index 0000000..edcf1a3 --- /dev/null +++ b/site/news/libreboot20220710.md @@ -0,0 +1,127 @@ +% Libreboot 20220710 released! +% Leah Rowe +% 10 July 2022 + +Free your BIOS today! +===================== + +Libreboot is [free](https://writefreesoftware.org/) (as in freedom) boot +firmware, which initializes the hardware +(e.g. memory controller, CPU, peripherals) in your computer so that software +can run. Libreboot then starts a bootloader to load your operating system. It +replaces the proprietary BIOS/UEFI firmware typically found on a computer. +Libreboot is compatible with specifical computer models that use the Intel/AMD +x86 architecture. Libreboot works well with Linux and BSD operating systems. + +The last Libreboot release, version 20211122, was released on November 22nd +in 2021. *This* new release, Libreboot 20220710, is released today on July +10th, 2022. This is intended to be a *stable* release, with some caveats. + +This is a *bug fix* release, relative to 20211122. No new boards or major +features have been added, but several problems that existed in the previous +release have now been fixed. + +Build from source +----------------- + +*This* release was build-tested on Debian 11. Your mileage may vary, with +other distros. + +Work done since the 20211122 release: +------------------------------------- + +* Lots and lots of improvements to the documentation. Previous 2021 testing + releases did not include snapshots of the documentation (which is actually + the Markdown source files for the website), but this release *does* include + now a snapshot of the current Libreboot documentation, as per the time of + release. +* grub.cfg: Many performance improvements, improving the boot speeds + when using the GRUB payload (courtesy Ferass 'Vitali64' EL HAFIDI with + additional improvements made by Leah Rowe) +* GM45/ICH9M laptops: Disable PECI in coreboot, to work around a microcode bug + causing SpeedStep (and possibly other CPU features) to fail. +* Do not treat warnings as errors when building flashrom (fixes building on + newer versions of GCC). +* Macbook2,1: 16MB configurations now available (you must first upgrade the + SPI flash) +* Build system improvement: automated scripts for modifying coreboot configs. +* Disable (by default) serial output on all boards, to prevent boot speed + issues. +* grub.cfg: Actually enable USB keyboards, explicitly (works around bug seen + on some laptops, when using the GRUB payload). +* Coreboot configs: Do not enable wifi during early init (security liability) +* Preliminary u-boot integration; not used in any boards yet, but future + full integration is planned, for several ARM platforms. U-boot is not + included in the release archives, but logic does exist in the build system. + Courtesy of Denis 'GNUtoo' Carikli. +* Scripts in lbmk: improved help output, courtesy of Denis 'GNUtoo' Carikli. +* scripts: process git versions when lbmk is a worktree or submodule. Courtesy + John Doe (cool guy) +* Updated to newer flashrom, in the build system +* Perform silentoldconfig in seabios before full make. This fixes a race + condition when rebuilding SeaBIOS with a high CPU count, resulting in failure + with the error message (fix courtesy of John Doe): + + cc1: fatal error: can't open 'out/src/asm-offsets.s' for writing: No such file or directory + +* lbmk: Specifically call python3, when python3 is to be used instead of 2. +* lbmk: Preliminary fix for git credentials check. Set a placeholder name/email + if one is not set. + +Caveats +------- + +Due to reported issues by users, these boards do not have ROM images +available in the Libreboot 20220710 release: + +* KGPE-D16 ROM images not included +* ditto KCMA-D8 +* ditto GA-G41M-ES2L + +The boards listed above can still be compiled, from the source code archive +in this release and from the Libreboot git repository; additionally, ROM images +are provided for these in the previous release. D8/D16 continue to have raminit +issues; for now, use the 2021 releases. The next Libreboot release will +merge newer patches that are available for this board, improving raminit +reliability (among other things); that new release will, when available, have +D16 ROMs included. + +All other boards are reasonably stable, and shouldn't provide any issues (no +major issues reported, and/or non-blocking issues only). + +Planned future work +=================== + +In general, you should also check the issue tracker to find other notes. +There is always more work to do, to improve Libreboot. + +Support for non-x86 platforms +----------------------------- + +This is still on hold, but will be done as part of a future release. +The coreboot firmware does support other platforms. + +Linux distro in flash +--------------------- + +This is another project that has been on hold for a while. The issue +has been that I need a decent userland project. I've looked at many +different userlands and recently (as of late June) decided to make +my own. I want a BusyBox-like solution, but based on code from OpenBSD, +ported to run under Linux with musl libc. + +I want this distro to provide a kexec bootloader in flash, similar to Heads, +and I also want it to use apk-tools, pointing at Alpine Linux repositories +so as to allow any number of packages to be downloaded. It could also provide +lots of utils in general, to be a live *rescue system* of sorts. Linux system +in flash, that can bootstrap other systems. + +Re-factor and optimize GRUB +--------------------------- + +GRUB is full of unused bloat that almost nobody uses, yet is in the current +Libreboot builds. It's been on TODO for some time, but work has not yet +begun on this project. My efforts are currently focused on the Linux distro. + +What I want is a fork of GRUB, optimized to run on bare metal as a coreboot +payload, on x86 and ARM platforms. diff --git a/site/news/mirrors.md b/site/news/mirrors.md new file mode 100644 index 0000000..b722c96 --- /dev/null +++ b/site/news/mirrors.md @@ -0,0 +1,53 @@ +% New Git repositories added as backup mirrors +% Leah Rowe +% 11 April 2023 + +Libreboot's mission is to help as many people use coreboot as possible. This +means Libreboot should reach out to as many people as possible. By maintaining +a presence on *several* websites, it can do just that! + +So today, I started making accounts on a few of the more popular Git hosting +platforms that seem *reasonable* from a +[software freedom](https://writefreesoftware.org/) perspective, or are +otherwise places where lots of freedom-minded people might see it. These +mirrors are provided as a *backup*, in case the main Codeberg mirror is ever +offline for any reason. + +I can now announce the following *official* mirrors of Libreboot's git +repository, controlled directly by the Libreboot project; first, the build +system (lbmk): + +* +* +* +* +* +* + +Secondly, lbwww (markdown files for the Libreboot website): + +* +* +* +* +* + +All of these mirrors were created *today*, and they are listed on the Git +page. See: + +[Libreboot git repositories / code review page](../git.md) + +More mirrors will be created over time, and added as they become available. +If you know of a decent Git site where you think Libreboot should mirror on, +or you're the *operator* of such a site and want Libreboot on there, feel free +to [get in touch](../contact.md)! + +UPDATE: on 12 April 2023, Libreboot gained these additional mirrors: + +* +* + +UPDATE: on 15 April 2023, Libreboot gained these additional mirrors: + +* +* diff --git a/site/news/news-list.md.include b/site/news/news-list.md.include new file mode 100644 index 0000000..54b932b --- /dev/null +++ b/site/news/news-list.md.include @@ -0,0 +1,10 @@ +--- +title: Libreboot news +x-toc-enable: true +... + +News about Libreboot, both technical and organisational. Releases are also +announced here. + +------------------------------------------------------------------------------- + diff --git a/site/news/news.cfg b/site/news/news.cfg new file mode 100644 index 0000000..89b9fbb --- /dev/null +++ b/site/news/news.cfg @@ -0,0 +1,2 @@ +BLOGTITLE="News for libreboot.org" +BLOGDESCRIPTION="News for libreboot.org" diff --git a/site/news/translations.de.md b/site/news/translations.de.md new file mode 100644 index 0000000..f0b9836 --- /dev/null +++ b/site/news/translations.de.md @@ -0,0 +1,77 @@ +% Übersetzungen benötigt +% Leah Rowe +% 4 January 2022 + +Die Libreboot Webseite ist derzeit nur in Englisch verfügbar. + +Ich habe kürzlich Unterstützung für Übersetzungen zum +[Untitled Static Site Generator](https://untitled.vimuser.org/) hinzugefügt, +welcher von der Libreboot Webseite verwendet wird. Die Seiten auf +libreboot.org sind in Markdown geschrieben, und diese Software erzeugt +HTML Seiten. + +Die Seite die Du gerade liest wurde auf diese Weise erstellt! + +Vorbereitung +=============== + +Die Libreboot Webseite ist verfügbar, in Markdown, über ein Git Repository:\ + + +Anleitungen zum senden von Patches sind hier verfügbar:\ + + +Wenn Du an einer Übersetzung arbeitest, notiere Dir die commit ID auf `lbwww.git` +und verfolge weitere Änderungen (an der englischen Webseite) in diesem +Repository. + +Wenn Du die Übersetzung sendest, gib bitte an mit welcher commit ID auf +`lbwww.git` diese übereinstimmt. Von dort an werde ich die Änderungen an +der englischen Seite nachverfolgen, an welcher ich arbeite. Meine +Muttersprache ist englisch. Wenn die erste Übersetzung auf libreboot.org +verfügbar ist, werde ich eine neue Seite erstellen (nur in englisch), und +dort jedesmal vermerken wenn ich Änderungen an der Seite vornehme, und +zeigen wo diese Änderungen dann auf übersetzten Seiten erledigt werden +müssen für jede Seite die ich ändere. + + +Wie übersetzt man libreboot.org +============================== + +Die Dokumentation auf erläutert wie Du +Übersetzungen handhaben kannst. + +Ich empfehle das Du einen lokalen Nginx HTTP Server auf deinem Computer +einrichtest, und Untitled hierfür konfigurierst, mithilfe der Anweisungen +auf der Untitled Webseite. Dies wird es vereinfachen zu sehen wie deine +übersetzte Seite aussieht, bevor diese live geht. + +**Es wird empfohlen das Du eine Firewall installierst, wenn Du Nginx +verwendest, sofern Du nicht tatsächlich möchtest das es öffentlich +zugänglich ist. Die `ufw` Software ist sehr nett** + + sudo apt-get install ufw + sudo ufw enable + +Dies wird jeglichen unerwünscht eingehenden Datenverkehr blocken. Dies ist +ohnehin eine bewährte Praktik, für Workstations. Du musst nicht ufw verwenden, +aber es ist ein nettes Frontend für iptables/ip6tables auf Systemen die +den Linux Kernel verwenden. Weitere Informationen über `ufw` sind hier +verfügbar: + + + +Wenn Du deine lokale Webseite betrachten möchtest, musst Du lediglich +`http://localhost/` in deinen Browser eingeben. Dies wird deine lokale +loopback Adresse aufrufen. + +Grundsätzlich wirst Du mit `md` und `include` Dateien arbeiten. +Halte Ausschau nach Dateien mit `template`, `footer` und `nav` im Dateinamen. +Weitere Informationen darüber wie Untitled funktioniert ist verfügbar auf +der Untitled Webseite. Du solltest ebenso eine übersetzte `strings.cfg` +Datei zu Untitled hinzufügen für deine Übersetzung, sofern Untitled diese +nicht unterstützt. + +Du kannst Seiten in jeder Sprache zu Untitled hinzufügen, Die Software +generiert automatisch ein Menü zur Sprach-Auswahl, auf Seitenbasis sofern +eine Übersetzung für die jeweilige Seite vorliegt. diff --git a/site/news/translations.md b/site/news/translations.md new file mode 100644 index 0000000..3ae0c7c --- /dev/null +++ b/site/news/translations.md @@ -0,0 +1,70 @@ +% Translations wanted +% Leah Rowe +% 4 January 2022 + +The libreboot website is currently only available in English. + +I've recently added support for translations to +the [Untitled Static Site Generator](https://untitled.vimuser.org/), which the +libreboot website uses. Pages on libreboot.org are written in Markdown, and +this software generates HTML pages. + +This very page that you are reading was created this way! + +Getting started +=============== + +The libreboot website is available, in Markdown, from a Git repository:\ + + +Instructions for how to send patches are available here:\ + + +If you're working on a translation, make note of the commit ID from `lbwww.git` +and keep track of further changes (to the English website) in that repository. + +When you send the translation, please specify what commit ID in `lbwww.git` it +is up to date with. From then on, I will keep track of changes to the English +website, which is what I work on. My native language is English. When the first +translation is made available on libreboot.org, I will create a new page (in +English only), and add notes to it whenever I make site changes, and show +where these changes need to then be performed in translated versions of each +page that I change. + +How to translate libreboot.org +============================== + +The documentation on tells you how to handle +translations. + +I recommend that you set up a local Nginx HTTP server on your computer, and +configure Untitled for it, using the instructions on the Untitled website. This +will make it easier to see what your translated website looks like, before it +goes live. + +**It is recommended that you install a firewall, if you're running Nginx, +unless you actually want it to be publicly accessible. The `ufw` software is +quite nice:** + + sudo apt-get install ufw + sudo ufw enable + +This will block all unsolicited incoming traffic. It's good practise anyway, +for workstations. You don't have to use ufw, but it's a nice frontend for +iptables/ip6tables on systems that use the Linux kernel. More information +about `ufw` available here: + + + +When viewing your local website, you can just type `http://localhost/` in your +browser. This will resolve to your local loopback address. + +In general, you will be working with `md` files and `include` files. +Keep an eye out for files with `template`, `footer` and `nav` in the name. +More information about how Untitled works is available on the Untitled +website. You should also add a translated `strings.cfg` file to Untitled, for +your translation, if Untitled doesn't support it. + +You can add pages in any language to Untitled. The software automatically +generates language selection menus, on a per-page basis, when a translation is +available for a given page. diff --git a/site/news/usa-libre-part2.md b/site/news/usa-libre-part2.md new file mode 100644 index 0000000..46ec068 --- /dev/null +++ b/site/news/usa-libre-part2.md @@ -0,0 +1,213 @@ +% New Hampshire once again on the cusp of enshrining Software Freedom into law. YOUR HELP IS NEEDED. +% Leah Rowe +% 12 February 2023 + +Introduction +============ + +This article makes use of the term *libre software*, which has the same meaning +as more popular terms such as *open source software* +or *[free software](https://writefreesoftware.org/)* +or *free and open source software*. More information can be found about +it [here](https://writefreesoftware.org/) - to the Libreboot +project, this is important because it talks about your *freedom* to study, +adapt, share and re-use software as you see fit, alongside the rest of +humanity in a collective development effort, as opposed to the alternative +where we would be restricted by companies like Microsoft or Apple, who only +care about *controlling us* to make money. + +You may recall last year's article: [New Hampshire (USA) may soon enshrine +Software Freedom into law](usa-libre.md) - a proposed bill, if it passed, +would have provided official legal protections in favour of libre software in +the state of New Hampshire, in the United States. The bill didn't pass, largely +because of a complaint that the bill was too all-encompassing, and so the idea +then was that the bill should be split into a series of smaller bills that, in +combination, achieve the same goals. + +Since then, Eric Gallager (the representative behind the original bill) in +New Hampshire has done exactly that, and a new hearing takes place very soon, +on the *16th of February, 2023, at 1PM*. + +I once again call to action, any person that lives in New Hampshire or the +surrounding states in the USA. Your participation could help secure the rights +of all libre software users and developers, well into the future. I myself do +not live in the US, so I'm hoping that my American readers will listen well to +what I have to say. + +With your help, libre software could suddenly find itself in a much stronger +position, with more users and more developers, encouraged by such positive +changes. + +When, who, what and where? +------------------ + +Eric Gallager, the representative behind the previous bill, has continued his +efforts and now has a new hearing for the following bill very soon: + +* **16 February 2023, 1PM**: prohibiting, with limited exceptions, state + agencies from requiring use of proprietary software in interactions with the + public (house bill: HB 617-FN) + +The text of the proposed bill can be read here: \ + + +It is critical that as many people show up as possible, to express support for +the bill, and to defend it against any opposition. + +**Location of hearing: Legislative Office Building in Concord, New Hampshire:\ +** + +The bill's hearing shall take place in room 306-308. + +Who to contact +-------------- + +Eric Gallager is the representative in charge of the proposed bill, and you can +contact him in the following ways: + +Email address: \ +[Eric.Gallager@leg.state.nh.us](mailto:Eric.Gallager@leg.state.nh.us) + +Mastodon page: \ + + +Twitter page (use of Twitter is ill advised, due +to its proprietary nature - use Mastodon or email if you can): \ + + +Why should you support this bill? +================================= + +If this newly proposed bill is passed, it will provide the libre software +movement a *foot in the door*, that could lead to greater reform at a later +date, and strengthen the entire movement. This is because of the knock-on +effect it would have: as more people benefit from it, more states (in the US) +and countries outside of the US may follow, implementing similar laws. + +Laws are often made that reduce our freedoms. If any law should be passed, it +should be a law that strengthens or otherwise reaffirms civil liberties, which +is what the proposed bill aims to do. + +Libre software is about civil liberties, as it pertains to computer science, +because of the *right to learn* and the *right to read*. Just as mathematics +or physics should be free for anyone to study and make use of, so too should +that be the case for computer science. + +Any civil liberties that we have today are the result of *laws* that protect +them, because the purpose of law is to provide punishment for violation; if +no law exists, for or against something, then no punishment can take place. +For example, most countries have a law that says you should not be robbed; if +someone then robs you, then they get punished with jail time. The right to +private property is an important right. + +If no laws exist that protect libre software projects, then they are +vulnerable. + +Just as you should have the right to property, you must also have the right to +pursue a happy, productive life - the right, in practise, to work on libre +software should be part of that, if computer science is something you're +interested in. + +This right *also pertains to property*, specifically the property that is your +computational devices; tablets, PCs (desktops, laptops), whatever you use. +Libre software lets you truly *own* your computer, because it doesn't leave +you beholden to a *licensor*. You have the right to study, adapt, share and +re-use the software infinitely, and other people also have this right. With +libre software, your computer is no longer a *product* for a specific purpose +per se, but rather, a general purpose machine that can be reprogrammed +for *any purpose as you see fit*. This is similar to your right to have your +car modified, or repaired by anyone, including you, or perhaps your right to +reorganise (even completely re-build) your house. + +The proposed bill's hearing, on the 16th, regards the usage of proprietary +software by state agencies. *State agencies* could include schools run by the +state, but it could also include things like your local tax office. When you +file taxes, it is often the case that it cannot be done without running some +proprietary software, and many schools will insist that their students use +Windows (or other proprietary OS) rather than, say, Linux or BSD. By mandating +in law that people should be able to use *libre* software, it will create a +level playing field, because the state would *have to* make accomodation for +libre software; while initially a burden (time and money spent), it would be +a huge social boon later on, because if states stop relying on proprietary +software licenses, the money they currently spend on that can instead be spent +elsewhere, or on paying programmers, providing *better software* to the public; +the actual overall cost may be exactly the same as today, but with more +benefits for everyone, not to mention greater freedoms for computer users. + +To put it simply: the right to your (computational) property would be enhanced +by this bill's passage, by forcing the state to support libre software, against +the whims of proprietary software vendors. This, like anything that strengthens +the libre software movement, would increase the likelihood that you can actually +use libre software, on computers that you buy in the future, which means that +your *right to your own property* is enhanced, because at the end of the day, +that's exactly what *software freedom* is all about. + +We can all agree about education. The idea that people should be able to learn +and grow as people is natural, and we all want to better ourselves. Libre +software is an important part of that, in the field of computer science. +We can also agree about private property. + +What about money? Is this not an important part too? Is it not true that, with +private property, you can also have *private enterprise*? + +Libre software is very *profitable*, to a far greater extent than proprietary +software. When the free exchange of ideas and knowledge is permitted to flow, +innovation is much more likely. We can talk all day about the right to education +but money matters too. Many software developers *learn* on libre software, +because that is the only way to get really good with computers. You can't become +a competent programmer by using Windows or MacOS. Linux or BSD are your only +real choice, because that's where all the interesting development happens. +Today's most profitable industries are powered by libre software; without +it, we would be living in a very different world today, locked down by the +likes of Microsoft or Apple who see software as a *product*, a *means to an +end*, rather than the end in itself, that end being knowledge and +self-empowerment. Technology has given us many freedoms today, thanks to the +tireless efforts of libre software developers everywhere. + +For example: nearly every website you visit runs on some Linux or BSD system, +probably running the Apache web server, or (much more common nowadays) nginx. +Windows just doesn't scale as a *server* OS, it is completely inflexible, but +linux and bsd systems can be tweaked to do whatever you want. + +When I say *libre software is profitable*, I'm not referring to Microsoft +or Apple's profits. No, I'm referring to *yours*. With libre software, *you* +have the freedom to make real money; I'm just one of many examples of people +who do just that. With *software freedom*, you can take existing technology +and build something completely new that becomes the Next Best Thing; everyone +else has this freedom aswell, and people share knowledge freely because of the +culture that type of world inspires. It's the world we live in, now. + +The people of New Hampshire will benefit greatly, if such freedoms are +enshrined in law. It will be a huge success, and it will lead to more +jurisdictions (both within and outside the US) to follow suit. It will lead to +the *end* of monopoly powers like Microsoft or Apple, completely opening up +the entire body of knowledge to everyone, because that will become the norm; +hoarding knowledge will become *unprofitable*, because the new culture would +simply not allow it, so companies like Microsoft and Apple, if they want to +remain relevant, would have to start releasing more source code themselves, +rather than keeping everything proprietary. The people of the world will stop +seeing them as a gold standard; they are not, and have never been. Libre +software has always been superior, in every way, to proprietary software, +because it allows you to actually *own* the computer you bought, in practise +and in spirit. + +Proprietary software is like renting a house; you have a license to use it, +but you don't have the freedom to really change anything, and the licensor +(equivalent to a landlord) can pull the plug at any time. Libre software, on +the other hand, is equivalent to owning a house. When you run all libre software +on your computer, *you* control that computer. You can modify whatever you want, +or pay whoever you want to do that for you, to maintain everything for you, +and you can share your work with others, something which other people already +do; it's the reason libre software is so successful, precisely that people +share their knowledge. + +The state is an important part of our lives, no matter which country or +jurisdiction we live in. We interact with it constantly, for services that we +all rely on, so it is important that we should be *able to* with the software +of our choice. This is why it's so important that the state, in any +jurisdiction, take steps to ensure that libre software users don't get left +behind. If passed, this will will strongly reinforce the *right* of computer +users everywhere, to their own computational property. + +Please, please please if you can take time out of your day, then please show +up to to defend this bill and make sure that it gets passed! diff --git a/site/news/usa-libre-part3.md b/site/news/usa-libre-part3.md new file mode 100644 index 0000000..b599878 --- /dev/null +++ b/site/news/usa-libre-part3.md @@ -0,0 +1,113 @@ +% NEW New Hampshire software freedom bill hearing on 21 February 2023 needs your support! +% Leah Rowe +% 20 February 2023 + +Introduction +============ + +You may recall last year's article: [New Hampshire (USA) may soon enshrine +Software Freedom into law](usa-libre.md) - a proposed bill, if it passed, +would have provided official legal protections in favour of libre software in +the state of New Hampshire, in the United States. + +Last year's bill didn't pass, so Eric Gallager, the person behind it, started +splitting it into smaller bills that are more likely to pass; this recently +cultimated first in [house bill 617-FN](usa-libre-part2.md) for which there was +a hearing. + +Now, there is another upcoming bill hearing: house bill 556-FN:\ + + +It is critical that as many people show up as possible, to defend the bill +and advance the cause of *[software freedom](https://writefreesoftware.org/)*. + +*New Hampshire residents: In addition to showing up on the day, you can also +contact your house representative, and ask them to support this bill! This +web page can let you find who your representative is:\ +* + +Can't attend? +------------- + +That's OK! You can still help. Please tell as many people about this as +possible, and spread the news on as many websites/blogs as possible. Post it +on your social media account, if you have one. Write to the media! + +When and where? +=============== + +**This bill's hearing is on 21 February 2023 at 9AM in the Legislative Office +Building, 33 N. State Ct., Concord, New Hampshire:**\ + + +Please, please if you can, show up to the hearing! New Hampshire needs *you*. +If this and similar bills pass, in New Hampshire, it will spread like wildfire +to many other states, and countries, bringing us many steps closer to a world +where *everyone* has the ability to use libre software *exclusively* - such is +the goal of the movement, and that of the Libreboot project which is a part of +said movement. + +Who to contact +============== + +Eric Gallager is the representative in charge of the proposed bill, and you can +contact him in the following ways: + +Email address: \ +[Eric.Gallager@leg.state.nh.us](mailto:Eric.Gallager@leg.state.nh.us) + +Mastodon page: \ + + +Twitter page (use of Twitter is ill advised, due +to its proprietary nature - use Mastodon or email if you can): \ + + +What does house bill 556-FN say? +================================ + +The actual text of the bill is provided here:\ + + +If passed, the New Hampshire Information Technology Council would then be +required, by law, to promote software freedom to the Department of Information +Technology Commissioner. This would include analysis of practical issues such +as cost, and deployment strategies for libre systems to replace current +proprietary systems; more importantly, it would require them to study ways of +reducing (or eliminating) the need for citizens to use proprietary software +for interactions with the state. The bill also promotes the principle +of *copyleft* licensing, such as the GPL; regardless of how you feel about +copyleft versus permissive (BSD-style) licensing, the advancement of *any* +libre software on such massive scale will help the entire movement. + +Live streams +============ + +Although not mentioned in previous articles on this agenda, the New Hampshire +court building provides live streams of hearings. + +Link to New Hampshire courthouse youtube channel: + + +The last few software freedom bills were streamed on this one: + +*House Executive Departments and Administration* + +Per the text of HB-556, the stream for *that* bill will be on: + +*Science, Technology and Energy* + +The links change, for each stream, so you should check them on the day. + +Use invidious! +-------------- + +The Youtube.com link is provided, above, for the sake of completion. However, +you should use an Invidious instance. Invidious acts as a proxy for Youtube, +preventing Google from sniffing your habits or collecting data, and it also +bypasses the need for running proprietary JavaScript code. + +Here's a link to the New Hampshire court channel, on an *excellent* Invidious +instance (excellent in terms of uptime, and speed): + + diff --git a/site/news/usa-libre.md b/site/news/usa-libre.md new file mode 100644 index 0000000..2bf5e52 --- /dev/null +++ b/site/news/usa-libre.md @@ -0,0 +1,273 @@ +% New Hampshire (USA) may soon enshrine Software Freedom into law. YOUR HELP IS NEEDED! +% Leah Rowe +% 8 January 2022 + +Introduction +============ + +This event of such global importance to libre software projects, and the +libre movement as a whole, has made me decide to write an article. **The +events in question, covered by this article, will occur on 11 January 2022. +This is just three days away from today, 8 January 2022 when this article was +written, so if you make a decision, you should make it now, today, and prepare. +Please continue reading.** + +If you live in New Hampshire or in one of the neighbouring states, especially +Massachusetts, please listen up! If you are further away and unable to reach +New Hampshire all that easily, please spread the following news anyway. It's +important. As alien as it may seem to many of my readers, I'm actually writing +parts of this article as though someone who has never heard of Libre Software +(often referred to as *Open Source Software*) is +reading it, because I expect precisely that such people *will* read this +particular article. + +When we say libre software, we mean software that gives people the +[freedom](https://writefreesoftware.org/) to +freely study, adapt, share, use and re-use all code or documentation, so as to +enable the free exchange of ideas and, simply speaking, democracy. This is your +Linux distros, BSD projects, and accompanying software that typically comes +packaged. It is sometimes referred to as *Open Source Software*. The word libre +is Spanish for "liberty", meaning freedom. With such software, you, the user, +are able to control your own computing according to your own priorities, which +you otherwise would not be able to do. + +The opposite of libre software is called *proprietary software*. The purpose +of Libreboot is to help users *avoid* proprietary software at the firmware +level, whenever feasible. + +What's happening in New Hampshire? +================================== + +An important bill is being proposed in New Hampshire, which would enshrine +much of what we know as Open Source *into law*. Here is the proposed bill, +technically named "HB1273":\ + + +You can read it for yourself, but here is a paraphrasing of what it proposes: + +* *Specifically* bans state-run websites from serving proprietary javascript to + clients +* Creates a commission to provide oversight, watching the use of libre code by state agencies +* Bans state agencies from using proprietary software - maybe this could include schools, in the future! +* If a person is tried in a criminal case, they have the right to audit the source code of any proprietary software that collects evidence against them +* Encourages data portability (able to transfer data from one program to another) +* Bans certain non-compete clauses and NDAs (non-disclosure agreements) pertaining to Libre Software projects +* Bans state/local law enforcement from assisting with the enforcement of copyright claims against libre software projects +* Bans state agencies from purchasing proprietary software if libre software exists, for a given task + +However, this is only a short summary. You are advised to read the bill in +detail. It's not very long. + +At first glance, it may not seem that the bill affects individuals, but don't +be fooled; this is a hugely positive step forward for everyone! If the state is +using Libre Software, that most likely means it'll be used in education aswell. + +Although perhaps not immediately and readily apparent, this is a stake in the +heart of proprietary software's current dominance, because it would remove one +key element of its attack against us; its abuse of education services. + +If education services are using Libre Software, that means they'll probably have +children (the ones being educated) using it too. This is a *huge* step, and it +will result in more Libre Software developers in the future. Libre Software will +become more and more mainstream to the masses, which can surely only be a good +thing! + +Freedom is always superior. The more people that have it, the better off we all +are, because freedom is also collective; it relies on others around us also +having it, so that we can defend each other. If more people have it, especially +if it results in more Libre Software developers in the future, that's one thing, +but imagine if *more* states like what they see and start to copy the new +legislation. + +Now imagine that countries besides the US start doing it, inspired by the US's +success (and I think it will be a resounding success). + +Imagine a world where such liberties over software are commonplace, actually +the default everywhere! Imagine a world where it's considered as important as +the ability to freely learn mathematics, or physics, as required reading +material in schools. *Imagine a world where any five year old can install a +libre operating system such as Linux/BSD, and Computer Science is mandatory in +schools from a young age. Imagine filing your tax returns with Libre Software, +exclusively. Imagine not even thinking about that, because it became the norm.* + +*Imagine a world where proprietary software doesn't exist, because it is +obsolete; entire generations of people are taught to value freedom, and to +staunchly defend it, helping each other learn and grow (and produce better +software in the process, with less bugs, because people are now free to do +that, without relying on some evil company).* + +Imagine a world where you're no longer being spied on because NSA, Apple and +Microsoft no longer have backdoor access to your computer. *Imagine having the +ability to say no, because that's what freedom is. Try to imagine it!* + +One of our biggest problem has been simply that schools and governments do not +teach people about free computing. The right to learn, the right to read and +the right to hack. Our governments are made up of human beings just like you or +me, and they can be bought/corrupted; Microsoft, Apple and many others (such as +IBM) have done this for years, having the national infrastructures governing us +run on their proprietary systems, instead of systems that respect freedom; it +is essential that these systems run libre software, because a free and democratic +society should expect nothing less. Those companies buy influence *and they own +your politicians*. + +All of this could change very soon. Something is happening in New Hampshire, +which could redefine our movement and give *libre software* real power +instead. + +HOW TO HELP +=========== + +TESTIFY IN SUPPORT OF THE BILL +------------------------------ + +**The reading of the bill is happening on 11 January 2022. This is when you +should go to New Hampshire.** + +**Location of hearing: Legislative Office Building in Concord, New Hampshire:\ +** + +The organizer of the proposed bill, *Eric Gallager*, has left instructions on +Twitter. The following is a *nitter* link, which lets you view the relevant +Twitter thread without running libre Javascript in your browser:\ + + +Further instructions for what room to go to, when you get there:\ + +See Nitter link:\ + + +(original twitter link: ) + +**Please read both threads very carefully!** + +**YOU NEED TO GO TO NEW HAMPSHIRE IN PERSON!** + +If you're able to go to New Hampshire to attend the reading of the bill, please +do so! Voice your support of the bill, and say why you think it's important. + +Tell the lawmakers that you demand freedom! + +This thread on Twitter is where Eric announced that the reading of the bill is +to proceed (original Twitter URL):\ + + +More states/countries will follow +--------------------------------- + +If this bill is passed in New Hampshire, more states will likely follow. It +will lead to a massively renewed drive to liberate all computer users, and US +laws tend to be copied/pasted around the world too. + +This bill, if passed, will have a hugely positive impact on Libre Software at a +global level. + +You *must* support this bill. If you want to see it pass, please go to New +Hampshire on 11 January 2022 to make sure your voice is heard. + +OUR ENEMIES WILL BE THERE +------------------------- + +The *proprietary* software companies like Microsoft and Apple will also be +there, trying to argue the case *against* the use of Libre Software. + +There is already precedent; please watch this video, which shows how Microsoft +(for example) might behave in the reading of the bill. This video is from a +discussion within the European Union, several years ago:\ + (invidious link. works without +javascript enabled, if you wish) + +They will try to trick the law makers by claiming things such as: + +* **"Open Source is insecure / you will get hacked"** - nothing could be + further from the truth! Free operating systems such as Linux, FreeBSD and + especially OpenBSD, are among the most secure operating systems available. +* **"Open Source is used by criminal hackers"** - here, they use the + term *hacker* to describe someone who illegally gains access to someone + elses computer. Don't fall for it. Maintainers of libre operating systems + like Linux distros or the BSDs are actively working to make the internet + and computers in general *more secure* +* **"Software authors deserve to be paid!"** - In fact, many libre software devs + are *paid* to work on Open Source! Many companies, including big ones, + work on it. There are also hobbyists or otherwise unpaid people, who might + work on Libre Software for a number of reasons (wanting to make the world a + better place, wanting the glory of recognition for solving a major problem, + and more often than not, simply because *it is fun to do so and you make a + lot of friends too!*) - No, these companies (e.g. Microsoft) are only arguing + in reality for the ability to pay their *shareholders*, and they control the + software exclusively. In fact, libre software has repeatedly and consistently + over the years *defined* the computing industry, creating all kinds of new + employment opportunities; for example, docker is widely used today and it is + libre software, used by millions of companies for commercial gain, and the + apache web server revolutionized the web back in the day, enabling lots of + ISPs to easily host websites - many of the common protocols that we depend + upon today, that businesses depend upon (and get paid to maintain or provide + services/support for) are in fact free as in freedom! +* **"Developers should get recognition for their work"** - in libre software, you + can easily make a name for yourself with relatively few resources except your + own computer and an internet connection, plus some cheap hosting. When most + developers work on *proprietary* software such as Windows, they don't get + recognition; their copyright is assigned to their employer (e.g. Microsoft) + who will take all the credit! +* **"Free software is unreliable / costly to maintain"** - actually, it has been + well known for years that libre software is generally more stable and reliable + than proprietary. In cases where it isn't, it is quickly improved, and in + complete freedom. Free software has a lower cost to maintain and service, and + you have a free market where you can choose who you hire to write/maintain it + for you (if you won't do that yourself); meanwhile, proprietary software + such as Windows is often full of bugs, crashes often and there is only one + provider of support most of the time, who will charge a heavy price, while + also charging a lot of money for the software itself - libre software + is *free as in freedom*, but also usually *free as in zero price*. +* **"Libre software comes from potentially untrustworthy sources"** - This is + pure nonsense, because the very freedoms provided by libre software (access + to source code, ability to work on it yourself, and see what others did) + means that people generally do not add malware to public software sources, + because they'd be discovered instantly. *Distributions* of Linux and + other free operating systems are often maintained by many people, who verify + the safety of each software package that they provide; they are also usually + provided by each *distro*, in a central repository unlike with, say, Windows + where you really *are* randomly executing binaries from all kinds of + locations (often even without checking the cryptographic checksums of those + files, to verify their integrity). It's very hard to become infected with + malware on a free system, precisely because security is handled much better; + the design of unix-like operating systems in particular is also naturally + more secure, due to better separation of root/user privileges. +* **"Libre software isn't controlled, and is unknown."** - this is completely + false. These non-libre software companies are only talking about *their* + control, and it's quite telling that they completely disregard yours, in this + very sentence. In fact, Libre Software *is* controlled, but it's not controlled + by some external entity; *your* installation of libre software is controlled + by *you*. + +If you're familiar with the *Matrix* films, proprietary operating systems like +Windows/MacOS are basically like the Matrix; bland, no individuality, no +independent thought, everything tightly controlled. By contrast, libre operating +systems (such as Linux distributions or the BSDs) are like zion/io; vibrant, +full of life, buzzing with activity, everything loose and free, and everyone +is different (a highly diverse culture of people from all walks of life, acting +in common cause but nonetheless individuals). + +Meanwhile, Windows is known to have backdoors. Microsoft actively informs the +NSA about how to exploit them, so that it can break into people's computers +and steal private data. + +Proprietary software companies are evil, and must be opposed. They know that +if this bill passes, their days are numbered. + +Defend freedom! Don't listen to any of the arguments against it by proprietary +software companies; they don't care about you, and instead only care about +profit. They fundamentally do not want you to have any sort of freedom over +your own computer, and they actively pursue tactics (such as DRM) to thwart you. + +Microsoft and Apple are not your friends. There is no such thing as the +Windows community. When you use proprietary systems, you are isolated from +everyone around you, and so are they. *You* are the product, for the proprietary +software to exploit at the behest of their developers who only care +about *money*. + +However, there *is* such a thing as the Libre Software community. It is a +vibrant community, consisting of millions of people collectively all over the +world, and they are all free to work with each other infinitely. It gave us +most of the technology that we take for granted today, including *the modern +internet, where ISPs run libre software almost exclusively!* + diff --git a/site/robots.txt b/site/robots.txt new file mode 100644 index 0000000..eb05362 --- /dev/null +++ b/site/robots.txt @@ -0,0 +1,2 @@ +User-agent: * +Disallow: diff --git a/site/sitemap.include b/site/sitemap.include new file mode 100644 index 0000000..6ce19d1 --- /dev/null +++ b/site/sitemap.include @@ -0,0 +1,9 @@ +--- +title: Site map +... + +Explore the vast mountains of [Libreland's](https://libreland.libreboot.org/) +capital city, libreboot.org. + +------------------------------------------------------------------------------- + diff --git a/site/template-license.md b/site/template-license.md new file mode 100644 index 0000000..b197464 --- /dev/null +++ b/site/template-license.md @@ -0,0 +1,49 @@ +--- +title: Template license +... + +This website is written in Markdown, and compiled into static HTML using +Pandoc. An HTML template is used, +Copyright (c) 2014--2017, John MacFarlane + +Modifications to it are copyright 2021 Leah Rowe, released under the terms of +Creative Commons Zero license version 1.0 universal, which you can find here: + + +You can find the template file here: [/template.include](/template.include) + +The file `template.include` is the modified version (modified by Leah Rowe). +The original version can be found here: [/template.original](/template.original) + +Other modified templates may be used, on specific pages. Check for this on the +Git repository for the libreboot website. + +The original template file named `template.original` by John MacFarlane was +released under these conditions: + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. + +Neither the name of John MacFarlane nor the names of other +contributors may be used to endorse or promote products derived +from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/site/template-license.uk.md b/site/template-license.uk.md new file mode 100644 index 0000000..92b4022 --- /dev/null +++ b/site/template-license.uk.md @@ -0,0 +1,46 @@ +--- +title: Ліцензія шаблона +... + +Цей веб-сайт написаний у Markdown і скомпільований у статичний HTML за допомогою +Pandoc. Використовується шаблон HTML, +Авторське право (c) 2014--2017, Джон Макфарлейн + +Зміни до нього захищені авторським правом Лією Роу 2021 року, випущені згідно з умовами +Creative Commons Zero license version 1.0 universal, яку ви можете знайти тут: + + +Ви можете знайти файл шаблону тут: [/template.include](/template.include) + +Файл `template.include` - це модифікована версія (змінена Лією Роу). +Оригінальний варіант можна знайти тут: [/template.original](/template.original) + +Інші модифіковані шаблони можуть бути використані на певних сторінках. Перевірте це в +репозиторії Git для веб-сайта libreboot. + +Оригінальний файл шаблону під назвою `template.original` від Джона Макфарлейна було +випущено за таких умов: + +Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. + +Neither the name of John MacFarlane nor the names of other +contributors may be used to endorse or promote products derived +from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/site/template.de.include b/site/template.de.include new file mode 100644 index 0000000..cbcab26 --- /dev/null +++ b/site/template.de.include @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + +$for(author-meta)$ + +$endfor$ +$if(date-meta)$ + +$endif$ +$if(keywords)$ + +$endif$ + $if(title-prefix)$$title-prefix$ – $endif$$pagetitle$ +$if(quotes)$ + +$endif$ +$if(highlighting-css)$ + +$endif$ +$for(css)$ + +$endfor$ +$if(math)$ + $math$ +$endif$ +$for(header-includes)$ + $header-includes$ +$endfor$ + + + +
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+This site shows what Libreboot would be if it +kept its blob extermination policy. +Libreboot replaced it with a blob reduction policy +to free more users, on more hardware. *This* version supports less hardware. Lots of info/boards +were deleted; FSDG/RYF +policy is censorship. A release is ready, based +on Libreboot 20230625.
+Fun fact: regular Libreboot ROM images with _noblobs_nomicrocode in +the filename are *identical* to Censored Libreboot images. +

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+This site shows what Libreboot would be if it +kept its blob extermination policy. +Libreboot replaced it with a blob reduction policy +to free more users, on more hardware. *This* version supports less hardware. Lots of info/boards +were deleted; FSDG/RYF +policy is censorship. A release is ready, based +on Libreboot 20230625.
+Fun fact: regular Libreboot ROM images with _noblobs_nomicrocode in +the filename are *identical* to Censored Libreboot images. +

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+This site shows what Libreboot would be if it +kept its blob extermination policy. +Libreboot replaced it with a blob reduction policy +to free more users, on more hardware. *This* version supports less hardware. Lots of info/boards +were deleted; FSDG/RYF +policy is censorship. A release is ready, based +on Libreboot 20230625.
+Fun fact: regular Libreboot ROM images with _noblobs_nomicrocode in +the filename are *identical* to Censored Libreboot images. +

+ +$if(toc)$ +
+$endif$ +
+ + diff --git a/site/template.zh-cn.include b/site/template.zh-cn.include new file mode 100644 index 0000000..23857e0 --- /dev/null +++ b/site/template.zh-cn.include @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + +$for(author-meta)$ + +$endfor$ +$if(date-meta)$ + +$endif$ +$if(keywords)$ + +$endif$ + $if(title-prefix)$$title-prefix$ – $endif$$pagetitle$ +$if(quotes)$ + +$endif$ +$if(highlighting-css)$ + +$endif$ +$for(css)$ + +$endfor$ +$if(math)$ + $math$ +$endif$ +$for(header-includes)$ + $header-includes$ +$endfor$ + + + +
+$for(include-before)$ +$include-before$ +$endfor$ +$if(title)$ +
+
+ +

$title$

+
+$if(subtitle)$ +

$subtitle$

+$endif$ +$for(author)$ +

$author$

+$endfor$ +$if(date)$ +

$date$

+$endif$ + +
+
+$endif$ +$if(return)$ +$return$ +$endif$ +$if(toc)$ + +$endif$ +$if(toc)$ +
+$endif$ +$body$ +$for(include-after)$ +$include-after$ +$endfor$ + + +

+This site shows what Libreboot would be if it +kept its blob extermination policy. +Libreboot replaced it with a blob reduction policy +to free more users, on more hardware. *This* version supports less hardware. Lots of info/boards +were deleted; FSDG/RYF +policy is censorship. A release is ready, based +on Libreboot 20230625.
+Fun fact: regular Libreboot ROM images with _noblobs_nomicrocode in +the filename are *identical* to Censored Libreboot images. +

+ +$if(toc)$ +
+$endif$ +
+ + diff --git a/site/who.de.md b/site/who.de.md new file mode 100644 index 0000000..0e67b0f --- /dev/null +++ b/site/who.de.md @@ -0,0 +1,58 @@ +--- +title: Who develops libreboot? +x-toc-enable: true +... + +Der Zweck dieser Seite ist klar zu definieren wer am Libreboot Projekt +arbeitet, wer das Projekt betreibt, wie Entscheidungen getroffen werden, +und wie das Projekt grundsätzlich funktioniert. + +Informationen über die wichtigsten Beteiligten an Libreboot sind auf +dieser Seite zu finden, +dort sind diese Leute aufgeführt: [Liste der Beteiligten](contrib.md) + +Leah Rowe (Gründerin, Chef Entwicklerin) +=================================== + +Leah Rowe ist die Gründerin des Libreboot Projekts. Leah beaufsichtigt +die gesamte Lbreboot Entwicklung, überprüft +externe Beiträge, and hat bei Entscheidungen das letzte Wort. +Leah ist Eigentümerin der libreboot.org Server, und betreibt diese von +ihrem Labor in Großbrittanien. + +Wenn Du mehr über Leah's Mitwirken an Libreboot erfahren möchtest, dann +kannst Du ihren Eintrag unter der +[Seite mit allen Mitwirkenden, Vergangenheit und Gegenwart](contrib.de.md) +lesen. + +Caleb La Grange +=============== + +Caleb ist online auch bekannt unter `shmalebx9`. +Caleb kümmert sich hauptsächlich um Verbesserungen am lbmk Build System, +das Hinzufügen neuer Boards sowie um die Dokumentation. + +Wenn Du mehr über Caleb's Mitwirken an Libreboot erfahren möchtest, dann +kannst Du seinen Eintrag unter der +[Seite mit allen Mitwirkenden, Vergangenheit und Gegenwart](contrib.de.md) +lesen. + +Alper Nebi Yasak +================ + +Alper kümmert sich um die Entwicklung der U-Boot Payload Unterstützung +in Libreboot, koordiniert Tests auf Chromebooks die dies nutzen, und +erledigt jegliche notwendige Upstream Arbeit an U-Boot selbst. +`alpernebbi` bei Libera IRC. + +Wenn Du mehr über Alper's Mitwirken an Libreboot erfahren möchtest, dann +kannst Du seinen Eintrag unter der +[Seite mit allen Mitwirkenden, Vergangenheit und Gegenwart](contrib.de.md) +lesen. + +Entwickler gesucht! +================== + +**Lerne wie Du Patches beisteuern kannst unter der [git Seite](git.de.md)** + +Jeder ist willkommen an der Entwicklung teilzunehmen. diff --git a/site/who.md b/site/who.md new file mode 100644 index 0000000..8b4d736 --- /dev/null +++ b/site/who.md @@ -0,0 +1,47 @@ +--- +title: Who develops libreboot? +x-toc-enable: true +... + +The purpose of this page is to clearly define who works on libreboot, who runs +the project, how decisions are made, and in general how the project functions. + +You can find information about major contributions made to libreboot, on this +page which lists such people: [List of contributors](contrib.md) + +Leah Rowe (founder, lead developer) +=================================== + +Leah Rowe is the founder of the libreboot project. Leah oversees all development of libreboot, reviewing +outside contributions, and has the final say over all decisions. Leah owns and +operates the libreboot.org servers from her lab in the UK. + +You can learn more about Leah's involvement with libreboot, by reading her +entry on the [page listing all contributors, past and present](contrib.md) + +Caleb La Grange +=============== + +Caleb goes by the screen name `shmalebx9`. +Caleb mainly deals with improvements to the lbmk build system, board porting, +and documentation. + +You can learn more about Caleb's involvement with libreboot, by reading his +entry on the [page listing all contributors, past and present](contrib.md) + +Alper Nebi Yasak +================ + +Alper handles development of the U-Boot payload support in Libreboot, +coordinates testing on Chromebooks that use it, and does any necessary +upstream work on U-Boot itself. `alpernebbi` on Libera IRC. + +You can learn more about Alper's involvement with Libreboot, by reading his +entry on the [page listing all contributors, past and present](contrib.md) + +Developers wanted! +================== + +**Learn how to contribute patches on the [git page](git.md)** + +All are welcome to join in on development. diff --git a/site/who.uk.md b/site/who.uk.md new file mode 100644 index 0000000..7debde5 --- /dev/null +++ b/site/who.uk.md @@ -0,0 +1,47 @@ +--- +title: Хто розробляє libreboot? +x-toc-enable: true +... + +Мета цієї сторінки - чітко визначити, хто працює над libreboot, хто виконує +проект, як приймаються рішення, і взагалі як проект функціонує. + +Ви можете знайти інформацію про великий внесок, зроблений у libreboot, на цій +сторінці, яка перелічує таких людей: [Список учасників](contrib.uk.md) + +Лія Роу (засновниця, провідний розробник) +=================================== + +Лія Роу є засновницею проекту libreboot. Лія контролює всю розробку libreboot, переглядає +зовнішні внески, і має останнє слово щодо всіх рішень. Лія володіє +і керує серверами libreboot.org зі своєї лабораторії у Великобританії. + +Ви можете дізнатися більше про участь Лії в libreboot, прочитавши її запис на +[сторінці зі списком усіх учасників, минулих і теперішніх](contrib.uk.md) + +Калеб Ла Гранж +=============== + +Калеб має псевдонім `shmalebx9`. +Калеб в основному займається вдосконаленням системи збірки lbmk, портуванням плати, +та документацією. + +Ви можете дізнатись більше про участь Калеба в libreboot, прочитавши його +запис на [сторінці зі списком усіх учасників, минулих і теперішніх](contrib.uk.md) + +Альпер Небі Ясак +================ + +Альпер займається розробкою підтримки корисного навантаження U-Boot в Libreboot, +координує тестування Chromebook, які його використовують, і виконує будь-які необхідну +апстрім роботу над самим U-Boot. `alpernebbi` на Libera IRC. + +Ви можете дізнатись більше про участь Альпера в Libreboot, читаючи його +запис на [сторінці зі списком усіх учасників, минулих і теперішніх](contrib.uk.md) + +Потрібні розробники! +================== + +**Дізнайтесь, як додати виправлення на [сторінці git](git.md)** + +Запрошуємо всіх долучитися до розробки.