230 lines
7.9 KiB
C
230 lines
7.9 KiB
C
/*
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* Copyright (c) 2016 Thomas Pornin <pornin@bolet.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef CONFIG_H__
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#define CONFIG_H__
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/*
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* This file contains compile-time flags that can override the
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* autodetection performed in relevant files. Each flag is a macro; it
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* deactivates the feature if defined to 0, activates it if defined to a
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* non-zero integer (normally 1). If the macro is not defined, then
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* autodetection applies.
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*/
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/*
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* When BR_64 is enabled, 64-bit integer types are assumed to be
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* efficient (i.e. the architecture has 64-bit registers and can
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* do 64-bit operations as fast as 32-bit operations).
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*
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#define BR_64 1
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*/
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/*
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* When BR_LOMUL is enabled, then multiplications of 32-bit values whose
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* result are truncated to the low 32 bits are assumed to be
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* substantially more efficient than 32-bit multiplications that yield
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* 64-bit results. This is typically the case on low-end ARM Cortex M
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* systems (M0, M0+, M1, and arguably M3 and M4 as well).
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*
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#define BR_LOMUL 1
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*/
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/*
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* When BR_SLOW_MUL is enabled, multiplications are assumed to be
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* substantially slow with regards to other integer operations, thus
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* making it worth to make more operations for a given task if it allows
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* using less multiplications.
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*
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#define BR_SLOW_MUL 1
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*/
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/*
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* When BR_SLOW_MUL15 is enabled, short multplications (on 15-bit words)
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* are assumed to be substantially slow with regards to other integer
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* operations, thus making it worth to make more integer operations if
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* it allows using less multiplications.
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*
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#define BR_SLOW_MUL15 1
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*/
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/*
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* When BR_CT_MUL31 is enabled, multiplications of 31-bit values (used
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* in the "i31" big integer implementation) use an alternate implementation
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* which is slower and larger than the normal multiplication, but should
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* ensure constant-time multiplications even on architectures where the
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* multiplication opcode takes a variable number of cycles to complete.
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*
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#define BR_CT_MUL31 1
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*/
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/*
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* When BR_CT_MUL15 is enabled, multiplications of 15-bit values (held
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* in 32-bit words) use an alternate implementation which is slower and
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* larger than the normal multiplication, but should ensure
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* constant-time multiplications on most/all architectures where the
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* basic multiplication is not constant-time.
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#define BR_CT_MUL15 1
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*/
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/*
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* When BR_NO_ARITH_SHIFT is enabled, arithmetic right shifts (with sign
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* extension) are performed with a sequence of operations which is bigger
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* and slower than a simple right shift on a signed value. This avoids
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* relying on an implementation-defined behaviour. However, most if not
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* all C compilers use sign extension for right shifts on signed values,
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* so this alternate macro is disabled by default.
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#define BR_NO_ARITH_SHIFT 1
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*/
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/*
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* When BR_RDRAND is enabled, the SSL engine will use the RDRAND opcode
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* to automatically obtain quality randomness for seeding its internal
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* PRNG. Since that opcode is present only in recent x86 CPU, its
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* support is dynamically tested; if the current CPU does not support
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* it, then another random source will be used, such as /dev/urandom or
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* CryptGenRandom().
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*
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#define BR_RDRAND 1
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*/
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/*
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* When BR_USE_URANDOM is enabled, the SSL engine will use /dev/urandom
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* to automatically obtain quality randomness for seedings its internal
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* PRNG.
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*
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#define BR_USE_URANDOM 1
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*/
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/*
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* When BR_USE_WIN32_RAND is enabled, the SSL engine will use the Win32
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* (CryptoAPI) functions (CryptAcquireContext(), CryptGenRandom()...) to
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* automatically obtain quality randomness for seedings its internal PRNG.
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*
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* Note: if both BR_USE_URANDOM and BR_USE_WIN32_RAND are defined, the
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* former takes precedence.
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*
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#define BR_USE_WIN32_RAND 1
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*/
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/*
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* When BR_USE_UNIX_TIME is enabled, the X.509 validation engine obtains
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* the current time from the OS by calling time(), and assuming that the
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* returned value (a 'time_t') is an integer that counts time in seconds
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* since the Unix Epoch (Jan 1st, 1970, 00:00 UTC).
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*
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#define BR_USE_UNIX_TIME 1
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*/
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/*
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* When BR_USE_WIN32_TIME is enabled, the X.509 validation engine obtains
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* the current time from the OS by calling the Win32 function
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* GetSystemTimeAsFileTime().
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*
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* Note: if both BR_USE_UNIX_TIME and BR_USE_WIN32_TIME are defined, the
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* former takes precedence.
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*
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#define BR_USE_WIN32_TIME 1
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*/
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/*
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* When BR_ARMEL_CORTEXM_GCC is enabled, some operations are replaced with
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* inline assembly which is shorter and/or faster. This should be used
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* only when all of the following are true:
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* - target architecture is ARM in Thumb mode
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* - target endianness is little-endian
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* - compiler is GCC (or GCC-compatible for inline assembly syntax)
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*
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* This is meant for the low-end cores (Cortex M0, M0+, M1, M3).
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* Note: if BR_LOMUL is not explicitly enabled or disabled, then
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* enabling BR_ARMEL_CORTEXM_GCC also enables BR_LOMUL.
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*
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#define BR_ARMEL_CORTEXM_GCC 1
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*/
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/*
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* When BR_AES_X86NI is enabled, the AES implementation using the x86 "NI"
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* instructions (dedicated AES opcodes) will be compiled. If this is not
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* enabled explicitly, then that AES implementation will be compiled only
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* if a compatible compiler is detected. If set explicitly to 0, the
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* implementation will not be compiled at all.
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*
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#define BR_AES_X86NI 1
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*/
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/*
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* When BR_SSE2 is enabled, SSE2 intrinsics will be used for some
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* algorithm implementations that use them (e.g. chacha20_sse2). If this
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* is not enabled explicitly, then support for SSE2 intrinsics will be
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* automatically detected. If set explicitly to 0, then SSE2 code will
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* not be compiled at all.
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*
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#define BR_SSE2 1
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*/
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/*
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* When BR_POWER8 is enabled, the AES implementation using the POWER ISA
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* 2.07 opcodes (available on POWER8 processors and later) is compiled.
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* If this is not enabled explicitly, then that implementation will be
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* compiled only if a compatible compiler is detected, _and_ the target
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* architecture is POWER8 or later.
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*
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#define BR_POWER8 1
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*/
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/*
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* When BR_INT128 is enabled, then code using the 'unsigned __int64'
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* and 'unsigned __int128' types will be used to leverage 64x64->128
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* unsigned multiplications. This should work with GCC and compatible
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* compilers on 64-bit architectures.
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*
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#define BR_INT128 1
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*/
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/*
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* When BR_UMUL128 is enabled, then code using the '_umul128()' and
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* '_addcarry_u64()' intrinsics will be used to implement 64x64->128
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* unsigned multiplications. This should work on Visual C on x64 systems.
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*
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#define BR_UMUL128 1
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*/
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/*
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* When BR_LE_UNALIGNED is enabled, then the current architecture is
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* assumed to use little-endian encoding for integers, and to tolerate
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* unaligned accesses with no or minimal time penalty.
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*
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#define BR_LE_UNALIGNED 1
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*/
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/*
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* When BR_BE_UNALIGNED is enabled, then the current architecture is
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* assumed to use big-endian encoding for integers, and to tolerate
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* unaligned accesses with no or minimal time penalty.
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*
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#define BR_BE_UNALIGNED 1
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*/
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#endif
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