289 lines
7.9 KiB
C
289 lines
7.9 KiB
C
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#ifndef _MIPS_H
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#define _MIPS_H
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#include "ao.h"
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//#include "driver.h"
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typedef void genf(void);
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typedef int offs_t;
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#define cpu_readop32(pc) program_read_dword_32le(pc)
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#define change_pc(pc) \
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#ifdef __GNUC__
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#if (__GNUC__ < 2) || ((__GNUC__ == 2) && (__GNUC_MINOR__ <= 7))
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#define UNUSEDARG
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#else
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#define UNUSEDARG __attribute__((__unused__))
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#endif
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#else
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#define UNUSEDARG
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#endif
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typedef int8 (*read8_handler) (UNUSEDARG offs_t offset);
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typedef void (*write8_handler) (UNUSEDARG offs_t offset, UNUSEDARG int8 data);
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typedef int16 (*read16_handler) (UNUSEDARG offs_t offset, UNUSEDARG int16 mem_mask);
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typedef void (*write16_handler)(UNUSEDARG offs_t offset, UNUSEDARG int16 data, UNUSEDARG int16 mem_mask);
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typedef int32 (*read32_handler) (UNUSEDARG offs_t offset, UNUSEDARG int32 mem_mask);
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typedef void (*write32_handler)(UNUSEDARG offs_t offset, UNUSEDARG int32 data, UNUSEDARG int32 mem_mask);
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typedef int64 (*read64_handler) (UNUSEDARG offs_t offset, UNUSEDARG int64 mem_mask);
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typedef void (*write64_handler)(UNUSEDARG offs_t offset, UNUSEDARG int64 data, UNUSEDARG int64 mem_mask);
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union read_handlers_t
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{
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genf * handler;
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read8_handler handler8;
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read16_handler handler16;
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read32_handler handler32;
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read64_handler handler64;
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};
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union write_handlers_t
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{
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genf * handler;
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write8_handler handler8;
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write16_handler handler16;
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write32_handler handler32;
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write64_handler handler64;
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};
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struct address_map_t
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{
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uint32 flags; /* flags and additional info about this entry */
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offs_t start, end; /* start/end (or mask/match) values */
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offs_t mirror; /* mirror bits */
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offs_t mask; /* mask bits */
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union read_handlers_t read; /* read handler callback */
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union write_handlers_t write; /* write handler callback */
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void * memory; /* pointer to memory backing this entry */
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uint32 share; /* index of a shared memory block */
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void ** base; /* receives pointer to memory (optional) */
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size_t * size; /* receives size of area in bytes (optional) */
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};
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typedef struct address_map_t *(*construct_map_t)(struct address_map_t *map);
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union cpuinfo
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{
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int64 i; /* generic integers */
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void * p; /* generic pointers */
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genf * f; /* generic function pointers */
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char * s; /* generic strings */
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void (*setinfo)(UINT32 state, union cpuinfo *info);/* CPUINFO_PTR_SET_INFO */
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void (*getcontext)(void *context); /* CPUINFO_PTR_GET_CONTEXT */
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void (*setcontext)(void *context); /* CPUINFO_PTR_SET_CONTEXT */
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void (*init)(void); /* CPUINFO_PTR_INIT */
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void (*reset)(void *param); /* CPUINFO_PTR_RESET */
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void (*exit)(void); /* CPUINFO_PTR_EXIT */
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int (*execute)(int cycles); /* CPUINFO_PTR_EXECUTE */
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void (*burn)(int cycles); /* CPUINFO_PTR_BURN */
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offs_t (*disassemble)(char *buffer, offs_t pc); /* CPUINFO_PTR_DISASSEMBLE */
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int (*irqcallback)(int state); /* CPUINFO_PTR_IRQCALLBACK */
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int * icount; /* CPUINFO_PTR_INSTRUCTION_COUNTER */
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construct_map_t internal_map; /* CPUINFO_PTR_INTERNAL_MEMORY_MAP */
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};
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enum
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{
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MIPS_PC = 1,
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MIPS_DELAYV, MIPS_DELAYR,
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MIPS_HI, MIPS_LO,
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MIPS_R0, MIPS_R1,
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MIPS_R2, MIPS_R3,
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MIPS_R4, MIPS_R5,
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MIPS_R6, MIPS_R7,
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MIPS_R8, MIPS_R9,
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MIPS_R10, MIPS_R11,
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MIPS_R12, MIPS_R13,
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MIPS_R14, MIPS_R15,
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MIPS_R16, MIPS_R17,
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MIPS_R18, MIPS_R19,
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MIPS_R20, MIPS_R21,
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MIPS_R22, MIPS_R23,
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MIPS_R24, MIPS_R25,
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MIPS_R26, MIPS_R27,
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MIPS_R28, MIPS_R29,
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MIPS_R30, MIPS_R31,
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MIPS_CP0R0, MIPS_CP0R1,
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MIPS_CP0R2, MIPS_CP0R3,
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MIPS_CP0R4, MIPS_CP0R5,
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MIPS_CP0R6, MIPS_CP0R7,
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MIPS_CP0R8, MIPS_CP0R9,
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MIPS_CP0R10, MIPS_CP0R11,
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MIPS_CP0R12, MIPS_CP0R13,
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MIPS_CP0R14, MIPS_CP0R15,
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MIPS_CP0R16, MIPS_CP0R17,
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MIPS_CP0R18, MIPS_CP0R19,
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MIPS_CP0R20, MIPS_CP0R21,
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MIPS_CP0R22, MIPS_CP0R23,
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MIPS_CP0R24, MIPS_CP0R25,
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MIPS_CP0R26, MIPS_CP0R27,
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MIPS_CP0R28, MIPS_CP0R29,
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MIPS_CP0R30, MIPS_CP0R31,
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MIPS_CP2DR0, MIPS_CP2DR1,
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MIPS_CP2DR2, MIPS_CP2DR3,
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MIPS_CP2DR4, MIPS_CP2DR5,
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MIPS_CP2DR6, MIPS_CP2DR7,
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MIPS_CP2DR8, MIPS_CP2DR9,
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MIPS_CP2DR10, MIPS_CP2DR11,
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MIPS_CP2DR12, MIPS_CP2DR13,
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MIPS_CP2DR14, MIPS_CP2DR15,
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MIPS_CP2DR16, MIPS_CP2DR17,
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MIPS_CP2DR18, MIPS_CP2DR19,
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MIPS_CP2DR20, MIPS_CP2DR21,
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MIPS_CP2DR22, MIPS_CP2DR23,
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MIPS_CP2DR24, MIPS_CP2DR25,
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MIPS_CP2DR26, MIPS_CP2DR27,
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MIPS_CP2DR28, MIPS_CP2DR29,
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MIPS_CP2DR30, MIPS_CP2DR31,
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MIPS_CP2CR0, MIPS_CP2CR1,
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MIPS_CP2CR2, MIPS_CP2CR3,
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MIPS_CP2CR4, MIPS_CP2CR5,
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MIPS_CP2CR6, MIPS_CP2CR7,
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MIPS_CP2CR8, MIPS_CP2CR9,
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MIPS_CP2CR10, MIPS_CP2CR11,
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MIPS_CP2CR12, MIPS_CP2CR13,
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MIPS_CP2CR14, MIPS_CP2CR15,
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MIPS_CP2CR16, MIPS_CP2CR17,
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MIPS_CP2CR18, MIPS_CP2CR19,
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MIPS_CP2CR20, MIPS_CP2CR21,
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MIPS_CP2CR22, MIPS_CP2CR23,
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MIPS_CP2CR24, MIPS_CP2CR25,
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MIPS_CP2CR26, MIPS_CP2CR27,
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MIPS_CP2CR28, MIPS_CP2CR29,
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MIPS_CP2CR30, MIPS_CP2CR31
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};
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#define MIPS_INT_NONE ( -1 )
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#define MIPS_IRQ0 ( 0 )
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#define MIPS_IRQ1 ( 1 )
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#define MIPS_IRQ2 ( 2 )
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#define MIPS_IRQ3 ( 3 )
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#define MIPS_IRQ4 ( 4 )
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#define MIPS_IRQ5 ( 5 )
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#define MIPS_BYTE_EXTEND( a ) ( (INT32)(INT8)a )
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#define MIPS_WORD_EXTEND( a ) ( (INT32)(INT16)a )
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#define INS_OP( op ) ( ( op >> 26 ) & 63 )
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#define INS_RS( op ) ( ( op >> 21 ) & 31 )
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#define INS_RT( op ) ( ( op >> 16 ) & 31 )
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#define INS_IMMEDIATE( op ) ( op & 0xffff )
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#define INS_TARGET( op ) ( op & 0x3ffffff )
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#define INS_RD( op ) ( ( op >> 11 ) & 31 )
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#define INS_SHAMT( op ) ( ( op >> 6 ) & 31 )
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#define INS_FUNCT( op ) ( op & 63 )
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#define INS_CODE( op ) ( ( op >> 6 ) & 0xfffff )
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#define INS_CO( op ) ( ( op >> 25 ) & 1 )
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#define INS_COFUN( op ) ( op & 0x1ffffff )
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#define INS_CF( op ) ( op & 63 )
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#define GTE_OP( op ) ( ( op >> 20 ) & 31 )
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#define GTE_SF( op ) ( ( op >> 19 ) & 1 )
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#define GTE_MX( op ) ( ( op >> 17 ) & 3 )
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#define GTE_V( op ) ( ( op >> 15 ) & 3 )
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#define GTE_CV( op ) ( ( op >> 13 ) & 3 )
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#define GTE_CD( op ) ( ( op >> 11 ) & 3 ) /* not used */
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#define GTE_LM( op ) ( ( op >> 10 ) & 1 )
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#define GTE_CT( op ) ( ( op >> 6 ) & 15 ) /* not used */
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#define GTE_FUNCT( op ) ( op & 63 )
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#define OP_SPECIAL ( 0 )
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#define OP_REGIMM ( 1 )
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#define OP_J ( 2 )
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#define OP_JAL ( 3 )
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#define OP_BEQ ( 4 )
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#define OP_BNE ( 5 )
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#define OP_BLEZ ( 6 )
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#define OP_BGTZ ( 7 )
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#define OP_ADDI ( 8 )
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#define OP_ADDIU ( 9 )
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#define OP_SLTI ( 10 )
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#define OP_SLTIU ( 11 )
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#define OP_ANDI ( 12 )
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#define OP_ORI ( 13 )
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#define OP_XORI ( 14 )
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#define OP_LUI ( 15 )
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#define OP_COP0 ( 16 )
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#define OP_COP1 ( 17 )
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#define OP_COP2 ( 18 )
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#define OP_LB ( 32 )
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#define OP_LH ( 33 )
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#define OP_LWL ( 34 )
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#define OP_LW ( 35 )
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#define OP_LBU ( 36 )
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#define OP_LHU ( 37 )
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#define OP_LWR ( 38 )
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#define OP_SB ( 40 )
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#define OP_SH ( 41 )
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#define OP_SWL ( 42 )
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#define OP_SW ( 43 )
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#define OP_SWR ( 46 )
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#define OP_LWC1 ( 49 )
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#define OP_LWC2 ( 50 )
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#define OP_SWC1 ( 57 )
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#define OP_SWC2 ( 58 )
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/* OP_SPECIAL */
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#define FUNCT_SLL ( 0 )
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#define FUNCT_SRL ( 2 )
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#define FUNCT_SRA ( 3 )
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#define FUNCT_SLLV ( 4 )
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#define FUNCT_SRLV ( 6 )
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#define FUNCT_SRAV ( 7 )
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#define FUNCT_JR ( 8 )
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#define FUNCT_JALR ( 9 )
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#define FUNCT_HLECALL ( 11 )
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#define FUNCT_SYSCALL ( 12 )
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#define FUNCT_BREAK ( 13 )
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#define FUNCT_MFHI ( 16 )
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#define FUNCT_MTHI ( 17 )
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#define FUNCT_MFLO ( 18 )
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#define FUNCT_MTLO ( 19 )
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#define FUNCT_MULT ( 24 )
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#define FUNCT_MULTU ( 25 )
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#define FUNCT_DIV ( 26 )
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#define FUNCT_DIVU ( 27 )
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#define FUNCT_ADD ( 32 )
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#define FUNCT_ADDU ( 33 )
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#define FUNCT_SUB ( 34 )
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#define FUNCT_SUBU ( 35 )
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#define FUNCT_AND ( 36 )
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#define FUNCT_OR ( 37 )
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#define FUNCT_XOR ( 38 )
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#define FUNCT_NOR ( 39 )
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#define FUNCT_SLT ( 42 )
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#define FUNCT_SLTU ( 43 )
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/* OP_REGIMM */
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#define RT_BLTZ ( 0 )
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#define RT_BGEZ ( 1 )
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#define RT_BLTZAL ( 16 )
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#define RT_BGEZAL ( 17 )
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/* OP_COP0/OP_COP1/OP_COP2 */
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#define RS_MFC ( 0 )
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#define RS_CFC ( 2 )
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#define RS_MTC ( 4 )
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#define RS_CTC ( 6 )
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#define RS_BC ( 8 )
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/* RS_BC */
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#define RT_BCF ( 0 )
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#define RT_BCT ( 1 )
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/* OP_COP0 */
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#define CF_RFE ( 16 )
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#ifdef MAME_DEBUG
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extern unsigned DasmMIPS(char *buff, unsigned _pc);
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#endif
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#if (HAS_PSXCPU)
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extern void psxcpu_get_info(UINT32 state, union cpuinfo *info);
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#endif
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#endif
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