2013-10-26 08:54:06 +00:00
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#ifdef SMP_CPP
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inline uint8_t SMP::ram_read(uint16_t addr) {
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if(addr >= 0xffc0 && status.iplrom_enable) return iplrom[addr & 0x3f];
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if(status.ram_disable) return 0x5a; //0xff on mini-SNES
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return apuram[addr];
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}
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inline void SMP::ram_write(uint16_t addr, uint8_t data) {
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//writes to $ffc0-$ffff always go to apuram, even if the iplrom is enabled
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if(status.ram_writable && !status.ram_disable) apuram[addr] = data;
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}
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uint8_t SMP::port_read(uint8_t port) const {
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return apuram[0xf4 + (port & 3)];
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}
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void SMP::port_write(uint8_t port, uint8_t data) {
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apuram[0xf4 + (port & 3)] = data;
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}
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uint8_t SMP::op_busread(uint16_t addr) {
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unsigned result;
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2013-10-27 22:00:13 +00:00
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if ( !(dsp.read( SPC_DSP::r_flg ) & 0x20) ) {
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int start = 0x100 * dsp.read( SPC_DSP::r_esa );
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int end = start + 0x800 * (dsp.read( SPC_DSP::r_edl ) & 0x0F);
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if ( end > 0x10000 )
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end = 0x10000;
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if ( addr >= start || addr < end) synchronize_dsp();
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}
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2013-10-26 08:54:06 +00:00
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switch(addr) {
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case 0xf0: //TEST -- write-only register
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return 0x00;
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case 0xf1: //CONTROL -- write-only register
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return 0x00;
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case 0xf2: //DSPADDR
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return status.dsp_addr;
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case 0xf3: //DSPDATA
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//0x80-0xff are read-only mirrors of 0x00-0x7f
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2013-10-27 22:00:13 +00:00
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synchronize_dsp();
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2013-10-26 08:54:06 +00:00
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return dsp.read(status.dsp_addr & 0x7f);
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case 0xf4: //CPUIO0
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case 0xf5: //CPUIO1
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case 0xf6: //CPUIO2
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case 0xf7: //CPUIO3
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if (sfm_queue && sfm_queue < sfm_queue_end) {
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sfm_last[addr - 0xf4] = *sfm_queue;
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return *sfm_queue++;
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}
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return sfm_last[addr - 0xf4];
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case 0xf8: //RAM0
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return status.ram00f8;
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case 0xf9: //RAM1
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return status.ram00f9;
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case 0xfa: //T0TARGET
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case 0xfb: //T1TARGET
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case 0xfc: //T2TARGET -- write-only registers
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return 0x00;
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case 0xfd: //T0OUT -- 4-bit counter value
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result = timer0.stage3_ticks;
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timer0.stage3_ticks = 0;
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return result;
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case 0xfe: //T1OUT -- 4-bit counter value
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result = timer1.stage3_ticks;
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timer1.stage3_ticks = 0;
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return result;
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case 0xff: //T2OUT -- 4-bit counter value
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result = timer2.stage3_ticks;
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timer2.stage3_ticks = 0;
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return result;
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}
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return ram_read(addr);
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}
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void SMP::op_buswrite(uint16_t addr, uint8_t data) {
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2013-10-27 22:00:13 +00:00
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synchronize_dsp();
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2013-10-26 08:54:06 +00:00
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switch(addr) {
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case 0xf0: //TEST
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if(regs.p.p) break; //writes only valid when P flag is clear
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status.clock_speed = (data >> 6) & 3;
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status.timer_speed = (data >> 4) & 3;
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status.timers_enable = data & 0x08;
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status.ram_disable = data & 0x04;
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status.ram_writable = data & 0x02;
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status.timers_disable = data & 0x01;
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status.timer_step = (1 << status.clock_speed) + (2 << status.timer_speed);
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timer0.synchronize_stage1();
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timer1.synchronize_stage1();
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timer2.synchronize_stage1();
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break;
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case 0xf1: //CONTROL
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status.iplrom_enable = data & 0x80;
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2013-10-26 22:25:06 +00:00
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if (data & 0x10) {
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sfm_last[ 0 ] = 0;
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sfm_last[ 1 ] = 0;
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}
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if (data & 0x20) {
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sfm_last[ 2 ] = 0;
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sfm_last[ 3 ] = 0;
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}
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2013-10-26 08:54:06 +00:00
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//0->1 transistion resets timers
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if(timer2.enable == false && (data & 0x04)) {
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timer2.stage2_ticks = 0;
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timer2.stage3_ticks = 0;
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}
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timer2.enable = data & 0x04;
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if(timer1.enable == false && (data & 0x02)) {
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timer1.stage2_ticks = 0;
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timer1.stage3_ticks = 0;
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}
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timer1.enable = data & 0x02;
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if(timer0.enable == false && (data & 0x01)) {
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timer0.stage2_ticks = 0;
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timer0.stage3_ticks = 0;
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}
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timer0.enable = data & 0x01;
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break;
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case 0xf2: //DSPADDR
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status.dsp_addr = data;
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break;
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case 0xf3: //DSPDATA
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if(status.dsp_addr & 0x80) break; //0x80-0xff are read-only mirrors of 0x00-0x7f
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dsp.write(status.dsp_addr & 0x7f, data);
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break;
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case 0xf4: //CPUIO0
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case 0xf5: //CPUIO1
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case 0xf6: //CPUIO2
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case 0xf7: //CPUIO3
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port_write(addr, data);
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break;
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case 0xf8: //RAM0
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status.ram00f8 = data;
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break;
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case 0xf9: //RAM1
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status.ram00f9 = data;
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break;
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case 0xfa: //T0TARGET
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timer0.target = data;
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break;
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case 0xfb: //T1TARGET
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timer1.target = data;
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break;
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case 0xfc: //T2TARGET
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timer2.target = data;
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break;
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case 0xfd: //T0OUT
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case 0xfe: //T1OUT
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case 0xff: //T2OUT -- read-only registers
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break;
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}
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ram_write(addr, data); //all writes, even to MMIO registers, appear on bus
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}
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void SMP::op_io() {
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add_clocks(24);
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cycle_edge();
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}
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uint8_t SMP::op_read(uint16_t addr) {
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add_clocks(12);
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uint8_t r = op_busread(addr);
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add_clocks(12);
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cycle_edge();
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return r;
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}
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void SMP::op_write(uint16_t addr, uint8_t data) {
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add_clocks(24);
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op_buswrite(addr, data);
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cycle_edge();
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}
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2013-10-27 12:42:03 +00:00
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uint8_t SMP::disassembler_read(uint16_t addr) {
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if((addr & 0xfff0) == 0x00f0) return 0x00;
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if((addr & 0xffc0) == 0xffc0 && status.iplrom_enable) return iplrom[addr & 0x3f];
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return apuram[addr];
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}
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2013-10-26 08:54:06 +00:00
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#endif
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