2013-09-28 03:24:23 +00:00
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// $package. http://www.slack.net/~ant/
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2007-10-11 23:11:58 +00:00
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#include "Hes_Cpu.h"
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#include "blargg_endian.h"
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2013-09-28 03:24:23 +00:00
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#include "Hes_Core.h"
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2007-10-11 23:11:58 +00:00
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//#include "hes_cpu_log.h"
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2013-09-28 03:24:23 +00:00
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/* Copyright (C) 2003-2008 Shay Green. This module is free software; you
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2007-10-11 23:11:58 +00:00
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can redistribute it and/or modify it under the terms of the GNU Lesser
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General Public License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version. This
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module is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
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details. You should have received a copy of the GNU Lesser General Public
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License along with this module; if not, write to the Free Software Foundation,
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Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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#include "blargg_source.h"
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2013-09-28 03:24:23 +00:00
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#define PAGE HES_CPU_PAGE
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2007-10-11 23:11:58 +00:00
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2013-09-28 03:24:23 +00:00
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int Hes_Core::read_mem( addr_t addr )
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2007-10-11 23:11:58 +00:00
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{
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check( addr < 0x10000 );
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int result = *cpu.get_code( addr );
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if ( cpu.mmr [PAGE( addr )] == 0xFF )
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result = read_mem_( addr );
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return result;
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2007-10-11 23:11:58 +00:00
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}
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2013-09-28 03:24:23 +00:00
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void Hes_Core::write_mem( addr_t addr, int data )
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2007-10-11 23:11:58 +00:00
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{
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2013-09-28 03:24:23 +00:00
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check( addr < 0x10000 );
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byte* out = write_pages [PAGE( addr )];
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if ( out )
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out [addr & (cpu.page_size - 1)] = data;
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else if ( cpu.mmr [PAGE( addr )] == 0xFF )
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write_mem_( addr, data );
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2007-10-11 23:11:58 +00:00
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}
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2013-09-28 03:24:23 +00:00
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void Hes_Core::set_mmr( int page, int bank )
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2007-10-11 23:11:58 +00:00
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{
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2013-09-28 03:24:23 +00:00
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write_pages [page] = 0;
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byte* data = rom.at_addr( bank * cpu.page_size );
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if ( bank >= 0x80 )
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{
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2013-09-28 03:24:23 +00:00
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data = 0;
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switch ( bank )
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{
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case 0xF8:
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data = ram;
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break;
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2007-10-11 23:11:58 +00:00
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2013-09-28 03:24:23 +00:00
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case 0xF9:
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case 0xFA:
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case 0xFB:
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data = &sgx [(bank - 0xF9) * cpu.page_size];
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break;
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2007-10-11 23:11:58 +00:00
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2013-09-28 03:24:23 +00:00
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default:
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if ( bank != 0xFF )
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dprintf( "Unmapped bank $%02X\n", bank );
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data = rom.unmapped();
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goto end;
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}
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write_pages [page] = data;
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2007-10-11 23:11:58 +00:00
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}
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2013-09-28 03:24:23 +00:00
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end:
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cpu.set_mmr( page, bank, data );
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}
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2007-10-11 23:11:58 +00:00
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2013-09-28 03:24:23 +00:00
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#define READ_FAST( addr, out ) \
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{\
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out = READ_CODE( addr );\
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if ( CPU.mmr [PAGE( addr )] == 0xFF )\
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{\
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FLUSH_TIME();\
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out = read_mem_( addr );\
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CACHE_TIME();\
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}\
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}
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2007-10-11 23:11:58 +00:00
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2013-09-28 03:24:23 +00:00
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#define WRITE_FAST( addr, data ) \
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{\
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int page = PAGE( addr );\
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byte* out = write_pages [page];\
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addr &= CPU.page_size - 1;\
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if ( out )\
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{\
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out [addr] = data;\
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2007-10-11 23:11:58 +00:00
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}\
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2013-09-28 03:24:23 +00:00
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else if ( CPU.mmr [page] == 0xFF )\
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{\
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FLUSH_TIME();\
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write_mem_( addr, data );\
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CACHE_TIME();\
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2013-09-28 03:24:23 +00:00
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}\
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}
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2007-10-11 23:11:58 +00:00
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2013-09-28 03:24:23 +00:00
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#define READ_LOW( addr ) (ram [addr])
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#define WRITE_LOW( addr, data ) (ram [addr] = data)
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#define READ_MEM( addr ) read_mem( addr )
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#define WRITE_MEM( addr, data ) write_mem( addr, data )
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#define WRITE_VDP( addr, data ) write_vdp( addr, data )
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#define CPU_DONE( result_out ) { FLUSH_TIME(); result_out = cpu_done(); CACHE_TIME(); }
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#define SET_MMR( reg, bank ) set_mmr( reg, bank )
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2007-10-11 23:11:58 +00:00
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2013-09-28 03:24:23 +00:00
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#define CPU cpu
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#define IDLE_ADDR idle_addr
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2007-10-11 23:11:58 +00:00
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2013-09-28 03:24:23 +00:00
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#define CPU_BEGIN \
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bool Hes_Core::run_cpu( time_t end_time )\
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{\
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cpu.set_end_time( end_time );
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2007-10-11 23:11:58 +00:00
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2013-09-28 03:24:23 +00:00
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#include "Hes_Cpu_run.h"
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2007-10-11 23:11:58 +00:00
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return illegal_encountered;
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}
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