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Updated lazyusf2

CQTexperiment
Chris Moeller 2015-03-10 18:34:02 -07:00
parent 6262a97203
commit 438b4143de
4 changed files with 68 additions and 17 deletions
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1
Frameworks/lazyusf/lazyusf/main/main.c
View File

@ -184,6 +184,7 @@ m64p_error main_start(usf_state_t * state)
state->g_delay_ai = 1;
state->g_delay_pi = 1;
state->g_delay_dp = 1;
state->enable_hle_audio = 0;
}
return M64ERR_SUCCESS;

52
Frameworks/lazyusf/lazyusf/rsp/rsp_core.c
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@ -23,6 +23,8 @@
#include "usf/usf_internal.h"
#include "usf/barray.h"
#include "rsp_lle/rsp_lle.h"
#include "rsp_core.h"
@ -53,13 +55,26 @@ void dma_sp_write(struct rsp_core* sp)
unsigned char *spmem = (unsigned char*)sp->mem + (sp->regs[SP_MEM_ADDR_REG] & 0x1000);
unsigned char *dram = (unsigned char*)sp->ri->rdram.dram;
for(j=0; j<count; j++) {
for(i=0; i<length; i++) {
spmem[memaddr^S8] = dram[dramaddr^S8];
memaddr++;
dramaddr++;
if (sp->r4300->state->enable_trimming_mode) {
for(j=0; j<count; j++) {
for(i=0; i<length; i++) {
spmem[memaddr^S8] = dram[dramaddr^S8];
if (!bit_array_test(sp->r4300->state->barray_ram_written_first, dramaddr / 4))
bit_array_set(sp->r4300->state->barray_ram_read, dramaddr / 4);
memaddr++;
dramaddr++;
}
dramaddr+=skip;
}
} else {
for(j=0; j<count; j++) {
for(i=0; i<length; i++) {
spmem[memaddr^S8] = dram[dramaddr^S8];
memaddr++;
dramaddr++;
}
dramaddr+=skip;
}
dramaddr+=skip;
}
}
@ -79,13 +94,26 @@ void dma_sp_read(struct rsp_core* sp)
unsigned char *spmem = (unsigned char*)sp->mem + (sp->regs[SP_MEM_ADDR_REG] & 0x1000);
unsigned char *dram = (unsigned char*)sp->ri->rdram.dram;
for(j=0; j<count; j++) {
for(i=0; i<length; i++) {
dram[dramaddr^S8] = spmem[memaddr^S8];
memaddr++;
dramaddr++;
if (sp->r4300->state->enable_trimming_mode) {
for(j=0; j<count; j++) {
for(i=0; i<length; i++) {
dram[dramaddr^S8] = spmem[memaddr^S8];
if (!bit_array_test(sp->r4300->state->barray_ram_read, dramaddr / 4))
bit_array_set(sp->r4300->state->barray_ram_written_first, dramaddr / 4);
memaddr++;
dramaddr++;
}
dramaddr+=skip;
}
} else {
for(j=0; j<count; j++) {
for(i=0; i<length; i++) {
dram[dramaddr^S8] = spmem[memaddr^S8];
memaddr++;
dramaddr++;
}
dramaddr+=skip;
}
dramaddr+=skip;
}
}

10
Frameworks/lazyusf/lazyusf/rsp_lle/vu/vsaw.h
View File

@ -14,13 +14,13 @@
#include "vu.h"
#ifdef VU_EMULATE_SCALAR_ACCUMULATOR_READ
static void VSAR(int vd, int vs, int vt, int e)
static void VSAR(usf_state_t * state, int vd, int vs, int vt, int e)
{
ALIGNED short oldval[N];
register int i;
for (i = 0; i < N; i++)
oldval[i] = VR[vs][i];
oldval[i] = state->VR[vs][i];
vt = 0;
/* Even though VT is ignored in VSAR, according to official sources as well
* as reversing, lots of games seem to specify it as non-zero, possibly to
@ -39,7 +39,7 @@ static void VSAR(int vd, int vs, int vt, int e)
vst1q_s16(VR[vd], zero);
#else
for (i = 0; i < N; i++)
VR[vd][i] = 0x0000; /* override behavior (zilmar) */
state->VR[vd][i] = 0x0000; /* override behavior (zilmar) */
#endif
}
else
@ -48,12 +48,12 @@ static void VSAR(int vd, int vs, int vt, int e)
vector_copy(VR[vd], VACC[e]);
#else
for (i = 0; i < N; i++)
VR[vd][i] = VACC[e][i];
state->VR[vd][i] = state->VACC[e][i];
#endif
}
for (i = 0; i < N; i++)
VACC[e][i] = oldval[i]; /* ... = VS */
state->VACC[e][i] = oldval[i]; /* ... = VS */
return;
}
#endif

22
Frameworks/lazyusf/lazyusf/si/si_controller.c
View File

@ -23,6 +23,8 @@
#include "usf/usf_internal.h"
#include "usf/barray.h"
#include "si_controller.h"
#include "api/m64p_types.h"
@ -53,6 +55,16 @@ static void dma_si_write(struct si_controller* si)
*((uint32_t*)(&si->pif.ram[i])) = sl(si->ri->rdram.dram[(si->regs[SI_DRAM_ADDR_REG]+i)/4]);
}
if (si->r4300->state->enable_trimming_mode)
{
for (i = 0; i < PIF_RAM_SIZE; i += 4)
{
unsigned int ram_address = si->regs[SI_DRAM_ADDR_REG] + i;
if (!bit_array_test(si->r4300->state->barray_ram_written_first, ram_address / 4))
bit_array_set(si->r4300->state->barray_ram_read, ram_address / 4);
}
}
update_pif_write(si);
update_count(si->r4300->state);
@ -81,6 +93,16 @@ static void dma_si_read(struct si_controller* si)
si->ri->rdram.dram[(si->regs[SI_DRAM_ADDR_REG]+i)/4] = sl(*(uint32_t*)(&si->pif.ram[i]));
}
if (si->r4300->state->enable_trimming_mode)
{
for (i = 0; i < PIF_RAM_SIZE; i += 4)
{
unsigned int ram_address = si->regs[SI_DRAM_ADDR_REG] + i;
if (!bit_array_test(si->r4300->state->barray_ram_read, ram_address / 4))
bit_array_set(si->r4300->state->barray_ram_written_first, ram_address / 4);
}
}
update_count(si->r4300->state);
if (si->r4300->state->g_delay_si) {