Highly Complete / USF: Fix playback for some USFs

The code now requires a variable to be set if Display Lists are to be
skipped by setting display processor interrupt as the bypass code is
supposed to. Also handle unsupported Ucode by calling the low level RSP
emulator instead.

Signed-off-by: Christopher Snowhill <kode54@gmail.com>
CQTexperiment
Christopher Snowhill 2022-03-09 20:55:15 -08:00
parent efadd1d012
commit 8abbf267e1
5 changed files with 24 additions and 3 deletions

View File

@ -187,6 +187,15 @@ m64p_error main_start(usf_state_t * state)
state->enable_hle_audio = 0;
}
// Assume it's a proper rip
if (state->enablecompare && state->enableFIFOfull)
{
state->g_delay_si = 1;
state->g_delay_ai = 1;
state->g_delay_pi = 1;
state->g_delay_dp = 1;
}
return M64ERR_SUCCESS;
}

View File

@ -32,6 +32,8 @@
#include "hle.h"
extern void rsp_lle_run_task(usf_state_t * state);
/* Global functions needed by HLE core */
void HleVerboseMessage(void* user_defined, const char *message, ...)
{
@ -123,5 +125,6 @@ void HleShowCFB(void* user_defined)
int HleForwardTask(void* user_defined)
{
/* disabled */
rsp_lle_run_task((usf_state_t *)user_defined);
return 0;
}

View File

@ -121,7 +121,7 @@ EX:
if (state->g_sp.regs[SP_STATUS_REG] & 0x00000040)
{ /* SP_STATUS_INTR_BREAK */
state->g_r4300.mi.regs[MI_INTR_REG] |= 0x00000001;
//check_interupt(state);
check_interupt(state);
}
CONTINUE
case 040: /* ADD */
@ -482,7 +482,7 @@ BRANCH:
if (state->g_sp.regs[SP_STATUS_REG] & 0x00000002) /* normal exit, from executing BREAK */
return;
else if (state->g_r4300.mi.regs[MI_INTR_REG] & 0x00000001) /* interrupt set by MTC0 to break */
/*check_interupt(state)*/;
check_interupt(state);
else if (CFG_WAIT_FOR_CPU_HOST != 0) /* plugin system hack to re-sync */
{}
else if (state->g_sp.regs[SP_SEMAPHORE_REG] != 0x00000000) /* semaphore lock fixes */

View File

@ -59,6 +59,11 @@ void real_run_rsp(usf_state_t * state, uint32_t cycles)
run_task(state);
}
void rsp_lle_run_task(usf_state_t * state)
{
run_task(state);
}
int32_t init_rsp_lle(usf_state_t * state)
{
state->CR[0x0] = &state->g_sp.regs[SP_MEM_ADDR_REG];
@ -105,5 +110,7 @@ int32_t init_rsp_lle(usf_state_t * state)
&state->g_dp.dpc_regs[DPC_TMEM_REG],
state);
state->hle.hle_gfx = 1;
return 0;
}

View File

@ -82,6 +82,8 @@ int32_t init_rsp_lle(usf_state_t * state);
NOINLINE static void run_task(usf_state_t * state);
#include "execute.h"
void rsp_lle_run_task(usf_state_t * state);
#ifdef SP_EXECUTE_LOG
#include "matrix.h"