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Cleaned up most of the warnings, including a few cases where operator precedence would have caused unintended behavior

CQTexperiment
Chris Moeller 2013-10-13 19:54:09 -07:00
parent e7b3b61bff
commit e6d83fc936
11 changed files with 67 additions and 44 deletions
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8
Frameworks/vio2sf/vio2sf/src/vio2sf/desmume/MMU.c
View File

@ -824,7 +824,7 @@ void FASTCALL MMU_write8(NDS_state *state, u32 proc, u32 adr, u8 val)
}
}
if (adr & 0xFF800000 == 0x04800000)
if ((adr & 0xFF800000) == 0x04800000)
{
/* is wifi hardware, dont intermix with regular hardware registers */
/* FIXME handle 8 bit writes */
@ -1405,7 +1405,7 @@ void FASTCALL MMU_write16(NDS_state *state, u32 proc, u32 adr, u16 val)
break;
case 1 : /* firmware memory device */
if(spicnt & 0x3 != 0) /* check SPI baudrate (must be 4mhz) */
if((spicnt & 0x3) != 0) /* check SPI baudrate (must be 4mhz) */
{
T1WriteWord(state->MMU->MMU_MEM[proc][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, 0);
break;
@ -1818,7 +1818,7 @@ void FASTCALL MMU_write32(NDS_state *state, u32 proc, u32 adr, u32 val)
}
}
if (adr & 0xFF800000 == 0x04800000) {
if ((adr & 0xFF800000) == 0x04800000) {
/* access to non regular hw registers */
/* return to not overwrite valid data */
return ;
@ -3112,6 +3112,7 @@ print_memory_profiling( void) {
}
#endif /* End of PROFILE_MEMORY_ACCESS area */
#ifdef GDB_STUB
static u16 FASTCALL
arm9_prefetch16( NDS_state *state, void *data, u32 adr) {
#ifdef PROFILE_MEMORY_ACCESS
@ -3378,7 +3379,6 @@ arm7_write32(NDS_state *state, void *data, u32 adr, u32 val) {
}
#ifdef GDB_STUB
/*
* the base memory interfaces
*/

2
Frameworks/vio2sf/vio2sf/src/vio2sf/desmume/MMU.h
View File

@ -126,12 +126,14 @@ struct armcpu_memory_iface {
void *data;
};
#if 0
static void mmu_select_savetype(NDS_state *state, int type, int *bmemtype, u32 *bmemsize) {
if (type<0 || type > 5) return;
*bmemtype=save_types[type][0];
*bmemsize=save_types[type][1];
mc_realloc(&state->MMU->bupmem, *bmemtype, *bmemsize);
}
#endif
void MMU_Init(NDS_state *);
void MMU_DeInit(NDS_state *);

4
Frameworks/vio2sf/vio2sf/src/vio2sf/desmume/NDSSystem.c
View File

@ -714,7 +714,7 @@ void NDS_exec_hframe(NDS_state *state, int cpu_clockdown_level_arm9, int cpu_clo
T1WriteWord(state->MMU->ARM7_REG, 6, state->nds->VCount);
vmatch = T1ReadWord(state->ARM9Mem->ARM9_REG, 4);
if((state->nds->VCount==(vmatch>>8)|((vmatch<<1)&(1<<8))))
if(state->nds->VCount==((vmatch>>8)|((vmatch<<1)&(1<<8))))
{
T1WriteWord(state->ARM9Mem->ARM9_REG, 4, T1ReadWord(state->ARM9Mem->ARM9_REG, 4) | 4);
if(T1ReadWord(state->ARM9Mem->ARM9_REG, 4) & 32)
@ -724,7 +724,7 @@ void NDS_exec_hframe(NDS_state *state, int cpu_clockdown_level_arm9, int cpu_clo
T1WriteWord(state->ARM9Mem->ARM9_REG, 4, T1ReadWord(state->ARM9Mem->ARM9_REG, 4) & 0xFFFB);
vmatch = T1ReadWord(state->MMU->ARM7_REG, 4);
if((state->nds->VCount==(vmatch>>8)|((vmatch<<1)&(1<<8))))
if(state->nds->VCount==((vmatch>>8)|((vmatch<<1)&(1<<8))))
{
T1WriteWord(state->MMU->ARM7_REG, 4, T1ReadWord(state->MMU->ARM7_REG, 4) | 4);
if(T1ReadWord(state->MMU->ARM7_REG, 4) & 32)

8
Frameworks/vio2sf/vio2sf/src/vio2sf/desmume/SPU.h
View File

@ -28,7 +28,13 @@
#include <math.h>
#include <assert.h>
#ifdef _MSC_VER
#define FORCEINLINE __forceinline
#elif defined(__GNUC__) || defined(__clang__)
#define FORCEINLINE __inline__ __attribute__((always_inline))
#else
#define FORCEINLINE
#endif
FORCEINLINE u32 u32floor(float f)
{
@ -72,8 +78,6 @@ static FORCEINLINE s32 spumuldiv7(s32 val, u8 multiplier) {
#define CHANSTAT_STOPPED 0
#define CHANSTAT_PLAY 1
typedef struct NDS_state;
enum SPUInterpolationMode
{
SPUInterpolation_None = 0,

53
Frameworks/vio2sf/vio2sf/src/vio2sf/desmume/arm_instructions.c
View File

@ -237,8 +237,7 @@
static u32 FASTCALL OP_UND(armcpu_t *cpu)
{
u32 i = cpu->instruction;
LOG("Undefined instruction: %08X\n", i);
LOG("Undefined instruction: %08X\n", (u32)cpu->instruction);
cpu->state->execute = FALSE;
return 1;
}
@ -3807,7 +3806,7 @@ static u32 FASTCALL OP_SMLAW_B(armcpu_t *cpu)
tmp = (tmp>>16);
cpu->R[REG_POS(i,16)] = tmp + a;
cpu->R[REG_POS(i,16)] = (s32)tmp + a;
if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)]))
cpu->CPSR.bits.Q = 1;
@ -3824,7 +3823,7 @@ static u32 FASTCALL OP_SMLAW_T(armcpu_t *cpu)
//LOG("SMLAWT %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, ((tmp>>16)&0xFFFFFFFF) + a);
tmp = ((tmp>>16)&0xFFFFFFFF);
cpu->R[REG_POS(i,16)] = tmp + a;
cpu->R[REG_POS(i,16)] = (s32)tmp + a;
if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)]))
cpu->CPSR.bits.Q = 1;
@ -5875,6 +5874,7 @@ static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu)
return 3 + cpu->state->MMU->MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
}
/*
static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND(armcpu_t *cpu)
{
u32 oldmode;
@ -5900,6 +5900,7 @@ static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND(armcpu_t *cpu)
return 3 + cpu->state->MMU->MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
}
*/
static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
{
@ -6170,6 +6171,7 @@ static u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu)
return 2 + cpu->state->MMU->MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
}
/*
static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND(armcpu_t *cpu)
{
u32 oldmode;
@ -6191,7 +6193,9 @@ static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND(armcpu_t *cpu)
return 2 + cpu->state->MMU->MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
}
*/
/*
static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND(armcpu_t *cpu)
{
u32 oldmode;
@ -6213,6 +6217,7 @@ static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND(armcpu_t *cpu)
return 2 + cpu->state->MMU->MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
}
*/
static u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
{
@ -6443,7 +6448,7 @@ static u32 FASTCALL OP_LDMIA(armcpu_t *cpu)
u32 start = cpu->R[REG_POS(i,16)];
u32 * registres = cpu->R;
u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
const u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
OP_L_IA(0, start);
OP_L_IA(1, start);
@ -6481,7 +6486,7 @@ static u32 FASTCALL OP_LDMIB(armcpu_t *cpu)
u32 start = cpu->R[REG_POS(i,16)];
u32 * registres = cpu->R;
u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
const u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
OP_L_IB(0, start);
OP_L_IB(1, start);
@ -6521,7 +6526,7 @@ static u32 FASTCALL OP_LDMDA(armcpu_t *cpu)
u32 start = cpu->R[REG_POS(i,16)];
u32 * registres = cpu->R;
u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
const u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
if(BIT15(i))
{
@ -6559,7 +6564,7 @@ static u32 FASTCALL OP_LDMDB(armcpu_t *cpu)
u32 start = cpu->R[REG_POS(i,16)];
u32 * registres = cpu->R;
u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
const u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
if(BIT15(i))
{
@ -6593,12 +6598,12 @@ static u32 FASTCALL OP_LDMDB(armcpu_t *cpu)
static u32 FASTCALL OP_LDMIA_W(armcpu_t *cpu)
{
u32 i = cpu->instruction, c = 0, count;
u32 i = cpu->instruction, c = 0;
u32 start = cpu->R[REG_POS(i,16)];
u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF;
u32 * registres = cpu->R;
u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
const u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
OP_L_IA(0, start);
OP_L_IA(1, start);
@ -6638,12 +6643,12 @@ static u32 FASTCALL OP_LDMIA_W(armcpu_t *cpu)
static u32 FASTCALL OP_LDMIB_W(armcpu_t *cpu)
{
u32 i = cpu->instruction, c = 0, count;
u32 i = cpu->instruction, c = 0;
u32 start = cpu->R[REG_POS(i,16)];
u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF;
u32 * registres = cpu->R;
u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
const u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
OP_L_IB(0, start);
OP_L_IB(1, start);
@ -6685,12 +6690,12 @@ static u32 FASTCALL OP_LDMIB_W(armcpu_t *cpu)
static u32 FASTCALL OP_LDMDA_W(armcpu_t *cpu)
{
u32 i = cpu->instruction, c = 0, count;
u32 i = cpu->instruction, c = 0;
u32 start = cpu->R[REG_POS(i,16)];
u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF;
u32 * registres = cpu->R;
u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
const u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
if(BIT15(i))
{
@ -6730,11 +6735,11 @@ static u32 FASTCALL OP_LDMDA_W(armcpu_t *cpu)
static u32 FASTCALL OP_LDMDB_W(armcpu_t *cpu)
{
u32 i = cpu->instruction, c = 0, count;
u32 i = cpu->instruction, c = 0;
u32 start = cpu->R[REG_POS(i,16)];
u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF;
u32 * registres = cpu->R;
u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
const u32 * waitState = cpu->state->MMU->MMU_WAIT32[cpu->proc_ID];
if(BIT15(i))
{
@ -6782,7 +6787,7 @@ static u32 FASTCALL OP_LDMIA2(armcpu_t *cpu)
u32 start = cpu->R[REG_POS(i,16)];
u32 * registres;
u32 * waitState;
const u32 * waitState;
if(BIT15(i)==0)
{
@ -6837,7 +6842,7 @@ static u32 FASTCALL OP_LDMIB2(armcpu_t *cpu)
u32 start = cpu->R[REG_POS(i,16)];
u32 * registres;
u32 * waitState;
const u32 * waitState;
//cpu->state->execute = FALSE;
LOG("Untested opcode: OP_LDMIB2");
@ -6894,7 +6899,7 @@ static u32 FASTCALL OP_LDMDA2(armcpu_t *cpu)
u32 oldmode;
u32 c = 0;
u32 * registres;
u32 * waitState;
const u32 * waitState;
u32 start = cpu->R[REG_POS(i,16)];
//cpu->state->execute = FALSE;
@ -6957,7 +6962,7 @@ static u32 FASTCALL OP_LDMDB2(armcpu_t *cpu)
u32 oldmode;
u32 c = 0;
u32 * registres;
u32 * waitState;
const u32 * waitState;
u32 start = cpu->R[REG_POS(i,16)];
if(BIT15(i)==0)
@ -7019,7 +7024,7 @@ static u32 FASTCALL OP_LDMIA2_W(armcpu_t *cpu)
u32 oldmode;
u32 start = cpu->R[REG_POS(i,16)];
u32 * registres;
u32 * waitState;
const u32 * waitState;
u32 tmp;
Status_Reg SPSR;
// cpu->state->execute = FALSE;
@ -7076,7 +7081,7 @@ static u32 FASTCALL OP_LDMIB2_W(armcpu_t *cpu)
u32 oldmode;
u32 start = cpu->R[REG_POS(i,16)];
u32 * registres;
u32 * waitState;
const u32 * waitState;
u32 tmp;
Status_Reg SPSR;
@ -7135,7 +7140,7 @@ static u32 FASTCALL OP_LDMDA2_W(armcpu_t *cpu)
u32 oldmode;
u32 start = cpu->R[REG_POS(i,16)];
u32 * registres;
u32 * waitState;
const u32 * waitState;
Status_Reg SPSR;
// cpu->state->execute = FALSE;
if(BIT15(i)==0)
@ -7195,7 +7200,7 @@ static u32 FASTCALL OP_LDMDB2_W(armcpu_t *cpu)
u32 oldmode;
u32 start = cpu->R[REG_POS(i,16)];
u32 * registres;
u32 * waitState;
const u32 * waitState;
Status_Reg SPSR;
// cpu->state->execute = FALSE;
if(BIT15(i)==0)

8
Frameworks/vio2sf/vio2sf/src/vio2sf/desmume/armcpu.c
View File

@ -125,6 +125,7 @@ remove_post_exec_fn( void *instance) {
}
#endif
#ifdef GDB_STUB
static u32
read_cpu_reg( void *instance, u32 reg_num) {
armcpu_t *armcpu = (armcpu_t *)instance;
@ -158,6 +159,7 @@ set_cpu_reg( void *instance, u32 reg_num, u32 value) {
/* FIXME: setting the CPSR */
}
}
#endif
#ifdef GDB_STUB
int armcpu_new( NDS_state *state, armcpu_t *armcpu, u32 id,
@ -357,7 +359,9 @@ u32 armcpu_switchMode(armcpu_t *armcpu, u8 mode)
static u32
armcpu_prefetch(armcpu_t *armcpu)
{
#ifdef GDB_STUB
u32 temp_instruction;
#endif
if(armcpu->CPSR.bits.T == 0)
{
@ -406,6 +410,7 @@ armcpu_prefetch(armcpu_t *armcpu)
}
#if 0
static BOOL FASTCALL test_EQ(Status_Reg CPSR) { return ( CPSR.bits.Z); }
static BOOL FASTCALL test_NE(Status_Reg CPSR) { return (!CPSR.bits.Z); }
static BOOL FASTCALL test_CS(Status_Reg CPSR) { return ( CPSR.bits.C); }
@ -434,6 +439,7 @@ static BOOL (FASTCALL* test_conditions[])(Status_Reg CPSR)= {
};
#define TEST_COND2(cond, CPSR) \
(cond<15&&test_conditions[cond](CPSR))
#endif
BOOL armcpu_irqExeption(armcpu_t *armcpu)
@ -485,6 +491,7 @@ static BOOL armcpu_prefetchExeption(armcpu_t *armcpu)
}
*/
/*
static BOOL armcpu_prefetchExeption(armcpu_t *armcpu)
{
Status_Reg tmp;
@ -513,6 +520,7 @@ static BOOL armcpu_prefetchExeption(armcpu_t *armcpu)
return TRUE;
}
*/
BOOL
armcpu_flagIrq( armcpu_t *armcpu) {

2
Frameworks/vio2sf/vio2sf/src/vio2sf/desmume/armcpu.h
View File

@ -235,7 +235,9 @@ int armcpu_new( NDS_state *, armcpu_t *armcpu, u32 id);
#endif
void armcpu_init(armcpu_t *armcpu, u32 adr);
u32 armcpu_switchMode(armcpu_t *armcpu, u8 mode);
#ifndef GDB_STUB
static u32 armcpu_prefetch(armcpu_t *armcpu);
#endif
u32 armcpu_exec(armcpu_t *armcpu);
BOOL armcpu_irqExeption(armcpu_t *armcpu);
//BOOL armcpu_prefetchExeption(armcpu_t *armcpu);

6
Frameworks/vio2sf/vio2sf/src/vio2sf/desmume/cp15.c
View File

@ -84,7 +84,7 @@ armcp15_t *armcp15_new(armcpu_t * c)
#define MASKFROMREG(val) (~((SIZEBINARY(val)-1) | 0x3F))
#define SETFROMREG(val) ((val) & MASKFROMREG(val))
/* sets the precalculated regions to mask,set for the affected accesstypes */
void armcp15_setSingleRegionAccess(armcp15_t *armcp15,unsigned long dAccess,unsigned long iAccess,unsigned char num, unsigned long mask,unsigned long set) {
void armcp15_setSingleRegionAccess(armcp15_t *armcp15,unsigned long dAccess,unsigned long iAccess,unsigned char num, u32 mask,u32 set) {
switch (ACCESSTYPE(dAccess,num)) {
case 4: /* UNP */
@ -368,7 +368,7 @@ BOOL armcp15_moveCP2ARM(armcp15_t *armcp15, u32 * R, u8 CRn, u8 CRm, u8 opcode1,
}
return FALSE;
case 9 :
if((opcode1==0))
if(opcode1==0)
{
switch(CRm)
{
@ -547,7 +547,7 @@ BOOL armcp15_moveARM2CP(armcp15_t *armcp15, u32 val, u8 CRn, u8 CRm, u8 opcode1,
}
return FALSE;
case 9 :
if((opcode1==0))
if(opcode1==0)
{
switch(CRm)
{

2
Frameworks/vio2sf/vio2sf/src/vio2sf/desmume/mc.h
View File

@ -45,6 +45,7 @@ extern "C" {
#define MC_SIZE_16MBITS 0x200000
#define MC_SIZE_64MBITS 0x800000
#if 0
static int save_types[6][2] = {
{MC_TYPE_AUTODETECT,1},
{MC_TYPE_EEPROM1,MC_SIZE_4KBITS},
@ -53,6 +54,7 @@ static int save_types[6][2] = {
{MC_TYPE_FLASH,MC_SIZE_256KBITS},
{MC_TYPE_FRAM,MC_SIZE_2MBITS}
};
#endif
typedef struct
{

2
Frameworks/vio2sf/vio2sf/src/vio2sf/desmume/spu_exports.h
View File

@ -31,6 +31,6 @@ typedef struct SoundInterface_struct
void (*SetVolume)(NDS_state *, int volume);
} SoundInterface_struct;
#endif _SPU_CPP_
#endif //_SPU_CPP_
#endif //_SPU_EXPORTS_H

16
Frameworks/vio2sf/vio2sf/src/vio2sf/desmume/state.c
View File

@ -391,7 +391,7 @@ void state_render(struct NDS_state *state, s16 * buffer, int sample_count)
while (sample_count)
{
unsigned remain_samples = state->sample_pointer;
unsigned long remain_samples = state->sample_pointer;
if (remain_samples > 0)
{
if (remain_samples > sample_count)
@ -490,7 +490,7 @@ static void SNDStateUpdateAudio(NDS_state *state, s16 *buffer, u32 num_samples)
static u32 SNDStateGetAudioSpace(NDS_state *state)
{
return state->sample_size - state->sample_pointer;
return (u32)(state->sample_size - state->sample_pointer);
}
static void SNDStateMuteAudio(NDS_state *state)
@ -657,7 +657,7 @@ static void load_setstate(struct NDS_state *state, const u8 *ss, u32 ss_size)
load_getu32(&state->NDS_ARM7->instruction, 1, &ss, sse);
load_getu32(&state->NDS_ARM7->instruct_adr, 1, &ss, sse);
load_getu32(&state->NDS_ARM7->next_instruction, 1, &ss, sse);
load_getu32(&state->NDS_ARM7->R, 16, &ss, sse);
load_getu32(state->NDS_ARM7->R, 16, &ss, sse);
load_getsta(&state->NDS_ARM7->CPSR, 1, &ss, sse);
load_getsta(&state->NDS_ARM7->SPSR, 1, &ss, sse);
load_getu32(&state->NDS_ARM7->R13_usr, 1, &ss, sse);
@ -693,7 +693,7 @@ static void load_setstate(struct NDS_state *state, const u8 *ss, u32 ss_size)
load_getu32(&state->NDS_ARM9->instruction, 1, &ss, sse);
load_getu32(&state->NDS_ARM9->instruct_adr, 1, &ss, sse);
load_getu32(&state->NDS_ARM9->next_instruction, 1, &ss, sse);
load_getu32(&state->NDS_ARM9->R, 16, &ss, sse);
load_getu32(state->NDS_ARM9->R, 16, &ss, sse);
load_getsta(&state->NDS_ARM9->CPSR, 1, &ss, sse);
load_getsta(&state->NDS_ARM9->SPSR, 1, &ss, sse);
load_getu32(&state->NDS_ARM9->R13_usr, 1, &ss, sse);
@ -728,10 +728,10 @@ static void load_setstate(struct NDS_state *state, const u8 *ss, u32 ss_size)
load_gets32(&state->nds->ARM9Cycle, 1, &ss, sse);
load_gets32(&state->nds->ARM7Cycle, 1, &ss, sse);
load_gets32(&state->nds->cycles, 1, &ss, sse);
load_gets32(&state->nds->timerCycle[0], 4, &ss, sse);
load_gets32(&state->nds->timerCycle[1], 4, &ss, sse);
load_getbool(&state->nds->timerOver[0], 4, &ss, sse);
load_getbool(&state->nds->timerOver[1], 4, &ss, sse);
load_gets32(state->nds->timerCycle[0], 4, &ss, sse);
load_gets32(state->nds->timerCycle[1], 4, &ss, sse);
load_getbool(state->nds->timerOver[0], 4, &ss, sse);
load_getbool(state->nds->timerOver[1], 4, &ss, sse);
load_gets32(&state->nds->nextHBlank, 1, &ss, sse);
load_getu32(&state->nds->VCount, 1, &ss, sse);
load_getu32(&state->nds->old, 1, &ss, sse);