117 lines
4.3 KiB
C
117 lines
4.3 KiB
C
/******************************************************************************\
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* Authors: Iconoclast *
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* Release: 2013.12.12 *
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* License: CC0 Public Domain Dedication *
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* *
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* To the extent possible under law, the author(s) have dedicated all copyright *
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* and related and neighboring rights to this software to the public domain *
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* worldwide. This software is distributed without any warranty. *
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* *
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* You should have received a copy of the CC0 Public Domain Dedication along *
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* with this software. *
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* If not, see <http://creativecommons.org/publicdomain/zero/1.0/>. *
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\******************************************************************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include "usf/usf.h"
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#include "usf/usf_internal.h"
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#include "api/callbacks.h"
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#undef JUMP
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#include "config.h"
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#include "rsp.h"
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#include "../rsp_hle/hle.h"
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void real_run_rsp(usf_state_t * state, uint32_t cycles)
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{
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(void)cycles;
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if (state->g_sp.regs[SP_STATUS_REG] & 0x00000003)
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{
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message(state, "SP_STATUS_HALT", 3);
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return;
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}
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switch (*(unsigned int *)(state->DMEM + 0xFC0))
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{ /* Simulation barrier to redirect processing externally. */
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case 0x00000002: /* OSTask.type == M_AUDTASK */
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if (state->enable_hle_audio == 0)
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break;
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hle_execute(&state->hle);
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return;
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/* XXX USF sets should not be processing DLists, but several of them
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require them at least once to boot properly. And for some reason,
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with this emulator core, Iconoclast's RSP core is not up to the
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task of running the DLists, so this HLE will do instead. */
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case 0x00000001:
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hle_execute(&state->hle);
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return;
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}
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run_task(state);
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}
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void rsp_lle_run_task(usf_state_t * state)
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{
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run_task(state);
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}
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int32_t init_rsp_lle(usf_state_t * state)
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{
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state->CR[0x0] = &state->g_sp.regs[SP_MEM_ADDR_REG];
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state->CR[0x1] = &state->g_sp.regs[SP_DRAM_ADDR_REG];
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state->CR[0x2] = &state->g_sp.regs[SP_RD_LEN_REG];
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state->CR[0x3] = &state->g_sp.regs[SP_WR_LEN_REG];
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state->CR[0x4] = &state->g_sp.regs[SP_STATUS_REG];
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state->CR[0x5] = &state->g_sp.regs[SP_DMA_FULL_REG];
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state->CR[0x6] = &state->g_sp.regs[SP_DMA_BUSY_REG];
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state->CR[0x7] = &state->g_sp.regs[SP_SEMAPHORE_REG];
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state->CR[0x8] = &state->g_dp.dpc_regs[DPC_START_REG];
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state->CR[0x9] = &state->g_dp.dpc_regs[DPC_END_REG];
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state->CR[0xA] = &state->g_dp.dpc_regs[DPC_CURRENT_REG];
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state->CR[0xB] = &state->g_dp.dpc_regs[DPC_STATUS_REG];
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state->CR[0xC] = &state->g_dp.dpc_regs[DPC_CLOCK_REG];
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state->CR[0xD] = &state->g_dp.dpc_regs[DPC_BUFBUSY_REG];
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state->CR[0xE] = &state->g_dp.dpc_regs[DPC_PIPEBUSY_REG];
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state->CR[0xF] = &state->g_dp.dpc_regs[DPC_TMEM_REG];
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state->DMEM = (unsigned char *)state->g_sp.mem;
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state->IMEM = (unsigned char *)state->g_sp.mem + 0x1000;
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hle_init(&state->hle,
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(unsigned char *)state->g_rdram,
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state->DMEM,
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state->IMEM,
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&state->g_r4300.mi.regs[MI_INTR_REG],
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&state->g_sp.regs[SP_MEM_ADDR_REG],
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&state->g_sp.regs[SP_DRAM_ADDR_REG],
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&state->g_sp.regs[SP_RD_LEN_REG],
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&state->g_sp.regs[SP_WR_LEN_REG],
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&state->g_sp.regs[SP_STATUS_REG],
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&state->g_sp.regs[SP_DMA_FULL_REG],
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&state->g_sp.regs[SP_DMA_BUSY_REG],
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&state->g_sp.regs[SP_PC_REG],
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&state->g_sp.regs[SP_SEMAPHORE_REG],
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&state->g_dp.dpc_regs[DPC_START_REG],
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&state->g_dp.dpc_regs[DPC_END_REG],
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&state->g_dp.dpc_regs[DPC_CURRENT_REG],
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&state->g_dp.dpc_regs[DPC_STATUS_REG],
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&state->g_dp.dpc_regs[DPC_CLOCK_REG],
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&state->g_dp.dpc_regs[DPC_BUFBUSY_REG],
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&state->g_dp.dpc_regs[DPC_PIPEBUSY_REG],
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&state->g_dp.dpc_regs[DPC_TMEM_REG],
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state);
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state->hle.hle_gfx = 1;
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return 0;
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}
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