721 lines
26 KiB
C
721 lines
26 KiB
C
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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* Mupen64plus - gcop1_d.c *
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* Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
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* Copyright (C) 2007 Richard Goedeken (Richard42) *
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* Copyright (C) 2002 Hacktarux *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
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* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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#include <stdio.h>
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#include "usf/usf.h"
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#include "usf/usf_internal.h"
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#include "assemble.h"
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#include "interpret.h"
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#include "r4300/recomph.h"
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#include "r4300/r4300.h"
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#include "r4300/ops.h"
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#include "r4300/cp1.h"
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#if defined(COUNT_INSTR)
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#include "r4300/instr_counters.h"
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#endif
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#ifdef DYNAREC
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void genadd_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[119]);
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#endif
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#ifdef INTERPRET_ADD_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.ADD_D, 0);
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#else
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gencheck_cop1_unusable(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
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fadd_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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fstp_preg64_qword(state, RAX);
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#endif
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}
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void gensub_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[120]);
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#endif
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#ifdef INTERPRET_SUB_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.SUB_D, 0);
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#else
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gencheck_cop1_unusable(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
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fsub_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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fstp_preg64_qword(state, RAX);
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#endif
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}
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void genmul_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[121]);
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#endif
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#ifdef INTERPRET_MUL_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.MUL_D, 0);
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#else
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gencheck_cop1_unusable(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
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fmul_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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fstp_preg64_qword(state, RAX);
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#endif
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}
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void gendiv_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[122]);
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#endif
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#ifdef INTERPRET_DIV_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.DIV_D, 0);
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#else
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gencheck_cop1_unusable(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
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fdiv_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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fstp_preg64_qword(state, RAX);
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#endif
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}
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void gensqrt_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[123]);
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#endif
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#ifdef INTERPRET_SQRT_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.SQRT_D, 0);
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#else
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gencheck_cop1_unusable(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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fsqrt(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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fstp_preg64_qword(state, RAX);
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#endif
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}
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void genabs_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[124]);
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#endif
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#ifdef INTERPRET_ABS_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.ABS_D, 0);
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#else
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gencheck_cop1_unusable(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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fabs_(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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fstp_preg64_qword(state, RAX);
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#endif
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}
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void genmov_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[125]);
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#endif
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#ifdef INTERPRET_MOV_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.MOV_D, 0);
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#else
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gencheck_cop1_unusable(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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mov_reg32_preg64(state, EBX, RAX);
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mov_reg32_preg64pimm32(state, ECX, RAX, 4);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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mov_preg64_reg32(state, RAX, EBX);
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mov_preg64pimm32_reg32(state, RAX, 4, ECX);
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#endif
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}
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void genneg_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[126]);
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#endif
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#ifdef INTERPRET_NEG_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.NEG_D, 0);
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#else
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gencheck_cop1_unusable(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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fchs(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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fstp_preg64_qword(state, RAX);
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#endif
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}
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void genround_l_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[127]);
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#endif
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#ifdef INTERPRET_ROUND_L_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.ROUND_L_D, 0);
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#else
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gencheck_cop1_unusable(state);
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fldcw_m16rel(state, (unsigned short*)&state->round_mode);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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fistp_preg64_qword(state, RAX);
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fldcw_m16rel(state, (unsigned short*)&state->rounding_mode);
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#endif
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}
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void gentrunc_l_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[128]);
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#endif
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#ifdef INTERPRET_TRUNC_L_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.TRUNC_L_D, 0);
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#else
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gencheck_cop1_unusable(state);
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fldcw_m16rel(state, (unsigned short*)&state->trunc_mode);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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fistp_preg64_qword(state, RAX);
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fldcw_m16rel(state, (unsigned short*)&state->rounding_mode);
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#endif
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}
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void genceil_l_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[129]);
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#endif
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#ifdef INTERPRET_CEIL_L_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.CEIL_L_D, 0);
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#else
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gencheck_cop1_unusable(state);
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fldcw_m16rel(state, (unsigned short*)&state->ceil_mode);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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fistp_preg64_qword(state, RAX);
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fldcw_m16rel(state, (unsigned short*)&state->rounding_mode);
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#endif
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}
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void genfloor_l_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[130]);
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#endif
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#ifdef INTERPRET_FLOOR_L_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.FLOOR_L_D, 0);
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#else
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gencheck_cop1_unusable(state);
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fldcw_m16rel(state, (unsigned short*)&state->floor_mode);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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fistp_preg64_qword(state, RAX);
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fldcw_m16rel(state, (unsigned short*)&state->rounding_mode);
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#endif
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}
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void genround_w_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[127]);
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#endif
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#ifdef INTERPRET_ROUND_W_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.ROUND_W_D, 0);
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#else
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gencheck_cop1_unusable(state);
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fldcw_m16rel(state, (unsigned short*)&state->round_mode);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_simple[state->dst->f.cf.fd]));
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fistp_preg64_dword(state, RAX);
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fldcw_m16rel(state, (unsigned short*)&state->rounding_mode);
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#endif
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}
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void gentrunc_w_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[128]);
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#endif
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#ifdef INTERPRET_TRUNC_W_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.TRUNC_W_D, 0);
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#else
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gencheck_cop1_unusable(state);
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fldcw_m16rel(state, (unsigned short*)&state->trunc_mode);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_simple[state->dst->f.cf.fd]));
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fistp_preg64_dword(state, RAX);
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fldcw_m16rel(state, (unsigned short*)&state->rounding_mode);
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#endif
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}
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void genceil_w_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[129]);
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#endif
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#ifdef INTERPRET_CEIL_W_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.CEIL_W_D, 0);
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#else
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gencheck_cop1_unusable(state);
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fldcw_m16rel(state, (unsigned short*)&state->ceil_mode);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_simple[state->dst->f.cf.fd]));
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fistp_preg64_dword(state, RAX);
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fldcw_m16rel(state, (unsigned short*)&state->rounding_mode);
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#endif
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}
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void genfloor_w_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[130]);
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#endif
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#ifdef INTERPRET_FLOOR_W_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.FLOOR_W_D, 0);
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#else
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gencheck_cop1_unusable(state);
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fldcw_m16rel(state, (unsigned short*)&state->floor_mode);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_simple[state->dst->f.cf.fd]));
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fistp_preg64_dword(state, RAX);
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fldcw_m16rel(state, (unsigned short*)&state->rounding_mode);
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#endif
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}
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void gencvt_s_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[117]);
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#endif
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#ifdef INTERPRET_CVT_S_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.CVT_S_D, 0);
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#else
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gencheck_cop1_unusable(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_simple[state->dst->f.cf.fd]));
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fstp_preg64_dword(state, RAX);
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#endif
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}
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void gencvt_w_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[117]);
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#endif
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#ifdef INTERPRET_CVT_W_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.CVT_W_D, 0);
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#else
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gencheck_cop1_unusable(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_simple[state->dst->f.cf.fd]));
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fistp_preg64_dword(state, RAX);
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#endif
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}
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void gencvt_l_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[117]);
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#endif
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#ifdef INTERPRET_CVT_L_D
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gencallinterp(state, (unsigned long long)state->current_instruction_table.CVT_L_D, 0);
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#else
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gencheck_cop1_unusable(state);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
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fld_preg64_qword(state, RAX);
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mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
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fistp_preg64_qword(state, RAX);
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#endif
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}
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void genc_f_d(usf_state_t * state)
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{
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#if defined(COUNT_INSTR)
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inc_m32rel(state, &state->instr_count[118]);
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#endif
|
|
#ifdef INTERPRET_C_F_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_F_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000);
|
|
#endif
|
|
}
|
|
|
|
void genc_un_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_UN_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_UN_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fucomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
jp_rj(state, 13);
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_eq_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_EQ_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_EQ_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fucomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
jne_rj(state, 13); // 2
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_ueq_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_UEQ_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_UEQ_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fucomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
jp_rj(state, 15);
|
|
jne_rj(state, 13);
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_olt_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_OLT_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_OLT_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fucomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
jae_rj(state, 13); // 2
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_ult_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_ULT_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_ULT_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fucomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
jp_rj(state, 15);
|
|
jae_rj(state, 13); // 2
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_ole_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_OLE_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_OLE_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fucomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
ja_rj(state, 13); // 2
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_ule_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_ULE_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_ULE_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fucomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
jp_rj(state, 15);
|
|
ja_rj(state, 13); // 2
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_sf_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_SF_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_SF_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fcomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000);
|
|
#endif
|
|
}
|
|
|
|
void genc_ngle_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_NGLE_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_NGLE_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fcomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
jp_rj(state, 13);
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_seq_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_SEQ_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_SEQ_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fcomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
jne_rj(state, 13); // 2
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_ngl_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_NGL_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_NGL_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fcomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
jp_rj(state, 15);
|
|
jne_rj(state, 13);
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_lt_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_LT_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_LT_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fcomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
jae_rj(state, 13); // 2
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_nge_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_NGE_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_NGE_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fcomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
jp_rj(state, 15);
|
|
jae_rj(state, 13); // 2
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_le_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_LE_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_LE_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fcomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
ja_rj(state, 13); // 2
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
#endif
|
|
}
|
|
|
|
void genc_ngt_d(usf_state_t * state)
|
|
{
|
|
#if defined(COUNT_INSTR)
|
|
inc_m32rel(state, &state->instr_count[118]);
|
|
#endif
|
|
#ifdef INTERPRET_C_NGT_D
|
|
gencallinterp(state, (unsigned long long)state->current_instruction_table.C_NGT_D, 0);
|
|
#else
|
|
gencheck_cop1_unusable(state);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.ft]));
|
|
fld_preg64_qword(state, RAX);
|
|
mov_xreg64_m64rel(state, RAX, (unsigned long long *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
|
|
fld_preg64_qword(state, RAX);
|
|
fcomip_fpreg(state, 1);
|
|
ffree_fpreg(state, 0);
|
|
jp_rj(state, 15);
|
|
ja_rj(state, 13); // 2
|
|
or_m32rel_imm32(state, (unsigned int*)&state->FCR31, 0x800000); // 11
|
|
jmp_imm_short(state, 11); // 2
|
|
and_m32rel_imm32(state, (unsigned int*)&state->FCR31, ~0x800000); // 11
|
|
#endif
|
|
}
|
|
#endif
|