rebase coreboot/next
same revision, but re-do the patches again. i wasn't quite as thorough with some of it yesterday. for example, i included the ifdtool nuke patch yesterday, which is not actually required in cbmk Signed-off-by: Leah Rowe <info@minifree.org>master
Leah Rowe
parent
b1319f5dbb
commit
a7a1534fb1
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@ -1,7 +1,7 @@
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From 8b951349f2ef77916633c817ad2fc1decd5c0920 Mon Sep 17 00:00:00 2001
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From 8761e8ff502e7df30ce7f5950e227c4aa3119c44 Mon Sep 17 00:00:00 2001
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From: Nicholas Chin <nic.c3.14@gmail.com>
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From: Nicholas Chin <nic.c3.14@gmail.com>
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Date: Mon, 30 Sep 2024 20:44:38 -0400
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Date: Mon, 30 Sep 2024 20:44:38 -0400
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Subject: [PATCH 1/3] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
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Subject: [PATCH 1/7] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
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Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
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Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
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Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
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Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
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@ -1,7 +1,7 @@
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From ddc7390d7750eb3b29a6d6fe7bf2400121d639b5 Mon Sep 17 00:00:00 2001
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From bfe4ae1951bf43f3f4a8512c16bbc10a55397461 Mon Sep 17 00:00:00 2001
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From: Nicholas Chin <nic.c3.14@gmail.com>
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From: Nicholas Chin <nic.c3.14@gmail.com>
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Date: Fri, 12 May 2023 19:55:15 -0600
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Date: Fri, 12 May 2023 19:55:15 -0600
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Subject: [PATCH 3/3] Remove warning for coreboot images built without a
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Subject: [PATCH 2/7] Remove warning for coreboot images built without a
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payload
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payload
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I added this in upstream to prevent people from accidentally flashing
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I added this in upstream to prevent people from accidentally flashing
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@ -1,205 +0,0 @@
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From 1b230f671ebc6e355a001ac7ffc9b031329de019 Mon Sep 17 00:00:00 2001
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From: Leah Rowe <info@minifree.org>
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Date: Sun, 19 Feb 2023 18:21:43 +0000
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Subject: [PATCH 2/3] util/ifdtool: add --nuke flag (all 0xFF on region)
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When this option is used, the region's contents are overwritten
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with all ones (0xFF).
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Example:
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./ifdtool --nuke gbe coreboot.rom
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./ifdtool --nuke bios coreboot.com
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./ifdtool --nuke me coreboot.com
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Rebased since the last revision update in lbmk.
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Signed-off-by: Leah Rowe <leah@libreboot.org>
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---
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util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
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1 file changed, 83 insertions(+), 31 deletions(-)
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diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
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index 36477eef66..3ebef74042 100644
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--- a/util/ifdtool/ifdtool.c
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+++ b/util/ifdtool/ifdtool.c
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@@ -2217,6 +2217,7 @@ static void print_usage(const char *name)
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" tgl - Tiger Lake\n"
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" wbg - Wellsburg\n"
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" -S | --setpchstrap Write a PCH strap\n"
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+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
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" -V | --newvalue The new value to write into PCH strap specified by -S\n"
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" -v | --version: print the version\n"
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" -h | --help: print this help\n\n"
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@@ -2225,6 +2226,60 @@ static void print_usage(const char *name)
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"\n");
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}
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+static int
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+get_region_type_string(const char *region_type_string)
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+{
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+ if (!strcasecmp("Descriptor", region_type_string))
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+ return 0;
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+ else if (!strcasecmp("BIOS", region_type_string))
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+ return 1;
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+ else if (!strcasecmp("ME", region_type_string))
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+ return 2;
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+ else if (!strcasecmp("GbE", region_type_string))
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+ return 3;
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+ else if (!strcasecmp("Platform Data", region_type_string))
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+ return 4;
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+ else if (!strcasecmp("Device Exp1", region_type_string))
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+ return 5;
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+ else if (!strcasecmp("Secondary BIOS", region_type_string))
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+ return 6;
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+ else if (!strcasecmp("Reserved", region_type_string))
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+ return 7;
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+ else if (!strcasecmp("EC", region_type_string))
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+ return 8;
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+ else if (!strcasecmp("Device Exp2", region_type_string))
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+ return 9;
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+ else if (!strcasecmp("IE", region_type_string))
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+ return 10;
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+ else if (!strcasecmp("10GbE_0", region_type_string))
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+ return 11;
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+ else if (!strcasecmp("10GbE_1", region_type_string))
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+ return 12;
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+ else if (!strcasecmp("PTT", region_type_string))
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+ return 15;
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+ return -1;
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+}
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+
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+static void
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+nuke(const char *filename, char *image, int size, int region_type)
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+{
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+ int i;
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+ struct region region;
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+ const struct frba *frba = find_frba(image, size);
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+ if (!frba)
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+ exit(EXIT_FAILURE);
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+
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+ region = get_region(frba, region_type);
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+ if (region.size > 0) {
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+ for (i = region.base; i <= region.limit; i++) {
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+ if ((i + 1) > (size))
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+ break;
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+ image[i] = 0xFF;
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+ }
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+ write_image(filename, image, size);
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+ }
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+}
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+
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int main(int argc, char *argv[])
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{
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int opt, option_index = 0;
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@@ -2232,6 +2287,7 @@ int main(int argc, char *argv[])
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int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
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int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
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int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
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+ int mode_nuke = 0;
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int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
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char *region_type_string = NULL, *region_fname = NULL;
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const char *layout_fname = NULL;
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@@ -2267,6 +2323,7 @@ int main(int argc, char *argv[])
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{"validate", 0, NULL, 't'},
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{"setpchstrap", 1, NULL, 'S'},
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{"newvalue", 1, NULL, 'V'},
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+ {"nuke", 1, NULL, 'N'},
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{0, 0, 0, 0}
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};
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@@ -2316,35 +2373,8 @@ int main(int argc, char *argv[])
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region_fname++;
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// Descriptor, BIOS, ME, GbE, Platform
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// valid type?
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- if (!strcasecmp("Descriptor", region_type_string))
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- region_type = 0;
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- else if (!strcasecmp("BIOS", region_type_string))
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- region_type = 1;
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- else if (!strcasecmp("ME", region_type_string))
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- region_type = 2;
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- else if (!strcasecmp("GbE", region_type_string))
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- region_type = 3;
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- else if (!strcasecmp("Platform Data", region_type_string))
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- region_type = 4;
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- else if (!strcasecmp("Device Exp1", region_type_string))
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- region_type = 5;
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- else if (!strcasecmp("Secondary BIOS", region_type_string))
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- region_type = 6;
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- else if (!strcasecmp("Reserved", region_type_string))
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- region_type = 7;
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- else if (!strcasecmp("EC", region_type_string))
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- region_type = 8;
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- else if (!strcasecmp("Device Exp2", region_type_string))
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- region_type = 9;
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- else if (!strcasecmp("IE", region_type_string))
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- region_type = 10;
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- else if (!strcasecmp("10GbE_0", region_type_string))
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- region_type = 11;
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- else if (!strcasecmp("10GbE_1", region_type_string))
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- region_type = 12;
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- else if (!strcasecmp("PTT", region_type_string))
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- region_type = 15;
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- if (region_type == -1) {
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+ if ((region_type =
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+ get_region_type_string(region_type_string)) == -1) {
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fprintf(stderr, "No such region type: '%s'\n\n",
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region_type_string);
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fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
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@@ -2521,6 +2551,22 @@ int main(int argc, char *argv[])
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case 't':
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mode_validate = 1;
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break;
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+ case 'N':
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+ region_type_string = strdup(optarg);
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+ if (!region_type_string) {
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+ fprintf(stderr, "No region specified\n");
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+ print_usage(argv[0]);
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+ exit(EXIT_FAILURE);
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+ }
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+ if ((region_type =
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+ get_region_type_string(region_type_string)) == -1) {
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+ fprintf(stderr, "No such region type: '%s'\n\n",
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+ region_type_string);
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+ print_usage(argv[0]);
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+ exit(EXIT_FAILURE);
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+ }
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+ mode_nuke = 1;
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+ break;
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case 'v':
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print_version();
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exit(EXIT_SUCCESS);
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@@ -2540,7 +2586,8 @@ int main(int argc, char *argv[])
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if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
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mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
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mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
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- (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) {
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+ (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
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+ mode_nuke) > 1) {
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fprintf(stderr, "You may not specify more than one mode.\n\n");
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fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
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exit(EXIT_FAILURE);
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@@ -2549,7 +2596,8 @@ int main(int argc, char *argv[])
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if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
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mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
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mode_locked + mode_unlocked + mode_density + mode_altmedisable +
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- mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) {
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+ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
|
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+ mode_nuke) == 0) {
|
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fprintf(stderr, "You need to specify a mode.\n\n");
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fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
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exit(EXIT_FAILURE);
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@@ -2662,6 +2710,10 @@ int main(int argc, char *argv[])
|
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write_image(new_filename, image, size);
|
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}
|
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|
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+ if (mode_nuke) {
|
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+ nuke(new_filename, image, size, region_type);
|
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+ }
|
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+
|
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if (mode_altmedisable) {
|
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struct fpsba *fpsba = find_fpsba(image, size);
|
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struct fmsba *fmsba = find_fmsba(image, size);
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--
|
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2.39.5
|
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|
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|
@ -1,7 +1,7 @@
|
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From 300f73eae58bfcde26f82814a5e295585b3e3a2a Mon Sep 17 00:00:00 2001
|
From 173989476c90e3d15c0f5f7e669b16bc496349aa Mon Sep 17 00:00:00 2001
|
||||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
From: Nicholas Chin <nic.c3.14@gmail.com>
|
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Date: Wed, 30 Oct 2024 20:55:25 -0600
|
Date: Wed, 30 Oct 2024 20:55:25 -0600
|
||||||
Subject: [PATCH 1/1] mb/dell/optiplex_780: Add USFF variant
|
Subject: [PATCH 3/7] mb/dell/optiplex_780: Add USFF variant
|
||||||
|
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Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103
|
Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103
|
||||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
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|
|
@ -1,7 +1,7 @@
|
||||||
From 146f8792f57ee237d07e4ca506fb77c93ed27932 Mon Sep 17 00:00:00 2001
|
From 268e6e585e38493fcb772b4bea967023fdaca413 Mon Sep 17 00:00:00 2001
|
||||||
From: Leah Rowe <leah@libreboot.org>
|
From: Leah Rowe <leah@libreboot.org>
|
||||||
Date: Thu, 12 Oct 2023 01:20:23 +0100
|
Date: Thu, 12 Oct 2023 01:20:23 +0100
|
||||||
Subject: [PATCH 1/2] never enable cpu microcode, even if told to
|
Subject: [PATCH 4/7] never enable cpu microcode, even if told to
|
||||||
|
|
||||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||||
---
|
---
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
From 7d63d1b21650238300250f7408335d650447c3d6 Mon Sep 17 00:00:00 2001
|
From ff1c1618fbdca6d53aa348c5970069ba1bae1de6 Mon Sep 17 00:00:00 2001
|
||||||
From: Leah Rowe <info@minifree.org>
|
From: Leah Rowe <info@minifree.org>
|
||||||
Date: Fri, 3 May 2024 06:24:49 +0100
|
Date: Fri, 3 May 2024 06:24:49 +0100
|
||||||
Subject: [PATCH 2/2] Never download blobs, even if USE_BLOBS=y
|
Subject: [PATCH 5/7] Never download blobs, even if USE_BLOBS=y
|
||||||
|
|
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same idea as my never-microcode patches. i maintain
|
same idea as my never-microcode patches. i maintain
|
||||||
canoeboot and i like to re-use the same configs from
|
canoeboot and i like to re-use the same configs from
|
||||||
|
|
@ -0,0 +1,47 @@
|
||||||
|
From eabfef6cdd2d10e8c5097839fb24a65d8ffedaed Mon Sep 17 00:00:00 2001
|
||||||
|
From: Leah Rowe <leah@libreboot.org>
|
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|
Date: Wed, 1 Dec 2021 02:53:00 +0000
|
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|
Subject: [PATCH 6/7] fix speedstep on x200/t400: Revert
|
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|
"cpu/intel/model_1067x: enable PECI"
|
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|
|
||||||
|
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
|
||||||
|
|
||||||
|
Enabling PECI without microcode updates loaded causes the CPUID feature set
|
||||||
|
to become corrupted. And one consequence is broken SpeedStep. At least, that's
|
||||||
|
my understanding looking at Intel Errata. This revert is not a fix, because
|
||||||
|
upstream is correct (upstream assumes microcode updates). We will simply
|
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|
maintain this revert patch in Libreboot, from now on.
|
||||||
|
---
|
||||||
|
src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
|
||||||
|
1 file changed, 9 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||||
|
index d051e8915b..30ba2bf0c6 100644
|
||||||
|
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||||
|
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||||
|
@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
|
||||||
|
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
|
||||||
|
}
|
||||||
|
|
||||||
|
-#define IA32_PECI_CTL 0x5a0
|
||||||
|
-
|
||||||
|
static void configure_misc(const int eist, const int tm2, const int emttm)
|
||||||
|
{
|
||||||
|
msr_t msr;
|
||||||
|
@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
|
||||||
|
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
|
||||||
|
wrmsr(IA32_MISC_ENABLE, msr);
|
||||||
|
}
|
||||||
|
-
|
||||||
|
- /* Enable PECI
|
||||||
|
- WARNING: due to Erratum AW67 described in Intel document #318733
|
||||||
|
- the microcode must be updated before this MSR is written to. */
|
||||||
|
- msr = rdmsr(IA32_PECI_CTL);
|
||||||
|
- msr.lo |= 1;
|
||||||
|
- wrmsr(IA32_PECI_CTL, msr);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PIC_SENS_CFG 0x1aa
|
||||||
|
--
|
||||||
|
2.39.5
|
||||||
|
|
||||||
|
|
@ -0,0 +1,173 @@
|
||||||
|
From 015cb964c94d46a2d06bf3add34031e2be40b260 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Leah Rowe <leah@libreboot.org>
|
||||||
|
Date: Mon, 17 Apr 2023 15:49:57 +0100
|
||||||
|
Subject: [PATCH 7/7] GM45-type CPUs: don't enable alternative SMRR
|
||||||
|
|
||||||
|
This reverts the changes in coreboot revision:
|
||||||
|
df7aecd92643d207feaf7fd840f8835097346644
|
||||||
|
|
||||||
|
While this fix is *technically correct*, the one in
|
||||||
|
coreboot, it breaks rebooting as tested on several
|
||||||
|
GM45 ThinkPads e.g. X200, T400, when microcode
|
||||||
|
updates are not applied.
|
||||||
|
|
||||||
|
Since November 2022, Libreboot includes microcode
|
||||||
|
updates by default, but it tells users how to remove
|
||||||
|
it from the ROM (with cbfstool) if they wish.
|
||||||
|
|
||||||
|
Well, with Libreboot 20221214, 20230319 and 20230413,
|
||||||
|
mitigations present in Libreboot 20220710 (which did
|
||||||
|
not have microcode updates) do not exist.
|
||||||
|
|
||||||
|
This patch, along with the other patch to remove PECI
|
||||||
|
support (which breaks speedstep when microcode updates
|
||||||
|
are not applied) have now been re-added to Libreboot.
|
||||||
|
|
||||||
|
It is still best to use microcode updates by default.
|
||||||
|
These patches in coreboot are not critically urgent,
|
||||||
|
and you can use the machines with or without them,
|
||||||
|
regardless of ucode.
|
||||||
|
|
||||||
|
I'll probably re-write this and the other patch at
|
||||||
|
some point, applying the change conditionally upon
|
||||||
|
whether or not microcode is applied.
|
||||||
|
|
||||||
|
Pragmatism is a good thing. I recommend it.
|
||||||
|
---
|
||||||
|
src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
|
||||||
|
src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
|
||||||
|
src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
|
||||||
|
src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
|
||||||
|
src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
|
||||||
|
5 files changed, 16 insertions(+), 26 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||||
|
index 30ba2bf0c6..312046901a 100644
|
||||||
|
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||||
|
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||||
|
@@ -8,6 +8,7 @@
|
||||||
|
#include <cpu/x86/cache.h>
|
||||||
|
#include <cpu/x86/name.h>
|
||||||
|
#include <cpu/intel/smm_reloc.h>
|
||||||
|
+#include <cpu/intel/common/common.h>
|
||||||
|
|
||||||
|
#define MSR_BBL_CR_CTL3 0x11e
|
||||||
|
|
||||||
|
@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
|
||||||
|
fill_processor_name(processor_name);
|
||||||
|
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
|
||||||
|
|
||||||
|
+ /* Set virtualization based on Kconfig option */
|
||||||
|
+ set_vmx_and_lock();
|
||||||
|
+
|
||||||
|
/* Configure C States */
|
||||||
|
configure_c_states(quad);
|
||||||
|
|
||||||
|
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
|
||||||
|
index bc53214310..72f40f6762 100644
|
||||||
|
--- a/src/cpu/intel/model_1067x/mp_init.c
|
||||||
|
+++ b/src/cpu/intel/model_1067x/mp_init.c
|
||||||
|
@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
|
||||||
|
smm_initialize();
|
||||||
|
}
|
||||||
|
|
||||||
|
-#define SMRR_SUPPORTED (1 << 11)
|
||||||
|
-
|
||||||
|
static void per_cpu_smm_trigger(void)
|
||||||
|
{
|
||||||
|
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
|
||||||
|
- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
|
||||||
|
- set_feature_ctrl_vmx();
|
||||||
|
- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
|
||||||
|
- /* We don't care if the lock is already setting
|
||||||
|
- as our smm relocation handler is able to handle
|
||||||
|
- setups where SMRR is not enabled here. */
|
||||||
|
- if (ia32_ft_ctrl.lo & (1 << 0)) {
|
||||||
|
- /* IA32_FEATURE_CONTROL locked. If we set it again we
|
||||||
|
- get an illegal instruction. */
|
||||||
|
- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
|
||||||
|
- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
|
||||||
|
- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
|
||||||
|
- } else {
|
||||||
|
- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
|
||||||
|
- printk(BIOS_INFO,
|
||||||
|
- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
|
||||||
|
- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
|
||||||
|
- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
|
||||||
|
- }
|
||||||
|
- } else {
|
||||||
|
- set_vmx_and_lock();
|
||||||
|
- }
|
||||||
|
-
|
||||||
|
/* Relocate the SMM handler. */
|
||||||
|
smm_relocate();
|
||||||
|
}
|
||||||
|
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
|
||||||
|
index 05f5f327cc..0450c2ad83 100644
|
||||||
|
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
|
||||||
|
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
|
||||||
|
@@ -7,6 +7,7 @@
|
||||||
|
#include <cpu/intel/speedstep.h>
|
||||||
|
#include <cpu/x86/cache.h>
|
||||||
|
#include <cpu/x86/name.h>
|
||||||
|
+#include <cpu/intel/common/common.h>
|
||||||
|
|
||||||
|
#define HIGHEST_CLEVEL 3
|
||||||
|
static void configure_c_states(void)
|
||||||
|
@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
|
||||||
|
fill_processor_name(processor_name);
|
||||||
|
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
|
||||||
|
|
||||||
|
+ /* Set virtualization based on Kconfig option */
|
||||||
|
+ set_vmx_and_lock();
|
||||||
|
+
|
||||||
|
/* Configure C States */
|
||||||
|
configure_c_states();
|
||||||
|
|
||||||
|
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
|
||||||
|
index 5bd1c32815..f3bb08cde3 100644
|
||||||
|
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
|
||||||
|
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
|
||||||
|
@@ -7,6 +7,7 @@
|
||||||
|
#include <cpu/intel/speedstep.h>
|
||||||
|
#include <cpu/x86/cache.h>
|
||||||
|
#include <cpu/x86/name.h>
|
||||||
|
+#include <cpu/intel/common/common.h>
|
||||||
|
|
||||||
|
#define HIGHEST_CLEVEL 3
|
||||||
|
static void configure_c_states(void)
|
||||||
|
@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
|
||||||
|
/* Setup Page Attribute Tables (PAT) */
|
||||||
|
// TODO set up PAT
|
||||||
|
|
||||||
|
+ /* Set virtualization based on Kconfig option */
|
||||||
|
+ set_vmx_and_lock();
|
||||||
|
+
|
||||||
|
/* Configure C States */
|
||||||
|
configure_c_states();
|
||||||
|
|
||||||
|
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
|
||||||
|
index 535fb8fae7..f7b05facd2 100644
|
||||||
|
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
|
||||||
|
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
|
||||||
|
@@ -7,6 +7,7 @@
|
||||||
|
#include <cpu/intel/speedstep.h>
|
||||||
|
#include <cpu/x86/cache.h>
|
||||||
|
#include <cpu/x86/name.h>
|
||||||
|
+#include <cpu/intel/common/common.h>
|
||||||
|
|
||||||
|
#define HIGHEST_CLEVEL 3
|
||||||
|
static void configure_c_states(void)
|
||||||
|
@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
|
||||||
|
/* Setup Page Attribute Tables (PAT) */
|
||||||
|
// TODO set up PAT
|
||||||
|
|
||||||
|
+ /* Set virtualization based on Kconfig option */
|
||||||
|
+ set_vmx_and_lock();
|
||||||
|
+
|
||||||
|
/* Configure C States */
|
||||||
|
configure_c_states();
|
||||||
|
|
||||||
|
--
|
||||||
|
2.39.5
|
||||||
|
|
||||||
Loading…
Reference in New Issue