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coreboot/default: Re-base all patches 

There were a lot of unnecessary patches, such as the VRAM
patches; as Nicholas Chin has explained to me, the drivers
for these machines will just allocate what RAM they want
anyway, so in a lot of cases the extra allocated Video RAM
simply reduces the total amount of memory for other uses.

In general, we have a lot of patches that have existed for
years. A much more aggressive sweep will be done in the next
major audit, especially when the revisions are updated again.

Signed-off-by: Leah Rowe <leah@libreboot.org>
m920qwip
Leah Rowe 2024-11-01 15:59:30 +00:00
parent 67c92889a8
commit 14b4838d49
64 changed files with 108 additions and 718 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch → config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch
View File

@ -1,7 +1,7 @@
From 2533ed49003c470a8dbfbf17f6c6a5ef0672c2e2 Mon Sep 17 00:00:00 2001
From f625e31ee3abb867e775ab0cb724550825699c36 Mon Sep 17 00:00:00 2001
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
Date: Wed, 27 Oct 2021 13:36:01 +0200
Subject: [PATCH 02/65] add c3 and clockgen to apple/macbook21
Subject: [PATCH 01/51] add c3 and clockgen to apple/macbook21
---
src/mainboard/apple/macbook21/Kconfig | 1 +

23
config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
View File

@ -1,23 +0,0 @@
From e8eb37e87abfdf6d2bcf60cb15d35650fcfa6665 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@retroboot.org>
Date: Fri, 19 Mar 2021 05:54:58 +0000
Subject: [PATCH 01/65] apple/macbook21: Set default VRAM to 64MiB instead of
8MiB
---
src/mainboard/apple/macbook21/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
index b744b11cda..9749e26547 100644
--- a/src/mainboard/apple/macbook21/cmos.default
+++ b/src/mainboard/apple/macbook21/cmos.default
@@ -7,4 +7,4 @@ boot_devices=''
boot_default=0x40
cmos_defaults_loaded=Yes
lpt=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.5

4
config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch → config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch
View File

@ -1,7 +1,7 @@
From 15003992f57b62ce59dc282cd089987306126cc9 Mon Sep 17 00:00:00 2001
From 8821f229d4fe48153ec7a45e0e04c3b2a3cd8c7c Mon Sep 17 00:00:00 2001
From: persmule <persmule@gmail.com>
Date: Sun, 31 Oct 2021 23:33:26 +0000
Subject: [PATCH 09/65] lenovo/t400: Enable all SATA ports
Subject: [PATCH 02/51] lenovo/t400: Enable all SATA ports
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its

9
config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch → config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
View File

@ -1,7 +1,7 @@
From 47483865af46a3d1f8732d1bd97f4a7155cc24d6 Mon Sep 17 00:00:00 2001
From 0298639b6e80c8950fbb4484180b7195883ab8c1 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 3 Jan 2022 19:06:22 +0000
Subject: [PATCH 11/65] lenovo/x230: set me_state=Disabled in cmos.default
Subject: [PATCH 03/51] lenovo/x230: set me_state=Disabled in cmos.default
I only recently found out about this. It's possible to use me_cleaner to
do the same thing, but some people might just flash coreboot and not do
@ -23,16 +23,15 @@ Date: Thu Nov 21 21:47:31 2019 +0300
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
index 3bb78960b9..ae47202aac 100644
index 732e214b32..8454f0eac0 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
@@ -17,5 +17,5 @@ trackpoint=Enable
@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
gfx_uma_size=224M
--
2.39.5

23
config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
View File

@ -1,23 +0,0 @@
From 14920409e51a9a0997d488b166d90bfad56f61f1 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Sun, 3 Jan 2021 03:34:01 +0000
Subject: [PATCH 03/65] lenovo/x60: 64MiB Video RAM changed to default
(previously it was 8MiB)
---
src/mainboard/lenovo/x60/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
index 58825c8a36..8e0aaf427d 100644
--- a/src/mainboard/lenovo/x60/cmos.default
+++ b/src/mainboard/lenovo/x60/cmos.default
@@ -17,4 +17,4 @@ trackpoint=Enable
sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.5

22
config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
View File

@ -1,22 +0,0 @@
From 92b009babd1e4a63dd34638924b9559727713369 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Mon, 22 Feb 2021 22:16:59 +0000
Subject: [PATCH 04/65] lenovo/t60: make 64MiB VRAM the default in cmos.default
---
src/mainboard/lenovo/t60/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
index 283a5747ee..91f6c0e6e2 100644
--- a/src/mainboard/lenovo/t60/cmos.default
+++ b/src/mainboard/lenovo/t60/cmos.default
@@ -17,4 +17,4 @@ trackpoint=Enable
sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.5

4
config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch → config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch
View File

@ -1,7 +1,7 @@
From 84f7622ea0c3a78742f129d2ec9f437e6c424839 Mon Sep 17 00:00:00 2001
From c697c90ace86edfe724c86bd6a680cf0ae0e4b58 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 2 Mar 2022 21:50:01 +0000
Subject: [PATCH 12/65] set me_state=Disabled on all cmos.default files!
Subject: [PATCH 04/51] set me_state=Disabled on all cmos.default files!
yeah. why the hell isn't this the default

23
config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch
View File

@ -1,23 +0,0 @@
From c7ad2407a7f515d487332382bb55025873c3d987 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:10:33 +0100
Subject: [PATCH 05/65] lenovo/t400: set VRAM to 256MiB VRAM by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/t400/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
index a16d386dd1..e7bb32306c 100644
--- a/src/mainboard/lenovo/t400/cmos.default
+++ b/src/mainboard/lenovo/t400/cmos.default
@@ -15,4 +15,4 @@ power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
hybrid_graphics_mode=Integrated Only
-gfx_uma_size=32M
+gfx_uma_size=256M
--
2.39.5

4
config/coreboot/default/patches/0013-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch → config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
View File

@ -1,7 +1,7 @@
From 851aa297808a4776634df5817cae54c226b4d750 Mon Sep 17 00:00:00 2001
From d2f579b82921c2c35e4cf756db0ca476fbadfac1 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sun, 19 Feb 2023 18:21:43 +0000
Subject: [PATCH 13/65] util/ifdtool: add --nuke flag (all 0xFF on region)
Subject: [PATCH 05/51] util/ifdtool: add --nuke flag (all 0xFF on region)
When this option is used, the region's contents are overwritten
with all ones (0xFF).

23
config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch
View File

@ -1,23 +0,0 @@
From 79f686dae47d2ef934b5c95979195f9d3c1978e6 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:11:59 +0100
Subject: [PATCH 06/65] lenovo/x200: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/x200/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
index 434af5d227..443ef54e41 100644
--- a/src/mainboard/lenovo/x200/cmos.default
+++ b/src/mainboard/lenovo/x200/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=256M
--
2.39.5

4
config/coreboot/default/patches/0016-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch → config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
View File

@ -1,7 +1,7 @@
From b925e95cc9d750c56fdbfbd1838b77339c124139 Mon Sep 17 00:00:00 2001
From a5bc59037dabd95b6595c5aaf38b83da2a91de54 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 6 May 2023 15:53:41 -0600
Subject: [PATCH 16/65] mb/dell/e6400: Enable 01.0 device in devicetree for
Subject: [PATCH 06/51] mb/dell/e6400: Enable 01.0 device in devicetree for
dGPU models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed

4
config/coreboot/default/patches/0017-Remove-warning-for-coreboot-images-built-without-a-p.patch → config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch
View File

@ -1,7 +1,7 @@
From f440b426378314bfbc0f397fdd9bd5bd68d81483 Mon Sep 17 00:00:00 2001
From f883599a362f1383f3712b72516f76187d0a9cbe Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
Subject: [PATCH 17/65] Remove warning for coreboot images built without a
Subject: [PATCH 07/51] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing

23
config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch
View File

@ -1,23 +0,0 @@
From a79498ab8a7eac809d99db2fad5b0f8c63870e43 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:18:26 +0100
Subject: [PATCH 07/65] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
index fe79c83570..4a1f97a9d8 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
@@ -4,4 +4,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
-gfx_uma_size=64M
+gfx_uma_size=256M
--
2.39.5

23
config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch
View File

@ -1,23 +0,0 @@
From 5fbdbb11b215e3aa4256dfaa468224fd0c2a1fb0 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:21:39 +0100
Subject: [PATCH 08/65] acer/g43t-am3: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/acer/g43t-am3/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
index 23f0e55f3e..8d6c4db1ce 100644
--- a/src/mainboard/acer/g43t-am3/cmos.default
+++ b/src/mainboard/acer/g43t-am3/cmos.default
@@ -5,4 +5,4 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=64M
+gfx_uma_size=256M
--
2.39.5

4
config/coreboot/default/patches/0018-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch → config/coreboot/default/patches/0008-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch
View File

@ -1,7 +1,7 @@
From e4509a2d3204d8798cc48be37f33e43d07ff5e3b Mon Sep 17 00:00:00 2001
From 40545928c415c27d3a30748e4bfdee7f9d8f82f9 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 19 Aug 2023 16:19:10 -0600
Subject: [PATCH 18/65] mb/dell: Add Latitude E6530 (Ivy Bridge)
Subject: [PATCH 08/51] mb/dell: Add Latitude E6530 (Ivy Bridge)
Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was
not tested. I do not physically have this system; someone with physical

4
config/coreboot/default/patches/0019-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch → config/coreboot/default/patches/0009-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch
View File

@ -1,7 +1,7 @@
From cfac9aa347e13065c2e24d62091636cc4d0e56be Mon Sep 17 00:00:00 2001
From 423e2e28618b08a4107aea0a2fbc1096f5a8be02 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 31 Jan 2024 22:57:07 -0700
Subject: [PATCH 19/65] mb/dell: Add Latitude E5530 (Ivy Bridge)
Subject: [PATCH 09/51] mb/dell: Add Latitude E5530 (Ivy Bridge)
Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board;
someone with physical access to one sent me the output of autoport which

22
config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch
View File

@ -1,22 +0,0 @@
From f8ea06883762c906a7f3ad7d286b628bca3443ab Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 20 Dec 2021 01:29:31 +0000
Subject: [PATCH 10/65] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
default
---
src/mainboard/lenovo/x230/cmos.default | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
index 732e214b32..3bb78960b9 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
@@ -18,3 +18,4 @@ backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
me_state=Normal
+gfx_uma_size=224M
--
2.39.5

4
config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch → config/coreboot/default/patches/0010-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch
View File

@ -1,7 +1,7 @@
From e5ed7361d41b89ee38b572beb921924b33cc174d Mon Sep 17 00:00:00 2001
From 200668a694f1c534a94a0bc8996416e246fe91b0 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 26 Nov 2023 17:08:52 -0700
Subject: [PATCH 20/65] mb/dell: Add Latitude E6420 (Sandy Bridge)
Subject: [PATCH 10/51] mb/dell: Add Latitude E6420 (Sandy Bridge)
Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was
not tested. I do not physically have this system; someone with physical

4
config/coreboot/default/patches/0021-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch → config/coreboot/default/patches/0011-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch
View File

@ -1,7 +1,7 @@
From 73313e682ba8808f8db6259ac7d93f54c11cb884 Mon Sep 17 00:00:00 2001
From 53abe363f2fa038080a976f2d3a2c63ee8da9022 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 31 Jan 2024 22:07:25 -0700
Subject: [PATCH 21/65] mb/dell: Add Latitude E6520 (Sandy Bridge)
Subject: [PATCH 11/51] mb/dell: Add Latitude E6520 (Sandy Bridge)
Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was
not tested. I do not physically have this system; someone with physical

4
config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E5520-Sandy-Bridge.patch → config/coreboot/default/patches/0012-mb-dell-Add-Latitude-E5520-Sandy-Bridge.patch
View File

@ -1,7 +1,7 @@
From a7e2fde426280a944916c341586361f3ac9fa9a8 Mon Sep 17 00:00:00 2001
From 3f8eade6150f582129332f6347e9a685f8a7b500 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 7 Feb 2024 10:23:38 -0700
Subject: [PATCH 22/65] mb/dell: Add Latitude E5520 (Sandy Bridge)
Subject: [PATCH 12/51] mb/dell: Add Latitude E5520 (Sandy Bridge)
Mainboard is Krug 15". I do not physically have this system; someone
with physical access to one sent me the output of autoport which I then

4
config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch → config/coreboot/default/patches/0013-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch
View File

@ -1,7 +1,7 @@
From f781a8bac250d4902ec3e7caa0628c77836a8ae3 Mon Sep 17 00:00:00 2001
From bbcd6a7f09ee99f3b26b0931f1dcd70970242ee8 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 4 Mar 2024 18:05:43 -0700
Subject: [PATCH 23/65] mb/dell: Add Latitude E5420 (Sandy Bridge)
Subject: [PATCH 13/51] mb/dell: Add Latitude E5420 (Sandy Bridge)
Mainboard is Krug 14". I do not physically have this system; someone
with physical access to one sent me the output of autoport which I then

47
config/coreboot/default/patches/0014-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
View File

@ -1,47 +0,0 @@
From a1a4312c9bea5b7fb5170174dbd14f914c11637c Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
Subject: [PATCH 14/65] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
Enabling PECI without microcode updates loaded causes the CPUID feature set
to become corrupted. And one consequence is broken SpeedStep. At least, that's
my understanding looking at Intel Errata. This revert is not a fix, because
upstream is correct (upstream assumes microcode updates). We will simply
maintain this revert patch in Libreboot, from now on.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index d051e8915b..30ba2bf0c6 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
}
-#define IA32_PECI_CTL 0x5a0
-
static void configure_misc(const int eist, const int tm2, const int emttm)
{
msr_t msr;
@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
}
-
- /* Enable PECI
- WARNING: due to Erratum AW67 described in Intel document #318733
- the microcode must be updated before this MSR is written to. */
- msr = rdmsr(IA32_PECI_CTL);
- msr.lo |= 1;
- wrmsr(IA32_PECI_CTL, msr);
}
#define PIC_SENS_CFG 0x1aa
--
2.39.5

4
config/coreboot/default/patches/0024-mb-dell-Add-Latitude-E6320-Sandy-Bridge.patch → config/coreboot/default/patches/0014-mb-dell-Add-Latitude-E6320-Sandy-Bridge.patch
View File

@ -1,7 +1,7 @@
From 85a0905b600c1f532c462047941da6e7c2bb47c2 Mon Sep 17 00:00:00 2001
From cd6e699649459fa5ff2623018ccf3585eb3d3821 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 7 Feb 2024 15:23:46 -0700
Subject: [PATCH 24/65] mb/dell: Add Latitude E6320 (Sandy Bridge)
Subject: [PATCH 14/51] mb/dell: Add Latitude E6320 (Sandy Bridge)
Mainboard is PAL70/LA-6611P. I do not physically have this system;
someone with physical access to one sent me the output of autoport which

173
config/coreboot/default/patches/0015-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
View File

@ -1,173 +0,0 @@
From 7e366e5d4d56aade1cb8de8433eb2b02cc9aceef Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 17 Apr 2023 15:49:57 +0100
Subject: [PATCH 15/65] GM45-type CPUs: don't enable alternative SMRR
This reverts the changes in coreboot revision:
df7aecd92643d207feaf7fd840f8835097346644
While this fix is *technically correct*, the one in
coreboot, it breaks rebooting as tested on several
GM45 ThinkPads e.g. X200, T400, when microcode
updates are not applied.
Since November 2022, Libreboot includes microcode
updates by default, but it tells users how to remove
it from the ROM (with cbfstool) if they wish.
Well, with Libreboot 20221214, 20230319 and 20230413,
mitigations present in Libreboot 20220710 (which did
not have microcode updates) do not exist.
This patch, along with the other patch to remove PECI
support (which breaks speedstep when microcode updates
are not applied) have now been re-added to Libreboot.
It is still best to use microcode updates by default.
These patches in coreboot are not critically urgent,
and you can use the machines with or without them,
regardless of ucode.
I'll probably re-write this and the other patch at
some point, applying the change conditionally upon
whether or not microcode is applied.
Pragmatism is a good thing. I recommend it.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
5 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 30ba2bf0c6..312046901a 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -8,6 +8,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/common/common.h>
#define MSR_BBL_CR_CTL3 0x11e
@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states(quad);
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index bc53214310..72f40f6762 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
smm_initialize();
}
-#define SMRR_SUPPORTED (1 << 11)
-
static void per_cpu_smm_trigger(void)
{
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
- set_feature_ctrl_vmx();
- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
- /* We don't care if the lock is already setting
- as our smm relocation handler is able to handle
- setups where SMRR is not enabled here. */
- if (ia32_ft_ctrl.lo & (1 << 0)) {
- /* IA32_FEATURE_CONTROL locked. If we set it again we
- get an illegal instruction. */
- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
- } else {
- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
- printk(BIOS_INFO,
- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
- }
- } else {
- set_vmx_and_lock();
- }
-
/* Relocate the SMM handler. */
smm_relocate();
}
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 05f5f327cc..0450c2ad83 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 5bd1c32815..f3bb08cde3 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 535fb8fae7..f7b05facd2 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
--
2.39.5

4
config/coreboot/default/patches/0025-mb-dell-Add-Latitude-E6220-Sandy-Bridge.patch → config/coreboot/default/patches/0015-mb-dell-Add-Latitude-E6220-Sandy-Bridge.patch
View File

@ -1,7 +1,7 @@
From 817b0d543444e52ddfde536ded52509456dcbbf2 Mon Sep 17 00:00:00 2001
From a32431d5f7574ffa6391221c7740f1739203eaa7 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 8 Mar 2024 09:27:36 -0700
Subject: [PATCH 25/65] mb/dell: Add Latitude E6220 (Sandy Bridge)
Subject: [PATCH 15/51] mb/dell: Add Latitude E6220 (Sandy Bridge)
Mainboard is codenamed Vida. I do not physically have this system;
someone with physical access to one sent me the output of autoport which

4
config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch → config/coreboot/default/patches/0016-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch
View File

@ -1,7 +1,7 @@
From 48347cf8bc52db7a454a7be8cbc6f9d9eb67b8b0 Mon Sep 17 00:00:00 2001
From 0889cc6b6f62cba616feff5ae8558be31f298069 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 8 Mar 2024 09:33:03 -0700
Subject: [PATCH 26/65] mb/dell: Add Latitude E6330 (Ivy Bridge)
Subject: [PATCH 16/51] mb/dell: Add Latitude E6330 (Ivy Bridge)
Mainboard is QAL70/LA-7741P. I do not physically have this system;
someone with physical access to one sent me the output of autoport which

4
config/coreboot/default/patches/0027-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch → config/coreboot/default/patches/0017-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch
View File

@ -1,7 +1,7 @@
From 80af5303da07197a7da5262e82a59b691ffed5a2 Mon Sep 17 00:00:00 2001
From 84d7f3201eb4492acd7d290a02d19c4850c85791 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Thu, 26 Oct 2017 21:26:43 +0800
Subject: [PATCH 27/65] mb/dell: Add Latitude E6230 (Ivy Bridge)
Subject: [PATCH 17/51] mb/dell: Add Latitude E6230 (Ivy Bridge)
This was adapted from CB:22693 from Iru Cai, which was based on
autoport. I do not physically have this system. Someone with physical

4
config/coreboot/default/patches/0028-HACK-Disable-coreboot-related-BL31-features.patch → config/coreboot/default/patches/0018-HACK-Disable-coreboot-related-BL31-features.patch
View File

@ -1,7 +1,7 @@
From 8fa72bedc6282ba581ede85d62a341917ec5d203 Mon Sep 17 00:00:00 2001
From ec27f5414c78d493ec7be4cd055ac877ce9ea178 Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Date: Thu, 22 Jun 2023 16:44:27 +0300
Subject: [PATCH 28/65] HACK: Disable coreboot related BL31 features
Subject: [PATCH 18/51] HACK: Disable coreboot related BL31 features
I don't know why, but removing this BL31 make argument lets gru-kevin
power off properly when shut down from Linux. Needs investigation.

4
config/coreboot/default/patches/0031-dell-e6430-use-ME-Soft-Temporary-Disable.patch → config/coreboot/default/patches/0019-dell-e6430-use-ME-Soft-Temporary-Disable.patch
View File

@ -1,7 +1,7 @@
From 7b1caf7260ab468fa2f0e6d73090c5412bc0254d Mon Sep 17 00:00:00 2001
From a15b59616e00c43c05d7853080859d4aefe26c5d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 11:41:41 +0000
Subject: [PATCH 31/65] dell/e6430: use ME Soft Temporary Disable
Subject: [PATCH 19/51] dell/e6430: use ME Soft Temporary Disable
i overlooked this. it's set on other boards.

4
config/coreboot/default/patches/0033-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch → config/coreboot/default/patches/0020-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch
View File

@ -1,7 +1,7 @@
From 3697d2e2df764bd2f1b05a6856e035b606f6a360 Mon Sep 17 00:00:00 2001
From 440ebbe1e10911dc3d8c53cf9eecb5519c2ecd67 Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Sat, 23 Dec 2023 19:02:10 +0200
Subject: [PATCH 33/65] mb/hp: Add Compaq Elite 8300 CMT port
Subject: [PATCH 20/51] mb/hp: Add Compaq Elite 8300 CMT port
Based on autoport and Z220 SuperIO code.

4
config/coreboot/default/patches/0034-nb-intel-haswell-make-IOMMU-a-runtime-option.patch → config/coreboot/default/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch
View File

@ -1,7 +1,7 @@
From 0ad294f2da8085d5612f7940ec8601d979cb2421 Mon Sep 17 00:00:00 2001
From 4c7577314f19e934d690c4cce3642fe693400c07 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 2 Mar 2024 22:51:09 +0000
Subject: [PATCH 34/65] nb/intel/haswell: make IOMMU a runtime option
Subject: [PATCH 21/51] nb/intel/haswell: make IOMMU a runtime option
When I tested graphics cards on a coreboot port for Dell
OptiPlex 9020 SFF, I could not use a graphics card unless

4
config/coreboot/default/patches/0035-dell-optiplex_9020-Disable-IOMMU-by-default.patch → config/coreboot/default/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch
View File

@ -1,7 +1,7 @@
From 80d728b91ec793f584bcf045f00e5fe4bba5e4ae Mon Sep 17 00:00:00 2001
From b5695d0f0dc44ed1eb1feac008e601040feda55d Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 2 Mar 2024 23:00:09 +0000
Subject: [PATCH 35/65] dell/optiplex_9020: Disable IOMMU by default
Subject: [PATCH 22/51] dell/optiplex_9020: Disable IOMMU by default
Needed to make graphics cards work. Turning it on is
recommended if only using iGPU, otherwise leave it off

4
config/coreboot/default/patches/0036-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch → config/coreboot/default/patches/0023-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch
View File

@ -1,7 +1,7 @@
From dba9c3776f90bf345070a90c048ff2bae7180f73 Mon Sep 17 00:00:00 2001
From d86824305f11bc684f1e91e3826158b8c7d7e0ee Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 6 Apr 2024 01:22:47 +0100
Subject: [PATCH 36/65] nb/haswell: Fully disable iGPU when dGPU is used
Subject: [PATCH 23/51] nb/haswell: Fully disable iGPU when dGPU is used
My earlier patch disabled decode *and* disabled the iGPU itself, but
a subsequent revision disabled only VGA decode. Upon revisiting, I

6
config/coreboot/default/patches/0037-ec-dell-mec5035-Replace-defines-with-enums.patch → config/coreboot/default/patches/0024-ec-dell-mec5035-Replace-defines-with-enums.patch
View File

@ -1,7 +1,7 @@
From 7420608acfca1790756fd80d718b737352379dbe Mon Sep 17 00:00:00 2001
From a1566875789469ebd91e472301be4b359aac0a4c Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Tue, 28 May 2024 17:23:21 -0600
Subject: [PATCH 37/38] ec/dell/mec5035: Replace defines with enums
Subject: [PATCH 24/51] ec/dell/mec5035: Replace defines with enums
Instead of using defines for command IDs and argument values, use enums
to provide more type safety. This also has the effect of moving the
@ -87,5 +87,5 @@ index fa15a9d621..32f791cb01 100644
void mec5035_early_init(void);
void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
--
2.47.0
2.39.5

6
config/coreboot/default/patches/0038-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch → config/coreboot/default/patches/0025-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch
View File

@ -1,7 +1,7 @@
From 762f5d95d2314c3d09c1562d36d111dcdb9c8b93 Mon Sep 17 00:00:00 2001
From 2fdd5bbb2bbec76c3c2238c4cd471b9b63073942 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 3 May 2024 11:03:32 -0600
Subject: [PATCH 38/38] ec/dell/mec5035: Add S3 suspend SMI handler
Subject: [PATCH 25/51] ec/dell/mec5035: Add S3 suspend SMI handler
This is necessary for S3 resume to work on SNB and newer Dell Latitude
laptops. If a command isn't sent, the EC cuts power to the DIMMs,
@ -143,5 +143,5 @@ index 0000000000..958733bf97
+ }
+}
--
2.47.0
2.39.5

4
config/coreboot/default/patches/0039-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch → config/coreboot/default/patches/0026-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
View File

@ -1,7 +1,7 @@
From b24c5caf5a8f63555d3b71e7a786c822a4c262cc Mon Sep 17 00:00:00 2001
From ce7d65790b9b8656ebbaa0ca715adff6a9c25588 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 4 May 2024 02:00:53 +0100
Subject: [PATCH 39/65] nb/haswell: lock policy regs when disabling IOMMU
Subject: [PATCH 26/51] nb/haswell: lock policy regs when disabling IOMMU
Angel Pons told me I should do it. See comments here:
https://review.coreboot.org/c/coreboot/+/81016

4
config/coreboot/default/patches/0040-nb-intel-gm45-Make-DDR2-raminit-work.patch → config/coreboot/default/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch
View File

@ -1,7 +1,7 @@
From c41e97f85f2a2677c742d62e3080af7cfeb2ef23 Mon Sep 17 00:00:00 2001
From c6181fe0c8b58cb5a4523d5763fc5fcdf61b3f10 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 10 May 2021 22:40:59 +0200
Subject: [PATCH 40/65] nb/intel/gm45: Make DDR2 raminit work
Subject: [PATCH 27/51] nb/intel/gm45: Make DDR2 raminit work
List of changes:
- Update some timing and ODT values

4
config/coreboot/default/patches/0041-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch → config/coreboot/default/patches/0028-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
View File

@ -1,7 +1,7 @@
From 3110c4392d40175716f167be5ef8234f2b4cd030 Mon Sep 17 00:00:00 2001
From b6f75374fa38e0b097c9eadb4916112707cb6747 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Tue, 6 Aug 2024 00:50:24 +0100
Subject: [PATCH 41/65] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
Subject: [PATCH 28/51] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
We add this patch:

4
config/coreboot/default/patches/0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch → config/coreboot/default/patches/0029-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
View File

@ -1,7 +1,7 @@
From 265fb9f4fd017de635bc44b5a762c69a8bec6158 Mon Sep 17 00:00:00 2001
From d3045b3dcebd94b78df2129cd81a20adf215e46a Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 20 May 2024 10:24:16 -0600
Subject: [PATCH 42/65] mb/dell/e6400: Use 100 MHz reference clock for display
Subject: [PATCH 29/51] mb/dell/e6400: Use 100 MHz reference clock for display
The E6400 uses a 100 MHz reference clock for spread spectrum support on
LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For

29
config/coreboot/default/patches/0029-use-own-mirror-for-acpica-files.patch
View File

@ -1,29 +0,0 @@
From 5b425149a2ba0d1c044c32f5e16ba4d4e59796a8 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Wed, 31 Jul 2024 00:03:02 +0100
Subject: [PATCH 29/65] use own mirror for acpica files
intel likes to break links for no reason,
so we host our own backups of acpica.
Signed-off-by: Leah Rowe <info@minifree.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index ad756652ed..5faff337b4 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -74,7 +74,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://downloadmirror.intel.com/783534"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.5

142
config/coreboot/default/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch
View File

@ -1,142 +0,0 @@
From 253f8eeb895e50b3394b58268594acf9e9596bd2 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 31 Oct 2023 18:24:39 +0000
Subject: [PATCH 30/65] crank up vram allocation on more intel boards
these were added to libreboot, and it's a policy of
libreboot to max out the vram settings. this was
overlooked, in prior revisions and releases.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/e6400/cmos.default | 2 +-
src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +-
src/mainboard/hp/compaq_8200_elite_sff/cmos.default | 2 +-
src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +-
src/mainboard/hp/snb_ivb_laptops/cmos.default | 1 +
src/mainboard/lenovo/t420/cmos.default | 1 +
src/mainboard/lenovo/t420s/cmos.default | 1 +
src/mainboard/lenovo/t430/cmos.default | 1 +
src/mainboard/lenovo/t520/cmos.default | 1 +
src/mainboard/lenovo/t530/cmos.default | 1 +
src/mainboard/lenovo/x201/cmos.default | 1 +
src/mainboard/lenovo/x220/cmos.default | 1 +
12 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
index 744a599708..6b8d478f06 100644
--- a/src/mainboard/dell/e6400/cmos.default
+++ b/src/mainboard/dell/e6400/cmos.default
@@ -4,4 +4,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Disable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=256M
diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default
index 76c16e6a8d..19364aae6e 100644
--- a/src/mainboard/dell/snb_ivb_workstations/cmos.default
+++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default
@@ -5,5 +5,5 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=128M
+gfx_uma_size=224M
fan_full_speed=Disable
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
index 497ae92e1f..64d43a07f7 100644
--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
@@ -5,5 +5,5 @@ debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=224M
psu_fan_lvl=3
diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
index f3dad88670..b60f28447b 100644
--- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
@@ -5,4 +5,4 @@ debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=224M
diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default
index e6042c0c27..a04026b70c 100644
--- a/src/mainboard/hp/snb_ivb_laptops/cmos.default
+++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default
@@ -5,3 +5,4 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
index 27a62d07b3..d1c9fcaaaf 100644
--- a/src/mainboard/lenovo/t420/cmos.default
+++ b/src/mainboard/lenovo/t420/cmos.default
@@ -17,3 +17,4 @@ trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
index 27a62d07b3..d1c9fcaaaf 100644
--- a/src/mainboard/lenovo/t420s/cmos.default
+++ b/src/mainboard/lenovo/t420s/cmos.default
@@ -17,3 +17,4 @@ trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
index 6d1e172056..c00b358314 100644
--- a/src/mainboard/lenovo/t430/cmos.default
+++ b/src/mainboard/lenovo/t430/cmos.default
@@ -18,3 +18,4 @@ backlight=Both
usb_always_on=Disable
hybrid_graphics_mode=Integrated Only
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
index ab1be1a678..c7ee9564f3 100644
--- a/src/mainboard/lenovo/t520/cmos.default
+++ b/src/mainboard/lenovo/t520/cmos.default
@@ -18,3 +18,4 @@ backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
index ab1be1a678..c7ee9564f3 100644
--- a/src/mainboard/lenovo/t530/cmos.default
+++ b/src/mainboard/lenovo/t530/cmos.default
@@ -18,3 +18,4 @@ backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
index 94f8e08a75..a1f2eacf11 100644
--- a/src/mainboard/lenovo/x201/cmos.default
+++ b/src/mainboard/lenovo/x201/cmos.default
@@ -17,3 +17,4 @@ power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
usb_always_on=Disable
+gfx_uma_size=128M
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
index b318ab9772..82292ea5d6 100644
--- a/src/mainboard/lenovo/x220/cmos.default
+++ b/src/mainboard/lenovo/x220/cmos.default
@@ -16,3 +16,4 @@ fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
me_state=Disabled
+gfx_uma_size=224M
--
2.39.5

4
config/coreboot/default/patches/0043-haswell-NRI-Initialise-MPLL.patch → config/coreboot/default/patches/0030-haswell-NRI-Initialise-MPLL.patch
View File

@ -1,7 +1,7 @@
From ab36967cce0593dd17f3018ab4a6661e4219d242 Mon Sep 17 00:00:00 2001
From 0966980e52286985fcd0fac6325bdd99f35ebcb8 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Thu, 11 Apr 2024 17:25:07 +0200
Subject: [PATCH 43/65] haswell NRI: Initialise MPLL
Subject: [PATCH 30/51] haswell NRI: Initialise MPLL
Add code to initialise the MPLL (Memory PLL). The procedure is similar
to the one for Sandy/Ivy Bridge, but it is not worth factoring out.

4
config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch → config/coreboot/default/patches/0031-haswell-NRI-Post-process-selected-timings.patch
View File

@ -1,7 +1,7 @@
From 876011559681881d950ad3b6742b40322f1f5a6d Mon Sep 17 00:00:00 2001
From 1dc22174b9b28b9ea9af59183ffd5d86d19a2721 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 16:29:55 +0200
Subject: [PATCH 44/65] haswell NRI: Post-process selected timings
Subject: [PATCH 31/51] haswell NRI: Post-process selected timings
Once the MPLL has been initialised, convert the timings from the SPD to
be in DCLKs, which is what the hardware expects. In addition, calculate

4
config/coreboot/default/patches/0045-haswell-NRI-Configure-initial-MC-settings.patch → config/coreboot/default/patches/0032-haswell-NRI-Configure-initial-MC-settings.patch
View File

@ -1,7 +1,7 @@
From e91b308fe5848b14cabbd29be4af60e3a9b7938d Mon Sep 17 00:00:00 2001
From a4f5deb78c2d4132bf857c57ffd53684f942ba62 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 17:22:07 +0200
Subject: [PATCH 45/65] haswell NRI: Configure initial MC settings
Subject: [PATCH 32/51] haswell NRI: Configure initial MC settings
Program initial memory controller settings. Many of these values will be
adjusted later during training.

36
config/coreboot/default/patches/0032-use-mirrorservice.org-for-gcc-downloads.patch
View File

@ -1,36 +0,0 @@
From b769a682016b7d231bb3d004698c8a2059bbf363 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 22:57:08 +0000
Subject: [PATCH 32/65] use mirrorservice.org for gcc downloads
the gnu.org 302 redirect often fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 5faff337b4..2743f96903 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -69,11 +69,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
# to the jenkins build as well, or the builder won't download it.
# GCC toolchain archive locations
-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.5

4
config/coreboot/default/patches/0046-haswell-NRI-Add-timings-refresh-programming.patch → config/coreboot/default/patches/0033-haswell-NRI-Add-timings-refresh-programming.patch
View File

@ -1,7 +1,7 @@
From 694d1650cad8573e899916c0d0a25604885f6e3b Mon Sep 17 00:00:00 2001
From 8f94c0428eea2145a97de943b093dee29001c4f9 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 20:59:58 +0200
Subject: [PATCH 46/65] haswell NRI: Add timings/refresh programming
Subject: [PATCH 33/51] haswell NRI: Add timings/refresh programming
Program the registers with timing and refresh parameters.

4
config/coreboot/default/patches/0047-haswell-NRI-Program-memory-map.patch → config/coreboot/default/patches/0034-haswell-NRI-Program-memory-map.patch
View File

@ -1,7 +1,7 @@
From 70d7333e1e0c2b0ce0f2a7e4c4c3ac5c1aca2094 Mon Sep 17 00:00:00 2001
From ded914f236f76715aa43cb439a3de7df9a3dfa11 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 21:24:50 +0200
Subject: [PATCH 47/65] haswell NRI: Program memory map
Subject: [PATCH 34/51] haswell NRI: Program memory map
This is very similar to Sandy/Ivy Bridge, except that there's several
registers to program in GDXCBAR. One of these GDXCBAR registers has a

4
config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch → config/coreboot/default/patches/0035-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch
View File

@ -1,7 +1,7 @@
From cc302630662eee011a903df4fd7a36d82bd22203 Mon Sep 17 00:00:00 2001
From db2b383a8ee5a4fc45c9ce0003ae45f25ed51f86 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 21:49:40 +0200
Subject: [PATCH 48/65] haswell NRI: Add DDR3 JEDEC reset and init
Subject: [PATCH 35/51] haswell NRI: Add DDR3 JEDEC reset and init
Implement JEDEC reset and init sequence for DDR3. The MRS commands are
issued through the REUT (Robust Electrical Unified Testing) hardware.

4
config/coreboot/default/patches/0049-haswell-NRI-Add-pre-training-steps.patch → config/coreboot/default/patches/0036-haswell-NRI-Add-pre-training-steps.patch
View File

@ -1,7 +1,7 @@
From 0f160dee563155e93422fc77c53251419043d4dc Mon Sep 17 00:00:00 2001
From 19bc8d27c8f52b205df218d5917ae67ac4646024 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 23:12:18 +0200
Subject: [PATCH 49/65] haswell NRI: Add pre-training steps
Subject: [PATCH 36/51] haswell NRI: Add pre-training steps
Implement pre-training steps, which consist of enabling ECC I/O and
filling the WDB (Write Data Buffer, stores test patterns) through a

4
config/coreboot/default/patches/0050-haswell-NRI-Add-REUT-I-O-test-library.patch → config/coreboot/default/patches/0037-haswell-NRI-Add-REUT-I-O-test-library.patch
View File

@ -1,7 +1,7 @@
From 78b25eb96baef7da2f5481572a6df2b88ee2b3d4 Mon Sep 17 00:00:00 2001
From 460a092b22c9800c5ee9d8c4198e8b241664693f Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 00:11:29 +0200
Subject: [PATCH 50/65] haswell NRI: Add REUT I/O test library
Subject: [PATCH 37/51] haswell NRI: Add REUT I/O test library
Implement a library to run I/O tests using the REUT hardware.

4
config/coreboot/default/patches/0051-haswell-NRI-Add-range-tracking-library.patch → config/coreboot/default/patches/0038-haswell-NRI-Add-range-tracking-library.patch
View File

@ -1,7 +1,7 @@
From ca6d92e13278832dfddbe7dcb4cbefa5861041e8 Mon Sep 17 00:00:00 2001
From 36b206a88281796458e6ebc30fe34a7c51c86548 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 00:56:00 +0200
Subject: [PATCH 51/65] haswell NRI: Add range tracking library
Subject: [PATCH 38/51] haswell NRI: Add range tracking library
Implement a small library used to keep track of passing ranges. This
will be used by 1D training algorithms when margining some parameter.

4
config/coreboot/default/patches/0052-haswell-NRI-Add-library-to-change-margins.patch → config/coreboot/default/patches/0039-haswell-NRI-Add-library-to-change-margins.patch
View File

@ -1,7 +1,7 @@
From f6d7bd420640a9ccb137113d69b97bc13fe6b0da Mon Sep 17 00:00:00 2001
From 926b1af1033c26ad231587fd3a4506efb4b0d8a3 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 01:11:03 +0200
Subject: [PATCH 52/65] haswell NRI: Add library to change margins
Subject: [PATCH 39/51] haswell NRI: Add library to change margins
Implement a library to change Rx/Tx margins. It will be expanded later.

4
config/coreboot/default/patches/0053-haswell-NRI-Add-RcvEn-training.patch → config/coreboot/default/patches/0040-haswell-NRI-Add-RcvEn-training.patch
View File

@ -1,7 +1,7 @@
From d3cd9ccb7d2eed7ecd5bcdc33d73a5e28b029dba Mon Sep 17 00:00:00 2001
From 61435822eb1d65b919bec45076737ce4ea91e1b1 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 00:05:41 +0200
Subject: [PATCH 53/65] haswell NRI: Add RcvEn training
Subject: [PATCH 40/51] haswell NRI: Add RcvEn training
Implement the RcvEn (Receive Enable) calibration procedure.

4
config/coreboot/default/patches/0054-haswell-NRI-Add-function-to-change-margins.patch → config/coreboot/default/patches/0041-haswell-NRI-Add-function-to-change-margins.patch
View File

@ -1,7 +1,7 @@
From dbf0fc28bbb939fe5a90c991b752f790828d462d Mon Sep 17 00:00:00 2001
From fc6c3edf561dd11eeb2ebe7f4cb93542e664935a Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 11:58:59 +0200
Subject: [PATCH 54/65] haswell NRI: Add function to change margins
Subject: [PATCH 41/51] haswell NRI: Add function to change margins
Implement a function to change margin parameters. Haswell provides a
register to apply an offset to margin parameters during training, so

4
config/coreboot/default/patches/0055-haswell-NRI-Add-read-MPR-training.patch → config/coreboot/default/patches/0042-haswell-NRI-Add-read-MPR-training.patch
View File

@ -1,7 +1,7 @@
From 0a557e3d09a9a53bb085c43e6bdb99fa4cd78b85 Mon Sep 17 00:00:00 2001
From 8f07ea076572dd3371dca7b3dbd5ff9c9b332c55 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 11:35:49 +0200
Subject: [PATCH 55/65] haswell NRI: Add read MPR training
Subject: [PATCH 42/51] haswell NRI: Add read MPR training
Implement read training using DDR3 MPR (Multi-Purpose Register).

4
config/coreboot/default/patches/0056-haswell-NRI-Add-write-leveling.patch → config/coreboot/default/patches/0043-haswell-NRI-Add-write-leveling.patch
View File

@ -1,7 +1,7 @@
From e8f50deac2a671f7ec3958b376c37dd6b9bad5bd Mon Sep 17 00:00:00 2001
From 6df4b7eb0512c24a5f53bc92e81ad6cf42cd28a7 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 12:56:04 +0200
Subject: [PATCH 56/65] haswell NRI: Add write leveling
Subject: [PATCH 43/51] haswell NRI: Add write leveling
Implement JEDEC write leveling, which is done in two steps. The first
step uses the JEDEC procedure to do "fine" write leveling, i.e. align

4
config/coreboot/default/patches/0057-haswell-NRI-Add-final-raminit-steps.patch → config/coreboot/default/patches/0044-haswell-NRI-Add-final-raminit-steps.patch
View File

@ -1,7 +1,7 @@
From 990ee284d48b66f06adb6c43a96439f7628390f5 Mon Sep 17 00:00:00 2001
From 9d1b945702006db5678c5dc81699699bf6e6741a Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 14:29:05 +0200
Subject: [PATCH 57/65] haswell NRI: Add final raminit steps
Subject: [PATCH 44/51] haswell NRI: Add final raminit steps
Implement the remaining raminit steps. Although many training steps are
missing, this is enough to boot on the Asrock B85M Pro4.

4
config/coreboot/default/patches/0058-Haswell-NRI-Implement-fast-boot-path.patch → config/coreboot/default/patches/0045-Haswell-NRI-Implement-fast-boot-path.patch
View File

@ -1,7 +1,7 @@
From 63e9aa1f998ebd41b4c638fa66bdb1a6272a9e85 Mon Sep 17 00:00:00 2001
From b6b89013630d535b68a005cede9e2540f273f4e7 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 13 Apr 2024 01:16:30 +0200
Subject: [PATCH 58/65] Haswell NRI: Implement fast boot path
Subject: [PATCH 45/51] Haswell NRI: Implement fast boot path
When the memory configuration hasn't changed, there is no need to do
full memory training. Instead, boot firmware can use saved training

4
config/coreboot/default/patches/0059-haswell-NRI-Do-sense-amplifier-offset-training.patch → config/coreboot/default/patches/0046-haswell-NRI-Do-sense-amplifier-offset-training.patch
View File

@ -1,7 +1,7 @@
From c22e06a8ef87f74cc9955ffc259e7052742269c4 Mon Sep 17 00:00:00 2001
From 02aa0c5612388e35f5dd1ff9c5f7a7b5b48fb9c0 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 17 Apr 2024 13:20:32 +0200
Subject: [PATCH 59/65] haswell NRI: Do sense amplifier offset training
Subject: [PATCH 46/51] haswell NRI: Do sense amplifier offset training
Quoting Wikipedia:

4
config/coreboot/default/patches/0060-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch → config/coreboot/default/patches/0047-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
View File

@ -1,7 +1,7 @@
From c0e95144b426ab323e0397942579261fbb7b922b Mon Sep 17 00:00:00 2001
From 53f2d47ee6ebaa8d47b076a6c2a1514c91247b95 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Mon, 12 Aug 2024 02:15:24 +0100
Subject: [PATCH 60/65] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
Subject: [PATCH 47/51] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
set it to 96MHz. fixes the following build error when
building for x4x boards e.g. gigabyte ga-g41m-es2l:

4
config/coreboot/default/patches/0062-mb-dell-Convert-E6400-into-a-variant.patch → config/coreboot/default/patches/0048-mb-dell-Convert-E6400-into-a-variant.patch
View File

@ -1,7 +1,7 @@
From 0caa5d97b67b2acf571e4fab2b7f85ef3d3a7260 Mon Sep 17 00:00:00 2001
From 92556743e92cc02524296b653de5241160876218 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Thu, 26 Sep 2024 19:48:26 -0600
Subject: [PATCH 62/65] mb/dell: Convert E6400 into a variant
Subject: [PATCH 48/51] mb/dell: Convert E6400 into a variant
All the GM45 Dell Latitudes should be nearly identical, so convert the
E6400 port into a variant so that future ports for the other systems can

4
config/coreboot/default/patches/0063-mb-dell-gm45_latitudes-Add-E4300-variant.patch → config/coreboot/default/patches/0049-mb-dell-gm45_latitudes-Add-E4300-variant.patch
View File

@ -1,7 +1,7 @@
From bc9836ac2708687dfe43656adba2833493fa4199 Mon Sep 17 00:00:00 2001
From ac8ac2543e3ebbc05f79f37d1460cde532a7ee1c Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Thu, 26 Sep 2024 19:51:25 -0600
Subject: [PATCH 63/65] mb/dell/gm45_latitudes: Add E4300 variant
Subject: [PATCH 49/51] mb/dell/gm45_latitudes: Add E4300 variant
Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>

6
config/coreboot/default/patches/0066-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch → config/coreboot/default/patches/0050-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
View File

@ -1,7 +1,7 @@
From 0fe1d4b9fe56a0f27a6ff39cfb94d63559b729b8 Mon Sep 17 00:00:00 2001
From 5e8b899654c31fe771e4b1e96c74c93d4509c3b2 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 3 May 2024 16:31:12 -0600
Subject: [PATCH 66/67] mb/dell: Add S3 SMI handler for Dell Latitudes
Subject: [PATCH 50/51] mb/dell: Add S3 SMI handler for Dell Latitudes
Integrate the previously added mec5035_smi_sleep() function into
mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
@ -66,5 +66,5 @@ index 0000000000..00e55b51db
+ mec5035_smi_sleep(slp_typ);
+}
--
2.47.0
2.39.5

6
config/coreboot/default/patches/0067-ec-dell-mec5035-Route-power-button-event-to-host.patch → config/coreboot/default/patches/0051-ec-dell-mec5035-Route-power-button-event-to-host.patch
View File

@ -1,7 +1,7 @@
From 32118fa1d21fad517f85cee5eb4edff5f2fd91ea Mon Sep 17 00:00:00 2001
From 1a342c20b8705bbea02d27a73e383ee2808f2558 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Tue, 18 Jun 2024 21:31:08 -0600
Subject: [PATCH 67/67] ec/dell/mec5035: Route power button event to host
Subject: [PATCH 51/51] ec/dell/mec5035: Route power button event to host
If command 0x3e with an argument of 1 isn't sent to the EC, pressing the
power button results in the EC powering off the system without letting
@ -88,5 +88,5 @@ index 8d4fded28b..51422598c4 100644
void mec5035_sleep_enable(void);
--
2.47.0
2.39.5