Merge pull request 'config: Add Dell Latitude E5420' (#191) from nic3-14159/lbmk:latitude-ports into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/1919020nri
Leah Rowe
commit
6b11f1b055
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@ -0,0 +1,774 @@
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From 7dd58c8b301404a8bafee25a1e97a8a5d614b3d6 Mon Sep 17 00:00:00 2001
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From: Nicholas Chin <nic.c3.14@gmail.com>
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Date: Mon, 4 Mar 2024 18:05:43 -0700
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Subject: [PATCH] mb/dell: Add Latitude E5420 (Sandy Bridge)
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---
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src/mainboard/dell/e5420/Kconfig | 37 ++++
|
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src/mainboard/dell/e5420/Kconfig.name | 2 +
|
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src/mainboard/dell/e5420/Makefile.mk | 5 +
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src/mainboard/dell/e5420/acpi/ec.asl | 9 +
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src/mainboard/dell/e5420/acpi/platform.asl | 12 ++
|
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src/mainboard/dell/e5420/acpi/superio.asl | 3 +
|
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src/mainboard/dell/e5420/acpi_tables.c | 16 ++
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src/mainboard/dell/e5420/board_info.txt | 6 +
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src/mainboard/dell/e5420/cmos.default | 9 +
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src/mainboard/dell/e5420/cmos.layout | 88 ++++++++++
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src/mainboard/dell/e5420/data.vbt | Bin 0 -> 6144 bytes
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src/mainboard/dell/e5420/devicetree.cb | 66 +++++++
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src/mainboard/dell/e5420/dsdt.asl | 30 ++++
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src/mainboard/dell/e5420/early_init.c | 32 ++++
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src/mainboard/dell/e5420/gma-mainboard.ads | 20 +++
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src/mainboard/dell/e5420/gpio.c | 195 +++++++++++++++++++++
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src/mainboard/dell/e5420/hda_verb.c | 33 ++++
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src/mainboard/dell/e5420/mainboard.c | 21 +++
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18 files changed, 584 insertions(+)
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create mode 100644 src/mainboard/dell/e5420/Kconfig
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create mode 100644 src/mainboard/dell/e5420/Kconfig.name
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create mode 100644 src/mainboard/dell/e5420/Makefile.mk
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|
create mode 100644 src/mainboard/dell/e5420/acpi/ec.asl
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create mode 100644 src/mainboard/dell/e5420/acpi/platform.asl
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create mode 100644 src/mainboard/dell/e5420/acpi/superio.asl
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|
create mode 100644 src/mainboard/dell/e5420/acpi_tables.c
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create mode 100644 src/mainboard/dell/e5420/board_info.txt
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create mode 100644 src/mainboard/dell/e5420/cmos.default
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create mode 100644 src/mainboard/dell/e5420/cmos.layout
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create mode 100755 src/mainboard/dell/e5420/data.vbt
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create mode 100644 src/mainboard/dell/e5420/devicetree.cb
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create mode 100644 src/mainboard/dell/e5420/dsdt.asl
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create mode 100644 src/mainboard/dell/e5420/early_init.c
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create mode 100644 src/mainboard/dell/e5420/gma-mainboard.ads
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create mode 100644 src/mainboard/dell/e5420/gpio.c
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create mode 100644 src/mainboard/dell/e5420/hda_verb.c
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create mode 100644 src/mainboard/dell/e5420/mainboard.c
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diff --git a/src/mainboard/dell/e5420/Kconfig b/src/mainboard/dell/e5420/Kconfig
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new file mode 100644
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index 0000000000..f4385045ae
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--- /dev/null
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+++ b/src/mainboard/dell/e5420/Kconfig
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@@ -0,0 +1,37 @@
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+if BOARD_DELL_LATITUDE_E5420
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+
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+config BOARD_SPECIFIC_OPTIONS
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+ def_bool y
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+ select BOARD_ROMSIZE_KB_6144
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+ select EC_ACPI
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+ select EC_DELL_MEC5035
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+ select GFX_GMA_PANEL_1_ON_LVDS
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+ select HAVE_ACPI_RESUME
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+ select HAVE_ACPI_TABLES
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+ select HAVE_CMOS_DEFAULT
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+ select HAVE_OPTION_TABLE
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+ select INTEL_GMA_HAVE_VBT
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+ select INTEL_INT15
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+ select MAINBOARD_HAS_LIBGFXINIT
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+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
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+ select SERIRQ_CONTINUOUS_MODE
|
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+ select SOUTHBRIDGE_INTEL_BD82X6X
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+ select SYSTEM_TYPE_LAPTOP
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+ select USE_NATIVE_RAMINIT
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+
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+config DRAM_RESET_GATE_GPIO
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+ default 60
|
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+
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+config MAINBOARD_DIR
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+ default "dell/e5420"
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+
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+config MAINBOARD_PART_NUMBER
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+ default "Latitude E5420"
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+
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+config USBDEBUG_HCD_INDEX
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+ default 2
|
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+
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+config VGA_BIOS_ID
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+ default "8086,0116"
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+
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+endif # BOARD_DELL_LATITUDE_E5420
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diff --git a/src/mainboard/dell/e5420/Kconfig.name b/src/mainboard/dell/e5420/Kconfig.name
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new file mode 100644
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index 0000000000..eb495fb705
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--- /dev/null
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+++ b/src/mainboard/dell/e5420/Kconfig.name
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@@ -0,0 +1,2 @@
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+config BOARD_DELL_LATITUDE_E5420
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+ bool "Latitude E5420"
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diff --git a/src/mainboard/dell/e5420/Makefile.mk b/src/mainboard/dell/e5420/Makefile.mk
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new file mode 100644
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index 0000000000..18391d8b18
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--- /dev/null
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+++ b/src/mainboard/dell/e5420/Makefile.mk
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@@ -0,0 +1,5 @@
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+bootblock-y += early_init.c
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+bootblock-y += gpio.c
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+romstage-y += early_init.c
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+romstage-y += gpio.c
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+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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diff --git a/src/mainboard/dell/e5420/acpi/ec.asl b/src/mainboard/dell/e5420/acpi/ec.asl
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new file mode 100644
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index 0000000000..0d429410a9
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|
--- /dev/null
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|
+++ b/src/mainboard/dell/e5420/acpi/ec.asl
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@@ -0,0 +1,9 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+Device(EC)
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+{
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+ Name (_HID, EISAID("PNP0C09"))
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+ Name (_UID, 0)
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+ Name (_GPE, 16)
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|
+/* FIXME: EC support */
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+}
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diff --git a/src/mainboard/dell/e5420/acpi/platform.asl b/src/mainboard/dell/e5420/acpi/platform.asl
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new file mode 100644
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||||||
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index 0000000000..2d24bbd9b9
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||||||
|
--- /dev/null
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||||||
|
+++ b/src/mainboard/dell/e5420/acpi/platform.asl
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@@ -0,0 +1,12 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+Method(_WAK, 1)
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+{
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+ /* FIXME: EC support */
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+ Return(Package() {0, 0})
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+}
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+
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||||||
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+Method(_PTS,1)
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+{
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+ /* FIXME: EC support */
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+}
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diff --git a/src/mainboard/dell/e5420/acpi/superio.asl b/src/mainboard/dell/e5420/acpi/superio.asl
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new file mode 100644
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||||||
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index 0000000000..55b1db5b11
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||||||
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--- /dev/null
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||||||
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+++ b/src/mainboard/dell/e5420/acpi/superio.asl
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@@ -0,0 +1,3 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+#include <drivers/pc80/pc/ps2_controller.asl>
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diff --git a/src/mainboard/dell/e5420/acpi_tables.c b/src/mainboard/dell/e5420/acpi_tables.c
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new file mode 100644
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index 0000000000..e2759659bf
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--- /dev/null
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+++ b/src/mainboard/dell/e5420/acpi_tables.c
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@@ -0,0 +1,16 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+#include <acpi/acpi_gnvs.h>
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+#include <soc/nvs.h>
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+
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+/* FIXME: check this function. */
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+void mainboard_fill_gnvs(struct global_nvs *gnvs)
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+{
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+ /* The lid is open by default. */
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+ gnvs->lids = 1;
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+
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+ /* Temperature at which OS will shutdown */
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|
+ gnvs->tcrt = 100;
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|
+ /* Temperature at which OS will throttle CPU */
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+ gnvs->tpsv = 90;
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+}
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diff --git a/src/mainboard/dell/e5420/board_info.txt b/src/mainboard/dell/e5420/board_info.txt
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new file mode 100644
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||||||
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index 0000000000..34d5ad9e0b
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||||||
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--- /dev/null
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+++ b/src/mainboard/dell/e5420/board_info.txt
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@@ -0,0 +1,6 @@
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+Category: laptop
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+ROM package: SOIC-8
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|
+ROM protocol: SPI
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|
+ROM socketed: n
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||||||
|
+Flashrom support: y
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|
+Release year: 2011
|
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|
diff --git a/src/mainboard/dell/e5420/cmos.default b/src/mainboard/dell/e5420/cmos.default
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new file mode 100644
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||||||
|
index 0000000000..279415dfd1
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||||||
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--- /dev/null
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||||||
|
+++ b/src/mainboard/dell/e5420/cmos.default
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||||||
|
@@ -0,0 +1,9 @@
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||||||
|
+boot_option=Fallback
|
||||||
|
+debug_level=Debug
|
||||||
|
+power_on_after_fail=Disable
|
||||||
|
+nmi=Enable
|
||||||
|
+bluetooth=Enable
|
||||||
|
+wwan=Enable
|
||||||
|
+wlan=Enable
|
||||||
|
+sata_mode=AHCI
|
||||||
|
+me_state=Disabled
|
||||||
|
diff --git a/src/mainboard/dell/e5420/cmos.layout b/src/mainboard/dell/e5420/cmos.layout
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000000..1aa7e77bce
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/src/mainboard/dell/e5420/cmos.layout
|
||||||
|
@@ -0,0 +1,88 @@
|
||||||
|
+## SPDX-License-Identifier: GPL-2.0-only
|
||||||
|
+
|
||||||
|
+# -----------------------------------------------------------------
|
||||||
|
+entries
|
||||||
|
+
|
||||||
|
+# -----------------------------------------------------------------
|
||||||
|
+0 120 r 0 reserved_memory
|
||||||
|
+
|
||||||
|
+# -----------------------------------------------------------------
|
||||||
|
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
|
+384 1 e 4 boot_option
|
||||||
|
+388 4 h 0 reboot_counter
|
||||||
|
+
|
||||||
|
+# -----------------------------------------------------------------
|
||||||
|
+# coreboot config options: console
|
||||||
|
+395 4 e 6 debug_level
|
||||||
|
+
|
||||||
|
+#400 8 r 0 reserved for century byte
|
||||||
|
+
|
||||||
|
+# coreboot config options: southbridge
|
||||||
|
+408 1 e 1 nmi
|
||||||
|
+409 2 e 7 power_on_after_fail
|
||||||
|
+411 1 e 9 sata_mode
|
||||||
|
+
|
||||||
|
+# coreboot config options: EC
|
||||||
|
+412 1 e 1 bluetooth
|
||||||
|
+413 1 e 1 wwan
|
||||||
|
+414 1 e 1 wlan
|
||||||
|
+
|
||||||
|
+# coreboot config options: ME
|
||||||
|
+424 1 e 14 me_state
|
||||||
|
+425 2 h 0 me_state_prev
|
||||||
|
+
|
||||||
|
+# coreboot config options: northbridge
|
||||||
|
+432 3 e 11 gfx_uma_size
|
||||||
|
+435 2 e 12 hybrid_graphics_mode
|
||||||
|
+440 8 h 0 volume
|
||||||
|
+
|
||||||
|
+# VBOOT
|
||||||
|
+448 128 r 0 vbnv
|
||||||
|
+
|
||||||
|
+# SandyBridge MRC Scrambler Seed values
|
||||||
|
+896 32 r 0 mrc_scrambler_seed
|
||||||
|
+928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
+960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
+
|
||||||
|
+# coreboot config options: check sums
|
||||||
|
+984 16 h 0 check_sum
|
||||||
|
+
|
||||||
|
+# -----------------------------------------------------------------
|
||||||
|
+
|
||||||
|
+enumerations
|
||||||
|
+
|
||||||
|
+#ID value text
|
||||||
|
+1 0 Disable
|
||||||
|
+1 1 Enable
|
||||||
|
+2 0 Enable
|
||||||
|
+2 1 Disable
|
||||||
|
+4 0 Fallback
|
||||||
|
+4 1 Normal
|
||||||
|
+6 0 Emergency
|
||||||
|
+6 1 Alert
|
||||||
|
+6 2 Critical
|
||||||
|
+6 3 Error
|
||||||
|
+6 4 Warning
|
||||||
|
+6 5 Notice
|
||||||
|
+6 6 Info
|
||||||
|
+6 7 Debug
|
||||||
|
+6 8 Spew
|
||||||
|
+7 0 Disable
|
||||||
|
+7 1 Enable
|
||||||
|
+7 2 Keep
|
||||||
|
+9 0 AHCI
|
||||||
|
+9 1 Compatible
|
||||||
|
+11 0 32M
|
||||||
|
+11 1 64M
|
||||||
|
+11 2 96M
|
||||||
|
+11 3 128M
|
||||||
|
+11 4 160M
|
||||||
|
+11 5 192M
|
||||||
|
+11 6 224M
|
||||||
|
+14 0 Normal
|
||||||
|
+14 1 Disabled
|
||||||
|
+
|
||||||
|
+# -----------------------------------------------------------------
|
||||||
|
+checksums
|
||||||
|
+
|
||||||
|
+checksum 392 447 984
|
||||||
|
diff --git a/src/mainboard/dell/e5420/data.vbt b/src/mainboard/dell/e5420/data.vbt
|
||||||
|
new file mode 100755
|
||||||
|
index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57
|
||||||
|
GIT binary patch
|
||||||
|
literal 6144
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
zR<5aEfv-b8M00Lk251!oO|8(YA6XaeXzkt-Z)@Ee!_{@z#Fro^?DqN4SGjRIu8KYp
|
||||||
|
zZEufuU@5MM@7jv%h;75FS}ezKv?JDzCH}d%tE)A-GuDb*+B%}~w%88r>}c;!*XQ5O
|
||||||
|
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||||||
|
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||||||
|
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||||||
|
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|
||||||
|
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||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
z#u>ACcP}M4exU`*MKVwl5+t6JBpTkmm}xWflKUe~7}`!#%z#gAo{NxUrpDAndYktu
|
||||||
|
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|
||||||
|
z=%+18z`-fT%z)9-TS$~Dh@2yeN7!UIt0h`fWxUu`JvA_ra*8P48l%7KR0&c1;0R75
|
||||||
|
z4f0oz(xQ3MWqz5>qW5M4tZWExHs8<H(e1G@4km@5wEzOOP^x<l`YmA|eKs6j3wl8B
|
||||||
|
z%C%;uygh%<#kGZ{fymL+OlV0!-*T!V5IB>X@p!@CBU=7e{5^Jl{s7by`po-AJqM2l
|
||||||
|
znk(=^0bHkF0rUw7)^7j;$=_UIs8`6P6b-;vPDZ#U9L)W1_PAYRDP9k~;5$stt5ZiV
|
||||||
|
zD0>;i-?OlYY2}P9WVnfGos4xee2r=EGWHR}ADH$VV>cO=xU?!4TjIi)OMBYI_PX#b
|
||||||
|
zm-eBHed5BOT-x6*W>;{IqAga~G6lCQT93k>Q}CpsomJR*1%FjEkv?fuT%c-8RklXO
|
||||||
|
zU8;6KWk*zeU)4TW+1D!mrE0EhHZfbBeN{4S7X@Pig%};A99QTdA~wZruL*8y?K!jP
|
||||||
|
zG5R*k=);S}Zn<T;W!Mxt`(!+z7_r@3LVpf|FESauM&4}+wqzXfba-zG>A}on(uzNF
|
||||||
|
zyu>BcjA})C@bg%<;+Eh2;Sz4heFFCbZ@C{FrXMIbYzu>?Bi-|vZ}JSFU%JA>7$7et
|
||||||
|
z0Yo%CnOVZm#ZA}4kWZOn15};h5*#OM3b+6vHzgruMP>=5MNJK1y42{YgveP-!j%#(
|
||||||
|
z0rGe@8t%!=66Ti%K4|Gx=o7gFp83wQ;+s3H7+r^SKlpp3KKcr!3@|n;NCH_=qL=3T
|
||||||
|
zq3WH?en`b+W-HR-fnrhw*9aZ%M}lHX7@H?E>!6wv_&YQFEHdA$%Z1R--yub>=c@p?
|
||||||
|
z6@7Fc$&>sAxwiz{BE$1kb$K9Co=ozlA973y^i(^BM|EZ$$^y`0KyHiMJ%O*XbfEX1
|
||||||
|
ziZaH>W(1pWL0bo|T!x__N$^$DpmxI=bL6WUK3JGyn?rw-qC4ZA$yGjIB}N(=ldD2O
|
||||||
|
zAJ@bxp<qR-3lIv<!P~SE8r*#_Ckl?$0|1fZ>2>n}u*mUIYFd>}O_wuwBD^r9<#=!0
|
||||||
|
X1LGbT_rSOZ#yv3ZfpHH!G!Og(1Xg~J
|
||||||
|
|
||||||
|
literal 0
|
||||||
|
HcmV?d00001
|
||||||
|
|
||||||
|
diff --git a/src/mainboard/dell/e5420/devicetree.cb b/src/mainboard/dell/e5420/devicetree.cb
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000000..f26413557d
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/src/mainboard/dell/e5420/devicetree.cb
|
||||||
|
@@ -0,0 +1,66 @@
|
||||||
|
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||||
|
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
|
||||||
|
+ register "gpu_cpu_backlight" = "0x00000c31"
|
||||||
|
+ register "gpu_dp_b_hotplug" = "4"
|
||||||
|
+ register "gpu_dp_c_hotplug" = "4"
|
||||||
|
+ register "gpu_dp_d_hotplug" = "4"
|
||||||
|
+ register "gpu_panel_port_select" = "0"
|
||||||
|
+ register "gpu_panel_power_backlight_off_delay" = "2300"
|
||||||
|
+ register "gpu_panel_power_backlight_on_delay" = "2300"
|
||||||
|
+ register "gpu_panel_power_cycle_delay" = "6"
|
||||||
|
+ register "gpu_panel_power_down_delay" = "400"
|
||||||
|
+ register "gpu_panel_power_up_delay" = "400"
|
||||||
|
+ register "gpu_pch_backlight" = "0x13121312"
|
||||||
|
+
|
||||||
|
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
|
||||||
|
+
|
||||||
|
+ device domain 0x0 on
|
||||||
|
+ subsystemid 0x1028 0x049b inherit
|
||||||
|
+
|
||||||
|
+ device ref host_bridge on end # Host bridge
|
||||||
|
+ device ref peg10 on end # PEG
|
||||||
|
+ device ref igd on end # iGPU
|
||||||
|
+
|
||||||
|
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||||
|
+ register "docking_supported" = "1"
|
||||||
|
+ register "gen1_dec" = "0x007c0681"
|
||||||
|
+ register "gen2_dec" = "0x007c0901"
|
||||||
|
+ register "gen3_dec" = "0x003c07e1"
|
||||||
|
+ register "gen4_dec" = "0x001c0901"
|
||||||
|
+ register "gpi0_routing" = "2"
|
||||||
|
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
|
||||||
|
+ register "pcie_port_coalesce" = "1"
|
||||||
|
+ register "sata_interface_speed_support" = "0x3"
|
||||||
|
+ register "sata_port_map" = "0x3b"
|
||||||
|
+ register "spi_lvscc" = "0x2005"
|
||||||
|
+ register "spi_uvscc" = "0x2005"
|
||||||
|
+
|
||||||
|
+ device ref mei1 off end
|
||||||
|
+ device ref mei2 off end
|
||||||
|
+ device ref me_ide_r off end
|
||||||
|
+ device ref me_kt off end
|
||||||
|
+ device ref gbe off end
|
||||||
|
+ device ref ehci2 on end
|
||||||
|
+ device ref hda on end
|
||||||
|
+ device ref pcie_rp1 on end
|
||||||
|
+ device ref pcie_rp2 on end
|
||||||
|
+ device ref pcie_rp3 on end
|
||||||
|
+ device ref pcie_rp4 off end
|
||||||
|
+ device ref pcie_rp5 on end
|
||||||
|
+ device ref pcie_rp6 on end
|
||||||
|
+ device ref pcie_rp7 on end
|
||||||
|
+ device ref pcie_rp8 off end
|
||||||
|
+ device ref ehci1 on end
|
||||||
|
+ device ref pci_bridge off end
|
||||||
|
+ device ref lpc on
|
||||||
|
+ chip ec/dell/mec5035
|
||||||
|
+ device pnp ff.0 on end
|
||||||
|
+ end
|
||||||
|
+ end
|
||||||
|
+ device ref sata1 on end
|
||||||
|
+ device ref smbus on end
|
||||||
|
+ device ref sata2 off end
|
||||||
|
+ device ref thermal off end
|
||||||
|
+ end
|
||||||
|
+ end
|
||||||
|
+end
|
||||||
|
diff --git a/src/mainboard/dell/e5420/dsdt.asl b/src/mainboard/dell/e5420/dsdt.asl
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000000..7d13c55b08
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/src/mainboard/dell/e5420/dsdt.asl
|
||||||
|
@@ -0,0 +1,30 @@
|
||||||
|
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
||||||
|
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||||
|
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+#include <acpi/acpi.h>
|
||||||
|
+
|
||||||
|
+DefinitionBlock(
|
||||||
|
+ "dsdt.aml",
|
||||||
|
+ "DSDT",
|
||||||
|
+ ACPI_DSDT_REV_2,
|
||||||
|
+ OEM_ID,
|
||||||
|
+ ACPI_TABLE_CREATOR,
|
||||||
|
+ 0x20141018 /* OEM revision */
|
||||||
|
+)
|
||||||
|
+{
|
||||||
|
+ #include <acpi/dsdt_top.asl>
|
||||||
|
+ #include "acpi/platform.asl"
|
||||||
|
+ #include <cpu/intel/common/acpi/cpu.asl>
|
||||||
|
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||||
|
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||||
|
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||||
|
+
|
||||||
|
+ Device (\_SB.PCI0)
|
||||||
|
+ {
|
||||||
|
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||||
|
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||||
|
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||||
|
+ }
|
||||||
|
+}
|
||||||
|
diff --git a/src/mainboard/dell/e5420/early_init.c b/src/mainboard/dell/e5420/early_init.c
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000000..7297921546
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/src/mainboard/dell/e5420/early_init.c
|
||||||
|
@@ -0,0 +1,32 @@
|
||||||
|
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+#include <bootblock_common.h>
|
||||||
|
+#include <device/pci_ops.h>
|
||||||
|
+#include <ec/dell/mec5035/mec5035.h>
|
||||||
|
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||||
|
+
|
||||||
|
+const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||||
|
+ { 1, 1, 0 },
|
||||||
|
+ { 1, 1, 0 },
|
||||||
|
+ { 1, 1, 1 },
|
||||||
|
+ { 1, 1, 1 },
|
||||||
|
+ { 1, 1, 2 },
|
||||||
|
+ { 1, 1, 2 },
|
||||||
|
+ { 1, 1, 3 },
|
||||||
|
+ { 1, 1, 3 },
|
||||||
|
+ { 1, 1, 5 },
|
||||||
|
+ { 1, 1, 5 },
|
||||||
|
+ { 1, 1, 7 },
|
||||||
|
+ { 1, 1, 6 },
|
||||||
|
+ { 1, 1, 6 },
|
||||||
|
+ { 1, 1, 7 },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+void bootblock_mainboard_early_init(void)
|
||||||
|
+{
|
||||||
|
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
|
||||||
|
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
|
||||||
|
+ | COMB_LPC_EN | COMA_LPC_EN);
|
||||||
|
+ mec5035_early_init();
|
||||||
|
+}
|
||||||
|
diff --git a/src/mainboard/dell/e5420/gma-mainboard.ads b/src/mainboard/dell/e5420/gma-mainboard.ads
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000000..2a16f44360
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/src/mainboard/dell/e5420/gma-mainboard.ads
|
||||||
|
@@ -0,0 +1,20 @@
|
||||||
|
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
+
|
||||||
|
+with HW.GFX.GMA;
|
||||||
|
+with HW.GFX.GMA.Display_Probing;
|
||||||
|
+
|
||||||
|
+use HW.GFX.GMA;
|
||||||
|
+use HW.GFX.GMA.Display_Probing;
|
||||||
|
+
|
||||||
|
+private package GMA.Mainboard is
|
||||||
|
+
|
||||||
|
+ ports : constant Port_List :=
|
||||||
|
+ (
|
||||||
|
+ HDMI1, -- mainboard HDMI
|
||||||
|
+ DP2, -- dock DP
|
||||||
|
+ DP3, -- dock DP
|
||||||
|
+ Analog, -- mainboard VGA
|
||||||
|
+ LVDS,
|
||||||
|
+ others => Disabled);
|
||||||
|
+
|
||||||
|
+end GMA.Mainboard;
|
||||||
|
diff --git a/src/mainboard/dell/e5420/gpio.c b/src/mainboard/dell/e5420/gpio.c
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000000..f76b93d9f0
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/src/mainboard/dell/e5420/gpio.c
|
||||||
|
@@ -0,0 +1,195 @@
|
||||||
|
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
+
|
||||||
|
+#include <southbridge/intel/common/gpio.h>
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||||
|
+ .gpio0 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio1 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio2 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio3 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio4 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio5 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio6 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio7 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio8 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio9 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio10 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio11 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio12 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio13 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio14 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio15 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio16 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio17 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio18 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio19 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio20 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio21 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio22 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio24 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio27 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio28 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio29 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio30 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio31 = GPIO_MODE_NATIVE,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||||
|
+ .gpio0 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio2 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio3 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio4 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio6 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio7 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio8 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio12 = GPIO_DIR_OUTPUT,
|
||||||
|
+ .gpio13 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio14 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio15 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio17 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio19 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio21 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio22 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio24 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio27 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio28 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio29 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio30 = GPIO_DIR_OUTPUT,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||||
|
+ .gpio12 = GPIO_LEVEL_HIGH,
|
||||||
|
+ .gpio30 = GPIO_LEVEL_HIGH,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||||
|
+ .gpio0 = GPIO_INVERT,
|
||||||
|
+ .gpio8 = GPIO_INVERT,
|
||||||
|
+ .gpio14 = GPIO_INVERT,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||||
|
+ .gpio32 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio33 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio34 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio35 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio36 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio37 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio38 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio39 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio45 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio46 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio48 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio49 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio50 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio51 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio52 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio53 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio54 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio55 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio56 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio57 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio60 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio61 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||||
|
+ .gpio33 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio34 = GPIO_DIR_OUTPUT,
|
||||||
|
+ .gpio35 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio36 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio37 = GPIO_DIR_OUTPUT,
|
||||||
|
+ .gpio38 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio39 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio46 = GPIO_DIR_OUTPUT,
|
||||||
|
+ .gpio48 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio50 = GPIO_DIR_OUTPUT,
|
||||||
|
+ .gpio51 = GPIO_DIR_OUTPUT,
|
||||||
|
+ .gpio52 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio53 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio54 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio55 = GPIO_DIR_OUTPUT,
|
||||||
|
+ .gpio56 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio57 = GPIO_DIR_INPUT,
|
||||||
|
+ .gpio60 = GPIO_DIR_OUTPUT,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||||
|
+ .gpio34 = GPIO_LEVEL_LOW,
|
||||||
|
+ .gpio37 = GPIO_LEVEL_LOW,
|
||||||
|
+ .gpio46 = GPIO_LEVEL_HIGH,
|
||||||
|
+ .gpio50 = GPIO_LEVEL_HIGH,
|
||||||
|
+ .gpio51 = GPIO_LEVEL_LOW,
|
||||||
|
+ .gpio55 = GPIO_LEVEL_LOW,
|
||||||
|
+ .gpio60 = GPIO_LEVEL_HIGH,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||||
|
+ .gpio64 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio66 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio68 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio69 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio70 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio71 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio72 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio73 = GPIO_MODE_NATIVE,
|
||||||
|
+ .gpio74 = GPIO_MODE_GPIO,
|
||||||
|
+ .gpio75 = GPIO_MODE_NATIVE,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||||
|
+ .gpio74 = GPIO_DIR_INPUT,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||||
|
+ .set1 = {
|
||||||
|
+ .mode = &pch_gpio_set1_mode,
|
||||||
|
+ .direction = &pch_gpio_set1_direction,
|
||||||
|
+ .level = &pch_gpio_set1_level,
|
||||||
|
+ .blink = &pch_gpio_set1_blink,
|
||||||
|
+ .invert = &pch_gpio_set1_invert,
|
||||||
|
+ .reset = &pch_gpio_set1_reset,
|
||||||
|
+ },
|
||||||
|
+ .set2 = {
|
||||||
|
+ .mode = &pch_gpio_set2_mode,
|
||||||
|
+ .direction = &pch_gpio_set2_direction,
|
||||||
|
+ .level = &pch_gpio_set2_level,
|
||||||
|
+ .reset = &pch_gpio_set2_reset,
|
||||||
|
+ },
|
||||||
|
+ .set3 = {
|
||||||
|
+ .mode = &pch_gpio_set3_mode,
|
||||||
|
+ .direction = &pch_gpio_set3_direction,
|
||||||
|
+ .level = &pch_gpio_set3_level,
|
||||||
|
+ .reset = &pch_gpio_set3_reset,
|
||||||
|
+ },
|
||||||
|
+};
|
||||||
|
diff --git a/src/mainboard/dell/e5420/hda_verb.c b/src/mainboard/dell/e5420/hda_verb.c
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000000..70e7c2e79a
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/src/mainboard/dell/e5420/hda_verb.c
|
||||||
|
@@ -0,0 +1,33 @@
|
||||||
|
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
+
|
||||||
|
+#include <device/azalia_device.h>
|
||||||
|
+
|
||||||
|
+const u32 cim_verb_data[] = {
|
||||||
|
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
|
||||||
|
+ 0x1028049b, /* Subsystem ID */
|
||||||
|
+ 11, /* Number of 4 dword sets */
|
||||||
|
+ AZALIA_SUBVENDOR(0, 0x1028049b),
|
||||||
|
+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
|
||||||
|
+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
|
||||||
|
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
|
||||||
|
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
||||||
|
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
|
||||||
|
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
|
||||||
|
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
|
||||||
|
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
|
||||||
|
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
|
||||||
|
+ AZALIA_PIN_CFG(0, 0x20, 0xd5a30130),
|
||||||
|
+
|
||||||
|
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
|
||||||
|
+ 0x80860101, /* Subsystem ID */
|
||||||
|
+ 4, /* Number of 4 dword sets */
|
||||||
|
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
||||||
|
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
||||||
|
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||||
|
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||||
|
+
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+const u32 pc_beep_verbs[0] = {};
|
||||||
|
+
|
||||||
|
+AZALIA_ARRAY_SIZES;
|
||||||
|
diff --git a/src/mainboard/dell/e5420/mainboard.c b/src/mainboard/dell/e5420/mainboard.c
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000000..31e49802fc
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/src/mainboard/dell/e5420/mainboard.c
|
||||||
|
@@ -0,0 +1,21 @@
|
||||||
|
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
+
|
||||||
|
+#include <device/device.h>
|
||||||
|
+#include <drivers/intel/gma/int15.h>
|
||||||
|
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||||
|
+#include <ec/acpi/ec.h>
|
||||||
|
+#include <console/console.h>
|
||||||
|
+#include <pc80/keyboard.h>
|
||||||
|
+
|
||||||
|
+static void mainboard_enable(struct device *dev)
|
||||||
|
+{
|
||||||
|
+
|
||||||
|
+ /* FIXME: fix these values. */
|
||||||
|
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||||
|
+ GMA_INT15_PANEL_FIT_DEFAULT,
|
||||||
|
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+struct chip_operations mainboard_ops = {
|
||||||
|
+ .enable_dev = mainboard_enable,
|
||||||
|
+};
|
||||||
|
--
|
||||||
|
2.44.0
|
||||||
|
|
||||||
|
|
@ -135,6 +135,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -133,6 +133,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -135,6 +135,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -133,6 +133,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,620 @@
|
||||||
|
#
|
||||||
|
# Automatically generated file; DO NOT EDIT.
|
||||||
|
# coreboot configuration
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# General setup
|
||||||
|
#
|
||||||
|
CONFIG_COREBOOT_BUILD=y
|
||||||
|
CONFIG_LOCALVERSION=""
|
||||||
|
CONFIG_CBFS_PREFIX="fallback"
|
||||||
|
CONFIG_COMPILER_GCC=y
|
||||||
|
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||||
|
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||||
|
# CONFIG_ANY_TOOLCHAIN is not set
|
||||||
|
# CONFIG_CCACHE is not set
|
||||||
|
# CONFIG_IWYU is not set
|
||||||
|
# CONFIG_FMD_GENPARSER is not set
|
||||||
|
# CONFIG_UTIL_GENPARSER is not set
|
||||||
|
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||||
|
CONFIG_USE_OPTION_TABLE=y
|
||||||
|
CONFIG_STATIC_OPTION_TABLE=y
|
||||||
|
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||||
|
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||||
|
CONFIG_SEPARATE_ROMSTAGE=y
|
||||||
|
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||||
|
CONFIG_COLLECT_TIMESTAMPS=y
|
||||||
|
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||||
|
CONFIG_USE_BLOBS=y
|
||||||
|
# CONFIG_USE_AMD_BLOBS is not set
|
||||||
|
# CONFIG_USE_QC_BLOBS is not set
|
||||||
|
# CONFIG_COVERAGE is not set
|
||||||
|
# CONFIG_UBSAN is not set
|
||||||
|
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||||
|
# CONFIG_ASAN is not set
|
||||||
|
CONFIG_NO_STAGE_CACHE=y
|
||||||
|
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||||
|
# CONFIG_UPDATE_IMAGE is not set
|
||||||
|
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||||
|
# CONFIG_FW_CONFIG is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Software Bill Of Materials (SBOM)
|
||||||
|
#
|
||||||
|
# CONFIG_SBOM is not set
|
||||||
|
# end of Software Bill Of Materials (SBOM)
|
||||||
|
# end of General setup
|
||||||
|
|
||||||
|
#
|
||||||
|
# Mainboard
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# Important: Run 'make distclean' before switching boards
|
||||||
|
#
|
||||||
|
# CONFIG_VENDOR_51NB is not set
|
||||||
|
# CONFIG_VENDOR_ACER is not set
|
||||||
|
# CONFIG_VENDOR_ADLINK is not set
|
||||||
|
# CONFIG_VENDOR_AMD is not set
|
||||||
|
# CONFIG_VENDOR_AOPEN is not set
|
||||||
|
# CONFIG_VENDOR_APPLE is not set
|
||||||
|
# CONFIG_VENDOR_ASROCK is not set
|
||||||
|
# CONFIG_VENDOR_ASUS is not set
|
||||||
|
# CONFIG_VENDOR_BIOSTAR is not set
|
||||||
|
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||||
|
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||||
|
# CONFIG_VENDOR_CAVIUM is not set
|
||||||
|
# CONFIG_VENDOR_CLEVO is not set
|
||||||
|
# CONFIG_VENDOR_COMPULAB is not set
|
||||||
|
CONFIG_VENDOR_DELL=y
|
||||||
|
# CONFIG_VENDOR_EMULATION is not set
|
||||||
|
# CONFIG_VENDOR_EXAMPLE is not set
|
||||||
|
# CONFIG_VENDOR_FACEBOOK is not set
|
||||||
|
# CONFIG_VENDOR_FOXCONN is not set
|
||||||
|
# CONFIG_VENDOR_GETAC is not set
|
||||||
|
# CONFIG_VENDOR_GIGABYTE is not set
|
||||||
|
# CONFIG_VENDOR_GOOGLE is not set
|
||||||
|
# CONFIG_VENDOR_HP is not set
|
||||||
|
# CONFIG_VENDOR_IBASE is not set
|
||||||
|
# CONFIG_VENDOR_IBM is not set
|
||||||
|
# CONFIG_VENDOR_INTEL is not set
|
||||||
|
# CONFIG_VENDOR_INVENTEC is not set
|
||||||
|
# CONFIG_VENDOR_KONTRON is not set
|
||||||
|
# CONFIG_VENDOR_LENOVO is not set
|
||||||
|
# CONFIG_VENDOR_LIBRETREND is not set
|
||||||
|
# CONFIG_VENDOR_MSI is not set
|
||||||
|
# CONFIG_VENDOR_OCP is not set
|
||||||
|
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||||
|
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||||
|
# CONFIG_VENDOR_PCENGINES is not set
|
||||||
|
# CONFIG_VENDOR_PINE64 is not set
|
||||||
|
# CONFIG_VENDOR_PORTWELL is not set
|
||||||
|
# CONFIG_VENDOR_PRODRIVE is not set
|
||||||
|
# CONFIG_VENDOR_PROTECTLI is not set
|
||||||
|
# CONFIG_VENDOR_PURISM is not set
|
||||||
|
# CONFIG_VENDOR_RAZER is not set
|
||||||
|
# CONFIG_VENDOR_RODA is not set
|
||||||
|
# CONFIG_VENDOR_SAMSUNG is not set
|
||||||
|
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||||
|
# CONFIG_VENDOR_SIEMENS is not set
|
||||||
|
# CONFIG_VENDOR_SIFIVE is not set
|
||||||
|
# CONFIG_VENDOR_STARLABS is not set
|
||||||
|
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||||
|
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||||
|
# CONFIG_VENDOR_TI is not set
|
||||||
|
# CONFIG_VENDOR_UP is not set
|
||||||
|
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||||
|
CONFIG_MAINBOARD_PART_NUMBER="Latitude E5420"
|
||||||
|
CONFIG_MAINBOARD_VERSION="1.0"
|
||||||
|
CONFIG_MAINBOARD_DIR="dell/e5420"
|
||||||
|
CONFIG_VGA_BIOS_ID="8086,0116"
|
||||||
|
CONFIG_DIMM_MAX=4
|
||||||
|
CONFIG_DIMM_SPD_SIZE=256
|
||||||
|
CONFIG_FMDFILE=""
|
||||||
|
# CONFIG_NO_POST is not set
|
||||||
|
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||||
|
CONFIG_CBFS_SIZE=0x5ea000
|
||||||
|
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
|
||||||
|
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
|
||||||
|
CONFIG_MAX_CPUS=8
|
||||||
|
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||||
|
CONFIG_POST_DEVICE=y
|
||||||
|
CONFIG_POST_IO=y
|
||||||
|
CONFIG_DEVICETREE="devicetree.cb"
|
||||||
|
# CONFIG_VBOOT is not set
|
||||||
|
CONFIG_OVERRIDE_DEVICETREE=""
|
||||||
|
# CONFIG_VGA_BIOS is not set
|
||||||
|
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||||
|
CONFIG_DRAM_RESET_GATE_GPIO=60
|
||||||
|
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||||
|
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||||
|
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||||
|
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
CONFIG_BOARD_DELL_LATITUDE_E5420=y
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||||
|
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||||
|
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||||
|
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||||
|
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||||
|
CONFIG_PS2K_EISAID="PNP0303"
|
||||||
|
CONFIG_PS2M_EISAID="PNP0F13"
|
||||||
|
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||||
|
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||||
|
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||||
|
CONFIG_DCACHE_RAM_BASE=0xfefe0000
|
||||||
|
CONFIG_DCACHE_RAM_SIZE=0x20000
|
||||||
|
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||||
|
CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
|
||||||
|
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||||
|
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||||
|
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||||
|
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||||
|
CONFIG_SPI_FLASH_WINBOND=y
|
||||||
|
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||||
|
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_sandybridge/6_ifd_nogbe"
|
||||||
|
CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_sandybridge/me.bin"
|
||||||
|
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||||
|
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||||
|
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||||
|
CONFIG_SPI_FLASH_STMICRO=y
|
||||||
|
# CONFIG_DEBUG_SMI is not set
|
||||||
|
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5420"
|
||||||
|
CONFIG_HAVE_IFD_BIN=y
|
||||||
|
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||||
|
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||||
|
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||||
|
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
|
||||||
|
CONFIG_D3COLD_SUPPORT=y
|
||||||
|
CONFIG_PCIEXP_ASPM=y
|
||||||
|
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||||
|
# CONFIG_PCIEXP_CLK_PM is not set
|
||||||
|
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||||
|
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||||
|
CONFIG_EC_GPE_SCI=0x50
|
||||||
|
CONFIG_BOARD_ROMSIZE_KB_6144=y
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||||
|
CONFIG_COREBOOT_ROMSIZE_KB_6144=y
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||||
|
CONFIG_COREBOOT_ROMSIZE_KB=6144
|
||||||
|
CONFIG_ROM_SIZE=0x00600000
|
||||||
|
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||||
|
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||||
|
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||||
|
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||||
|
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||||
|
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||||
|
# end of Mainboard
|
||||||
|
|
||||||
|
CONFIG_SYSTEM_TYPE_LAPTOP=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Chipset
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# SoC
|
||||||
|
#
|
||||||
|
CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
|
||||||
|
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||||
|
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||||
|
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||||
|
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||||
|
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||||
|
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||||
|
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
|
||||||
|
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||||
|
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||||
|
CONFIG_EHCI_BAR=0xfef00000
|
||||||
|
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||||
|
CONFIG_STACK_SIZE=0x2000
|
||||||
|
CONFIG_IED_REGION_SIZE=0x400000
|
||||||
|
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||||
|
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||||
|
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||||
|
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||||
|
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||||
|
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||||
|
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||||
|
CONFIG_HPET_MIN_TICKS=0x80
|
||||||
|
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||||
|
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||||
|
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||||
|
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||||
|
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||||
|
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||||
|
CONFIG_CBFS_CACHE_ALIGN=8
|
||||||
|
|
||||||
|
#
|
||||||
|
# CPU
|
||||||
|
#
|
||||||
|
CONFIG_CPU_INTEL_MODEL_206AX=y
|
||||||
|
CONFIG_CPU_INTEL_COMMON=y
|
||||||
|
CONFIG_ENABLE_VMX=y
|
||||||
|
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||||
|
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||||
|
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||||
|
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||||
|
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||||
|
CONFIG_PARALLEL_MP=y
|
||||||
|
CONFIG_XAPIC_ONLY=y
|
||||||
|
# CONFIG_X2APIC_ONLY is not set
|
||||||
|
# CONFIG_X2APIC_RUNTIME is not set
|
||||||
|
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||||
|
CONFIG_UDELAY_TSC=y
|
||||||
|
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||||
|
CONFIG_TSC_SYNC_MFENCE=y
|
||||||
|
CONFIG_HAVE_SMI_HANDLER=y
|
||||||
|
CONFIG_SMM_TSEG=y
|
||||||
|
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||||
|
CONFIG_AP_STACK_SIZE=0x800
|
||||||
|
CONFIG_SMP=y
|
||||||
|
CONFIG_SSE=y
|
||||||
|
CONFIG_SSE2=y
|
||||||
|
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||||
|
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||||
|
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||||
|
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||||
|
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||||
|
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Northbridge
|
||||||
|
#
|
||||||
|
CONFIG_USE_NATIVE_RAMINIT=y
|
||||||
|
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||||
|
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||||
|
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
|
||||||
|
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
|
||||||
|
# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
|
||||||
|
CONFIG_RAMINIT_ENABLE_ECC=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Southbridge
|
||||||
|
#
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||||
|
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||||
|
CONFIG_PCIEXP_HOTPLUG=y
|
||||||
|
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||||
|
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||||
|
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||||
|
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||||
|
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||||
|
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||||
|
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||||
|
CONFIG_RCBA_LENGTH=0x4000
|
||||||
|
|
||||||
|
#
|
||||||
|
# Super I/O
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# Embedded Controllers
|
||||||
|
#
|
||||||
|
CONFIG_EC_ACPI=y
|
||||||
|
CONFIG_EC_DELL_MEC5035=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Intel Firmware
|
||||||
|
#
|
||||||
|
CONFIG_HAVE_ME_BIN=y
|
||||||
|
# CONFIG_STITCH_ME_BIN is not set
|
||||||
|
# CONFIG_CHECK_ME is not set
|
||||||
|
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||||
|
# CONFIG_USE_ME_CLEANER is not set
|
||||||
|
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||||
|
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||||
|
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||||
|
CONFIG_ARCH_X86=y
|
||||||
|
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||||
|
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||||
|
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||||
|
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||||
|
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||||
|
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||||
|
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
|
||||||
|
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||||
|
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||||
|
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||||
|
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||||
|
CONFIG_PC80_SYSTEM=y
|
||||||
|
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||||
|
CONFIG_POSTCAR_STAGE=y
|
||||||
|
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||||
|
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||||
|
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||||
|
CONFIG_HAVE_CF9_RESET=y
|
||||||
|
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||||
|
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||||
|
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||||
|
# end of Chipset
|
||||||
|
|
||||||
|
#
|
||||||
|
# Devices
|
||||||
|
#
|
||||||
|
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||||
|
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||||
|
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||||
|
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||||
|
# CONFIG_VGA_ROM_RUN is not set
|
||||||
|
# CONFIG_NO_GFX_INIT is not set
|
||||||
|
CONFIG_NO_EARLY_GFX_INIT=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Display
|
||||||
|
#
|
||||||
|
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||||
|
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||||
|
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||||
|
# CONFIG_BOOTSPLASH is not set
|
||||||
|
# end of Display
|
||||||
|
|
||||||
|
CONFIG_PCI=y
|
||||||
|
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||||
|
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||||
|
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||||
|
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||||
|
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||||
|
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||||
|
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||||
|
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||||
|
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||||
|
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||||
|
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||||
|
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||||
|
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||||
|
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||||
|
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||||
|
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||||
|
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||||
|
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||||
|
# CONFIG_SOFTWARE_I2C is not set
|
||||||
|
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||||
|
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||||
|
CONFIG_USE_DDR3=y
|
||||||
|
# end of Devices
|
||||||
|
|
||||||
|
#
|
||||||
|
# Generic Drivers
|
||||||
|
#
|
||||||
|
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||||
|
# CONFIG_ELOG is not set
|
||||||
|
CONFIG_CACHE_MRC_SETTINGS=y
|
||||||
|
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||||
|
# CONFIG_SMMSTORE is not set
|
||||||
|
CONFIG_SPI_FLASH=y
|
||||||
|
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||||
|
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||||
|
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||||
|
CONFIG_SPI_FLASH_ADESTO=y
|
||||||
|
CONFIG_SPI_FLASH_AMIC=y
|
||||||
|
CONFIG_SPI_FLASH_ATMEL=y
|
||||||
|
CONFIG_SPI_FLASH_EON=y
|
||||||
|
CONFIG_SPI_FLASH_MACRONIX=y
|
||||||
|
CONFIG_SPI_FLASH_SPANSION=y
|
||||||
|
CONFIG_SPI_FLASH_SST=y
|
||||||
|
CONFIG_SPI_FLASH_ISSI=y
|
||||||
|
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||||
|
CONFIG_HAVE_USBDEBUG=y
|
||||||
|
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||||
|
# CONFIG_USBDEBUG is not set
|
||||||
|
# CONFIG_VPD is not set
|
||||||
|
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||||
|
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||||
|
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||||
|
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||||
|
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||||
|
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||||
|
CONFIG_INTEL_INT15=y
|
||||||
|
CONFIG_INTEL_GMA_ACPI=y
|
||||||
|
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||||
|
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||||
|
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||||
|
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||||
|
CONFIG_GFX_GMA=y
|
||||||
|
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
|
||||||
|
CONFIG_GFX_GMA_DYN_CPU=y
|
||||||
|
CONFIG_GFX_GMA_GENERATION="Ironlake"
|
||||||
|
CONFIG_GFX_GMA_PCH="Cougar_Point"
|
||||||
|
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||||
|
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||||
|
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||||
|
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||||
|
CONFIG_DRIVERS_MC146818=y
|
||||||
|
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||||
|
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||||
|
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||||
|
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||||
|
# end of Generic Drivers
|
||||||
|
|
||||||
|
#
|
||||||
|
# Security
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# CBFS verification
|
||||||
|
#
|
||||||
|
# CONFIG_CBFS_VERIFICATION is not set
|
||||||
|
# end of CBFS verification
|
||||||
|
|
||||||
|
#
|
||||||
|
# Verified Boot (vboot)
|
||||||
|
#
|
||||||
|
# end of Verified Boot (vboot)
|
||||||
|
|
||||||
|
#
|
||||||
|
# Trusted Platform Module
|
||||||
|
#
|
||||||
|
CONFIG_NO_TPM=y
|
||||||
|
CONFIG_PCR_BOOT_MODE=1
|
||||||
|
CONFIG_PCR_HWID=1
|
||||||
|
CONFIG_PCR_SRTM=2
|
||||||
|
CONFIG_PCR_FW_VER=10
|
||||||
|
CONFIG_PCR_RUNTIME_DATA=3
|
||||||
|
# end of Trusted Platform Module
|
||||||
|
|
||||||
|
#
|
||||||
|
# Memory initialization
|
||||||
|
#
|
||||||
|
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||||
|
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||||
|
# end of Memory initialization
|
||||||
|
|
||||||
|
# CONFIG_STM is not set
|
||||||
|
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||||
|
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||||
|
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||||
|
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||||
|
# end of Security
|
||||||
|
|
||||||
|
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||||
|
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||||
|
CONFIG_ACPI_SOC_NVS=y
|
||||||
|
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||||
|
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||||
|
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||||
|
CONFIG_HAVE_ACPI_TABLES=y
|
||||||
|
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||||
|
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||||
|
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||||
|
CONFIG_RTC=y
|
||||||
|
CONFIG_HEAP_SIZE=0x100000
|
||||||
|
|
||||||
|
#
|
||||||
|
# Console
|
||||||
|
#
|
||||||
|
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||||
|
CONFIG_POSTCAR_CONSOLE=y
|
||||||
|
CONFIG_SQUELCH_EARLY_SMP=y
|
||||||
|
# CONFIG_SPKMODEM is not set
|
||||||
|
# CONFIG_CONSOLE_NE2K is not set
|
||||||
|
CONFIG_CONSOLE_CBMEM=y
|
||||||
|
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||||
|
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||||
|
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||||
|
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||||
|
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||||
|
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||||
|
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||||
|
# CONFIG_CMOS_POST is not set
|
||||||
|
CONFIG_POST_DEVICE_NONE=y
|
||||||
|
# CONFIG_POST_DEVICE_LPC is not set
|
||||||
|
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||||
|
CONFIG_POST_IO_PORT=0x80
|
||||||
|
CONFIG_HWBASE_DEBUG_CB=y
|
||||||
|
# end of Console
|
||||||
|
|
||||||
|
CONFIG_HAVE_ACPI_RESUME=y
|
||||||
|
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||||
|
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||||
|
CONFIG_HAVE_OPTION_TABLE=y
|
||||||
|
CONFIG_IOAPIC=y
|
||||||
|
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# System tables
|
||||||
|
#
|
||||||
|
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||||
|
CONFIG_BIOS_VENDOR="coreboot"
|
||||||
|
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||||
|
# end of System tables
|
||||||
|
|
||||||
|
#
|
||||||
|
# Payload
|
||||||
|
#
|
||||||
|
CONFIG_PAYLOAD_NONE=y
|
||||||
|
# end of Payload
|
||||||
|
|
||||||
|
#
|
||||||
|
# Debugging
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# CPU Debug Settings
|
||||||
|
#
|
||||||
|
# CONFIG_DISPLAY_MTRRS is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Vendorcode Debug Settings
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# BLOB Debug Settings
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# General Debug Settings
|
||||||
|
#
|
||||||
|
# CONFIG_FATAL_ASSERTS is not set
|
||||||
|
# CONFIG_DEBUG_CBFS is not set
|
||||||
|
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||||
|
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||||
|
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||||
|
# CONFIG_DEBUG_SMBUS is not set
|
||||||
|
# CONFIG_DEBUG_MALLOC is not set
|
||||||
|
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||||
|
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||||
|
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||||
|
# CONFIG_DEBUG_ADA_CODE is not set
|
||||||
|
CONFIG_HAVE_EM100_SUPPORT=y
|
||||||
|
# CONFIG_EM100 is not set
|
||||||
|
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||||
|
# end of Debugging
|
||||||
|
|
||||||
|
CONFIG_RAMSTAGE_ADA=y
|
||||||
|
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||||
|
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||||
|
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||||
|
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||||
|
CONFIG_DECOMPRESS_OFAST=y
|
||||||
|
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||||
|
CONFIG_MAX_REBOOT_CNT=3
|
||||||
|
CONFIG_RELOCATABLE_MODULES=y
|
||||||
|
CONFIG_HAVE_BOOTBLOCK=y
|
||||||
|
CONFIG_HAVE_ROMSTAGE=y
|
||||||
|
CONFIG_HAVE_RAMSTAGE=y
|
||||||
|
|
@ -0,0 +1,617 @@
|
||||||
|
#
|
||||||
|
# Automatically generated file; DO NOT EDIT.
|
||||||
|
# coreboot configuration
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# General setup
|
||||||
|
#
|
||||||
|
CONFIG_COREBOOT_BUILD=y
|
||||||
|
CONFIG_LOCALVERSION=""
|
||||||
|
CONFIG_CBFS_PREFIX="fallback"
|
||||||
|
CONFIG_COMPILER_GCC=y
|
||||||
|
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||||
|
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||||
|
# CONFIG_ANY_TOOLCHAIN is not set
|
||||||
|
# CONFIG_CCACHE is not set
|
||||||
|
# CONFIG_IWYU is not set
|
||||||
|
# CONFIG_FMD_GENPARSER is not set
|
||||||
|
# CONFIG_UTIL_GENPARSER is not set
|
||||||
|
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||||
|
CONFIG_USE_OPTION_TABLE=y
|
||||||
|
CONFIG_STATIC_OPTION_TABLE=y
|
||||||
|
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||||
|
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||||
|
CONFIG_SEPARATE_ROMSTAGE=y
|
||||||
|
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||||
|
CONFIG_COLLECT_TIMESTAMPS=y
|
||||||
|
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||||
|
CONFIG_USE_BLOBS=y
|
||||||
|
# CONFIG_USE_AMD_BLOBS is not set
|
||||||
|
# CONFIG_USE_QC_BLOBS is not set
|
||||||
|
# CONFIG_COVERAGE is not set
|
||||||
|
# CONFIG_UBSAN is not set
|
||||||
|
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||||
|
# CONFIG_ASAN is not set
|
||||||
|
CONFIG_NO_STAGE_CACHE=y
|
||||||
|
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||||
|
# CONFIG_UPDATE_IMAGE is not set
|
||||||
|
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||||
|
# CONFIG_FW_CONFIG is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Software Bill Of Materials (SBOM)
|
||||||
|
#
|
||||||
|
# CONFIG_SBOM is not set
|
||||||
|
# end of Software Bill Of Materials (SBOM)
|
||||||
|
# end of General setup
|
||||||
|
|
||||||
|
#
|
||||||
|
# Mainboard
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# Important: Run 'make distclean' before switching boards
|
||||||
|
#
|
||||||
|
# CONFIG_VENDOR_51NB is not set
|
||||||
|
# CONFIG_VENDOR_ACER is not set
|
||||||
|
# CONFIG_VENDOR_ADLINK is not set
|
||||||
|
# CONFIG_VENDOR_AMD is not set
|
||||||
|
# CONFIG_VENDOR_AOPEN is not set
|
||||||
|
# CONFIG_VENDOR_APPLE is not set
|
||||||
|
# CONFIG_VENDOR_ASROCK is not set
|
||||||
|
# CONFIG_VENDOR_ASUS is not set
|
||||||
|
# CONFIG_VENDOR_BIOSTAR is not set
|
||||||
|
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||||
|
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||||
|
# CONFIG_VENDOR_CAVIUM is not set
|
||||||
|
# CONFIG_VENDOR_CLEVO is not set
|
||||||
|
# CONFIG_VENDOR_COMPULAB is not set
|
||||||
|
CONFIG_VENDOR_DELL=y
|
||||||
|
# CONFIG_VENDOR_EMULATION is not set
|
||||||
|
# CONFIG_VENDOR_EXAMPLE is not set
|
||||||
|
# CONFIG_VENDOR_FACEBOOK is not set
|
||||||
|
# CONFIG_VENDOR_FOXCONN is not set
|
||||||
|
# CONFIG_VENDOR_GETAC is not set
|
||||||
|
# CONFIG_VENDOR_GIGABYTE is not set
|
||||||
|
# CONFIG_VENDOR_GOOGLE is not set
|
||||||
|
# CONFIG_VENDOR_HP is not set
|
||||||
|
# CONFIG_VENDOR_IBASE is not set
|
||||||
|
# CONFIG_VENDOR_IBM is not set
|
||||||
|
# CONFIG_VENDOR_INTEL is not set
|
||||||
|
# CONFIG_VENDOR_INVENTEC is not set
|
||||||
|
# CONFIG_VENDOR_KONTRON is not set
|
||||||
|
# CONFIG_VENDOR_LENOVO is not set
|
||||||
|
# CONFIG_VENDOR_LIBRETREND is not set
|
||||||
|
# CONFIG_VENDOR_MSI is not set
|
||||||
|
# CONFIG_VENDOR_OCP is not set
|
||||||
|
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||||
|
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||||
|
# CONFIG_VENDOR_PCENGINES is not set
|
||||||
|
# CONFIG_VENDOR_PINE64 is not set
|
||||||
|
# CONFIG_VENDOR_PORTWELL is not set
|
||||||
|
# CONFIG_VENDOR_PRODRIVE is not set
|
||||||
|
# CONFIG_VENDOR_PROTECTLI is not set
|
||||||
|
# CONFIG_VENDOR_PURISM is not set
|
||||||
|
# CONFIG_VENDOR_RAZER is not set
|
||||||
|
# CONFIG_VENDOR_RODA is not set
|
||||||
|
# CONFIG_VENDOR_SAMSUNG is not set
|
||||||
|
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||||
|
# CONFIG_VENDOR_SIEMENS is not set
|
||||||
|
# CONFIG_VENDOR_SIFIVE is not set
|
||||||
|
# CONFIG_VENDOR_STARLABS is not set
|
||||||
|
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||||
|
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||||
|
# CONFIG_VENDOR_TI is not set
|
||||||
|
# CONFIG_VENDOR_UP is not set
|
||||||
|
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||||
|
CONFIG_MAINBOARD_PART_NUMBER="Latitude E5420"
|
||||||
|
CONFIG_MAINBOARD_VERSION="1.0"
|
||||||
|
CONFIG_MAINBOARD_DIR="dell/e5420"
|
||||||
|
CONFIG_VGA_BIOS_ID="8086,0116"
|
||||||
|
CONFIG_DIMM_MAX=4
|
||||||
|
CONFIG_DIMM_SPD_SIZE=256
|
||||||
|
CONFIG_FMDFILE=""
|
||||||
|
# CONFIG_NO_POST is not set
|
||||||
|
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||||
|
CONFIG_CBFS_SIZE=0x5ea000
|
||||||
|
CONFIG_MAX_CPUS=8
|
||||||
|
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||||
|
CONFIG_POST_DEVICE=y
|
||||||
|
CONFIG_POST_IO=y
|
||||||
|
CONFIG_DEVICETREE="devicetree.cb"
|
||||||
|
# CONFIG_VBOOT is not set
|
||||||
|
CONFIG_OVERRIDE_DEVICETREE=""
|
||||||
|
# CONFIG_VGA_BIOS is not set
|
||||||
|
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||||
|
CONFIG_DRAM_RESET_GATE_GPIO=60
|
||||||
|
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||||
|
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||||
|
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||||
|
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
CONFIG_BOARD_DELL_LATITUDE_E5420=y
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||||
|
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||||
|
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||||
|
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||||
|
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||||
|
CONFIG_PS2K_EISAID="PNP0303"
|
||||||
|
CONFIG_PS2M_EISAID="PNP0F13"
|
||||||
|
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||||
|
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||||
|
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||||
|
CONFIG_DCACHE_RAM_BASE=0xfefe0000
|
||||||
|
CONFIG_DCACHE_RAM_SIZE=0x20000
|
||||||
|
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||||
|
CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
|
||||||
|
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||||
|
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||||
|
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||||
|
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||||
|
CONFIG_SPI_FLASH_WINBOND=y
|
||||||
|
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||||
|
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_sandybridge/6_ifd_nogbe"
|
||||||
|
CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_sandybridge/me.bin"
|
||||||
|
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||||
|
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||||
|
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||||
|
CONFIG_SPI_FLASH_STMICRO=y
|
||||||
|
# CONFIG_DEBUG_SMI is not set
|
||||||
|
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5420"
|
||||||
|
CONFIG_HAVE_IFD_BIN=y
|
||||||
|
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||||
|
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||||
|
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||||
|
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
|
||||||
|
CONFIG_D3COLD_SUPPORT=y
|
||||||
|
CONFIG_PCIEXP_ASPM=y
|
||||||
|
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||||
|
# CONFIG_PCIEXP_CLK_PM is not set
|
||||||
|
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||||
|
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||||
|
CONFIG_EC_GPE_SCI=0x50
|
||||||
|
CONFIG_BOARD_ROMSIZE_KB_6144=y
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||||
|
CONFIG_COREBOOT_ROMSIZE_KB_6144=y
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||||
|
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||||
|
CONFIG_COREBOOT_ROMSIZE_KB=6144
|
||||||
|
CONFIG_ROM_SIZE=0x00600000
|
||||||
|
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||||
|
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||||
|
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||||
|
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||||
|
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||||
|
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||||
|
# end of Mainboard
|
||||||
|
|
||||||
|
CONFIG_SYSTEM_TYPE_LAPTOP=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Chipset
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# SoC
|
||||||
|
#
|
||||||
|
CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
|
||||||
|
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||||
|
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||||
|
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||||
|
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||||
|
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||||
|
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||||
|
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
|
||||||
|
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||||
|
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||||
|
CONFIG_EHCI_BAR=0xfef00000
|
||||||
|
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||||
|
CONFIG_STACK_SIZE=0x2000
|
||||||
|
CONFIG_IED_REGION_SIZE=0x400000
|
||||||
|
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||||
|
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||||
|
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||||
|
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||||
|
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||||
|
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||||
|
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||||
|
CONFIG_HPET_MIN_TICKS=0x80
|
||||||
|
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||||
|
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||||
|
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||||
|
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||||
|
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||||
|
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||||
|
CONFIG_CBFS_CACHE_ALIGN=8
|
||||||
|
|
||||||
|
#
|
||||||
|
# CPU
|
||||||
|
#
|
||||||
|
CONFIG_CPU_INTEL_MODEL_206AX=y
|
||||||
|
CONFIG_CPU_INTEL_COMMON=y
|
||||||
|
CONFIG_ENABLE_VMX=y
|
||||||
|
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||||
|
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||||
|
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||||
|
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||||
|
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||||
|
CONFIG_PARALLEL_MP=y
|
||||||
|
CONFIG_XAPIC_ONLY=y
|
||||||
|
# CONFIG_X2APIC_ONLY is not set
|
||||||
|
# CONFIG_X2APIC_RUNTIME is not set
|
||||||
|
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||||
|
CONFIG_UDELAY_TSC=y
|
||||||
|
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||||
|
CONFIG_TSC_SYNC_MFENCE=y
|
||||||
|
CONFIG_HAVE_SMI_HANDLER=y
|
||||||
|
CONFIG_SMM_TSEG=y
|
||||||
|
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||||
|
CONFIG_AP_STACK_SIZE=0x800
|
||||||
|
CONFIG_SMP=y
|
||||||
|
CONFIG_SSE=y
|
||||||
|
CONFIG_SSE2=y
|
||||||
|
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||||
|
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||||
|
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||||
|
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||||
|
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||||
|
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Northbridge
|
||||||
|
#
|
||||||
|
CONFIG_USE_NATIVE_RAMINIT=y
|
||||||
|
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||||
|
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||||
|
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
|
||||||
|
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
|
||||||
|
# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
|
||||||
|
CONFIG_RAMINIT_ENABLE_ECC=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Southbridge
|
||||||
|
#
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||||
|
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||||
|
CONFIG_PCIEXP_HOTPLUG=y
|
||||||
|
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||||
|
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||||
|
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||||
|
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||||
|
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||||
|
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||||
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||||
|
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||||
|
CONFIG_RCBA_LENGTH=0x4000
|
||||||
|
|
||||||
|
#
|
||||||
|
# Super I/O
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# Embedded Controllers
|
||||||
|
#
|
||||||
|
CONFIG_EC_ACPI=y
|
||||||
|
CONFIG_EC_DELL_MEC5035=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Intel Firmware
|
||||||
|
#
|
||||||
|
CONFIG_HAVE_ME_BIN=y
|
||||||
|
# CONFIG_STITCH_ME_BIN is not set
|
||||||
|
# CONFIG_CHECK_ME is not set
|
||||||
|
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||||
|
# CONFIG_USE_ME_CLEANER is not set
|
||||||
|
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||||
|
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||||
|
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||||
|
CONFIG_ARCH_X86=y
|
||||||
|
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||||
|
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||||
|
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||||
|
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||||
|
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||||
|
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||||
|
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
|
||||||
|
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||||
|
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||||
|
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||||
|
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||||
|
CONFIG_PC80_SYSTEM=y
|
||||||
|
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||||
|
CONFIG_POSTCAR_STAGE=y
|
||||||
|
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||||
|
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||||
|
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||||
|
CONFIG_HAVE_CF9_RESET=y
|
||||||
|
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||||
|
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||||
|
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||||
|
# end of Chipset
|
||||||
|
|
||||||
|
#
|
||||||
|
# Devices
|
||||||
|
#
|
||||||
|
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||||
|
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||||
|
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||||
|
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||||
|
# CONFIG_VGA_ROM_RUN is not set
|
||||||
|
# CONFIG_NO_GFX_INIT is not set
|
||||||
|
CONFIG_NO_EARLY_GFX_INIT=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Display
|
||||||
|
#
|
||||||
|
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||||
|
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||||
|
# end of Display
|
||||||
|
|
||||||
|
CONFIG_PCI=y
|
||||||
|
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||||
|
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||||
|
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||||
|
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||||
|
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||||
|
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||||
|
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||||
|
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||||
|
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||||
|
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||||
|
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||||
|
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||||
|
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||||
|
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||||
|
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||||
|
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||||
|
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||||
|
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||||
|
# CONFIG_SOFTWARE_I2C is not set
|
||||||
|
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||||
|
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||||
|
CONFIG_USE_DDR3=y
|
||||||
|
# end of Devices
|
||||||
|
|
||||||
|
#
|
||||||
|
# Generic Drivers
|
||||||
|
#
|
||||||
|
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||||
|
# CONFIG_ELOG is not set
|
||||||
|
CONFIG_CACHE_MRC_SETTINGS=y
|
||||||
|
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||||
|
# CONFIG_SMMSTORE is not set
|
||||||
|
CONFIG_SPI_FLASH=y
|
||||||
|
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||||
|
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||||
|
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||||
|
CONFIG_SPI_FLASH_ADESTO=y
|
||||||
|
CONFIG_SPI_FLASH_AMIC=y
|
||||||
|
CONFIG_SPI_FLASH_ATMEL=y
|
||||||
|
CONFIG_SPI_FLASH_EON=y
|
||||||
|
CONFIG_SPI_FLASH_MACRONIX=y
|
||||||
|
CONFIG_SPI_FLASH_SPANSION=y
|
||||||
|
CONFIG_SPI_FLASH_SST=y
|
||||||
|
CONFIG_SPI_FLASH_ISSI=y
|
||||||
|
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||||
|
CONFIG_HAVE_USBDEBUG=y
|
||||||
|
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||||
|
# CONFIG_USBDEBUG is not set
|
||||||
|
# CONFIG_VPD is not set
|
||||||
|
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||||
|
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||||
|
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||||
|
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||||
|
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||||
|
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||||
|
CONFIG_INTEL_INT15=y
|
||||||
|
CONFIG_INTEL_GMA_ACPI=y
|
||||||
|
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||||
|
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||||
|
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||||
|
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||||
|
CONFIG_GFX_GMA=y
|
||||||
|
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
|
||||||
|
CONFIG_GFX_GMA_DYN_CPU=y
|
||||||
|
CONFIG_GFX_GMA_GENERATION="Ironlake"
|
||||||
|
CONFIG_GFX_GMA_PCH="Cougar_Point"
|
||||||
|
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||||
|
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||||
|
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||||
|
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||||
|
CONFIG_DRIVERS_MC146818=y
|
||||||
|
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||||
|
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||||
|
CONFIG_VGA=y
|
||||||
|
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||||
|
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||||
|
# end of Generic Drivers
|
||||||
|
|
||||||
|
#
|
||||||
|
# Security
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# CBFS verification
|
||||||
|
#
|
||||||
|
# CONFIG_CBFS_VERIFICATION is not set
|
||||||
|
# end of CBFS verification
|
||||||
|
|
||||||
|
#
|
||||||
|
# Verified Boot (vboot)
|
||||||
|
#
|
||||||
|
# end of Verified Boot (vboot)
|
||||||
|
|
||||||
|
#
|
||||||
|
# Trusted Platform Module
|
||||||
|
#
|
||||||
|
CONFIG_NO_TPM=y
|
||||||
|
CONFIG_PCR_BOOT_MODE=1
|
||||||
|
CONFIG_PCR_HWID=1
|
||||||
|
CONFIG_PCR_SRTM=2
|
||||||
|
CONFIG_PCR_FW_VER=10
|
||||||
|
CONFIG_PCR_RUNTIME_DATA=3
|
||||||
|
# end of Trusted Platform Module
|
||||||
|
|
||||||
|
#
|
||||||
|
# Memory initialization
|
||||||
|
#
|
||||||
|
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||||
|
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||||
|
# end of Memory initialization
|
||||||
|
|
||||||
|
# CONFIG_STM is not set
|
||||||
|
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||||
|
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||||
|
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||||
|
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||||
|
# end of Security
|
||||||
|
|
||||||
|
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||||
|
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||||
|
CONFIG_ACPI_SOC_NVS=y
|
||||||
|
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||||
|
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||||
|
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||||
|
CONFIG_HAVE_ACPI_TABLES=y
|
||||||
|
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||||
|
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||||
|
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||||
|
CONFIG_RTC=y
|
||||||
|
CONFIG_HEAP_SIZE=0x100000
|
||||||
|
|
||||||
|
#
|
||||||
|
# Console
|
||||||
|
#
|
||||||
|
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||||
|
CONFIG_POSTCAR_CONSOLE=y
|
||||||
|
CONFIG_SQUELCH_EARLY_SMP=y
|
||||||
|
# CONFIG_SPKMODEM is not set
|
||||||
|
# CONFIG_CONSOLE_NE2K is not set
|
||||||
|
CONFIG_CONSOLE_CBMEM=y
|
||||||
|
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||||
|
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||||
|
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||||
|
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||||
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||||
|
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||||
|
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||||
|
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||||
|
# CONFIG_CMOS_POST is not set
|
||||||
|
CONFIG_POST_DEVICE_NONE=y
|
||||||
|
# CONFIG_POST_DEVICE_LPC is not set
|
||||||
|
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||||
|
CONFIG_POST_IO_PORT=0x80
|
||||||
|
CONFIG_HWBASE_DEBUG_CB=y
|
||||||
|
# end of Console
|
||||||
|
|
||||||
|
CONFIG_HAVE_ACPI_RESUME=y
|
||||||
|
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||||
|
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||||
|
CONFIG_HAVE_OPTION_TABLE=y
|
||||||
|
CONFIG_IOAPIC=y
|
||||||
|
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# System tables
|
||||||
|
#
|
||||||
|
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||||
|
CONFIG_BIOS_VENDOR="coreboot"
|
||||||
|
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||||
|
# end of System tables
|
||||||
|
|
||||||
|
#
|
||||||
|
# Payload
|
||||||
|
#
|
||||||
|
CONFIG_PAYLOAD_NONE=y
|
||||||
|
# end of Payload
|
||||||
|
|
||||||
|
#
|
||||||
|
# Debugging
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# CPU Debug Settings
|
||||||
|
#
|
||||||
|
# CONFIG_DISPLAY_MTRRS is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Vendorcode Debug Settings
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# BLOB Debug Settings
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# General Debug Settings
|
||||||
|
#
|
||||||
|
# CONFIG_FATAL_ASSERTS is not set
|
||||||
|
# CONFIG_DEBUG_CBFS is not set
|
||||||
|
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||||
|
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||||
|
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||||
|
# CONFIG_DEBUG_SMBUS is not set
|
||||||
|
# CONFIG_DEBUG_MALLOC is not set
|
||||||
|
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||||
|
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||||
|
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||||
|
# CONFIG_DEBUG_ADA_CODE is not set
|
||||||
|
CONFIG_HAVE_EM100_SUPPORT=y
|
||||||
|
# CONFIG_EM100 is not set
|
||||||
|
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||||
|
# end of Debugging
|
||||||
|
|
||||||
|
CONFIG_RAMSTAGE_ADA=y
|
||||||
|
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||||
|
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||||
|
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||||
|
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||||
|
CONFIG_DECOMPRESS_OFAST=y
|
||||||
|
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||||
|
CONFIG_MAX_REBOOT_CNT=3
|
||||||
|
CONFIG_RELOCATABLE_MODULES=y
|
||||||
|
CONFIG_HAVE_BOOTBLOCK=y
|
||||||
|
CONFIG_HAVE_ROMSTAGE=y
|
||||||
|
CONFIG_HAVE_RAMSTAGE=y
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
tree="default"
|
||||||
|
romtype="normal"
|
||||||
|
arch="x86_64"
|
||||||
|
payload_grub="n"
|
||||||
|
payload_grub_withseabios="n"
|
||||||
|
payload_seabios="y"
|
||||||
|
payload_memtest="y"
|
||||||
|
payload_seabios_withgrub="y"
|
||||||
|
payload_seabios_grubonly="y"
|
||||||
|
grub_scan_disk="ahci"
|
||||||
|
microcode_required="n"
|
||||||
|
|
@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
CONFIG_BOARD_DELL_LATITUDE_E5520=y
|
CONFIG_BOARD_DELL_LATITUDE_E5520=y
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
CONFIG_BOARD_DELL_LATITUDE_E5520=y
|
CONFIG_BOARD_DELL_LATITUDE_E5520=y
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
CONFIG_BOARD_DELL_LATITUDE_E5530=y
|
CONFIG_BOARD_DELL_LATITUDE_E5530=y
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
CONFIG_BOARD_DELL_LATITUDE_E5530=y
|
CONFIG_BOARD_DELL_LATITUDE_E5530=y
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -135,6 +135,7 @@ CONFIG_USBDEBUG_HCD_INDEX=2
|
||||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||||
# CONFIG_CONSOLE_POST is not set
|
# CONFIG_CONSOLE_POST is not set
|
||||||
CONFIG_TPM_PIRQ=0x0
|
CONFIG_TPM_PIRQ=0x0
|
||||||
|
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||||
# CONFIG_BOARD_DELL_E6400 is not set
|
# CONFIG_BOARD_DELL_E6400 is not set
|
||||||
|
|
|
||||||
|
|
@ -156,7 +156,7 @@
|
||||||
E6400_VGA_romname mod_21.bin
|
E6400_VGA_romname mod_21.bin
|
||||||
}
|
}
|
||||||
|
|
||||||
{e5520 e6420 e6520}{
|
{e5420 e5520 e6420 e6520}{
|
||||||
DL_hash 81c9917938c4a2a4f128c976250451931efd0f25b51ff34f058ddacb8eec27272691371864a683ec7abcb924fea32592d061584c7b2571a5d3e84eb870281cc3
|
DL_hash 81c9917938c4a2a4f128c976250451931efd0f25b51ff34f058ddacb8eec27272691371864a683ec7abcb924fea32592d061584c7b2571a5d3e84eb870281cc3
|
||||||
DL_url https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe
|
DL_url https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe
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||||||
DL_url_bkup https://web.archive.org/web/20220202201637/https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe
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DL_url_bkup https://web.archive.org/web/20220202201637/https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe
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||||||
|
|
|
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Reference in New Issue