Fix E6400 display issue with 1440 x 900 panel

The E6400 uses a 100 MHz reference clock on DPLL_REF_SSCLK, whereas
libgfxinit assumed that the reference was always 96 MHz. The frequency
difference caused by a 100 MHz reference with PLL config values
calculated assuming a 96 MHz reference were not significant enough to
cause noticable issues with the more common 1280 x 800 panels, but are
enough to matter for the 1440 x 900 panels which use a higher pixel
clock. This only affected the pre-OS graphics environment provided by
libgfxinit, as Linux drivers would determine the reference clock
frequency based on data in the VBT.

Fix this by making the reference clock frequency in libgfxinit
configurable for GM45 based on a new coreboot Kconfig, which is set to
100 MHz for the E6400.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
20240612_branch
Nicholas Chin 2024-05-20 10:46:25 -06:00
parent 1e54db2989
commit 8629873a60
No known key found for this signature in database
GPG Key ID: 2D0EB28C84678DAA
5 changed files with 81 additions and 0 deletions

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@ -0,0 +1,36 @@
From c35d431a0f1b326b18cd5bbb7d1d49e67d3309bd Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 20 May 2024 10:24:16 -0600
Subject: [PATCH] mb/dell/e6400: Use 100 MHz reference clock for display
The E6400 uses a 100 MHz reference clock for spread spectrum support on
LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
the more common 1280 x 800 display panels, the numerical error was not
large enough to cause noticable issues, but the actual pixel clock
frequency derived from a 100 MHz reference using PLL configs calculated
assuming a 96 MHz reference was not close enough for 1440 x 900 panels,
which require a much higher pixel clock. This resulted in a garbled
display in the pre-OS graphics environment provided by libgfxinit.
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6400/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
index 034de4be2b..4cb16af697 100644
--- a/src/mainboard/dell/e6400/Kconfig
+++ b/src/mainboard/dell/e6400/Kconfig
@@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_GMA_HAVE_VBT
select EC_DELL_MEC5035
+config INTEL_GMA_DPLL_REF_FREQ
+ default 100000000
+
config MAINBOARD_DIR
default "dell/e6400"
--
2.45.1

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@ -136,6 +136,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_BOARD_DELL_E6400=y
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"

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@ -134,6 +134,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_BOARD_DELL_E6400=y
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"

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@ -133,6 +133,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_BOARD_DELL_E6400=y
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"

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@ -0,0 +1,42 @@
From 2c29f01a18d0a104bcc4f785e3901de584d02d7e Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 20 May 2024 10:10:03 -0600
Subject: [PATCH] g45/hw-gfx-gma-plls.adb: Make reference clock frequency
configurable
Instead of assuming a 96 MHz reference clock frequency, use the value
specified by the new INTEL_GMA_DPLL_REF_FREQ Kconfig. This defaults to
96 MHz to preserve the existing behavior. An example of where this is
needed is the DPLL_REF_SSCLK input, which will typically be 100 MHz
to support LVDS spread spectrum clocking.
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
common/g45/hw-gfx-gma-plls.adb | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/common/g45/hw-gfx-gma-plls.adb b/common/g45/hw-gfx-gma-plls.adb
index 67242f2..1aee576 100644
--- a/common/g45/hw-gfx-gma-plls.adb
+++ b/common/g45/hw-gfx-gma-plls.adb
@@ -12,6 +12,8 @@
-- GNU General Public License for more details.
--
+with CB.Config
+
with HW.Time;
with HW.GFX.GMA.Config;
with HW.GFX.GMA.Registers;
@@ -460,7 +462,7 @@ is
(Display => Port_Cfg.Display,
Target_Dotclock => Target_Clock,
-- should be, but doesn't has to be always the same:
- Reference_Clock => 96_000_000,
+ Reference_Clock => CB.Config.INTEL_GMA_DPLL_REF_FREQ,
Best_Clock => Clk,
Valid => Success);
else
--
2.45.1