Update dell 3050 patch to patch 15 (pwm fix)

Use patchset 15 instead of 14:
config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch

Rebase the verb patch; patchset 15 modified the Makefile:
config/coreboot/default/patches/0064-dell-optiplex_3050-add-hda_verb.c.patch

We were using patchset 14 for the 3050 micro:
https://review.coreboot.org/c/coreboot/+/82053/14

Now we use patchset 15:
https://review.coreboot.org/c/coreboot/+/82053/15

Without this patch, the fans are always on a low setting, on
the Dell OptiPlex 3050 Micro, even under stress conditions. With
this patch, the fans change speed according to CPU temperature.

I had to rebase my verb patch, because Mate modified the Makefile
to add his sch5555 handler, on the same line where I add hda_verb.

Mate tells me he will merge my verb and vbt patches into a further
patchset later on. For now, I've simply rebased these patches on
top of Mate's newer work; I've told him he can use them in his port.

I'm probably going to now issue a new revision ROM image for
Libreboot 20241008, so that users can get this fix sooner.

Signed-off-by: Leah Rowe <leah@libreboot.org>

config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch

@@ -1,7 +1,7 @@
-From 2d9f38a12b883e1ddcdae5de107f204e522146e2 Mon Sep 17 00:00:00 2001
+From e8eb37e87abfdf6d2bcf60cb15d35650fcfa6665 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@retroboot.org>
 Date: Fri, 19 Mar 2021 05:54:58 +0000
-Subject: [PATCH 01/39] apple/macbook21: Set default VRAM to 64MiB instead of
+Subject: [PATCH 01/65] apple/macbook21: Set default VRAM to 64MiB instead of
  8MiB
 
 ---
@@ -19,5 +19,5 @@ index b744b11cda..9749e26547 100644
 -gfx_uma_size=8M
 +gfx_uma_size=64M
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch

@@ -1,7 +1,7 @@
-From e60ec1c7304e3f167fd2bf762f28b7eacd0b169a Mon Sep 17 00:00:00 2001
+From 2533ed49003c470a8dbfbf17f6c6a5ef0672c2e2 Mon Sep 17 00:00:00 2001
 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
 Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 02/39] add c3 and clockgen to apple/macbook21
+Subject: [PATCH 02/65] add c3 and clockgen to apple/macbook21
 
 ---
  src/mainboard/apple/macbook21/Kconfig       |  1 +
@@ -64,5 +64,5 @@ index fd86e939b9..263fbabcd1 100644
  	end
  end
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch

@@ -1,7 +1,7 @@
-From 9a0157b1459365cf52f90e66b78dd6b60a259587 Mon Sep 17 00:00:00 2001
+From 14920409e51a9a0997d488b166d90bfad56f61f1 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@osboot.org>
 Date: Sun, 3 Jan 2021 03:34:01 +0000
-Subject: [PATCH 03/39] lenovo/x60: 64MiB Video RAM changed to default
+Subject: [PATCH 03/65] lenovo/x60: 64MiB Video RAM changed to default
  (previously it was 8MiB)
 
 ---
@@ -19,5 +19,5 @@ index 58825c8a36..8e0aaf427d 100644
 -gfx_uma_size=8M
 +gfx_uma_size=64M
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch

@@ -1,7 +1,7 @@
-From 5b2a26e72bce37f7b0a92f1ed93fd607cea8de9b Mon Sep 17 00:00:00 2001
+From 92b009babd1e4a63dd34638924b9559727713369 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@osboot.org>
 Date: Mon, 22 Feb 2021 22:16:59 +0000
-Subject: [PATCH 04/39] lenovo/t60: make 64MiB VRAM the default in cmos.default
+Subject: [PATCH 04/65] lenovo/t60: make 64MiB VRAM the default in cmos.default
 
 ---
  src/mainboard/lenovo/t60/cmos.default | 2 +-
@@ -18,5 +18,5 @@ index 283a5747ee..91f6c0e6e2 100644
 -gfx_uma_size=8M
 +gfx_uma_size=64M
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch

@@ -1,7 +1,7 @@
-From 945d84782e706e8f3effab57edca68d9463d21fc Mon Sep 17 00:00:00 2001
+From c7ad2407a7f515d487332382bb55025873c3d987 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:10:33 +0100
-Subject: [PATCH 05/39] lenovo/t400: set VRAM to 256MiB VRAM by default
+Subject: [PATCH 05/65] lenovo/t400: set VRAM to 256MiB VRAM by default
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -19,5 +19,5 @@ index a16d386dd1..e7bb32306c 100644
 -gfx_uma_size=32M
 +gfx_uma_size=256M
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch

@@ -1,7 +1,7 @@
-From 112470b4f7b046ec2656699336211ba63ff448fa Mon Sep 17 00:00:00 2001
+From 79f686dae47d2ef934b5c95979195f9d3c1978e6 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:11:59 +0100
-Subject: [PATCH 06/39] lenovo/x200: set VRAM to 256MiB by default
+Subject: [PATCH 06/65] lenovo/x200: set VRAM to 256MiB by default
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -19,5 +19,5 @@ index 434af5d227..443ef54e41 100644
 -gfx_uma_size=32M
 +gfx_uma_size=256M
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch

@@ -1,7 +1,7 @@
-From 37418629a56cb740cae2870317458ea52daad8c9 Mon Sep 17 00:00:00 2001
+From a79498ab8a7eac809d99db2fad5b0f8c63870e43 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:18:26 +0100
-Subject: [PATCH 07/39] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
+Subject: [PATCH 07/65] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -19,5 +19,5 @@ index fe79c83570..4a1f97a9d8 100644
 -gfx_uma_size=64M
 +gfx_uma_size=256M
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch

@@ -1,7 +1,7 @@
-From e785387dffe382a02d4c0cb006cced48c235484c Mon Sep 17 00:00:00 2001
+From 5fbdbb11b215e3aa4256dfaa468224fd0c2a1fb0 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:21:39 +0100
-Subject: [PATCH 08/39] acer/g43t-am3: set VRAM to 256MiB by default
+Subject: [PATCH 08/65] acer/g43t-am3: set VRAM to 256MiB by default
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -19,5 +19,5 @@ index 23f0e55f3e..8d6c4db1ce 100644
 -gfx_uma_size=64M
 +gfx_uma_size=256M
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch

@@ -1,7 +1,7 @@
-From 3659aec797baa40e4336e88361a705295fb72b0f Mon Sep 17 00:00:00 2001
+From 15003992f57b62ce59dc282cd089987306126cc9 Mon Sep 17 00:00:00 2001
 From: persmule <persmule@gmail.com>
 Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 09/39] lenovo/t400: Enable all SATA ports
+Subject: [PATCH 09/65] lenovo/t400: Enable all SATA ports
 
 There are 2 SATA ports on the chassis of t400(s), but at least one dock for
 t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -30,5 +30,5 @@ index 259c3e1b21..3d007533a4 100644
  			register "sata_traffic_monitor"		= "0"
  
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch

@@ -1,7 +1,7 @@
-From 820c2d64a7415f7159fd7cdac4746049c91f89a2 Mon Sep 17 00:00:00 2001
+From f8ea06883762c906a7f3ad7d286b628bca3443ab Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 20 Dec 2021 01:29:31 +0000
-Subject: [PATCH 10/39] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
+Subject: [PATCH 10/65] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
  default
 
 ---
@@ -18,5 +18,5 @@ index 732e214b32..3bb78960b9 100644
  me_state=Normal
 +gfx_uma_size=224M
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch

@@ -1,7 +1,7 @@
-From 6bc13399517009917538cd4ddb426c4b1550bfad Mon Sep 17 00:00:00 2001
+From 47483865af46a3d1f8732d1bd97f4a7155cc24d6 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 3 Jan 2022 19:06:22 +0000
-Subject: [PATCH 11/39] lenovo/x230: set me_state=Disabled in cmos.default
+Subject: [PATCH 11/65] lenovo/x230: set me_state=Disabled in cmos.default
 
 I only recently found out about this. It's possible to use me_cleaner to
 do the same thing, but some people might just flash coreboot and not do
@@ -34,5 +34,5 @@ index 3bb78960b9..ae47202aac 100644
 +me_state=Disabled
  gfx_uma_size=224M
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch

@@ -1,7 +1,7 @@
-From 72c9e1403fb93c025be75536f5520e2ef9d4da9e Mon Sep 17 00:00:00 2001
+From 84f7622ea0c3a78742f129d2ec9f437e6c424839 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 2 Mar 2022 21:50:01 +0000
-Subject: [PATCH 12/39] set me_state=Disabled on all cmos.default files!
+Subject: [PATCH 12/65] set me_state=Disabled on all cmos.default files!
 
 yeah. why the hell isn't this the default
 
@@ -120,5 +120,5 @@ index d61046df6b..8c793fd1c3 100644
 -me_state=Enable
 +me_state=Disabled
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0013-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch

@@ -1,7 +1,7 @@
-From 70cf6905b54d39285025373dae1c897c9c727f83 Mon Sep 17 00:00:00 2001
+From 851aa297808a4776634df5817cae54c226b4d750 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 13/39] util/ifdtool: add --nuke flag (all 0xFF on region)
+Subject: [PATCH 13/65] util/ifdtool: add --nuke flag (all 0xFF on region)
 
 When this option is used, the region's contents are overwritten
 with all ones (0xFF).
@@ -201,5 +201,5 @@ index 32b2081d93..1473cf058b 100644
  		struct fpsba *fpsba = find_fpsba(image, size);
  		struct fmsba *fmsba = find_fmsba(image, size);
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0014-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch

@@ -1,7 +1,7 @@
-From c53e5035b612710595abc93f0b4c3c65ca61ebad Mon Sep 17 00:00:00 2001
+From a1a4312c9bea5b7fb5170174dbd14f914c11637c Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 1 Dec 2021 02:53:00 +0000
-Subject: [PATCH 14/39] fix speedstep on x200/t400: Revert
+Subject: [PATCH 14/65] fix speedstep on x200/t400: Revert
  "cpu/intel/model_1067x: enable PECI"
 
 This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
@@ -43,5 +43,5 @@ index d051e8915b..30ba2bf0c6 100644
  
  #define PIC_SENS_CFG	0x1aa
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0015-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch

@@ -1,7 +1,7 @@
-From dabe942b006082f6e592a26f1d0f13a2586b53d6 Mon Sep 17 00:00:00 2001
+From 7e366e5d4d56aade1cb8de8433eb2b02cc9aceef Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 17 Apr 2023 15:49:57 +0100
-Subject: [PATCH 15/39] GM45-type CPUs: don't enable alternative SMRR
+Subject: [PATCH 15/65] GM45-type CPUs: don't enable alternative SMRR
 
 This reverts the changes in coreboot revision:
 df7aecd92643d207feaf7fd840f8835097346644
@@ -169,5 +169,5 @@ index 535fb8fae7..f7b05facd2 100644
  	configure_c_states();
  
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0016-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch

@@ -1,7 +1,7 @@
-From 6426e07c7da50d588ee1ca30e0911040d89e4c96 Mon Sep 17 00:00:00 2001
+From b925e95cc9d750c56fdbfbd1838b77339c124139 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 16/39] mb/dell/e6400: Enable 01.0 device in devicetree for
+Subject: [PATCH 16/65] mb/dell/e6400: Enable 01.0 device in devicetree for
  dGPU models
 
 Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
@@ -24,5 +24,5 @@ index bb954cbd7b..e9f3915d17 100644
  		device pci 02.1 on end # Display
  		device pci 03.0 on end # ME
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0017-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -1,7 +1,7 @@
-From 29a654eaaa7bf924f9681a2520dbabfe12619269 Mon Sep 17 00:00:00 2001
+From f440b426378314bfbc0f397fdd9bd5bd68d81483 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 17/39] Remove warning for coreboot images built without a
+Subject: [PATCH 17/65] Remove warning for coreboot images built without a
  payload
 
 I added this in upstream to prevent people from accidentally flashing
@@ -35,5 +35,5 @@ index 5f988dac1b..516133880f 100644
 -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
 +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0018-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch

@@ -1,7 +1,7 @@
-From 892b6244c27590cbf1d82125340c57273e42b911 Mon Sep 17 00:00:00 2001
+From e4509a2d3204d8798cc48be37f33e43d07ff5e3b Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sat, 19 Aug 2023 16:19:10 -0600
-Subject: [PATCH 18/39] mb/dell: Add Latitude E6530 (Ivy Bridge)
+Subject: [PATCH 18/65] mb/dell: Add Latitude E6530 (Ivy Bridge)
 
 Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was
 not tested. I do not physically have this system; someone with physical
@@ -426,5 +426,5 @@ index 0000000000..8b9c82fba4
 +	end
 +end
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0019-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch

@@ -1,7 +1,7 @@
-From 9b0766b86ac010b7edfe27d1f7edbb3f27dc742e Mon Sep 17 00:00:00 2001
+From cfac9aa347e13065c2e24d62091636cc4d0e56be Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Wed, 31 Jan 2024 22:57:07 -0700
-Subject: [PATCH 19/39] mb/dell: Add Latitude E5530 (Ivy Bridge)
+Subject: [PATCH 19/65] mb/dell: Add Latitude E5530 (Ivy Bridge)
 
 Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board;
 someone with physical access to one sent me the output of autoport which
@@ -426,5 +426,5 @@ index 0000000000..85c448d010
 +	end
 +end
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch

@@ -1,7 +1,7 @@
-From 5d8a651a71d19918130f58c637700539dd320789 Mon Sep 17 00:00:00 2001
+From e5ed7361d41b89ee38b572beb921924b33cc174d Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sun, 26 Nov 2023 17:08:52 -0700
-Subject: [PATCH 20/39] mb/dell: Add Latitude E6420 (Sandy Bridge)
+Subject: [PATCH 20/65] mb/dell: Add Latitude E6420 (Sandy Bridge)
 
 Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was
 not tested. I do not physically have this system; someone with physical
@@ -431,5 +431,5 @@ index 0000000000..3012a3177f
 +	end
 +end
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0021-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch

@@ -1,7 +1,7 @@
-From 1111dcab65ca83f175f1bb9c0496cae24fbfb7c2 Mon Sep 17 00:00:00 2001
+From 73313e682ba8808f8db6259ac7d93f54c11cb884 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Wed, 31 Jan 2024 22:07:25 -0700
-Subject: [PATCH 21/39] mb/dell: Add Latitude E6520 (Sandy Bridge)
+Subject: [PATCH 21/65] mb/dell: Add Latitude E6520 (Sandy Bridge)
 
 Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was
 not tested. I do not physically have this system; someone with physical
@@ -445,5 +445,5 @@ index 0000000000..f90f2dee1f
 +	end
 +end
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E5520-Sandy-Bridge.patch

@@ -1,7 +1,7 @@
-From 39dcb2dcada8821c49a3a042d9e70a6cda81a4ab Mon Sep 17 00:00:00 2001
+From a7e2fde426280a944916c341586361f3ac9fa9a8 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Wed, 7 Feb 2024 10:23:38 -0700
-Subject: [PATCH 22/39] mb/dell: Add Latitude E5520 (Sandy Bridge)
+Subject: [PATCH 22/65] mb/dell: Add Latitude E5520 (Sandy Bridge)
 
 Mainboard is Krug 15". I do not physically have this system; someone
 with physical access to one sent me the output of autoport which I then
@@ -438,5 +438,5 @@ index 0000000000..479d1b696e
 +	end
 +end
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0023-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch

@@ -1,7 +1,7 @@
-From 948221e226340c1c5852a73d005ada18120de393 Mon Sep 17 00:00:00 2001
+From f781a8bac250d4902ec3e7caa0628c77836a8ae3 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Mon, 4 Mar 2024 18:05:43 -0700
-Subject: [PATCH 23/39] mb/dell: Add Latitude E5420 (Sandy Bridge)
+Subject: [PATCH 23/65] mb/dell: Add Latitude E5420 (Sandy Bridge)
 
 Mainboard is Krug 14". I do not physically have this system; someone
 with physical access to one sent me the output of autoport which I then
@@ -438,5 +438,5 @@ index 0000000000..3f55bfd49d
 +	end
 +end
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0024-mb-dell-Add-Latitude-E6320-Sandy-Bridge.patch

@@ -1,7 +1,7 @@
-From 5ebb21be501cf43d41d1690c29d047bd98fbc942 Mon Sep 17 00:00:00 2001
+From 85a0905b600c1f532c462047941da6e7c2bb47c2 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Wed, 7 Feb 2024 15:23:46 -0700
-Subject: [PATCH 24/39] mb/dell: Add Latitude E6320 (Sandy Bridge)
+Subject: [PATCH 24/65] mb/dell: Add Latitude E6320 (Sandy Bridge)
 
 Mainboard is PAL70/LA-6611P. I do not physically have this system;
 someone with physical access to one sent me the output of autoport which
@@ -431,5 +431,5 @@ index 0000000000..3bfe6b57ed
 +	end
 +end
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0025-mb-dell-Add-Latitude-E6220-Sandy-Bridge.patch

@@ -1,7 +1,7 @@
-From fbe48205a55b4a03082affe9f66e81ee509d5f44 Mon Sep 17 00:00:00 2001
+From 817b0d543444e52ddfde536ded52509456dcbbf2 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 8 Mar 2024 09:27:36 -0700
-Subject: [PATCH 25/39] mb/dell: Add Latitude E6220 (Sandy Bridge)
+Subject: [PATCH 25/65] mb/dell: Add Latitude E6220 (Sandy Bridge)
 
 Mainboard is codenamed Vida. I do not physically have this system;
 someone with physical access to one sent me the output of autoport which
@@ -434,5 +434,5 @@ index 0000000000..9faf27e27b
 +	end
 +end
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch

@@ -1,7 +1,7 @@
-From 87e6f8bf38c5dcb4075d0df32507bf9151338b92 Mon Sep 17 00:00:00 2001
+From 48347cf8bc52db7a454a7be8cbc6f9d9eb67b8b0 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 8 Mar 2024 09:33:03 -0700
-Subject: [PATCH 26/39] mb/dell: Add Latitude E6330 (Ivy Bridge)
+Subject: [PATCH 26/65] mb/dell: Add Latitude E6330 (Ivy Bridge)
 
 Mainboard is QAL70/LA-7741P. I do not physically have this system;
 someone with physical access to one sent me the output of autoport which
@@ -432,5 +432,5 @@ index 0000000000..4125159367
 +	end
 +end
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0027-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch

@@ -1,7 +1,7 @@
-From 611b5b3b4794eeda7ffb0a1876e1033705c50545 Mon Sep 17 00:00:00 2001
+From 80af5303da07197a7da5262e82a59b691ffed5a2 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Thu, 26 Oct 2017 21:26:43 +0800
-Subject: [PATCH 27/39] mb/dell: Add Latitude E6230 (Ivy Bridge)
+Subject: [PATCH 27/65] mb/dell: Add Latitude E6230 (Ivy Bridge)
 
 This was adapted from CB:22693 from Iru Cai, which was based on
 autoport. I do not physically have this system. Someone with physical
@@ -436,5 +436,5 @@ index 0000000000..3a0fa720da
 +	end
 +end
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0028-HACK-Disable-coreboot-related-BL31-features.patch

@@ -1,7 +1,7 @@
-From ea6e8749112dee4f458e9cf591e13e9097d56bab Mon Sep 17 00:00:00 2001
+From 8fa72bedc6282ba581ede85d62a341917ec5d203 Mon Sep 17 00:00:00 2001
 From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
 Date: Thu, 22 Jun 2023 16:44:27 +0300
-Subject: [PATCH 28/39] HACK: Disable coreboot related BL31 features
+Subject: [PATCH 28/65] HACK: Disable coreboot related BL31 features
 
 I don't know why, but removing this BL31 make argument lets gru-kevin
 power off properly when shut down from Linux. Needs investigation.
@@ -24,5 +24,5 @@ index cb43897efd..a9e5ff399a 100644
  BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
  
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0029-use-own-mirror-for-acpica-files.patch

@@ -1,7 +1,7 @@
-From 5c385ef4b4424ed8c37e549a00866edda960563f Mon Sep 17 00:00:00 2001
+From 5b425149a2ba0d1c044c32f5e16ba4d4e59796a8 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Wed, 31 Jul 2024 00:03:02 +0100
-Subject: [PATCH 29/39] use own mirror for acpica files
+Subject: [PATCH 29/65] use own mirror for acpica files
 
 intel likes to break links for no reason,
 so we host our own backups of acpica.
@@ -25,5 +25,5 @@ index ad756652ed..5faff337b4 100755
  LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
  CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch

@@ -1,7 +1,7 @@
-From c1065a638f2af40d8ef2c8586074bb82b96c02db Mon Sep 17 00:00:00 2001
+From 253f8eeb895e50b3394b58268594acf9e9596bd2 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Tue, 31 Oct 2023 18:24:39 +0000
-Subject: [PATCH 30/39] crank up vram allocation on more intel boards
+Subject: [PATCH 30/65] crank up vram allocation on more intel boards
 
 these were added to libreboot, and it's a policy of
 libreboot to max out the vram settings. this was
@@ -138,5 +138,5 @@ index b318ab9772..82292ea5d6 100644
  me_state=Disabled
 +gfx_uma_size=224M
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0031-dell-e6430-use-ME-Soft-Temporary-Disable.patch

@@ -1,7 +1,7 @@
-From dc02595f99566f71513ee16f1883e315b725241a Mon Sep 17 00:00:00 2001
+From 7b1caf7260ab468fa2f0e6d73090c5412bc0254d Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 11:41:41 +0000
-Subject: [PATCH 31/39] dell/e6430: use ME Soft Temporary Disable
+Subject: [PATCH 31/65] dell/e6430: use ME Soft Temporary Disable
 
 i overlooked this. it's set on other boards.
 
@@ -26,5 +26,5 @@ index 2a5b30f2b7..279415dfd1 100644
 -me_state=Normal
 +me_state=Disabled
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0032-use-mirrorservice.org-for-gcc-downloads.patch

@@ -1,7 +1,7 @@
-From adb6121970034aa63da8c6303292ff81f340d9db Mon Sep 17 00:00:00 2001
+From b769a682016b7d231bb3d004698c8a2059bbf363 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 22:57:08 +0000
-Subject: [PATCH 32/39] use mirrorservice.org for gcc downloads
+Subject: [PATCH 32/65] use mirrorservice.org for gcc downloads
 
 the gnu.org 302 redirect often fails
 
@@ -32,5 +32,5 @@ index 5faff337b4..2743f96903 100755
  # CLANG toolchain archive locations
  LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0033-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch

@@ -1,7 +1,7 @@
-From 67b7a9e4d06d595adf8382ee83e82b5019e23afa Mon Sep 17 00:00:00 2001
+From 3697d2e2df764bd2f1b05a6856e035b606f6a360 Mon Sep 17 00:00:00 2001
 From: Riku Viitanen <riku.viitanen@protonmail.com>
 Date: Sat, 23 Dec 2023 19:02:10 +0200
-Subject: [PATCH 1/1] mb/hp: Add Compaq Elite 8300 CMT port
+Subject: [PATCH 33/65] mb/hp: Add Compaq Elite 8300 CMT port
 
 Based on autoport and Z220 SuperIO code.
 
@@ -868,5 +868,5 @@ index 0000000000..8dbd95ef96
 +	.enable_dev = mainboard_enable,
 +};
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0034-nb-intel-haswell-make-IOMMU-a-runtime-option.patch

@@ -1,7 +1,7 @@
-From eef3e0d517bde40d4761a9af3c004801a89db887 Mon Sep 17 00:00:00 2001
+From 0ad294f2da8085d5612f7940ec8601d979cb2421 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 2 Mar 2024 22:51:09 +0000
-Subject: [PATCH 34/39] nb/intel/haswell: make IOMMU a runtime option
+Subject: [PATCH 34/65] nb/intel/haswell: make IOMMU a runtime option
 
 When I tested graphics cards on a coreboot port for Dell
 OptiPlex 9020 SFF, I could not use a graphics card unless
@@ -288,5 +288,5 @@ index e47deb5da6..1a7e0b1076 100644
  	if (capid0_a & VTD_DISABLE)
  		return;
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0035-dell-optiplex_9020-Disable-IOMMU-by-default.patch

@@ -1,7 +1,7 @@
-From b7a80abe673c279e755efbe92851ec0600467fae Mon Sep 17 00:00:00 2001
+From 80d728b91ec793f584bcf045f00e5fe4bba5e4ae Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 2 Mar 2024 23:00:09 +0000
-Subject: [PATCH 35/39] dell/optiplex_9020: Disable IOMMU by default
+Subject: [PATCH 35/65] dell/optiplex_9020: Disable IOMMU by default
 
 Needed to make graphics cards work. Turning it on is
 recommended if only using iGPU, otherwise leave it off
@@ -25,5 +25,5 @@ index 8000eea8c0..0700f971ee 100644
 -iommu=Enable
 +iommu=Disable
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0036-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch

@@ -1,7 +1,7 @@
-From 4c0f0d139cdc0fbfadf76ee576d69503b81dc9dc Mon Sep 17 00:00:00 2001
+From dba9c3776f90bf345070a90c048ff2bae7180f73 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 6 Apr 2024 01:22:47 +0100
-Subject: [PATCH 36/39] nb/haswell: Fully disable iGPU when dGPU is used
+Subject: [PATCH 36/65] nb/haswell: Fully disable iGPU when dGPU is used
 
 My earlier patch disabled decode *and* disabled the iGPU itself, but
 a subsequent revision disabled only VGA decode. Upon revisiting, I
@@ -47,5 +47,5 @@ index f7fad3183d..1b188e92e1 100644
  
  static struct device_operations gma_func0_ops = {
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0037-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch

@@ -1,7 +1,7 @@
-From 7e921212d3113320b2d28e66cd6a6788533fcab7 Mon Sep 17 00:00:00 2001
+From 726d0001bda013a094779149828e2bc1be581fa8 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 3 May 2024 11:03:32 -0600
-Subject: [PATCH 37/39] ec/dell/mec5035: Add S3 suspend SMI handler
+Subject: [PATCH 37/65] ec/dell/mec5035: Add S3 suspend SMI handler
 
 Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -113,5 +113,5 @@ index 0000000000..1db834773d
 +	}
 +}
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0038-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch

@@ -1,7 +1,7 @@
-From 53bddae0fc8436fe262ca7fc2e19049afa7a38f8 Mon Sep 17 00:00:00 2001
+From 451b3e3e334d350c060444d79bc964bd90ec1152 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 3 May 2024 16:31:12 -0600
-Subject: [PATCH 38/39] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes
+Subject: [PATCH 38/65] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes
 
 This should fix S3 suspend on these systems
 
@@ -27,5 +27,5 @@ index 0000000000..334d7b1a5f
 +	mec5035_sleep(slp_typ);
 +}
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0039-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch

@@ -1,7 +1,7 @@
-From 919cbfa034db5d2ef9e56dd71ef329c38c5ede3c Mon Sep 17 00:00:00 2001
+From b24c5caf5a8f63555d3b71e7a786c822a4c262cc Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 4 May 2024 02:00:53 +0100
-Subject: [PATCH 39/39] nb/haswell: lock policy regs when disabling IOMMU
+Subject: [PATCH 39/65] nb/haswell: lock policy regs when disabling IOMMU
 
 Angel Pons told me I should do it. See comments here:
 https://review.coreboot.org/c/coreboot/+/81016
@@ -51,5 +51,5 @@ index 1a7e0b1076..e9506ee830 100644
  	/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
  	u32 reg32;
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0040-nb-intel-gm45-Make-DDR2-raminit-work.patch

@@ -1,7 +1,7 @@
-From fe5e1655be8cdb8eff1659e5ce6acbd06b9a7620 Mon Sep 17 00:00:00 2001
+From c41e97f85f2a2677c742d62e3080af7cfeb2ef23 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Mon, 10 May 2021 22:40:59 +0200
-Subject: [PATCH 1/3] nb/intel/gm45: Make DDR2 raminit work
+Subject: [PATCH 40/65] nb/intel/gm45: Make DDR2 raminit work
 
 List of changes:
  - Update some timing and ODT values
@@ -219,5 +219,5 @@ index aef863f05a..b74765fd9c 100644
 +	mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
  }
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0041-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch

@@ -1,7 +1,7 @@
-From 88a9c562b77316f1217139e62425f9af1c351c6f Mon Sep 17 00:00:00 2001
+From 3110c4392d40175716f167be5ef8234f2b4cd030 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Tue, 6 Aug 2024 00:50:24 +0100
-Subject: [PATCH 41/59] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
+Subject: [PATCH 41/65] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
 
 We add this patch:
 
@@ -236,5 +236,5 @@ index b74765fd9c..5d4505e063 100644
 +	}
  }
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch

@@ -1,7 +1,7 @@
-From b42ca30081b25cbabfb2659adca9d935ef3a8399 Mon Sep 17 00:00:00 2001
+From 265fb9f4fd017de635bc44b5a762c69a8bec6158 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Mon, 20 May 2024 10:24:16 -0600
-Subject: [PATCH 3/3] mb/dell/e6400: Use 100 MHz reference clock for display
+Subject: [PATCH 42/65] mb/dell/e6400: Use 100 MHz reference clock for display
 
 The E6400 uses a 100 MHz reference clock for spread spectrum support on
 LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
@@ -48,5 +48,5 @@ index 8059e7ee80..5df5a93296 100644
  	select VBOOT_STARTS_IN_BOOTBLOCK
  
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0043-haswell-NRI-Initialise-MPLL.patch

@@ -1,7 +1,7 @@
-From 8b584165a99c69cc808f86efcdd55acb06a4464c Mon Sep 17 00:00:00 2001
+From ab36967cce0593dd17f3018ab4a6661e4219d242 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Thu, 11 Apr 2024 17:25:07 +0200
-Subject: [PATCH 01/17] haswell NRI: Initialise MPLL
+Subject: [PATCH 43/65] haswell NRI: Initialise MPLL
 
 Add code to initialise the MPLL (Memory PLL). The procedure is similar
 to the one for Sandy/Ivy Bridge, but it is not worth factoring out.
@@ -344,5 +344,5 @@ index 5610e7089a..45f8174995 100644
  #define SAPMCTL			0x5f00
  
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch

@@ -1,7 +1,7 @@
-From adde2e8d038b2d07ab7287eedab5888d92a56a60 Mon Sep 17 00:00:00 2001
+From 876011559681881d950ad3b6742b40322f1f5a6d Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 16:29:55 +0200
-Subject: [PATCH 02/17] haswell NRI: Post-process selected timings
+Subject: [PATCH 44/65] haswell NRI: Post-process selected timings
 
 Once the MPLL has been initialised, convert the timings from the SPD to
 be in DCLKs, which is what the hardware expects. In addition, calculate
@@ -245,5 +245,5 @@ index eff993800b..4f7fe46494 100644
 +	return RAMINIT_STATUS_SUCCESS;
 +}
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0045-haswell-NRI-Configure-initial-MC-settings.patch

@@ -1,7 +1,7 @@
-From 0001039f5ea6be6700a453f511069be2ce1b4e7e Mon Sep 17 00:00:00 2001
+From e91b308fe5848b14cabbd29be4af60e3a9b7938d Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 17:22:07 +0200
-Subject: [PATCH 03/17] haswell NRI: Configure initial MC settings
+Subject: [PATCH 45/65] haswell NRI: Configure initial MC settings
 
 Program initial memory controller settings. Many of these values will be
 adjusted later during training.
@@ -1590,5 +1590,5 @@ index 45f8174995..4c3f399b5d 100644
  #define HDAUDRID		0x6008
  #define UMAGFXCTL		0x6020
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0046-haswell-NRI-Add-timings-refresh-programming.patch

@@ -1,7 +1,7 @@
-From 44032c7df6f4537c43ba80ae2f4a239616bd8d2d Mon Sep 17 00:00:00 2001
+From 694d1650cad8573e899916c0d0a25604885f6e3b Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 20:59:58 +0200
-Subject: [PATCH 04/17] haswell NRI: Add timings/refresh programming
+Subject: [PATCH 46/65] haswell NRI: Add timings/refresh programming
 
 Program the registers with timing and refresh parameters.
 
@@ -537,5 +537,5 @@ index 4c3f399b5d..2acc5cbbc8 100644
  /* MCMAIN broadcast */
  #define MCSCHEDS_CBIT		0x4c20
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0047-haswell-NRI-Program-memory-map.patch

@@ -1,7 +1,7 @@
-From 406e474c7f9f83dc10c7c0fa7cd9765ae822ad4e Mon Sep 17 00:00:00 2001
+From 70d7333e1e0c2b0ce0f2a7e4c4c3ac5c1aca2094 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 21:24:50 +0200
-Subject: [PATCH 05/17] haswell NRI: Program memory map
+Subject: [PATCH 47/65] haswell NRI: Program memory map
 
 This is very similar to Sandy/Ivy Bridge, except that there's several
 registers to program in GDXCBAR. One of these GDXCBAR registers has a
@@ -259,5 +259,5 @@ index 1ee0ab2890..0228cf6bb9 100644
  #define PAM0		0x80
  #define PAM1		0x81
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch

@@ -1,7 +1,7 @@
-From eb8150a07c472078ad37887de13a166e6cf8bdad Mon Sep 17 00:00:00 2001
+From cc302630662eee011a903df4fd7a36d82bd22203 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 21:49:40 +0200
-Subject: [PATCH 06/17] haswell NRI: Add DDR3 JEDEC reset and init
+Subject: [PATCH 48/65] haswell NRI: Add DDR3 JEDEC reset and init
 
 Implement JEDEC reset and init sequence for DDR3. The MRS commands are
 issued through the REUT (Robust Electrical Unified Testing) hardware.
@@ -1032,5 +1032,5 @@ index 07f4b9dc16..5b3696347c 100644
  #define PMSYNC_CONFIG2	0x33cc	/* 32bit */
  #define SOFT_RESET_CTRL 0x38f4
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0049-haswell-NRI-Add-pre-training-steps.patch

@@ -1,7 +1,7 @@
-From 19890277e3a0d411b016efbe1b54e511d4f36c0d Mon Sep 17 00:00:00 2001
+From 0f160dee563155e93422fc77c53251419043d4dc Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 23:12:18 +0200
-Subject: [PATCH 07/17] haswell NRI: Add pre-training steps
+Subject: [PATCH 49/65] haswell NRI: Add pre-training steps
 
 Implement pre-training steps, which consist of enabling ECC I/O and
 filling the WDB (Write Data Buffer, stores test patterns) through a
@@ -388,5 +388,5 @@ index 4fc78a7f43..f8408e51a0 100644
  
  #define REUT_ch_SEQ_CFG(ch)			(0x48a8 + 8 * (ch))
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0050-haswell-NRI-Add-REUT-I-O-test-library.patch

@@ -1,7 +1,7 @@
-From 5ea55ac3f02a8a10f05e84ab9fbace424194869f Mon Sep 17 00:00:00 2001
+From 78b25eb96baef7da2f5481572a6df2b88ee2b3d4 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 00:11:29 +0200
-Subject: [PATCH 08/17] haswell NRI: Add REUT I/O test library
+Subject: [PATCH 50/65] haswell NRI: Add REUT I/O test library
 
 Implement a library to run I/O tests using the REUT hardware.
 
@@ -1126,5 +1126,5 @@ index f8408e51a0..817a9f8bf8 100644
  #define MCSCHEDS_CBIT		0x4c20
  
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0051-haswell-NRI-Add-range-tracking-library.patch

@@ -1,7 +1,7 @@
-From 07970f6dc64e5563c26013d842a929734e2bf8ed Mon Sep 17 00:00:00 2001
+From ca6d92e13278832dfddbe7dcb4cbefa5861041e8 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 00:56:00 +0200
-Subject: [PATCH 09/17] haswell NRI: Add range tracking library
+Subject: [PATCH 51/65] haswell NRI: Add range tracking library
 
 Implement a small library used to keep track of passing ranges. This
 will be used by 1D training algorithms when margining some parameter.
@@ -218,5 +218,5 @@ index 0000000000..235392df96
 +
 +#endif
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0052-haswell-NRI-Add-library-to-change-margins.patch

@@ -1,7 +1,7 @@
-From 66db8447d6cf724c4b25618c94d5a53d501f214e Mon Sep 17 00:00:00 2001
+From f6d7bd420640a9ccb137113d69b97bc13fe6b0da Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 01:11:03 +0200
-Subject: [PATCH 10/17] haswell NRI: Add library to change margins
+Subject: [PATCH 52/65] haswell NRI: Add library to change margins
 
 Implement a library to change Rx/Tx margins. It will be expanded later.
 
@@ -290,5 +290,5 @@ index 817a9f8bf8..a81559bb1e 100644
  
  #define REUT_ch_SEQ_ADDR_INC_CTL(ch)		(0x4910 + 8 * (ch))
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0053-haswell-NRI-Add-RcvEn-training.patch

@@ -1,7 +1,7 @@
-From 0826d1e9ba50daad13c3d5adccba4b180c82296b Mon Sep 17 00:00:00 2001
+From d3cd9ccb7d2eed7ecd5bcdc33d73a5e28b029dba Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 00:05:41 +0200
-Subject: [PATCH 11/17] haswell NRI: Add RcvEn training
+Subject: [PATCH 53/65] haswell NRI: Add RcvEn training
 
 Implement the RcvEn (Receive Enable) calibration procedure.
 
@@ -704,5 +704,5 @@ index a81559bb1e..9172d4f2b0 100644
  #define REUT_ch_PAT_WDB_CL_MUX_CFG(ch)		_MCMAIN_C(0x4040, ch)
  
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0054-haswell-NRI-Add-function-to-change-margins.patch

@@ -1,7 +1,7 @@
-From 36ec2cfa730ba720ef7ded21cc3e84c47f4e2623 Mon Sep 17 00:00:00 2001
+From dbf0fc28bbb939fe5a90c991b752f790828d462d Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 11:58:59 +0200
-Subject: [PATCH 12/17] haswell NRI: Add function to change margins
+Subject: [PATCH 54/65] haswell NRI: Add function to change margins
 
 Implement a function to change margin parameters. Haswell provides a
 register to apply an offset to margin parameters during training, so
@@ -268,5 +268,5 @@ index 9172d4f2b0..0acafbc826 100644
  
  /* DDR CKE per-channel */
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0055-haswell-NRI-Add-read-MPR-training.patch

@@ -1,7 +1,7 @@
-From 87015f060aa208f37481deef460b3545ce2d757f Mon Sep 17 00:00:00 2001
+From 0a557e3d09a9a53bb085c43e6bdb99fa4cd78b85 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 11:35:49 +0200
-Subject: [PATCH 13/17] haswell NRI: Add read MPR training
+Subject: [PATCH 55/65] haswell NRI: Add read MPR training
 
 Implement read training using DDR3 MPR (Multi-Purpose Register).
 
@@ -328,5 +328,5 @@ index 0acafbc826..6a31d3a32c 100644
  #define REUT_ch_PAT_CADB_MRS(ch)		_MCMAIN_C(0x419c, ch)
  #define REUT_ch_PAT_CADB_MUX_CTRL(ch)		_MCMAIN_C(0x41a0, ch)
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0056-haswell-NRI-Add-write-leveling.patch

@@ -1,7 +1,7 @@
-From ce0ed94f993506e75b711c214b49ba480037e7d3 Mon Sep 17 00:00:00 2001
+From e8f50deac2a671f7ec3958b376c37dd6b9bad5bd Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 12:56:04 +0200
-Subject: [PATCH 14/17] haswell NRI: Add write leveling
+Subject: [PATCH 56/65] haswell NRI: Add write leveling
 
 Implement JEDEC write leveling, which is done in two steps. The first
 step uses the JEDEC procedure to do "fine" write leveling, i.e. align
@@ -685,5 +685,5 @@ index 6a31d3a32c..7c0b5a49de 100644
  #define REUT_ch_MISC_ODT_CTRL(ch)		_MCMAIN_C(0x4194, ch)
  #define REUT_ch_MISC_PAT_CADB_CTRL(ch)		_MCMAIN_C(0x4198, ch)
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0057-haswell-NRI-Add-final-raminit-steps.patch

@@ -1,7 +1,7 @@
-From e30c9c431ef11d87c6f46071ec43cc34391b8349 Mon Sep 17 00:00:00 2001
+From 990ee284d48b66f06adb6c43a96439f7628390f5 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 14:29:05 +0200
-Subject: [PATCH 15/17] haswell NRI: Add final raminit steps
+Subject: [PATCH 57/65] haswell NRI: Add final raminit steps
 
 Implement the remaining raminit steps. Although many training steps are
 missing, this is enough to boot on the Asrock B85M Pro4.
@@ -566,5 +566,5 @@ index 7c0b5a49de..49a215aa71 100644
  #define RCOMP_TIMER		0x5084
  
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0058-Haswell-NRI-Implement-fast-boot-path.patch

@@ -1,7 +1,7 @@
-From 50c9d184cc89cd718c1cb95e1a3cabed24e09e1e Mon Sep 17 00:00:00 2001
+From 63e9aa1f998ebd41b4c638fa66bdb1a6272a9e85 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 13 Apr 2024 01:16:30 +0200
-Subject: [PATCH 16/17] Haswell NRI: Implement fast boot path
+Subject: [PATCH 58/65] Haswell NRI: Implement fast boot path
 
 When the memory configuration hasn't changed, there is no need to do
 full memory training. Instead, boot firmware can use saved training
@@ -718,5 +718,5 @@ index 0000000000..f1f50e3ff8
 +	return RAMINIT_STATUS_SUCCESS;
 +}
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0059-haswell-NRI-Do-sense-amplifier-offset-training.patch

@@ -1,7 +1,7 @@
-From 8528c7aa2a3cfcf0fe494a515a2e531ff0f1dab8 Mon Sep 17 00:00:00 2001
+From c22e06a8ef87f74cc9955ffc259e7052742269c4 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Wed, 17 Apr 2024 13:20:32 +0200
-Subject: [PATCH 17/17] haswell NRI: Do sense amplifier offset training
+Subject: [PATCH 59/65] haswell NRI: Do sense amplifier offset training
 
 Quoting Wikipedia:
 
@@ -472,5 +472,5 @@ index 49a215aa71..1a168a3fc8 100644
  
  #define DQ_CONTROL_1(ch, byte)			_DDRIO_C_R_B(0x0060, ch, 0, byte)
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0060-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch

@@ -1,7 +1,7 @@
-From f52188b46ce60383b67aeea2bda7ec52d631c822 Mon Sep 17 00:00:00 2001
+From c0e95144b426ab323e0397942579261fbb7b922b Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Mon, 12 Aug 2024 02:15:24 +0100
-Subject: [PATCH 1/1] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
+Subject: [PATCH 60/65] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
 
 set it to 96MHz. fixes the following build error when
 building for x4x boards e.g. gigabyte ga-g41m-es2l:
@@ -48,5 +48,5 @@ index 9af063819b..93ba575b95 100644
  	default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
  
 -- 
-2.39.2
+2.39.5
 

config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch

@@ -1,13 +1,12 @@
-From 76a22c32d673f7e9afe66424512035586433a78c Mon Sep 17 00:00:00 2001
+From 66896f156eaade2c01636ac445cfd47afa6a32cc Mon Sep 17 00:00:00 2001
 From: Mate Kukri <kukri.mate@gmail.com>
-Date: Sun, 14 Jul 2024 14:24:12 +0100
+Date: Thu, 24 Oct 2024 18:05:19 +0100
-Subject: [PATCH 1/1] [WIP] OptiPlex 3050 Micro port
+Subject: [PATCH 61/65] [WIP] OptiPlex 3050 Micro port
 
 - Boots Linux
 - SMSC SCH5553 SIO/EC
-  + Early EC init + HWM init implemented
+  + Serial port works
-  + Console on serial port tested
+  + PWM fan control works
-  + TODO: late HWM init for fan control (fan runs at low speed now)
 - Realtek Gigabit LAN works
 - WiFi slot works
 - NVMe SSD slot works
@@ -27,25 +26,25 @@ Subject: [PATCH 1/1] [WIP] OptiPlex 3050 Micro port
 Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2
 Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
 ---
- src/mainboard/dell/optiplex_3050/Kconfig      |  34 +++
+ src/mainboard/dell/optiplex_3050/Kconfig      |  32 ++
  src/mainboard/dell/optiplex_3050/Kconfig.name |   4 +
  src/mainboard/dell/optiplex_3050/Makefile.mk  |   9 +
  src/mainboard/dell/optiplex_3050/acpi/ec.asl  |   3 +
  .../dell/optiplex_3050/acpi/superio.asl       |   3 +
  .../dell/optiplex_3050/board_info.txt         |   7 +
- src/mainboard/dell/optiplex_3050/bootblock.c  | 107 ++++++++
+ src/mainboard/dell/optiplex_3050/bootblock.c  | 107 ++++
  src/mainboard/dell/optiplex_3050/cmos.default |   5 +
- src/mainboard/dell/optiplex_3050/cmos.layout  |  54 ++++
+ src/mainboard/dell/optiplex_3050/cmos.layout  |  54 ++
- .../dell/optiplex_3050/devicetree.cb          | 123 +++++++++
+ .../dell/optiplex_3050/devicetree.cb          | 119 ++++
- src/mainboard/dell/optiplex_3050/dsdt.asl     |  27 ++
+ src/mainboard/dell/optiplex_3050/dsdt.asl     |  27 +
- .../dell/optiplex_3050/gma-mainboard.ads      |  19 ++
+ .../dell/optiplex_3050/gma-mainboard.ads      |  19 +
  .../dell/optiplex_3050/include/early_gpio.h   |  11 +
- .../dell/optiplex_3050/include/gpio.h         | 241 ++++++++++++++++++
+ .../dell/optiplex_3050/include/gpio.h         | 241 ++++++++
- src/mainboard/dell/optiplex_3050/ramstage.c   |  17 ++
+ src/mainboard/dell/optiplex_3050/ramstage.c   | 513 ++++++++++++++++++
- src/mainboard/dell/optiplex_3050/romstage.c   |  26 ++
+ src/mainboard/dell/optiplex_3050/romstage.c   |  26 +
- src/mainboard/dell/optiplex_3050/sch5555_ec.c |  54 ++++
+ src/mainboard/dell/optiplex_3050/sch5555_ec.c |  54 ++
  src/mainboard/dell/optiplex_3050/sch5555_ec.h |  10 +
- 18 files changed, 754 insertions(+)
+ 18 files changed, 1244 insertions(+)
  create mode 100644 src/mainboard/dell/optiplex_3050/Kconfig
  create mode 100644 src/mainboard/dell/optiplex_3050/Kconfig.name
  create mode 100644 src/mainboard/dell/optiplex_3050/Makefile.mk
@@ -67,10 +66,10 @@ Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
 
 diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig
 new file mode 100644
-index 0000000000..763acda0b2
+index 0000000000..2f0dccb98d
 --- /dev/null
 +++ b/src/mainboard/dell/optiplex_3050/Kconfig
-@@ -0,0 +1,34 @@
+@@ -0,0 +1,32 @@
 +## SPDX-License-Identifier: GPL-2.0-only
 +
 +if BOARD_DELL_OPTIPLEX_3050
@@ -84,10 +83,8 @@ index 0000000000..763acda0b2
 +	select HAVE_OPTION_TABLE
 +	# select INTEL_GMA_HAVE_VBT
 +	select MAINBOARD_HAS_LIBGFXINIT
-+	select MAINBOARD_HAS_TPM2
 +	select MAINBOARD_SUPPORTS_KABYLAKE_CPU
 +	select MAINBOARD_SUPPORTS_SKYLAKE_CPU
-+	select MEMORY_MAPPED_TPM
 +	select SKYLAKE_SOC_PCH_H
 +	select SOC_INTEL_KABYLAKE
 +	select SUPERIO_SMSC_SCH555x
@@ -117,7 +114,7 @@ index 0000000000..14eab7f52c
 +	bool "OptiPlex 3050 Micro"
 diff --git a/src/mainboard/dell/optiplex_3050/Makefile.mk b/src/mainboard/dell/optiplex_3050/Makefile.mk
 new file mode 100644
-index 0000000000..c078124332
+index 0000000000..d50ea40879
 --- /dev/null
 +++ b/src/mainboard/dell/optiplex_3050/Makefile.mk
 @@ -0,0 +1,9 @@
@@ -128,7 +125,7 @@ index 0000000000..c078124332
 +
 +romstage-y += romstage.c
 +
-+ramstage-y += ramstage.c
++ramstage-y += ramstage.c sch5555_ec.c
 +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 diff --git a/src/mainboard/dell/optiplex_3050/acpi/ec.asl b/src/mainboard/dell/optiplex_3050/acpi/ec.asl
 new file mode 100644
@@ -347,10 +344,10 @@ index 0000000000..54a5147b7d
 +checksum 392 415 984
 diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb
 new file mode 100644
-index 0000000000..49b2d7f603
+index 0000000000..eb731fe48f
 --- /dev/null
 +++ b/src/mainboard/dell/optiplex_3050/devicetree.cb
-@@ -0,0 +1,123 @@
+@@ -0,0 +1,119 @@
 +## SPDX-License-Identifier: GPL-2.0-only
 +
 +chip soc/intel/skylake
@@ -461,10 +458,6 @@ index 0000000000..49b2d7f603
 +				device pnp 2e.b  off end	# Floppy Controller
 +				device pnp 2e.11 off end	# Parallel Port
 +			end
-+
-+			chip drivers/pc80/tpm
-+				device pnp 0c31.0 on end
-+			end
 +		end
 +
 +		device ref hda on
@@ -798,27 +791,523 @@ index 0000000000..83293c32a9
 +#endif
 diff --git a/src/mainboard/dell/optiplex_3050/ramstage.c b/src/mainboard/dell/optiplex_3050/ramstage.c
 new file mode 100644
-index 0000000000..0badd89620
+index 0000000000..5cf2c81e50
 --- /dev/null
 +++ b/src/mainboard/dell/optiplex_3050/ramstage.c
-@@ -0,0 +1,17 @@
+@@ -0,0 +1,513 @@
 +/* SPDX-License-Identifier: GPL-2.0-only */
 +
++#include <bootstate.h>
++#include <arch/cpuid.h>
++#include <cpu/x86/msr.h>
++#include <soc/gpio.h>
 +#include <soc/ramstage.h>
 +#include "include/gpio.h"
++#include "sch5555_ec.h"
 +
 +void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 +{
 +	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 +}
 +
-+static void init_mainboard(void *chip_info)
++#define FORM_FACTOR_MICRO	0
++#define FORM_FACTOR_SFF		1
++// NOTE: one of these is MT, but 2 and 3 both get the same table anyways
++#define FORM_FACTOR_UNK2	2
++#define FORM_FACTOR_UNK3	3
++
++#define HWM_TAB_ADD_TEMP_TARGET	1
++#define HWM_TAB_PKG_POWER_ANY	0xffff
++
++struct hwm_tab_entry {
++	uint16_t addr;
++	uint8_t val;
++	uint8_t flags;
++	uint16_t pkg_power;
++};
++
++static const struct hwm_tab_entry HWM_TAB_MICRO_BASE[] = {
++	{ 0x005, 0x33, 0, 0xffff },
++	{ 0x018, 0x2f, 0, 0xffff },
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x01a, 0x2f, 0, 0xffff },
++	{ 0x01b, 0x0f, 0, 0xffff },
++	{ 0x057, 0xff, 0, 0xffff },
++	{ 0x059, 0xff, 0, 0xffff },
++	{ 0x05b, 0xff, 0, 0xffff },
++	{ 0x05d, 0xff, 0, 0xffff },
++	{ 0x05f, 0xff, 0, 0xffff },
++	{ 0x061, 0xff, 0, 0xffff },
++	{ 0x06e, 0x00, 0, 0xffff },
++	{ 0x06f, 0x03, 0, 0xffff },
++	{ 0x070, 0x03, 0, 0xffff },
++	{ 0x071, 0x02, 0, 0xffff },
++	{ 0x072, 0x02, 0, 0xffff },
++	{ 0x073, 0x01, 0, 0xffff },
++	{ 0x074, 0x06, 0, 0xffff },
++	{ 0x075, 0x07, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x80, 0, 0xffff },
++	{ 0x082, 0x80, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0xf1, 0, 0xffff },
++	{ 0x086, 0x88, 0, 0xffff },
++	{ 0x087, 0x61, 0, 0xffff },
++	{ 0x088, 0x08, 0, 0xffff },
++	{ 0x089, 0x00, 0, 0xffff },
++	{ 0x08a, 0x73, 0, 0xffff },
++	{ 0x08b, 0x73, 0, 0xffff },
++	{ 0x08c, 0x73, 0, 0xffff },
++	{ 0x090, 0x6d, 0, 0xffff },
++	{ 0x091, 0x7e, 0, 0xffff },
++	{ 0x092, 0x66, 0, 0xffff },
++	{ 0x093, 0xa4, 0, 0xffff },
++	{ 0x094, 0x7c, 0, 0xffff },
++	{ 0x095, 0xa4, 0, 0xffff },
++	{ 0x096, 0xa4, 0, 0xffff },
++	{ 0x097, 0xa4, 0, 0xffff },
++	{ 0x098, 0xa4, 0, 0xffff },
++	{ 0x099, 0xa4, 0, 0xffff },
++	{ 0x09a, 0xa4, 0, 0xffff },
++	{ 0x09b, 0xa4, 0, 0xffff },
++	{ 0x0a0, 0x2e, 0, 0xffff },
++	{ 0x0a1, 0x00, 0, 0xffff },
++	{ 0x0a2, 0x00, 0, 0xffff },
++	{ 0x0ae, 0xa4, 0, 0xffff },
++	{ 0x0af, 0xa4, 0, 0xffff },
++	{ 0x0b0, 0xa4, 0, 0xffff },
++	{ 0x0b1, 0xa4, 0, 0xffff },
++	{ 0x0b2, 0xa4, 0, 0xffff },
++	{ 0x0b3, 0xa4, 0, 0xffff },
++	{ 0x0b6, 0x00, 0, 0xffff },
++	{ 0x0b7, 0x00, 0, 0xffff },
++	{ 0x0d1, 0xff, 0, 0xffff },
++	{ 0x0d6, 0xff, 0, 0xffff },
++	{ 0x0db, 0xff, 0, 0xffff },
++	{ 0x0ea, 0x5c, 0, 0xffff },
++	{ 0x0eb, 0x5c, 0, 0xffff },
++	{ 0x0ef, 0xff, 0, 0xffff },
++	{ 0x0f8, 0x15, 0, 0xffff },
++	{ 0x0f9, 0x00, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x184, 0xff, 0, 0xffff },
++	{ 0x186, 0xff, 0, 0xffff },
++	{ 0x1a1, 0xce, 0, 0xffff },
++	{ 0x1a2, 0x0c, 0, 0xffff },
++	{ 0x1a3, 0x0c, 0, 0xffff },
++	{ 0x1a6, 0x00, 0, 0xffff },
++	{ 0x1a7, 0x00, 0, 0xffff },
++	{ 0x1a8, 0xa4, 0, 0xffff },
++	{ 0x1a9, 0xa4, 0, 0xffff },
++	{ 0x1ab, 0x2d, 0, 0xffff },
++	{ 0x1ac, 0x2d, 0, 0xffff },
++	{ 0x1b1, 0x00, 0, 0xffff },
++	{ 0x1bb, 0x00, 0, 0xffff },
++	{ 0x1bc, 0x00, 0, 0xffff },
++	{ 0x1bd, 0x00, 0, 0xffff },
++	{ 0x1be, 0x01, 0, 0xffff },
++	{ 0x1bf, 0x01, 0, 0xffff },
++	{ 0x1c0, 0x01, 0, 0xffff },
++	{ 0x1c1, 0x01, 0, 0xffff },
++	{ 0x1c2, 0x01, 0, 0xffff },
++	{ 0x280, 0x00, 0, 0xffff },
++	{ 0x281, 0x00, 0, 0xffff },
++	{ 0x282, 0x03, 0, 0xffff },
++	{ 0x283, 0x0a, 0, 0xffff },
++	{ 0x284, 0x80, 0, 0xffff },
++	{ 0x285, 0x03, 0, 0xffff },
++	{ 0x040, 0x01, 0, 0xffff },
++};
++
++static const struct hwm_tab_entry HWM_TAB_MICRO_TEMP80[] = {
++	{ 0x005, 0x33, 0, 0xffff },
++	{ 0x018, 0x2f, 0, 0xffff },
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x01a, 0x2f, 0, 0xffff },
++	{ 0x01b, 0x0f, 0, 0xffff },
++	{ 0x057, 0xff, 0, 0xffff },
++	{ 0x059, 0xff, 0, 0xffff },
++	{ 0x05b, 0xff, 0, 0xffff },
++	{ 0x05d, 0xff, 0, 0xffff },
++	{ 0x05f, 0xff, 0, 0xffff },
++	{ 0x061, 0xff, 0, 0xffff },
++	{ 0x06e, 0x00, 0, 0xffff },
++	{ 0x06f, 0x03, 0, 0xffff },
++	{ 0x070, 0x03, 0, 0xffff },
++	{ 0x071, 0x02, 0, 0xffff },
++	{ 0x072, 0x02, 0, 0xffff },
++	{ 0x073, 0x01, 0, 0xffff },
++	{ 0x074, 0x06, 0, 0xffff },
++	{ 0x075, 0x07, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x80, 0, 0xffff },
++	{ 0x082, 0x80, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0xf6, 0, 0xffff },
++	{ 0x086, 0x88, 0, 0xffff },
++	{ 0x087, 0x61, 0, 0xffff },
++	{ 0x088, 0x08, 0, 0xffff },
++	{ 0x089, 0x00, 0, 0xffff },
++	{ 0x08a, 0x73, 0, 0xffff },
++	{ 0x08b, 0x73, 0, 0xffff },
++	{ 0x08c, 0x73, 0, 0xffff },
++	{ 0x090, 0x6d, 0, 0xffff },
++	{ 0x091, 0x86, 0, 0xffff },
++	{ 0x092, 0x66, 0, 0xffff },
++	{ 0x093, 0xa4, 0, 0xffff },
++	{ 0x094, 0x7c, 0, 0xffff },
++	{ 0x095, 0xa4, 0, 0xffff },
++	{ 0x096, 0xa4, 0, 0xffff },
++	{ 0x097, 0xa4, 0, 0xffff },
++	{ 0x098, 0xa4, 0, 0xffff },
++	{ 0x099, 0xa4, 0, 0xffff },
++	{ 0x09a, 0xa4, 0, 0xffff },
++	{ 0x09b, 0xa4, 0, 0xffff },
++	{ 0x0a0, 0x2e, 0, 0xffff },
++	{ 0x0a1, 0x00, 0, 0xffff },
++	{ 0x0a2, 0x00, 0, 0xffff },
++	{ 0x0ae, 0xa4, 0, 0xffff },
++	{ 0x0af, 0xa4, 0, 0xffff },
++	{ 0x0b0, 0xa4, 0, 0xffff },
++	{ 0x0b1, 0xa4, 0, 0xffff },
++	{ 0x0b2, 0xa4, 0, 0xffff },
++	{ 0x0b3, 0xa4, 0, 0xffff },
++	{ 0x0b6, 0x00, 0, 0xffff },
++	{ 0x0b7, 0x00, 0, 0xffff },
++	{ 0x0d1, 0xff, 0, 0xffff },
++	{ 0x0d6, 0xff, 0, 0xffff },
++	{ 0x0db, 0xff, 0, 0xffff },
++	{ 0x0ea, 0x50, 0, 0xffff },
++	{ 0x0eb, 0x50, 0, 0xffff },
++	{ 0x0ef, 0xff, 0, 0xffff },
++	{ 0x0f8, 0x15, 0, 0xffff },
++	{ 0x0f9, 0x00, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x184, 0xff, 0, 0xffff },
++	{ 0x186, 0xff, 0, 0xffff },
++	{ 0x1a1, 0xce, 0, 0xffff },
++	{ 0x1a2, 0x0c, 0, 0xffff },
++	{ 0x1a3, 0x0c, 0, 0xffff },
++	{ 0x1a6, 0x00, 0, 0xffff },
++	{ 0x1a7, 0x00, 0, 0xffff },
++	{ 0x1a8, 0xa4, 0, 0xffff },
++	{ 0x1a9, 0xa4, 0, 0xffff },
++	{ 0x1ab, 0x2d, 0, 0xffff },
++	{ 0x1ac, 0x2d, 0, 0xffff },
++	{ 0x1b1, 0x00, 0, 0xffff },
++	{ 0x1bb, 0x00, 0, 0xffff },
++	{ 0x1bc, 0x00, 0, 0xffff },
++	{ 0x1bd, 0x00, 0, 0xffff },
++	{ 0x1be, 0x01, 0, 0xffff },
++	{ 0x1bf, 0x01, 0, 0xffff },
++	{ 0x1c0, 0x01, 0, 0xffff },
++	{ 0x1c1, 0x01, 0, 0xffff },
++	{ 0x1c2, 0x01, 0, 0xffff },
++	{ 0x280, 0x00, 0, 0xffff },
++	{ 0x281, 0x00, 0, 0xffff },
++	{ 0x282, 0x03, 0, 0xffff },
++	{ 0x283, 0x0a, 0, 0xffff },
++	{ 0x284, 0x80, 0, 0xffff },
++	{ 0x285, 0x03, 0, 0xffff },
++	{ 0x040, 0x01, 0, 0xffff },
++};
++
++static const struct hwm_tab_entry HWM_TAB_MICRO_EARLY_STEPPING[] = {
++	{ 0x005, 0x33, 0, 0xffff },
++	{ 0x018, 0x2f, 0, 0xffff },
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x01a, 0x2f, 0, 0xffff },
++	{ 0x01b, 0x0f, 0, 0xffff },
++	{ 0x057, 0xff, 0, 0xffff },
++	{ 0x059, 0xff, 0, 0xffff },
++	{ 0x05b, 0xff, 0, 0xffff },
++	{ 0x05d, 0xff, 0, 0xffff },
++	{ 0x05f, 0xff, 0, 0xffff },
++	{ 0x061, 0xff, 0, 0xffff },
++	{ 0x06e, 0x01, 0, 0xffff },
++	{ 0x06f, 0x03, 0, 0xffff },
++	{ 0x070, 0x03, 0, 0xffff },
++	{ 0x071, 0x02, 0, 0xffff },
++	{ 0x072, 0x02, 0, 0xffff },
++	{ 0x073, 0x01, 0, 0xffff },
++	{ 0x074, 0x06, 0, 0xffff },
++	{ 0x075, 0x07, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x80, 0, 0xffff },
++	{ 0x082, 0x80, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0xfd, 0, 0xffff },
++	{ 0x086, 0x60, 0, 0xffff },
++	{ 0x087, 0x50, 0, 0xffff },
++	{ 0x088, 0x08, 0, 0xffff },
++	{ 0x089, 0x00, 0, 0xffff },
++	{ 0x08a, 0x73, 0, 0xffff },
++	{ 0x08b, 0x73, 0, 0xffff },
++	{ 0x08c, 0x73, 0, 0xffff },
++	{ 0x090, 0x6d, 0, 0xffff },
++	{ 0x091, 0x7a, 0, 0xffff },
++	{ 0x092, 0x6b, 0, 0xffff },
++	{ 0x093, 0xa4, 0, 0xffff },
++	{ 0x094, 0x78, 0, 0xffff },
++	{ 0x095, 0xa4, 0, 0xffff },
++	{ 0x096, 0xa4, 0, 0xffff },
++	{ 0x097, 0xa4, 0, 0xffff },
++	{ 0x098, 0xa4, 0, 0xffff },
++	{ 0x099, 0xa4, 0, 0xffff },
++	{ 0x09a, 0xa4, 0, 0xffff },
++	{ 0x09b, 0xa4, 0, 0xffff },
++	{ 0x0a0, 0x2e, 0, 0xffff },
++	{ 0x0a1, 0x00, 0, 0xffff },
++	{ 0x0a2, 0x00, 0, 0xffff },
++	{ 0x0ae, 0xa4, 0, 0xffff },
++	{ 0x0af, 0xa4, 0, 0xffff },
++	{ 0x0b0, 0xa4, 0, 0xffff },
++	{ 0x0b1, 0xa4, 0, 0xffff },
++	{ 0x0b2, 0xa4, 0, 0xffff },
++	{ 0x0b3, 0xa4, 0, 0xffff },
++	{ 0x0b6, 0x00, 0, 0xffff },
++	{ 0x0b7, 0x00, 0, 0xffff },
++	{ 0x0d1, 0xff, 0, 0xffff },
++	{ 0x0d6, 0xff, 0, 0xffff },
++	{ 0x0db, 0xff, 0, 0xffff },
++	{ 0x0ea, 0x64, 0, 0xffff },
++	{ 0x0eb, 0x64, 0, 0xffff },
++	{ 0x0ef, 0xff, 0, 0xffff },
++	{ 0x0f8, 0x15, 0, 0xffff },
++	{ 0x0f9, 0x00, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x184, 0xff, 0, 0xffff },
++	{ 0x186, 0xff, 0, 0xffff },
++	{ 0x1a1, 0xce, 0, 0xffff },
++	{ 0x1a2, 0x0c, 0, 0xffff },
++	{ 0x1a3, 0x0c, 0, 0xffff },
++	{ 0x1a6, 0x00, 0, 0xffff },
++	{ 0x1a7, 0x00, 0, 0xffff },
++	{ 0x1a8, 0xa4, 0, 0xffff },
++	{ 0x1a9, 0xa4, 0, 0xffff },
++	{ 0x1ab, 0x2d, 0, 0xffff },
++	{ 0x1ac, 0x2d, 0, 0xffff },
++	{ 0x1b1, 0x00, 0, 0xffff },
++	{ 0x1bb, 0x00, 0, 0xffff },
++	{ 0x1bc, 0x00, 0, 0xffff },
++	{ 0x1bd, 0x00, 0, 0xffff },
++	{ 0x1be, 0x01, 0, 0xffff },
++	{ 0x1bf, 0x01, 0, 0xffff },
++	{ 0x1c0, 0x01, 0, 0xffff },
++	{ 0x1c1, 0x01, 0, 0xffff },
++	{ 0x1c2, 0x01, 0, 0xffff },
++	{ 0x280, 0x00, 0, 0xffff },
++	{ 0x281, 0x00, 0, 0xffff },
++	{ 0x282, 0x03, 0, 0xffff },
++	{ 0x283, 0x0a, 0, 0xffff },
++	{ 0x284, 0x80, 0, 0xffff },
++	{ 0x285, 0x03, 0, 0xffff },
++	{ 0x040, 0x01, 0, 0xffff },
++};
++
++static const struct hwm_tab_entry HWM_TAB_SFF[] = {
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x040, 0x01, 0, 0xffff },
++	{ 0x072, 0x03, 0, 0xffff },
++	{ 0x075, 0x06, 0, 0xffff },
++	{ 0x07c, 0x00, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x00, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0x59, 0, 0xffff },
++	{ 0x086, 0x6a, 0, 0xffff },
++	{ 0x087, 0xc0, 0, 0xffff },
++	{ 0x08a, 0x33, 0, 0xffff },
++	{ 0x090, 0x77, 0, 0xffff },
++	{ 0x091, 0x66, 0, 0xffff },
++	{ 0x092, 0x94, 0, 0xffff },
++	{ 0x093, 0x90, 0, 0xffff },
++	{ 0x094, 0x68, 0, 0xffff },
++	{ 0x096, 0xa4, 0, 0xffff },
++	{ 0x097, 0xa4, 0, 0xffff },
++	{ 0x098, 0xa4, 0, 0xffff },
++	{ 0x099, 0xa4, 0, 0xffff },
++	{ 0x09a, 0xa4, 0, 0xffff },
++	{ 0x09b, 0xa4, 0, 0xffff },
++	{ 0x0a0, 0x3e, 0, 0xffff },
++	{ 0x0ae, 0x86, 0, 0xffff },
++	{ 0x0af, 0x86, 0, 0xffff },
++	{ 0x0b0, 0xa4, 0, 0xffff },
++	{ 0x0b1, 0xa4, 0, 0xffff },
++	{ 0x0b2, 0x90, 0, 0xffff },
++	{ 0x0b6, 0x48, 0, 0xffff },
++	{ 0x0b7, 0x48, 0, 0xffff },
++	{ 0x0ea, 0x64, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x1b1, 0x48, 0, 0xffff },
++	{ 0x1b8, 0x00, 0, 0xffff },
++	{ 0x1be, 0x95, 0, 0xffff },
++	{ 0x1c1, 0x90, 0, 0xffff },
++	{ 0x1c6, 0x00, 0, 0xffff },
++	{ 0x1c9, 0x00, 0, 0xffff },
++	{ 0x280, 0x68, 0, 0xffff },
++	{ 0x281, 0x10, 0, 0xffff },
++	{ 0x282, 0x03, 0, 0xffff },
++	{ 0x283, 0x0a, 0, 0xffff },
++	{ 0x284, 0x80, 0, 0xffff },
++	{ 0x285, 0x03, 0, 0xffff}
++};
++
++static const struct hwm_tab_entry HWM_TAB_MT[] = {
++	{ 0x005, 0x33, 0, 0xffff },
++	{ 0x018, 0x2f, 0, 0xffff },
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x01a, 0x2f, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x00, 0, 0xffff },
++	{ 0x082, 0x80, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0xb9, 0, 0x0010 },
++	{ 0x086, 0xac, 0, 0x0010 },
++	{ 0x087, 0x87, 0, 0x0010 },
++	{ 0x08a, 0x51, 0, 0x0010 },
++	{ 0x08b, 0x39, 0, 0x0010 },
++	{ 0x090, 0x78, 0, 0xffff },
++	{ 0x091, 0x6a, 0, 0xffff },
++	{ 0x092, 0x8f, 0, 0xffff },
++	{ 0x094, 0x68, 0, 0xffff },
++	{ 0x095, 0x5b, 0, 0xffff },
++	{ 0x096, 0x92, 0, 0xffff },
++	{ 0x097, 0x86, 0, 0xffff },
++	{ 0x098, 0xa4, 0, 0xffff },
++	{ 0x09a, 0x8b, 0, 0xffff },
++	{ 0x0a0, 0x0a, 0, 0xffff },
++	{ 0x0a1, 0x26, 0, 0xffff },
++	{ 0x0a2, 0xd1, 0, 0xffff },
++	{ 0x0ae, 0x7c, 0, 0xffff },
++	{ 0x0af, 0x7c, 0, 0xffff },
++	{ 0x0b0, 0x9a, 0, 0xffff },
++	{ 0x0b3, 0x7c, 0, 0xffff },
++	{ 0x0b6, 0x08, 0, 0xffff },
++	{ 0x0b7, 0x00, 0, 0xffff },
++	{ 0x0ea, 0x64, 0, 0xffff },
++	{ 0x0ef, 0xff, 0, 0xffff },
++	{ 0x0f8, 0x15, 0, 0xffff },
++	{ 0x0f9, 0x00, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x0fd, 0x01, 0, 0xffff },
++	{ 0x1a1, 0x99, 0, 0xffff },
++	{ 0x1a2, 0x00, 0, 0xffff },
++	{ 0x1a4, 0x00, 0, 0xffff },
++	{ 0x1b1, 0x00, 0, 0xffff },
++	{ 0x1be, 0x90, 0, 0xffff },
++	{ 0x280, 0xc4, 0, 0xffff },
++	{ 0x281, 0x09, 0, 0xffff },
++	{ 0x282, 0x0a, 0, 0xffff },
++	{ 0x283, 0x14, 0, 0xffff },
++	{ 0x284, 0x01, 0, 0xffff },
++	{ 0x285, 0x01, 0, 0xffff },
++	{ 0x288, 0x94, 0, 0xffff },
++	{ 0x289, 0x11, 0, 0xffff },
++	{ 0x28a, 0x0a, 0, 0xffff },
++	{ 0x28b, 0x14, 0, 0xffff },
++	{ 0x28c, 0x01, 0, 0xffff },
++	{ 0x28d, 0x01, 0, 0xffff },
++	{ 0x294, 0x24, 0, 0xffff },
++};
++
++static uint8_t get_temp_target(void)
 +{
++	uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff;
++	if (!val)
++		val = 20;
++	return 0x95 - val;
 +}
 +
-+struct chip_operations mainboard_ops = {
++static uint16_t get_pkg_power(void)
-+	.init = init_mainboard,
++{
-+};
++	const unsigned int pkg_power = rdmsr(0x614).lo & 0x7fff;
++	const unsigned int power_unit = 1 << (rdmsr(0x606).lo & 0xf);
++	if (pkg_power / power_unit > 65)
++		return 32;
++	else
++		return 16;
++}
++
++static uint8_t get_core_cnt(void)
++{
++	// Intel describes this CPUID field as:
++	// > Maximum number of addressable IDs for processor cores in the physical package
++	if (cpuid(0).eax >= 4)
++		return cpuid_ext(4, 0).eax >> 26;
++	return 0;
++}
++
++static void apply_hwm_tab(const struct hwm_tab_entry *arr, size_t size)
++{
++	uint8_t temp_target = get_temp_target();
++	uint16_t pkg_power = get_pkg_power();
++
++	printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target);
++	printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power);
++
++	for (size_t i = 0; i < size; ++i) {
++		// Skip entry if it doesn't apply for this package power
++		if (arr[i].pkg_power != pkg_power &&
++		    arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY)
++			continue;
++
++		uint8_t val = arr[i].val;
++
++		// Add temp target to value if requested (current tables never do)
++		if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET)
++			val += temp_target;
++
++		// Perform write
++		sch5555_mbox_write(1, arr[i].addr, val);
++
++	}
++}
++
++static void sch5555_ec_hwm_init(void *arg)
++{
++	uint8_t form_fac_id, saved_2fc, core_cnt;
++
++	printk(BIOS_DEBUG, "OptiPlex 3050 late HWM init\n");
++
++	form_fac_id = gpio_get(GPP_G2) | gpio_get(GPP_G3) << 1;
++	printk(BIOS_DEBUG, "Form Factor ID = %#x\n", form_fac_id);
++
++	saved_2fc = sch5555_mbox_read(1, 0x2fc);
++	sch5555_mbox_write(1, 0x2fc, 0xa0);
++	sch5555_mbox_write(1, 0x2fd, 0x32);
++
++	switch (form_fac_id) {
++	case FORM_FACTOR_MICRO:
++		// CPU stepping <= 3
++		if ((cpuid(1).eax & 0xf) <= 3)
++			apply_hwm_tab(HWM_TAB_MICRO_EARLY_STEPPING, ARRAY_SIZE(HWM_TAB_MICRO_EARLY_STEPPING));
++		// Tjunction == 80
++		else if ((rdmsr(0x1a2).lo >> 16 & 0xff) == 80)
++			apply_hwm_tab(HWM_TAB_MICRO_TEMP80, ARRAY_SIZE(HWM_TAB_MICRO_TEMP80));
++		else
++			apply_hwm_tab(HWM_TAB_MICRO_BASE, ARRAY_SIZE(HWM_TAB_MICRO_BASE));
++		break;
++	case FORM_FACTOR_SFF:
++		apply_hwm_tab(HWM_TAB_SFF, ARRAY_SIZE(HWM_TAB_SFF));
++		break;
++	default:
++		apply_hwm_tab(HWM_TAB_MT, ARRAY_SIZE(HWM_TAB_MT));
++		break;
++	}
++
++	core_cnt = get_core_cnt();
++	printk(BIOS_DEBUG, "CPU Core Count = %#x\n", core_cnt);
++	if (get_core_cnt() > 2) {
++		sch5555_mbox_write(1, 0x9e, 0x30);
++		sch5555_mbox_write(1, 0xeb, sch5555_mbox_read(1, 0xea));
++	}
++
++	sch5555_mbox_write(1, 0x2fc, saved_2fc);
++	sch5555_mbox_read(1, 0xb8);
++}
++
++BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL);
 diff --git a/src/mainboard/dell/optiplex_3050/romstage.c b/src/mainboard/dell/optiplex_3050/romstage.c
 new file mode 100644
 index 0000000000..a4734e5d61

config/coreboot/default/patches/0062-mb-dell-Convert-E6400-into-a-variant.patch

@@ -1,7 +1,7 @@
-From e74fe3cf69a9c44b226359814f0c177090e5a56c Mon Sep 17 00:00:00 2001
+From 0caa5d97b67b2acf571e4fab2b7f85ef3d3a7260 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Thu, 26 Sep 2024 19:48:26 -0600
-Subject: [PATCH 62/63] mb/dell: Convert E6400 into a variant
+Subject: [PATCH 62/65] mb/dell: Convert E6400 into a variant
 
 All the GM45 Dell Latitudes should be nearly identical, so convert the
 E6400 port into a variant so that future ports for the other systems can
@@ -239,5 +239,5 @@ index 0000000000..acc34a2252
 +	end
 +end
 -- 
-2.46.1
+2.39.5
 

config/coreboot/default/patches/0063-mb-dell-gm45_latitudes-Add-E4300-variant.patch

@@ -1,7 +1,7 @@
-From f8c8ab28f22c90e4104b272cb33c890d6fa1e940 Mon Sep 17 00:00:00 2001
+From bc9836ac2708687dfe43656adba2833493fa4199 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Thu, 26 Sep 2024 19:51:25 -0600
-Subject: [PATCH 63/63] mb/dell/gm45_latitudes: Add E4300 variant
+Subject: [PATCH 63/65] mb/dell/gm45_latitudes: Add E4300 variant
 
 Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -328,5 +328,5 @@ index 0000000000..20dfa245fb
 +	end
 +end
 -- 
-2.46.1
+2.39.5
 

config/coreboot/default/patches/0064-dell-optiplex_3050-add-hda_verb.c.patch

@@ -1,7 +1,7 @@
-From 6731fef7759f4c67a6d0e85d16de9d99302c9b49 Mon Sep 17 00:00:00 2001
+From 782562bca3d9904e1e34f2cc6089876412b276cd Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sun, 6 Oct 2024 17:25:27 +0100
-Subject: [PATCH 1/1] dell/optiplex_3050: add hda_verb.c
+Subject: [PATCH 64/65] dell/optiplex_3050: add hda_verb.c
 
 Configured for the line jack at the front of the machine.
 
@@ -10,16 +10,16 @@ Based on dumps from the vendor BIOS.
 Signed-off-by: Leah Rowe <info@minifree.org>
 ---
  src/mainboard/dell/optiplex_3050/Kconfig     |  1 +
- src/mainboard/dell/optiplex_3050/Makefile.mk |  2 +
+ src/mainboard/dell/optiplex_3050/Makefile.mk |  3 +-
  src/mainboard/dell/optiplex_3050/hda_verb.c  | 90 ++++++++++++++++++++
- 3 files changed, 93 insertions(+)
+ 3 files changed, 93 insertions(+), 1 deletion(-)
  create mode 100644 src/mainboard/dell/optiplex_3050/hda_verb.c
 
 diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig
-index 763acda0b2..777e29745a 100644
+index 2f0dccb98d..eab6034158 100644
 --- a/src/mainboard/dell/optiplex_3050/Kconfig
 +++ b/src/mainboard/dell/optiplex_3050/Kconfig
-@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS
+@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
  	select SKYLAKE_SOC_PCH_H
  	select SOC_INTEL_KABYLAKE
  	select SUPERIO_SMSC_SCH555x
@@ -28,14 +28,15 @@ index 763acda0b2..777e29745a 100644
  config CBFS_SIZE
  	default 0x900000
 diff --git a/src/mainboard/dell/optiplex_3050/Makefile.mk b/src/mainboard/dell/optiplex_3050/Makefile.mk
-index c078124332..1e2626967a 100644
+index d50ea40879..90b3cc4c48 100644
 --- a/src/mainboard/dell/optiplex_3050/Makefile.mk
 +++ b/src/mainboard/dell/optiplex_3050/Makefile.mk
-@@ -6,4 +6,6 @@ bootblock-y += sch5555_ec.c
+@@ -5,5 +5,6 @@ bootblock-y += sch5555_ec.c
+ 
  romstage-y += romstage.c
  
- ramstage-y += ramstage.c
+-ramstage-y += ramstage.c sch5555_ec.c
-+ramstage-y += hda_verb.c
++ramstage-y += ramstage.c sch5555_ec.c hda_verb.c
 +
  ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 diff --git a/src/mainboard/dell/optiplex_3050/hda_verb.c b/src/mainboard/dell/optiplex_3050/hda_verb.c

config/coreboot/default/patches/0065-dell-optiplex_3050-Add-data.vbt.patch

@@ -1,7 +1,7 @@
-From bfce6c7e9464daa2756e34678d27e38946162132 Mon Sep 17 00:00:00 2001
+From 60de0b27075ef9cc8339896e769e4231a43ceeea Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sun, 6 Oct 2024 23:48:05 +0100
-Subject: [PATCH 1/1] dell/optiplex_3050: Add data.vbt
+Subject: [PATCH 65/65] dell/optiplex_3050: Add data.vbt
 
 Signed-off-by: Leah Rowe <info@minifree.org>
 ---
@@ -11,10 +11,10 @@ Signed-off-by: Leah Rowe <info@minifree.org>
  create mode 100644 src/mainboard/dell/optiplex_3050/data.vbt
 
 diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig
-index 777e29745a..c978626d55 100644
+index eab6034158..523a160ae3 100644
 --- a/src/mainboard/dell/optiplex_3050/Kconfig
 +++ b/src/mainboard/dell/optiplex_3050/Kconfig
-@@ -19,6 +19,8 @@ config BOARD_SPECIFIC_OPTIONS
+@@ -17,6 +17,8 @@ config BOARD_SPECIFIC_OPTIONS
  	select SOC_INTEL_KABYLAKE
  	select SUPERIO_SMSC_SCH555x
  	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
@@ -23,7 +23,7 @@ index 777e29745a..c978626d55 100644
  
  config CBFS_SIZE
  	default 0x900000
-@@ -29,6 +31,9 @@ config MAINBOARD_DIR
+@@ -27,6 +29,9 @@ config MAINBOARD_DIR
  config MAINBOARD_PART_NUMBER
  	default "OptiPlex 3050 Micro"
  

config/coreboot/dell3050micro_fsp_16mb/config/libgfxinit_corebootfb

@@ -140,7 +140,6 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_MAX_SOCKET=1
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
-CONFIG_TPM_PIRQ=0x0
 CONFIG_USE_PM_ACPI_TIMER=y
 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
 # CONFIG_BOARD_DELL_E4300 is not set
@@ -606,8 +605,6 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_MEMORY_MAPPED_TPM=y
-CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
 CONFIG_DRIVERS_MTK_WIFI=y
@@ -632,10 +629,6 @@ CONFIG_DRIVERS_MTK_WIFI=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
-# CONFIG_TPM1 is not set
-# CONFIG_TPM2 is not set
-CONFIG_MAINBOARD_HAS_TPM2=y
-# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2

config/coreboot/dell3050micro_fsp_16mb/config/libgfxinit_txtmode

@@ -138,7 +138,6 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_MAX_SOCKET=1
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
-CONFIG_TPM_PIRQ=0x0
 CONFIG_USE_PM_ACPI_TIMER=y
 # CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
 # CONFIG_BOARD_DELL_E4300 is not set
@@ -602,8 +601,6 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_MEMORY_MAPPED_TPM=y
-CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
@@ -629,10 +626,6 @@ CONFIG_DRIVERS_MTK_WIFI=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
-# CONFIG_TPM1 is not set
-# CONFIG_TPM2 is not set
-CONFIG_MAINBOARD_HAS_TPM2=y
-# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2