rebase haswell nri patches to coreboot/default

scrap the haswell tree. handle mrc- and nri-based haswell
configurations from the same default coreboot tree

this means that it will now be possible to use it on the
dell 9020 sff/mt ports

only txtmode configs were available before, on libremrc
setups for w541/t440p. because the grub payload was added,
i've now added the corebootfb configs.

the libremrc configs have been re-done, by re-copying the
mrc ones and then turning off mrc, instead enabling nri

Signed-off-by: Leah Rowe <leah@libreboot.org>

config/coreboot/default/patches/0043-haswell-NRI-Initialise-MPLL.patch

@@ -1,7 +1,7 @@
-From 77a89d55ab7a715dc20c34a6edacaaf781b56087 Mon Sep 17 00:00:00 2001
+From f3c5218c6d7e211c9e8425e5e71cda76a7de1fad Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 14:36:10 +0200
-Subject: [PATCH 11/26] haswell NRI: Initialise MPLL
+Subject: [PATCH 01/15] haswell NRI: Initialise MPLL
 
 Add code to initialise the MPLL (Memory PLL). The procedure is similar
 to the one for Sandy/Ivy Bridge, but it is not worth factoring out.
@@ -9,20 +9,20 @@ to the one for Sandy/Ivy Bridge, but it is not worth factoring out.
 Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- .../intel/haswell/native_raminit/Makefile.inc |   2 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   2 +
  .../intel/haswell/native_raminit/init_mpll.c  | 210 ++++++++++++++++++
  .../haswell/native_raminit/io_comp_control.c  |  22 ++
- .../haswell/native_raminit/raminit_main.c     |   1 +
+ .../haswell/native_raminit/raminit_main.c     |   3 +-
  .../haswell/native_raminit/raminit_native.h   |  11 +
  .../intel/haswell/registers/mchbar.h          |   3 +
- 6 files changed, 249 insertions(+)
+ 6 files changed, 250 insertions(+), 1 deletion(-)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/init_mpll.c
  create mode 100644 src/northbridge/intel/haswell/native_raminit/io_comp_control.c
 
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index ebf7abc6ec..c125d84f0b 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -1,5 +1,7 @@
  ## SPDX-License-Identifier: GPL-2.0-or-later
  
@@ -276,13 +276,15 @@ index 0000000000..7e96c08938
 +	return RAMINIT_STATUS_POLL_TIMEOUT;
 +}
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 2d2cfa48bb..09545422c0 100644
+index b06330c4eb..09545422c0 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -21,6 +21,7 @@ struct task_entry {
+@@ -20,7 +20,8 @@ struct task_entry {
+ };
  
  static const struct task_entry cold_boot[] = {
- 	{ collect_spd_info,                                       true, "PROCSPD",    },
+-	{ collect_spd_info,           true, "PROCSPD",    },
++	{ collect_spd_info,                                       true, "PROCSPD",    },
 +	{ initialise_mpll,                                        true, "INITMPLL",   },
  };
  

config/coreboot/default/patches/0044-haswell-NRI-Post-process-selected-timings.patch

@@ -1,7 +1,7 @@
-From faabed9ca8974b2e7192c55b59a9d28d75e72df6 Mon Sep 17 00:00:00 2001
+From e344871e519441d1f7bc6891ca1eda911e3e4bf5 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 16:29:55 +0200
-Subject: [PATCH 12/26] haswell NRI: Post-process selected timings
+Subject: [PATCH 02/15] haswell NRI: Post-process selected timings
 
 Once the MPLL has been initialised, convert the timings from the SPD to
 be in DCLKs, which is what the hardware expects. In addition, calculate
@@ -10,7 +10,7 @@ the values for tREFI and tXP.
 Change-Id: Id02caf858f75b9e08016762b3aefda282b274386
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../haswell/native_raminit/lookup_timings.c   |  62 +++++++++++
  .../haswell/native_raminit/raminit_main.c     |   1 +
  .../haswell/native_raminit/raminit_native.h   |   8 ++
@@ -18,10 +18,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  5 files changed, 172 insertions(+)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/lookup_timings.c
 
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index c125d84f0b..2769e0bbb4 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -1,5 +1,6 @@
  ## SPDX-License-Identifier: GPL-2.0-or-later
  
@@ -137,7 +137,7 @@ index a54581abc7..01e5ed1bd6 100644
 +
  #endif
 diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
-index dbe02c72d0..becbea0725 100644
+index 2dab8504c4..9ba695fb64 100644
 --- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
 +++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
 @@ -204,3 +204,103 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl)

config/coreboot/default/patches/0045-haswell-NRI-Configure-initial-MC-settings.patch

@@ -1,7 +1,7 @@
-From 1b0b17d85256193de825fa7ff0e04767c818f2fc Mon Sep 17 00:00:00 2001
+From 5d39edaa35e2dc5c3bd0e5b2e8bf821f5f6ff90c Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 17:22:07 +0200
-Subject: [PATCH 13/26] haswell NRI: Configure initial MC settings
+Subject: [PATCH 03/15] haswell NRI: Configure initial MC settings
 
 Program initial memory controller settings. Many of these values will be
 adjusted later during training.
@@ -9,7 +9,7 @@ adjusted later during training.
 Change-Id: If33846b51cb1bab5d0458fe626e13afb1bdc900e
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- .../intel/haswell/native_raminit/Makefile.inc |   2 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   2 +
  .../haswell/native_raminit/configure_mc.c     | 822 ++++++++++++++++++
  .../haswell/native_raminit/raminit_main.c     |   2 +
  .../haswell/native_raminit/raminit_native.h   | 101 +++
@@ -21,10 +21,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  create mode 100644 src/northbridge/intel/haswell/native_raminit/reg_structs.h
  create mode 100644 src/northbridge/intel/haswell/native_raminit/timings_refresh.c
 
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index 2769e0bbb4..fc55277a65 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -1,8 +1,10 @@
  ## SPDX-License-Identifier: GPL-2.0-or-later
  

config/coreboot/default/patches/0046-haswell-NRI-Add-timings-refresh-programming.patch

@@ -1,7 +1,7 @@
-From b64d728bfe7c8ee44af252338257e95d87864659 Mon Sep 17 00:00:00 2001
+From 136a9f660bda9cb515cbbe1e859bc68e7aa04d92 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 20:59:58 +0200
-Subject: [PATCH 14/26] haswell NRI: Add timings/refresh programming
+Subject: [PATCH 04/15] haswell NRI: Add timings/refresh programming
 
 Program the registers with timing and refresh parameters.
 

config/coreboot/default/patches/0047-haswell-NRI-Program-memory-map.patch

@@ -1,7 +1,7 @@
-From 89ff35083af68d1b24c1633886202ecc153af67d Mon Sep 17 00:00:00 2001
+From f2f47233a17045d1fb2338ca62ce0b107fbdf765 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 21:24:50 +0200
-Subject: [PATCH 15/26] haswell NRI: Program memory map
+Subject: [PATCH 05/15] haswell NRI: Program memory map
 
 This is very similar to Sandy/Ivy Bridge, except that there's several
 registers to program in GDXCBAR. One of these GDXCBAR registers has a
@@ -12,7 +12,7 @@ bit was the only reason why native raminit did not work.
 Change-Id: I3af73a018a7ba948701a542e661e7fefd57591fe
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../intel/haswell/native_raminit/memory_map.c | 183 ++++++++++++++++++
  .../haswell/native_raminit/raminit_main.c     |   1 +
  .../haswell/native_raminit/raminit_native.h   |   1 +
@@ -20,10 +20,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  5 files changed, 188 insertions(+)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/memory_map.c
 
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index fc55277a65..37d527e972 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -4,6 +4,7 @@ romstage-y += configure_mc.c
  romstage-y += lookup_timings.c
  romstage-y += init_mpll.c

config/coreboot/default/patches/0048-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch

@@ -1,7 +1,7 @@
-From d24def01ec15f41a48331ef1e236270b2df90b84 Mon Sep 17 00:00:00 2001
+From bf6173834e306cec9c1086bc7189f60ddfd956ef Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 21:49:40 +0200
-Subject: [PATCH 16/26] haswell NRI: Add DDR3 JEDEC reset and init
+Subject: [PATCH 06/15] haswell NRI: Add DDR3 JEDEC reset and init
 
 Implement JEDEC reset and init sequence for DDR3. The MRS commands are
 issued through the REUT (Robust Electrical Unified Testing) hardware.
@@ -9,7 +9,7 @@ issued through the REUT (Robust Electrical Unified Testing) hardware.
 Change-Id: I2a0c066537021b587599228086727cb1e041bff5
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- .../intel/haswell/native_raminit/Makefile.inc |   3 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   3 +
  .../intel/haswell/native_raminit/ddr3.c       | 217 ++++++++++++++++++
  .../haswell/native_raminit/io_comp_control.c  |  19 ++
  .../haswell/native_raminit/jedec_reset.c      | 120 ++++++++++
@@ -24,10 +24,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  create mode 100644 src/northbridge/intel/haswell/native_raminit/jedec_reset.c
  create mode 100644 src/northbridge/intel/haswell/native_raminit/reut.c
 
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index 37d527e972..e9212df9e6 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -1,11 +1,14 @@
  ## SPDX-License-Identifier: GPL-2.0-or-later
  
@@ -1021,7 +1021,7 @@ index 2acc5cbbc8..4fc78a7f43 100644
  
  /* MCDECS */
 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
-index 74b4d50017..16bef5032a 100644
+index 07f4b9dc16..5b3696347c 100644
 --- a/src/southbridge/intel/lynxpoint/pch.h
 +++ b/src/southbridge/intel/lynxpoint/pch.h
 @@ -586,6 +586,8 @@ void mainboard_config_rcba(void);

config/coreboot/default/patches/0049-haswell-NRI-Add-pre-training-steps.patch

@@ -1,7 +1,7 @@
-From 42e43eb210bbb172af8e5ad064326c4570be8654 Mon Sep 17 00:00:00 2001
+From 1992c1119e36e7cdbfb676dc167157b0df22f7a4 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 23:12:18 +0200
-Subject: [PATCH 17/26] haswell NRI: Add pre-training steps
+Subject: [PATCH 07/15] haswell NRI: Add pre-training steps
 
 Implement pre-training steps, which consist of enabling ECC I/O and
 filling the WDB (Write Data Buffer, stores test patterns) through a
@@ -10,7 +10,7 @@ magic LDAT port.
 Change-Id: Ie2e09e3b218c4569ed8de5c5e1b05d491032e0f1
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../haswell/native_raminit/raminit_main.c     |  34 ++++
  .../haswell/native_raminit/raminit_native.h   |  24 +++
  .../haswell/native_raminit/reg_structs.h      |  45 +++++
@@ -19,10 +19,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  6 files changed, 272 insertions(+)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/setup_wdb.c
 
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index e9212df9e6..8d7d4e4db0 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -10,5 +10,6 @@ romstage-y += memory_map.c
  romstage-y += raminit_main.c
  romstage-y += raminit_native.c

config/coreboot/default/patches/0050-haswell-NRI-Add-REUT-I-O-test-library.patch

@@ -1,14 +1,14 @@
-From f4dd460d609276de7cb7db91f145a404451a2301 Mon Sep 17 00:00:00 2001
+From 9427dcddf5d8ee60c8d272344f10fb440dbd45dd Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 00:11:29 +0200
-Subject: [PATCH 18/26] haswell NRI: Add REUT I/O test library
+Subject: [PATCH 08/15] haswell NRI: Add REUT I/O test library
 
 Implement a library to run I/O tests using the REUT hardware.
 
 Change-Id: Id7b207cd0a3989ddd23c88c6b1f0cfa79d2c861f
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../haswell/native_raminit/raminit_native.h   | 110 +++
  .../haswell/native_raminit/reg_structs.h      | 121 +++
  .../intel/haswell/native_raminit/testing_io.c | 742 ++++++++++++++++++
@@ -16,10 +16,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  5 files changed, 1004 insertions(+)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/testing_io.c
 
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index 8d7d4e4db0..6e1b365602 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -12,4 +12,5 @@ romstage-y += raminit_native.c
  romstage-y += reut.c
  romstage-y += setup_wdb.c

config/coreboot/default/patches/0051-haswell-NRI-Add-range-tracking-library.patch

@@ -1,7 +1,7 @@
-From 9fba0468e75877cbda62f5eaeef1946d6489a8f9 Mon Sep 17 00:00:00 2001
+From 3cd11e7e31e0416ead9782213d582aefc6461e94 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 00:56:00 +0200
-Subject: [PATCH 19/26] haswell NRI: Add range tracking library
+Subject: [PATCH 09/15] haswell NRI: Add range tracking library
 
 Implement a small library used to keep track of passing ranges. This
 will be used by 1D training algorithms when margining some parameter.
@@ -9,17 +9,17 @@ will be used by 1D training algorithms when margining some parameter.
 Change-Id: I8718e85165160afd7c0c8e730b5ce6c9c00f8a60
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../intel/haswell/native_raminit/ranges.c     | 109 ++++++++++++++++++
  .../intel/haswell/native_raminit/ranges.h     |  68 +++++++++++
  3 files changed, 178 insertions(+)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.c
  create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.h
 
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index 6e1b365602..2da950771d 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -9,6 +9,7 @@ romstage-y += io_comp_control.c
  romstage-y += memory_map.c
  romstage-y += raminit_main.c

config/coreboot/default/patches/0052-haswell-NRI-Add-library-to-change-margins.patch

@@ -1,24 +1,24 @@
-From 54cfbe4cf53d16f747bfcfadd20445a0f5f1e5db Mon Sep 17 00:00:00 2001
+From 9d416f00d53bda9f074b9f843fef4a6d4537202a Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 01:11:03 +0200
-Subject: [PATCH 20/26] haswell NRI: Add library to change margins
+Subject: [PATCH 10/15] haswell NRI: Add library to change margins
 
 Implement a library to change Rx/Tx margins. It will be expanded later.
 
 Change-Id: I0b55aba428d8b4d4e16d2fbdec57235ce3ce8adf
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../haswell/native_raminit/change_margin.c    | 154 ++++++++++++++++++
  .../haswell/native_raminit/raminit_native.h   |  50 ++++++
  .../intel/haswell/registers/mchbar.h          |   9 +
  4 files changed, 214 insertions(+)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/change_margin.c
 
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index 2da950771d..ebe9e9b762 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -1,5 +1,6 @@
  ## SPDX-License-Identifier: GPL-2.0-or-later
  

config/coreboot/default/patches/0053-haswell-NRI-Add-RcvEn-training.patch

@@ -1,14 +1,14 @@
-From ac8843553af34855d0331554c03280e66c4ea582 Mon Sep 17 00:00:00 2001
+From 770d4ea91297f76038e9351f4611def640df2137 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 00:05:41 +0200
-Subject: [PATCH 21/26] haswell NRI: Add RcvEn training
+Subject: [PATCH 11/15] haswell NRI: Add RcvEn training
 
 Implement the RcvEn (Receive Enable) calibration procedure.
 
 Change-Id: Ifbfa520f3e0486c56d0988ce67af2ddb9cf29888
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../haswell/native_raminit/raminit_main.c     |   1 +
  .../haswell/native_raminit/raminit_native.h   |  14 +
  .../haswell/native_raminit/reg_structs.h      |  13 +
@@ -17,10 +17,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  6 files changed, 593 insertions(+)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
 
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index ebe9e9b762..e2fbfb4211 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -16,3 +16,4 @@ romstage-y += setup_wdb.c
  romstage-y += spd_bitmunching.c
  romstage-y += testing_io.c

config/coreboot/default/patches/0054-haswell-NRI-Add-function-to-change-margins.patch

@@ -1,7 +1,7 @@
-From 8c3874195c0fc1af9d0b84611496689da1c19d8c Mon Sep 17 00:00:00 2001
+From be7b1c72cff3403ecfd746255fccb80c8cee6403 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 11:58:59 +0200
-Subject: [PATCH 22/26] haswell NRI: Add function to change margins
+Subject: [PATCH 12/15] haswell NRI: Add function to change margins
 
 Implement a function to change margin parameters. Haswell provides a
 register to apply an offset to margin parameters during training, so

config/coreboot/default/patches/0055-haswell-NRI-Add-read-MPR-training.patch

@@ -1,14 +1,14 @@
-From 6781cec818501f7afd6ee26464fd4556ac3068cb Mon Sep 17 00:00:00 2001
+From ec3dd2a40834e363a5ddaef5e8093e1baa1af56e Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 11:35:49 +0200
-Subject: [PATCH 23/26] haswell NRI: Add read MPR training
+Subject: [PATCH 13/15] haswell NRI: Add read MPR training
 
 Implement read training using DDR3 MPR (Multi-Purpose Register).
 
 Change-Id: Id17cb2c4c399ac9bcc937b595b58f863c152461b
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../haswell/native_raminit/raminit_main.c     |   1 +
  .../haswell/native_raminit/raminit_native.h   |   4 +
  .../haswell/native_raminit/train_read_mpr.c   | 240 ++++++++++++++++++
@@ -16,10 +16,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  5 files changed, 247 insertions(+), 1 deletion(-)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
 
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index e2fbfb4211..c442be0728 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -16,4 +16,5 @@ romstage-y += setup_wdb.c
  romstage-y += spd_bitmunching.c
  romstage-y += testing_io.c

config/coreboot/default/patches/0056-haswell-NRI-Add-write-leveling.patch

@@ -1,7 +1,7 @@
-From 20fe4fa852d3e13851a01b51dc984ec5976c864e Mon Sep 17 00:00:00 2001
+From f091b29ba192afe0eb90a737613ec0735c876830 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 12:56:04 +0200
-Subject: [PATCH 24/26] haswell NRI: Add write leveling
+Subject: [PATCH 14/15] haswell NRI: Add write leveling
 
 Implement JEDEC write leveling, which is done in two steps. The first
 step uses the JEDEC procedure to do "fine" write leveling, i.e. align
@@ -11,7 +11,7 @@ read-write test to correct "coarse" cycle errors.
 Change-Id: I27678523fe22c38173a688e2a4751c259a20f009
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../haswell/native_raminit/raminit_main.c     |   1 +
  .../haswell/native_raminit/raminit_native.h   |  10 +
  .../train_jedec_write_leveling.c              | 580 ++++++++++++++++++
@@ -19,10 +19,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  5 files changed, 594 insertions(+)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
 
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index c442be0728..40c2f5e014 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -16,5 +16,6 @@ romstage-y += setup_wdb.c
  romstage-y += spd_bitmunching.c
  romstage-y += testing_io.c

config/coreboot/default/patches/0057-haswell-NRI-Add-final-raminit-steps.patch

@@ -1,7 +1,7 @@
-From d041b14f3af69db5f4598c84e3f53c9cd572ffb5 Mon Sep 17 00:00:00 2001
+From 94230b02f22d871af5de5c83e2efc6204394475e Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 14:29:05 +0200
-Subject: [PATCH 25/26] haswell NRI: Add final raminit steps
+Subject: [PATCH 15/15] haswell NRI: Add final raminit steps
 
 Implement the remaining raminit steps. Although many training steps are
 missing, this is enough to boot on the Asrock B85M Pro4.
@@ -10,7 +10,7 @@ Change-Id: I94f3b65f0218d4da4fda4d84592dfd91f77f8f21
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
  src/northbridge/intel/haswell/Kconfig         |   4 +-
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../haswell/native_raminit/activate_mc.c      | 388 ++++++++++++++++++
  .../haswell/native_raminit/raminit_main.c     |   5 +-
  .../haswell/native_raminit/raminit_native.c   |   5 +-
@@ -21,10 +21,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  create mode 100644 src/northbridge/intel/haswell/native_raminit/activate_mc.c
 
 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
-index b659bf6d98..61f2a3c64c 100644
+index 4b83a25bc1..c6ab27184e 100644
 --- a/src/northbridge/intel/haswell/Kconfig
 +++ b/src/northbridge/intel/haswell/Kconfig
-@@ -10,12 +10,12 @@ config NORTHBRIDGE_INTEL_HASWELL
+@@ -11,12 +11,12 @@ config NORTHBRIDGE_INTEL_HASWELL
  if NORTHBRIDGE_INTEL_HASWELL
  
  config USE_NATIVE_RAMINIT
@@ -39,10 +39,10 @@ index b659bf6d98..61f2a3c64c 100644
  
  config HASWELL_VBOOT_IN_BOOTBLOCK
  	depends on VBOOT
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 index 40c2f5e014..d97da72890 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
 @@ -1,5 +1,6 @@
  ## SPDX-License-Identifier: GPL-2.0-or-later
  
@@ -466,7 +466,7 @@ index 1ff23be615..3a65fb01fb 100644
 -	die("NATIVE RAMINIT: More Magic (tm) required.\n");
  }
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index bd9bc8e692..1ea729b23d 100644
+index ffb5e825f0..6bf7e7cdfb 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
 @@ -200,8 +200,6 @@ void perform_raminit(const int s3resume)
@@ -478,7 +478,7 @@ index bd9bc8e692..1ea729b23d 100644
  		intel_early_me_init_done(me_status);
  	}
  
-@@ -217,7 +215,8 @@ void perform_raminit(const int s3resume)
+@@ -215,7 +213,8 @@ void perform_raminit(const int s3resume)
  	}
  
  	/* Save training data on non-S3 resumes */

config/coreboot/default/patches/0058-haswell-NRI-include-commonlib-bsd-clamp.h.patch

@@ -0,0 +1,109 @@
+From 0310d8b3fcf8f305f655dacc3322de60bdc2adc4 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Mon, 8 Apr 2024 00:38:18 +0100
+Subject: [PATCH 1/1] haswell NRI: include commonlib/bsd/clamp.h
+
+the location of clamp.h changed. these sources were rebased
+from an older coreboot revision. update to match new code.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/northbridge/intel/haswell/native_raminit/change_margin.c   | 2 +-
+ src/northbridge/intel/haswell/native_raminit/configure_mc.c    | 2 +-
+ src/northbridge/intel/haswell/native_raminit/init_mpll.c       | 2 +-
+ src/northbridge/intel/haswell/native_raminit/io_comp_control.c | 2 +-
+ src/northbridge/intel/haswell/native_raminit/lookup_timings.c  | 2 +-
+ src/northbridge/intel/haswell/native_raminit/timings_refresh.c | 2 +-
+ src/northbridge/intel/haswell/native_raminit/train_read_mpr.c  | 2 +-
+ 7 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
+index 4ba9cfa5c6..299c44a6b0 100644
+--- a/src/northbridge/intel/haswell/native_raminit/change_margin.c
++++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
+@@ -1,7 +1,7 @@
+ /* SPDX-License-Identifier: GPL-2.0-or-later */
+ 
+ #include <assert.h>
+-#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
+ #include <console/console.h>
+ #include <delay.h>
+ #include <northbridge/intel/haswell/haswell.h>
+diff --git a/src/northbridge/intel/haswell/native_raminit/configure_mc.c b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
+index 2a667b075b..003fa0e941 100644
+--- a/src/northbridge/intel/haswell/native_raminit/configure_mc.c
++++ b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
+@@ -1,7 +1,7 @@
+ /* SPDX-License-Identifier: GPL-2.0-or-later */
+ 
+ #include <assert.h>
+-#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
+ #include <console/console.h>
+ #include <delay.h>
+ #include <lib.h>
+diff --git a/src/northbridge/intel/haswell/native_raminit/init_mpll.c b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
+index 2faa183724..1f3f2c29a9 100644
+--- a/src/northbridge/intel/haswell/native_raminit/init_mpll.c
++++ b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-or-later */
+ 
+-#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
+ #include <console/console.h>
+ #include <delay.h>
+ #include <device/pci_ops.h>
+diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
+index ad8c848e57..8a55fd81b2 100644
+--- a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
++++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-or-later */
+ 
+-#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
+ #include <console/console.h>
+ #include <northbridge/intel/haswell/haswell.h>
+ #include <timer.h>
+diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
+index afe2c615d2..b8d6c1ef40 100644
+--- a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
++++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-or-later */
+ 
+-#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
+ #include <types.h>
+ 
+ #include "raminit_native.h"
+diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
+index 20a05b359b..820bb336b0 100644
+--- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
++++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
+@@ -1,7 +1,7 @@
+ /* SPDX-License-Identifier: GPL-2.0-or-later */
+ 
+ #include <assert.h>
+-#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
+ #include <console/console.h>
+ #include <delay.h>
+ #include <device/pci_ops.h>
+diff --git a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
+index 0225e1a384..86f79942d3 100644
+--- a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
++++ b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-or-later */
+ 
+-#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
+ #include <console/console.h>
+ #include <delay.h>
+ #include <northbridge/intel/haswell/haswell.h>
+-- 
+2.39.2
+

config/coreboot/default/patches/0059-haswell-NRI-mitigate-compiler-warnings.patch

@@ -0,0 +1,81 @@
+From 2728c87b7f792aa8e4db29d4dc3d2d2f71f6dafd Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Mon, 8 Apr 2024 00:54:44 +0100
+Subject: [PATCH 1/1] haswell NRI: mitigate compiler warnings
+
+Random -Werror warnings. I'd rather patch these up
+than disable warnings-as-errors in the code.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ .../intel/haswell/native_raminit/raminit_native.h            | 1 +
+ src/northbridge/intel/haswell/native_raminit/reut.c          | 5 +++--
+ src/northbridge/intel/haswell/native_raminit/testing_io.c    | 2 +-
+ .../intel/haswell/native_raminit/timings_refresh.c           | 2 +-
+ 4 files changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index 98e39cb76e..76a74d6569 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -397,6 +397,7 @@ static inline void tick_delay(const uint32_t delay)
+ 	/* Just perform reads to a random register */
+ 	for (uint32_t start = 0; start <= delay; start++)
+ 		junk = mchbar_read32(REUT_ERR_DATA_STATUS);
++	(void)junk; /* mitigate -Werror=unused-but-set-variable */
+ }
+ 
+ /*
+diff --git a/src/northbridge/intel/haswell/native_raminit/reut.c b/src/northbridge/intel/haswell/native_raminit/reut.c
+index c55cdd9c7e..c861528a92 100644
+--- a/src/northbridge/intel/haswell/native_raminit/reut.c
++++ b/src/northbridge/intel/haswell/native_raminit/reut.c
+@@ -153,7 +153,7 @@ enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_
+ {
+ 	/** TODO: Issuing ZQ commands differs for LPDDR **/
+ 	if (ctrl->lpddr)
+-		die("%s: LPDDR not yet supported in ZQ calibration\n");
++		die("LPDDR not yet supported in ZQ calibration\n");
+ 
+ 	uint8_t opcode; /* NOTE: Only used for LPDDR */
+ 	uint16_t zq = 0;
+@@ -173,8 +173,9 @@ enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_
+ 		opcode = 0xc3;
+ 		break;
+ 	default:
+-		die("%s: ZQ type %u is invalid\n", zq_type);
++		die("ZQ type %u is invalid\n", zq_type);
+ 	}
++	(void)opcode; /* Mitigate -Werror=unused-but-set-variable */
+ 
+ 	/* ZQCS on single-channel needs a longer delay */
+ 	const uint8_t delay = zq_type == ZQ_SHORT && (!ctrl->dpc[0] || !ctrl->dpc[1]) ? 7 : 1;
+diff --git a/src/northbridge/intel/haswell/native_raminit/testing_io.c b/src/northbridge/intel/haswell/native_raminit/testing_io.c
+index 7716fc4285..63ae59c33e 100644
+--- a/src/northbridge/intel/haswell/native_raminit/testing_io.c
++++ b/src/northbridge/intel/haswell/native_raminit/testing_io.c
+@@ -221,7 +221,7 @@ void setup_io_test(
+ 	const uint8_t subseq_wait)
+ {
+ 	if (!chanmask)
+-		die("\n%s: invalid chanmask\n", __func__, chanmask);
++		die("\n%d: invalid chanmask\n", chanmask);
+ 
+ 	/*
+ 	 * Prepare variables needed for both channels.
+diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
+index 820bb336b0..e5d8088912 100644
+--- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
++++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
+@@ -189,7 +189,7 @@ static union tc_srftp_reg make_tc_srftp(const struct sysinfo *const ctrl)
+ void configure_timings(struct sysinfo *ctrl)
+ {
+ 	if (ctrl->lpddr)
+-		die("%s: Missing support for LPDDR\n");
++		die("Missing support for LPDDR\n");
+ 
+ 	const uint8_t odt_stretch = get_odt_stretch(ctrl);
+ 	const union tc_bank_reg tc_bank = make_tc_bank(ctrl);
+-- 
+2.39.2
+

config/coreboot/haswell/patches/0001-commonlib-clamp.h-Add-more-clamping-functions.patch

@@ -1,54 +0,0 @@
-From dd58f5e9108bc596c93071705d2b53233d13ade6 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 7 May 2022 20:36:10 +0200
-Subject: [PATCH 01/26] commonlib/clamp.h: Add more clamping functions
-
-Add more clamping functions that work with different types.
-
-Change-Id: I14cf335d5a54f769f8fd9184450957e876affd6b
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- src/commonlib/include/commonlib/clamp.h | 26 +++++++++++++++++--------
- 1 file changed, 18 insertions(+), 8 deletions(-)
-
-diff --git a/src/commonlib/include/commonlib/clamp.h b/src/commonlib/include/commonlib/clamp.h
-index e01a107ed4..526185195c 100644
---- a/src/commonlib/include/commonlib/clamp.h
-+++ b/src/commonlib/include/commonlib/clamp.h
-@@ -8,15 +8,25 @@
- /*
-  * Clamp a value, so that it is between a lower and an upper bound.
-  */
--static inline u32 clamp_u32(const u32 min, const u32 val, const u32 max)
--{
--	if (val > max)
--		return max;
-+#define __MAKE_CLAMP_FUNC(type) \
-+	static inline type clamp_##type(const type min, const type val, const type max) \
-+	{				\
-+		if (val > max)		\
-+			return max;	\
-+		if (val < min)		\
-+			return min;	\
-+		return val;		\
-+	}				\
- 
--	if (val < min)
--		return min;
-+__MAKE_CLAMP_FUNC(s8)	/* clamp_s8  */
-+__MAKE_CLAMP_FUNC(u8)	/* clamp_u8  */
-+__MAKE_CLAMP_FUNC(s16)	/* clamp_s16 */
-+__MAKE_CLAMP_FUNC(u16)	/* clamp_u16 */
-+__MAKE_CLAMP_FUNC(s32)	/* clamp_s32 */
-+__MAKE_CLAMP_FUNC(u32)	/* clamp_u32 */
-+__MAKE_CLAMP_FUNC(s64)	/* clamp_s64 */
-+__MAKE_CLAMP_FUNC(u64)	/* clamp_u64 */
- 
--	return val;
--}
-+#undef __MAKE_CLAMP_FUNC
- 
- #endif /* COMMONLIB_CLAMP_H */
--- 
-2.39.2
-

config/coreboot/haswell/patches/0002-nb-intel-haswell-Introduce-option-to-not-use-MRC.bin.patch

@@ -1,143 +0,0 @@
-From c07391821c32cafea950574b85468f5b3284b6df Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Fri, 6 May 2022 21:12:14 +0200
-Subject: [PATCH 02/26] nb/intel/haswell: Introduce option to not use MRC.bin
-
-Introduce the `USE_NATIVE_RAMINIT` Kconfig option, which should allow
-booting coreboot on Haswell mainboards without the need of the closed
-source MRC.bin. For now, this option does not work at all; the needed
-magic will be implemented in subsequent commits. Add a config file to
-make sure the newly-introduced option gets build-tested.
-
-Change-Id: I46c77586f9b5771624082e07c60c205e578edd8e
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- configs/config.asrock_b85m_pro4.native_raminit    |  5 +++++
- src/northbridge/intel/haswell/Kconfig             | 13 +++++++++++++
- src/northbridge/intel/haswell/Makefile.inc        |  7 ++++++-
- .../intel/haswell/native_raminit/Makefile.inc     |  3 +++
- .../intel/haswell/native_raminit/raminit_native.c | 15 +++++++++++++++
- 5 files changed, 42 insertions(+), 1 deletion(-)
- create mode 100644 configs/config.asrock_b85m_pro4.native_raminit
- create mode 100644 src/northbridge/intel/haswell/native_raminit/Makefile.inc
- create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_native.c
-
-diff --git a/configs/config.asrock_b85m_pro4.native_raminit b/configs/config.asrock_b85m_pro4.native_raminit
-new file mode 100644
-index 0000000000..2de538926f
---- /dev/null
-+++ b/configs/config.asrock_b85m_pro4.native_raminit
-@@ -0,0 +1,5 @@
-+# Configuration used to build-test native raminit
-+CONFIG_VENDOR_ASROCK=y
-+CONFIG_BOARD_ASROCK_B85M_PRO4=y
-+CONFIG_USE_NATIVE_RAMINIT=y
-+CONFIG_DEBUG_RAM_SETUP=y
-diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
-index 50acb09a91..b659bf6d98 100644
---- a/src/northbridge/intel/haswell/Kconfig
-+++ b/src/northbridge/intel/haswell/Kconfig
-@@ -9,6 +9,14 @@ config NORTHBRIDGE_INTEL_HASWELL
- 
- if NORTHBRIDGE_INTEL_HASWELL
- 
-+config USE_NATIVE_RAMINIT
-+	bool "[NOT WORKING] Use native raminit"
-+	default n
-+	select HAVE_DEBUG_RAM_SETUP
-+	help
-+	  Select if you want to use coreboot implementation of raminit rather than
-+	  MRC.bin. Currently incomplete and does not boot.
-+
- config HASWELL_VBOOT_IN_BOOTBLOCK
- 	depends on VBOOT
- 	bool "Start verstage in bootblock"
-@@ -45,6 +53,7 @@ config DCACHE_RAM_BASE
- 
- config DCACHE_RAM_SIZE
- 	hex
-+	default 0x40000 if USE_NATIVE_RAMINIT
- 	default 0x10000
- 	help
- 	  The size of the cache-as-ram region required during bootblock
-@@ -53,12 +62,14 @@ config DCACHE_RAM_SIZE
- 
- config DCACHE_RAM_MRC_VAR_SIZE
- 	hex
-+	default 0x0 if USE_NATIVE_RAMINIT
- 	default 0x30000
- 	help
- 	  The amount of cache-as-ram region required by the reference code.
- 
- config DCACHE_BSP_STACK_SIZE
- 	hex
-+	default 0x20000 if USE_NATIVE_RAMINIT
- 	default 0x2000
- 	help
- 	  The amount of anticipated stack usage in CAR by bootblock and
-@@ -66,6 +77,7 @@ config DCACHE_BSP_STACK_SIZE
- 
- config HAVE_MRC
- 	bool "Add a System Agent binary"
-+	depends on !USE_NATIVE_RAMINIT
- 	help
- 	  Select this option to add a System Agent binary to
- 	  the resulting coreboot image.
-@@ -82,6 +94,7 @@ config MRC_FILE
- 
- config HASWELL_HIDE_PEG_FROM_MRC
- 	bool "Hide PEG devices from MRC to work around hardcoded MRC behavior"
-+	depends on !USE_NATIVE_RAMINIT
- 	default y
- 	help
- 	  If set, hides all PEG devices from MRC. This allows the iGPU
-diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
-index 2d1532be05..329f1f7ffe 100644
---- a/src/northbridge/intel/haswell/Makefile.inc
-+++ b/src/northbridge/intel/haswell/Makefile.inc
-@@ -19,6 +19,11 @@ romstage-y += report_platform.c
- 
- postcar-y += memmap.c
- 
--subdirs-y += haswell_mrc
-+ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
-+subdirs-y  += native_raminit
-+
-+else
-+subdirs-y  += haswell_mrc
-+endif
- 
- endif
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-new file mode 100644
-index 0000000000..8cfb4fb33e
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -0,0 +1,3 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+romstage-y += raminit_native.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-new file mode 100644
-index 0000000000..1aafdf8659
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <console/console.h>
-+#include <northbridge/intel/haswell/raminit.h>
-+
-+void perform_raminit(const int s3resume)
-+{
-+	/*
-+	 * See, this function's name is a lie. There are more things to
-+	 * do that memory initialisation, but they are relatively easy.
-+	 */
-+
-+	/** TODO: Implement the required magic **/
-+	die("NATIVE RAMINIT: More Magic (tm) required.\n");
-+}
--- 
-2.39.2
-

config/coreboot/haswell/patches/0003-haswell-lynxpoint-Add-native-DMI-init.patch

@@ -1,615 +0,0 @@
-From 6ec71c6df97eded010e96c4ea2bd37cc6a13849d Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Fri, 6 May 2022 21:56:48 +0200
-Subject: [PATCH 03/26] haswell/lynxpoint: Add native DMI init
-
-Implement native DMI init for Haswell and Lynx Point. This is only
-needed on non-ULT platforms, and only when MRC.bin is not used.
-
-TEST=Verify DMI initialises correctly on Asrock B85M Pro4.
-
-Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- src/northbridge/intel/haswell/Makefile.inc    |   1 +
- src/northbridge/intel/haswell/early_dmi.c     |  96 ++++++++++++
- src/northbridge/intel/haswell/early_pcie.c    | 121 ++++++++++++++
- src/northbridge/intel/haswell/haswell.h       |   3 +
- .../haswell/native_raminit/raminit_native.c   |  15 ++
- src/northbridge/intel/haswell/vcu_mailbox.c   | 147 ++++++++++++++++++
- src/northbridge/intel/haswell/vcu_mailbox.h   |  16 ++
- src/southbridge/intel/lynxpoint/Makefile.inc  |   2 +
- .../intel/lynxpoint/early_pch_native.c        |  52 +++++++
- src/southbridge/intel/lynxpoint/pch.h         |  20 ++-
- 10 files changed, 472 insertions(+), 1 deletion(-)
- create mode 100644 src/northbridge/intel/haswell/early_dmi.c
- create mode 100644 src/northbridge/intel/haswell/early_pcie.c
- create mode 100644 src/northbridge/intel/haswell/vcu_mailbox.c
- create mode 100644 src/northbridge/intel/haswell/vcu_mailbox.h
- create mode 100644 src/southbridge/intel/lynxpoint/early_pch_native.c
-
-diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
-index 329f1f7ffe..df0b097296 100644
---- a/src/northbridge/intel/haswell/Makefile.inc
-+++ b/src/northbridge/intel/haswell/Makefile.inc
-@@ -20,6 +20,7 @@ romstage-y += report_platform.c
- postcar-y += memmap.c
- 
- ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
-+romstage-y += early_dmi.c early_pcie.c vcu_mailbox.c
- subdirs-y  += native_raminit
- 
- else
-diff --git a/src/northbridge/intel/haswell/early_dmi.c b/src/northbridge/intel/haswell/early_dmi.c
-new file mode 100644
-index 0000000000..9941242fd5
---- /dev/null
-+++ b/src/northbridge/intel/haswell/early_dmi.c
-@@ -0,0 +1,96 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <console/console.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <southbridge/intel/lynxpoint/pch.h>
-+#include <types.h>
-+
-+static void dmi_print_link_status(int loglevel)
-+{
-+	const uint16_t dmilsts = dmibar_read16(DMILSTS);
-+	printk(loglevel, "DMI: Running at Gen%u x%u\n", dmilsts & 0xf, dmilsts >> 4 & 0x1f);
-+}
-+
-+#define RETRAIN	(1 << 5)
-+
-+#define LTRN	(1 << 11)
-+
-+static void dmi_setup_physical_layer(void)
-+{
-+	/* Program DMI AFE settings, which are needed for DMI to work */
-+	peg_dmi_recipe(false, 0);
-+
-+	/* Additional DMI programming steps */
-+	dmibar_setbits32(0x258, 1 << 29);
-+	dmibar_clrsetbits32(0x208, 0x7ff, 0x6b5);
-+	dmibar_clrsetbits32(0x22c, 0xffff, 0x2020);
-+
-+	/* Write SA reference code version */
-+	dmibar_write32(0x71c, 0x0000000f);
-+	dmibar_write32(0x720, 0x01060200);
-+
-+	/* We also have to bring up the PCH side of the DMI link */
-+	pch_dmi_setup_physical_layer();
-+
-+	/* Write-once settings */
-+	dmibar_clrsetbits32(DMILCAP, 0x3f00f, 2 << 0);
-+
-+	printk(BIOS_DEBUG, "Retraining DMI at Gen2 speeds...\n");
-+	dmi_print_link_status(BIOS_DEBUG);
-+
-+	/* Retrain link */
-+	dmibar_setbits16(DMILCTL, RETRAIN);
-+	do {} while (dmibar_read16(DMILSTS) & LTRN);
-+	dmi_print_link_status(BIOS_DEBUG);
-+
-+	/* Retrain link again for DMI Gen2 speeds */
-+	dmibar_setbits16(DMILCTL, RETRAIN);
-+	do {} while (dmibar_read16(DMILSTS) & LTRN);
-+	dmi_print_link_status(BIOS_INFO);
-+}
-+
-+#define VC_ACTIVE	(1U << 31)
-+
-+#define VCNEGPND	(1 << 1)
-+
-+#define DMI_VC_CFG(vcid, tcmap)	(VC_ACTIVE | ((vcid) << 24) | (tcmap))
-+
-+static void dmi_tc_vc_mapping(void)
-+{
-+	printk(BIOS_DEBUG, "Programming SA  DMI VC/TC mappings...\n");
-+
-+	if (CONFIG(INTEL_LYNXPOINT_LP))
-+		dmibar_setbits8(0xa78, 1 << 1);
-+
-+	/* Each TC is mapped to one and only one VC */
-+	const u32 vc0 = DMI_VC_CFG(0, (1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 0));
-+	const u32 vc1 = DMI_VC_CFG(1, (1 << 1));
-+	const u32 vcp = DMI_VC_CFG(2, (1 << 2));
-+	const u32 vcm = DMI_VC_CFG(7, (1 << 7));
-+	dmibar_write32(DMIVC0RCTL, vc0);
-+	dmibar_write32(DMIVC1RCTL, vc1);
-+	dmibar_write32(DMIVCPRCTL, vcp);
-+	dmibar_write32(DMIVCMRCTL, vcm);
-+
-+	/* Set Extended VC Count (EVCC) to 1 if VC1 is active */
-+	dmibar_clrsetbits8(DMIPVCCAP1, 7, !!(vc1 & VC_ACTIVE));
-+
-+	/*
-+	 * We also have to program the PCH side of the DMI link. Since both ends
-+	 * must use the same Virtual Channel settings, we pass them as arguments.
-+	 */
-+	pch_dmi_tc_vc_mapping(vc0, vc1, vcp, vcm);
-+
-+	printk(BIOS_DEBUG, "Waiting for SA  DMI VC negotiation... ");
-+	do {} while (dmibar_read16(DMIVC0RSTS) & VCNEGPND);
-+	do {} while (dmibar_read16(DMIVC1RSTS) & VCNEGPND);
-+	do {} while (dmibar_read16(DMIVCPRSTS) & VCNEGPND);
-+	do {} while (dmibar_read16(DMIVCMRSTS) & VCNEGPND);
-+	printk(BIOS_DEBUG, "done!\n");
-+}
-+
-+void dmi_early_init(void)
-+{
-+	dmi_setup_physical_layer();
-+	dmi_tc_vc_mapping();
-+}
-diff --git a/src/northbridge/intel/haswell/early_pcie.c b/src/northbridge/intel/haswell/early_pcie.c
-new file mode 100644
-index 0000000000..d3940e3fac
---- /dev/null
-+++ b/src/northbridge/intel/haswell/early_pcie.c
-@@ -0,0 +1,121 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <console/console.h>
-+#include <device/pci_def.h>
-+#include <device/pci_mmio_cfg.h>
-+#include <device/pci_ops.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <northbridge/intel/haswell/vcu_mailbox.h>
-+#include <types.h>
-+
-+#define PEG_DEV(func)		PCI_DEV(0, 1, func)
-+
-+#define MAX_PEG_FUNC		3
-+
-+static void peg_dmi_unset_and_set_mask_pcicfg(
-+	volatile union pci_bank *const bank,
-+	const uint32_t offset,
-+	const uint32_t unset_mask,
-+	const uint32_t set_mask,
-+	const uint32_t shift,
-+	const bool valid)
-+{
-+	if (!valid)
-+		return;
-+
-+	volatile uint32_t *const addr = &bank->reg32[offset / sizeof(uint32_t)];
-+	clrsetbits32(addr, unset_mask << shift, set_mask << shift);
-+}
-+
-+static void peg_dmi_unset_and_set_mask_common(
-+	const bool is_peg,
-+	const uint32_t offset,
-+	const uint32_t unset,
-+	const uint32_t set,
-+	const uint32_t shift,
-+	const bool valid)
-+{
-+	const uint32_t unset_mask = unset << shift;
-+	const uint32_t   set_mask =   set << shift;
-+	if (is_peg) {
-+		for (uint8_t i = 0; i < MAX_PEG_FUNC; i++)
-+			pci_update_config32(PEG_DEV(i), offset, ~unset_mask, set_mask);
-+	} else {
-+		dmibar_clrsetbits32(offset, unset_mask, set_mask);
-+	}
-+}
-+
-+static void peg_dmi_unset_and_set_mask_vcu_mmio(
-+	const uint32_t addr,
-+	const uint32_t unset_mask,
-+	const uint32_t set_mask,
-+	const uint32_t shift,
-+	const bool valid)
-+{
-+	if (!valid)
-+		return;
-+
-+	vcu_update_mmio(addr, ~(unset_mask << shift), set_mask << shift);
-+}
-+
-+#define BUNDLE_STEP	0x20
-+
-+static void *const dmibar = (void *)(uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE;
-+
-+void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev)
-+{
-+	const bool always = true;
-+	const bool is_dmi = !is_peg;
-+
-+	/* Treat DMIBAR and PEG devices the same way */
-+	volatile union pci_bank *const bank = is_peg ? pci_map_bus(dev) : dmibar;
-+
-+	const size_t bundles = (is_peg ? 8 : 2) * BUNDLE_STEP;
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP) {
-+		/* These are actually per-lane */
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa00 + i, 0x1f, 0x0c,  0, always);
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa10 + i, 0x1f, 0x0c,  0, always);
-+	}
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x02,  0, is_peg);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x03,  5, is_peg);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x3f, 0x09,  5, always);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x0f, 0x05, 21, is_peg);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x08,  6, is_peg);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x00, 10, always);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x07, 0x00, 18, always);
-+
-+	peg_dmi_unset_and_set_mask_vcu_mmio(0x0c008001, 0x1f, 0x03, 25, is_peg);
-+	peg_dmi_unset_and_set_mask_vcu_mmio(0x0c0c8001, 0x3f, 0x00, 23, is_dmi);
-+
-+	peg_dmi_unset_and_set_mask_pcicfg(bank, 0xc28, 0x1f, 0x13, 18, always);
-+
-+	peg_dmi_unset_and_set_mask_common(is_peg, 0xc38, 0x01, 0x00,  6, always);
-+	peg_dmi_unset_and_set_mask_common(is_peg, 0x260, 0x03, 0x02,  0, always);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x900 + i, 0x03, 0x00, 26, always);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x03, 0x03, 10, always);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x1f, 0x07, 25, is_peg);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x91c + i, 0x07, 0x05, 27, is_peg);
-+}
-diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
-index 1b29f6baf0..30b4abd0a7 100644
---- a/src/northbridge/intel/haswell/haswell.h
-+++ b/src/northbridge/intel/haswell/haswell.h
-@@ -34,6 +34,9 @@ void haswell_early_initialization(void);
- void haswell_late_initialization(void);
- void haswell_unhide_peg(void);
- 
-+void dmi_early_init(void);
-+void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev);
-+
- void report_platform_info(void);
- 
- struct acpi_rsdp;
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index 1aafdf8659..0938e026e3 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -1,7 +1,19 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
- #include <console/console.h>
-+#include <northbridge/intel/haswell/haswell.h>
- #include <northbridge/intel/haswell/raminit.h>
-+#include <types.h>
-+
-+static bool early_init_native(int s3resume)
-+{
-+	printk(BIOS_DEBUG, "Starting native platform initialisation\n");
-+
-+	if (!CONFIG(INTEL_LYNXPOINT_LP))
-+		dmi_early_init();
-+
-+	return false;
-+}
- 
- void perform_raminit(const int s3resume)
- {
-@@ -9,6 +21,9 @@ void perform_raminit(const int s3resume)
- 	 * See, this function's name is a lie. There are more things to
- 	 * do that memory initialisation, but they are relatively easy.
- 	 */
-+	const bool cpu_replaced = early_init_native(s3resume);
-+
-+	(void)cpu_replaced;
- 
- 	/** TODO: Implement the required magic **/
- 	die("NATIVE RAMINIT: More Magic (tm) required.\n");
-diff --git a/src/northbridge/intel/haswell/vcu_mailbox.c b/src/northbridge/intel/haswell/vcu_mailbox.c
-new file mode 100644
-index 0000000000..aead144023
---- /dev/null
-+++ b/src/northbridge/intel/haswell/vcu_mailbox.c
-@@ -0,0 +1,147 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <assert.h>
-+#include <console/console.h>
-+#include <delay.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <northbridge/intel/haswell/vcu_mailbox.h>
-+#include <stdint.h>
-+
-+/*
-+ * This is a library for the VCU (Validation Control Unit) mailbox. This
-+ * mailbox is primarily used to adjust some magic PCIe tuning parameters.
-+ *
-+ * There are two revisions of the VCU mailbox. Rev1 is specific to Haswell
-+ * stepping A0, and all other steppings use Rev2. Haswell stepping A0 CPUs
-+ * are early Engineering Samples with undocumented errata, and most likely
-+ * need special microcode updates to boot. Thus, the code does not support
-+ * VCU mailbox Rev1, because no one should need it anymore.
-+ */
-+
-+#define VCU_MAILBOX_INTERFACE	0x6c00
-+#define VCU_MAILBOX_DATA	0x6c04
-+
-+#define VCU_RUN_BUSY		(1 << 31)
-+
-+enum vcu_opcode {
-+	VCU_OPCODE_READ_VCU_API_VER_ID	= 0x01,
-+	VCU_OPCODE_OPEN_SEQ		= 0x02,
-+	VCU_OPCODE_CLOSE_SEQ		= 0x03,
-+	VCU_OPCODE_READ_DATA		= 0x07,
-+	VCU_OPCODE_WRITE_DATA		= 0x08,
-+	VCU_OPCODE_READ_CSR		= 0x13,
-+	VCU_OPCODE_WRITE_CSR		= 0x14,
-+	VCU_OPCODE_READ_MMIO		= 0x15,
-+	VCU_OPCODE_WRITE_MMIO		= 0x16,
-+};
-+
-+enum vcu_sequence {
-+	SEQ_ID_READ_CSR		= 0x1,
-+	SEQ_ID_WRITE_CSR	= 0x2,
-+	SEQ_ID_READ_MMIO	= 0x3,
-+	SEQ_ID_WRITE_MMIO	= 0x4,
-+};
-+
-+#define VCU_RESPONSE_MASK		0xffff
-+#define VCU_RESPONSE_SUCCESS		0x40
-+#define VCU_RESPONSE_BUSY		0x80
-+#define VCU_RESPONSE_THREAD_UNAVAILABLE	0x82
-+#define VCU_RESPONSE_ILLEGAL		0x90
-+
-+/* FIXME: Use timer API */
-+static void send_vcu_command(const enum vcu_opcode opcode, const uint32_t data)
-+{
-+	for (unsigned int i = 0; i < 10; i++) {
-+		mchbar_write32(VCU_MAILBOX_DATA, data);
-+		mchbar_write32(VCU_MAILBOX_INTERFACE, opcode | VCU_RUN_BUSY);
-+		uint32_t vcu_interface;
-+		for (unsigned int j = 0; j < 100; j++) {
-+			vcu_interface = mchbar_read32(VCU_MAILBOX_INTERFACE);
-+			if (!(vcu_interface & VCU_RUN_BUSY))
-+				break;
-+
-+			udelay(10);
-+		}
-+		if (vcu_interface & VCU_RUN_BUSY)
-+			continue;
-+
-+		if ((vcu_interface & VCU_RESPONSE_MASK) == VCU_RESPONSE_SUCCESS)
-+			return;
-+	}
-+	printk(BIOS_ERR, "VCU: Failed to send command\n");
-+}
-+
-+static enum vcu_opcode get_register_opcode(enum vcu_sequence seq)
-+{
-+	switch (seq) {
-+	case SEQ_ID_READ_CSR:
-+		return VCU_OPCODE_READ_CSR;
-+	case SEQ_ID_WRITE_CSR:
-+		return VCU_OPCODE_WRITE_CSR;
-+	case SEQ_ID_READ_MMIO:
-+		return VCU_OPCODE_READ_MMIO;
-+	case SEQ_ID_WRITE_MMIO:
-+		return VCU_OPCODE_WRITE_MMIO;
-+	default:
-+		return dead_code_t(enum vcu_opcode);
-+	}
-+}
-+
-+static enum vcu_opcode get_data_opcode(enum vcu_sequence seq)
-+{
-+	switch (seq) {
-+	case SEQ_ID_READ_CSR:
-+	case SEQ_ID_READ_MMIO:
-+		return VCU_OPCODE_READ_DATA;
-+	case SEQ_ID_WRITE_CSR:
-+	case SEQ_ID_WRITE_MMIO:
-+		return VCU_OPCODE_WRITE_DATA;
-+	default:
-+		return dead_code_t(enum vcu_opcode);
-+	}
-+}
-+
-+static uint32_t send_vcu_sequence(uint32_t addr, enum vcu_sequence seq, uint32_t wr_data)
-+{
-+	send_vcu_command(VCU_OPCODE_OPEN_SEQ, seq);
-+
-+	send_vcu_command(get_register_opcode(seq), addr);
-+
-+	send_vcu_command(get_data_opcode(seq), wr_data);
-+
-+	const uint32_t rd_data = mchbar_read32(VCU_MAILBOX_DATA);
-+
-+	send_vcu_command(VCU_OPCODE_CLOSE_SEQ, seq);
-+
-+	return rd_data;
-+}
-+
-+uint32_t vcu_read_csr(uint32_t addr)
-+{
-+	return send_vcu_sequence(addr, SEQ_ID_READ_CSR, 0);
-+}
-+
-+void vcu_write_csr(uint32_t addr, uint32_t data)
-+{
-+	send_vcu_sequence(addr, SEQ_ID_WRITE_CSR, data);
-+}
-+
-+void vcu_update_csr(uint32_t addr, uint32_t andvalue, uint32_t orvalue)
-+{
-+	vcu_write_csr(addr, (vcu_read_csr(addr) & andvalue) | orvalue);
-+}
-+
-+uint32_t vcu_read_mmio(uint32_t addr)
-+{
-+	return send_vcu_sequence(addr, SEQ_ID_READ_MMIO, 0);
-+}
-+
-+void vcu_write_mmio(uint32_t addr, uint32_t data)
-+{
-+	send_vcu_sequence(addr, SEQ_ID_WRITE_MMIO, data);
-+}
-+
-+void vcu_update_mmio(uint32_t addr, uint32_t andvalue, uint32_t orvalue)
-+{
-+	vcu_write_mmio(addr, (vcu_read_mmio(addr) & andvalue) | orvalue);
-+}
-diff --git a/src/northbridge/intel/haswell/vcu_mailbox.h b/src/northbridge/intel/haswell/vcu_mailbox.h
-new file mode 100644
-index 0000000000..ba0a62e486
---- /dev/null
-+++ b/src/northbridge/intel/haswell/vcu_mailbox.h
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#ifndef HASWELL_VCU_MAILBOX_H
-+#define HASWELL_VCU_MAILBOX_H
-+
-+#include <stdint.h>
-+
-+uint32_t vcu_read_csr(uint32_t addr);
-+void vcu_write_csr(uint32_t addr, uint32_t data);
-+void vcu_update_csr(uint32_t addr, uint32_t andvalue, uint32_t orvalue);
-+
-+uint32_t vcu_read_mmio(uint32_t addr);
-+void vcu_write_mmio(uint32_t addr, uint32_t data);
-+void vcu_update_mmio(uint32_t addr, uint32_t andvalue, uint32_t orvalue);
-+
-+#endif /* HASWELL_VCU_MAILBOX_H */
-diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
-index 02022d348d..b8503ac8bc 100644
---- a/src/southbridge/intel/lynxpoint/Makefile.inc
-+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
-@@ -37,6 +37,8 @@ bootblock-y += early_pch.c
- romstage-y += early_usb.c early_me.c me_status.c early_pch.c
- romstage-y += pmutil.c
- 
-+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c
-+
- ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
- romstage-y += lp_gpio.c
- ramstage-y += lp_gpio.c
-diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c
-new file mode 100644
-index 0000000000..c28ddfcf5d
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/early_pch_native.c
-@@ -0,0 +1,52 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <console/console.h>
-+#include <device/pci_ops.h>
-+#include <southbridge/intel/lynxpoint/pch.h>
-+#include <types.h>
-+
-+void pch_dmi_setup_physical_layer(void)
-+{
-+	/* FIXME: We need to make sure the SA supports Gen2 as well */
-+	if ((RCBA32(0x21a4) & 0x0f) == 0x02) {
-+		/* Set Gen 2 Common Clock N_FTS */
-+		RCBA32_AND_OR(0x2340, ~0x00ff0000, 0x3a << 16);
-+
-+		/* Set Target Link Speed to DMI Gen2 */
-+		RCBA8_AND_OR(DLCTL2, ~0x07, 0x02);
-+	}
-+}
-+
-+#define VC_ACTIVE	(1U << 31)
-+
-+#define VCNEGPND	(1 << 1)
-+
-+void pch_dmi_tc_vc_mapping(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm)
-+{
-+	printk(BIOS_DEBUG, "Programming PCH DMI VC/TC mappings...\n");
-+
-+	RCBA32_AND_OR(CIR0050, ~(0xf << 20), 2 << 20);
-+	if (vcp & VC_ACTIVE)
-+		RCBA32_OR(CIR0050, 1 << 19 | 1 << 17);
-+
-+	RCBA32(CIR0050);	/* Posted Write */
-+
-+	/* Use the same virtual channel mapping on both ends of the DMI link */
-+	RCBA32(V0CTL) = vc0;
-+	RCBA32(V1CTL) = vc1;
-+	RCBA32(V1CTL);		/* Posted Write */
-+	RCBA32(VPCTL) = vcp;
-+	RCBA32(VPCTL);		/* Posted Write */
-+	RCBA32(VMCTL) = vcm;
-+
-+	/* Lock the registers */
-+	RCBA32_OR(CIR0050, 1U << 31);
-+	RCBA32(CIR0050);	/* Posted Write */
-+
-+	printk(BIOS_DEBUG, "Waiting for PCH DMI VC negotiation... ");
-+	do {} while (RCBA16(V0STS) & VCNEGPND);
-+	do {} while (RCBA16(V1STS) & VCNEGPND);
-+	do {} while (RCBA16(VPSTS) & VCNEGPND);
-+	do {} while (RCBA16(VMSTS) & VCNEGPND);
-+	printk(BIOS_DEBUG, "done!\n");
-+}
-diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
-index 7d9fc6d6af..b5e0c2a830 100644
---- a/src/southbridge/intel/lynxpoint/pch.h
-+++ b/src/southbridge/intel/lynxpoint/pch.h
-@@ -113,6 +113,9 @@ enum pch_platform_type {
- 	PCH_TYPE_ULT	 = 5,
- };
- 
-+void pch_dmi_setup_physical_layer(void);
-+void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
-+
- void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
- void usb_ehci_disable(pci_devfn_t dev);
- void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
-@@ -406,9 +409,10 @@ void mainboard_config_rcba(void);
- 
- /* Southbridge IO BARs */
- 
-+#define PMBASE			0x40
- #define GPIOBASE		0x48
- 
--#define PMBASE		0x40
-+#define CIR0050		0x0050	/* 32bit */
- 
- #define RPC		0x0400	/* 32bit */
- #define RPFN		0x0404	/* 32bit */
-@@ -431,6 +435,20 @@ void mainboard_config_rcba(void);
- #define IOTR2		0x1e90	/* 64bit */
- #define IOTR3		0x1e98	/* 64bit */
- 
-+#define V0CTL		0x2014	/* 32bit */
-+#define V0STS		0x201a	/* 16bit */
-+
-+#define V1CTL		0x2020	/* 32bit */
-+#define V1STS		0x2026	/* 16bit */
-+
-+#define VPCTL		0x2030	/* 32bit */
-+#define VPSTS		0x2038	/* 16bit */
-+
-+#define VMCTL		0x2040	/* 32bit */
-+#define VMSTS		0x2048	/* 16bit */
-+
-+#define DLCTL2		0x21b0
-+
- #define TCTL		0x3000	/*  8bit */
- 
- #define NOINT		0
--- 
-2.39.2
-

config/coreboot/haswell/patches/0004-haswell-lynxpoint-Add-native-early-ME-init.patch

@@ -1,148 +0,0 @@
-From 98142e01fc8ebb3b762974e9e4de75e7f5c073b4 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Fri, 6 May 2022 22:18:21 +0200
-Subject: [PATCH 04/26] haswell/lynxpoint: Add native early ME init
-
-Implement native early ME init for Lynx Point. This is only needed when
-MRC.bin is not used.
-
-Change-Id: If416e2078f139f26b4742c564b70e018725bf003
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../haswell/native_raminit/raminit_native.c   | 17 ++++++++++-
- src/southbridge/intel/lynxpoint/early_me.c    | 30 ++++++++++++++++++-
- src/southbridge/intel/lynxpoint/me.h          |  7 +++--
- 3 files changed, 50 insertions(+), 4 deletions(-)
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index 0938e026e3..6a002548c1 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -1,18 +1,24 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
- #include <console/console.h>
-+#include <delay.h>
- #include <northbridge/intel/haswell/haswell.h>
- #include <northbridge/intel/haswell/raminit.h>
-+#include <southbridge/intel/lynxpoint/me.h>
- #include <types.h>
- 
- static bool early_init_native(int s3resume)
- {
- 	printk(BIOS_DEBUG, "Starting native platform initialisation\n");
- 
-+	intel_early_me_init();
-+	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
-+	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
-+
- 	if (!CONFIG(INTEL_LYNXPOINT_LP))
- 		dmi_early_init();
- 
--	return false;
-+	return cpu_replaced;
- }
- 
- void perform_raminit(const int s3resume)
-@@ -25,6 +31,15 @@ void perform_raminit(const int s3resume)
- 
- 	(void)cpu_replaced;
- 
-+	/** TODO: Move after raminit */
-+	if (intel_early_me_uma_size() > 0) {
-+		/** TODO: Update status once raminit is implemented **/
-+		uint8_t me_status = ME_INIT_STATUS_ERROR;
-+		intel_early_me_init_done(me_status);
-+	}
-+
-+	intel_early_me_status();
-+
- 	/** TODO: Implement the required magic **/
- 	die("NATIVE RAMINIT: More Magic (tm) required.\n");
- }
-diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
-index 947c570e16..07013c5539 100644
---- a/src/southbridge/intel/lynxpoint/early_me.c
-+++ b/src/southbridge/intel/lynxpoint/early_me.c
-@@ -1,11 +1,12 @@
- /* SPDX-License-Identifier: GPL-2.0-only */
- 
- #include <arch/io.h>
-+#include <cf9_reset.h>
- #include <device/pci_ops.h>
- #include <console/console.h>
- #include <delay.h>
- #include <halt.h>
--
-+#include <timer.h>
- #include "me.h"
- #include "pch.h"
- 
-@@ -60,6 +61,33 @@ int intel_early_me_init(void)
- 	return 0;
- }
- 
-+bool intel_early_me_cpu_replacement_check(void)
-+{
-+	printk(BIOS_DEBUG, "ME: Checking whether CPU was replaced... ");
-+
-+	struct stopwatch timer;
-+	stopwatch_init_msecs_expire(&timer, 50);
-+
-+	union me_hfs2 hfs2;
-+	do {
-+		hfs2.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2);
-+		if (stopwatch_expired(&timer)) {
-+			/* Assume CPU was replaced just in case */
-+			printk(BIOS_DEBUG, "timed out, assuming CPU was replaced\n");
-+			return true;
-+		}
-+		udelay(ME_DELAY);
-+	} while (!hfs2.cpu_replaced_valid);
-+
-+	if (hfs2.warm_reset_request) {
-+		printk(BIOS_DEBUG, "warm reset needed for dynamic fusing\n");
-+		system_reset();
-+	}
-+
-+	printk(BIOS_DEBUG, "%sreplaced\n", hfs2.cpu_replaced_sts ? "" : "not ");
-+	return hfs2.cpu_replaced_sts;
-+}
-+
- int intel_early_me_uma_size(void)
- {
- 	union me_uma uma = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA) };
-diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h
-index fe8b0260c4..6990322651 100644
---- a/src/southbridge/intel/lynxpoint/me.h
-+++ b/src/southbridge/intel/lynxpoint/me.h
-@@ -177,14 +177,16 @@ union me_did {
- union me_hfs2 {
- 	struct __packed {
- 		u32 bist_in_progress: 1;
--		u32 reserved1: 2;
-+		u32 icc_prog_sts: 2;
- 		u32 invoke_mebx: 1;
- 		u32 cpu_replaced_sts: 1;
- 		u32 mbp_rdy: 1;
- 		u32 mfs_failure: 1;
- 		u32 warm_reset_request: 1;
- 		u32 cpu_replaced_valid: 1;
--		u32 reserved2: 4;
-+		u32 reserved: 2;
-+		u32 fw_upd_ipu: 1;
-+		u32 reserved2: 1;
- 		u32 mbp_cleared: 1;
- 		u32 reserved3: 2;
- 		u32 current_state: 8;
-@@ -338,6 +340,7 @@ void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2);
- 
- void intel_early_me_status(void);
- int intel_early_me_init(void);
-+bool intel_early_me_cpu_replacement_check(void);
- int intel_early_me_uma_size(void);
- int intel_early_me_init_done(u8 status);
- 
--- 
-2.39.2
-

config/coreboot/haswell/patches/0005-sb-intel-lynxpoint-Add-native-USB-init.patch

@@ -1,783 +0,0 @@
-From 9bfb8614dbf1d9800ef8251cb3d839bcdbe5577f Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Fri, 6 May 2022 23:17:39 +0200
-Subject: [PATCH 05/26] sb/intel/lynxpoint: Add native USB init
-
-Implement native USB initialisation for Lynx Point. This is only needed
-when MRC.bin is not used.
-
-TO DO: Figure out how to deal with the FIXME's and TODO's lying around.
-
-Change-Id: Ie0fbeeca7b1ca1557173772d733fd2fa27703373
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../haswell/native_raminit/raminit_native.c   |   3 +
- src/southbridge/intel/lynxpoint/Makefile.inc  |   2 +-
- src/southbridge/intel/lynxpoint/early_usb.c   |  11 -
- .../intel/lynxpoint/early_usb_native.c        | 584 ++++++++++++++++++
- src/southbridge/intel/lynxpoint/pch.h         |  49 ++
- 5 files changed, 637 insertions(+), 12 deletions(-)
- create mode 100644 src/southbridge/intel/lynxpoint/early_usb_native.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index 6a002548c1..ef61d4ee09 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -5,6 +5,7 @@
- #include <northbridge/intel/haswell/haswell.h>
- #include <northbridge/intel/haswell/raminit.h>
- #include <southbridge/intel/lynxpoint/me.h>
-+#include <southbridge/intel/lynxpoint/pch.h>
- #include <types.h>
- 
- static bool early_init_native(int s3resume)
-@@ -15,6 +16,8 @@ static bool early_init_native(int s3resume)
- 	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
- 	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
- 
-+	early_usb_init();
-+
- 	if (!CONFIG(INTEL_LYNXPOINT_LP))
- 		dmi_early_init();
- 
-diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
-index b8503ac8bc..0e1f2fe4eb 100644
---- a/src/southbridge/intel/lynxpoint/Makefile.inc
-+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
-@@ -37,7 +37,7 @@ bootblock-y += early_pch.c
- romstage-y += early_usb.c early_me.c me_status.c early_pch.c
- romstage-y += pmutil.c
- 
--romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c
-+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c
- 
- ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
- romstage-y += lp_gpio.c
-diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
-index a753681ce0..52e8ac17f8 100644
---- a/src/southbridge/intel/lynxpoint/early_usb.c
-+++ b/src/southbridge/intel/lynxpoint/early_usb.c
-@@ -4,17 +4,6 @@
- #include <device/pci_def.h>
- #include "pch.h"
- 
--/* HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index
-- * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
-- */
--#if CONFIG_USBDEBUG_HCD_INDEX != 2
--#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
--#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
--#else
--#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
--#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
--#endif
--
- /*
-  * Setup USB controller MMIO BAR to prevent the
-  * reference code from resetting the controller.
-diff --git a/src/southbridge/intel/lynxpoint/early_usb_native.c b/src/southbridge/intel/lynxpoint/early_usb_native.c
-new file mode 100644
-index 0000000000..cb6f6ee8e6
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/early_usb_native.c
-@@ -0,0 +1,584 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <console/console.h>
-+#include <delay.h>
-+#include <device/mmio.h>
-+#include <device/pci_def.h>
-+#include <device/pci_ops.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <northbridge/intel/haswell/raminit.h>
-+#include <southbridge/intel/lynxpoint/iobp.h>
-+#include <southbridge/intel/lynxpoint/pch.h>
-+#include <timer.h>
-+#include <types.h>
-+
-+static unsigned int is_usbr_enabled(void)
-+{
-+	return !!(pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) & BIT(5));
-+}
-+
-+static char *const xhci_bar = (char *)PCH_XHCI_TEMP_BAR0;
-+
-+static void ehci_hcs_init(const pci_devfn_t dev, const uintptr_t ehci_bar)
-+{
-+	pci_write_config32(dev, PCI_BASE_ADDRESS_0, ehci_bar);
-+
-+	/** FIXME: Determine whether Bus Master is required (or clean it up afterwards) **/
-+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-+
-+	char *const mem_bar = (char *)ehci_bar;
-+
-+	/**
-+	 * Shared EHCI/XHCI ports w/a.
-+	 * This step is required when some of the ports are routed to EHCI
-+	 * and other ports are routed XHCI at the same time.
-+	 *
-+	 * FIXME: Under which conditions should this be done?
-+	 */
-+	pci_and_config16(dev, 0x78, ~0x03);
-+
-+	/* Skip reset if usbdebug is enabled */
-+	if (!CONFIG(USBDEBUG_IN_PRE_RAM))
-+		setbits32(mem_bar + EHCI_USB_CMD, EHCI_USB_CMD_HCRESET);
-+
-+	/* 2: Configure number of controllers and ports */
-+	pci_or_config16(dev, EHCI_ACCESS_CNTL, ACCESS_CNTL_ENABLE);
-+	clrsetbits32(mem_bar + EHCI_HCS_PARAMS, 0xf << 12, 0);
-+	clrsetbits32(mem_bar + EHCI_HCS_PARAMS, 0xf <<  0, 2 + is_usbr_enabled());
-+	pci_and_config16(dev, EHCI_ACCESS_CNTL, ~ACCESS_CNTL_ENABLE);
-+
-+	pci_or_config16(dev, 0x78, BIT(2));
-+	pci_or_config16(dev, 0x7c, BIT(14) | BIT(7));
-+	pci_update_config32(dev, 0x8c, ~(0xf << 8), (4 << 8));
-+	pci_update_config32(dev, 0x8c, ~BIT(26), BIT(17));
-+}
-+
-+static inline unsigned int physical_port_count(void)
-+{
-+	return MAX_USB2_PORTS;
-+}
-+
-+static unsigned int hs_port_count(void)
-+{
-+	/** TODO: Apparently, WPT-LP has 10 USB2 ports **/
-+	if (CONFIG(INTEL_LYNXPOINT_LP))
-+		return 8;
-+
-+	switch ((pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) >> 1) & 3) {
-+	case 3:
-+		return 8;
-+	case 2:
-+		return 10;
-+	case 1:
-+		return 12;
-+	case 0:
-+	default:
-+		return 14;
-+	}
-+}
-+
-+static unsigned int ss_port_count(void)
-+{
-+	if (CONFIG(INTEL_LYNXPOINT_LP))
-+		return 4;
-+
-+	switch ((pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) >> 3) & 3) {
-+	case 3:
-+		return 0;
-+	case 2:
-+		return 2;
-+	case 1:
-+		return 4;
-+	case 0:
-+	default:
-+		return 6;
-+	}
-+}
-+
-+static void common_ehci_hcs_init(void)
-+{
-+	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
-+
-+	ehci_hcs_init(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0);
-+	if (!is_lp)
-+		ehci_hcs_init(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0);
-+
-+	pch_iobp_update(0xe5007f04, 0, 0x00004481);
-+
-+	for (unsigned int port = 0; port < physical_port_count(); port++)
-+		pch_iobp_update(0xe500400f + port * 0x100, ~(1 << 0), 0 << 0);
-+
-+	pch_iobp_update(0xe5007f14, ~(3 << 19), (3 << 19));
-+
-+	if (is_lp)
-+		pch_iobp_update(0xe5007f02, ~(3 << 22), (0 << 22));
-+}
-+
-+static void xhci_open_memory_space(void)
-+{
-+	/** FIXME: Determine whether Bus Master is required (or clean it up afterwards) **/
-+	pci_write_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0, (uintptr_t)xhci_bar);
-+	pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-+}
-+
-+static void xhci_close_memory_space(void)
-+{
-+	pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY));
-+	pci_write_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0, 0);
-+}
-+
-+static void common_xhci_hc_init(void)
-+{
-+	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
-+
-+	if (!is_lp) {
-+		const unsigned int max_ports = 15 + ss_port_count();
-+		clrsetbits32(xhci_bar + XHCI_HCS_PARAMS_1, 0xf << 28, max_ports << 28);
-+	}
-+
-+	clrsetbits32(xhci_bar + XHCI_HCS_PARAMS_3, 0xffff << 16 | 0xff, 0x200 << 16 | 0x0a);
-+	clrsetbits32(xhci_bar + XHCI_HCC_PARAMS, BIT(5), BIT(10) | BIT(9));
-+
-+	if (!is_lp)
-+		clrsetbits32(xhci_bar + 0x8008, BIT(19), 0);
-+
-+	if (is_lp)
-+		clrsetbits32(xhci_bar + 0x8058, BIT(8), BIT(16));
-+	else
-+		clrsetbits32(xhci_bar + 0x8058, BIT(8), BIT(16) | BIT(20));
-+
-+	clrsetbits32(xhci_bar + 0x8060, 0, BIT(25) | BIT(18));
-+	clrsetbits32(xhci_bar + 0x8090, 0, BIT(14) | BIT(8));
-+	clrsetbits32(xhci_bar + 0x8094, 0, BIT(23) | BIT(21) | BIT(14));
-+	clrsetbits32(xhci_bar + 0x80e0, BIT(16), BIT(6));
-+	clrsetbits32(xhci_bar + 0x80ec, (7 << 12) | (7 << 9), (0 << 12) | (6 << 9));
-+	clrsetbits32(xhci_bar + 0x80f0, BIT(20), 0);
-+
-+	if (is_lp)
-+		clrsetbits32(xhci_bar + 0x80fc, 0, BIT(25));
-+
-+	if (is_lp)
-+		clrsetbits32(xhci_bar + 0x8110, BIT(8) | BIT(2), BIT(20) | BIT(11));
-+	else
-+		clrsetbits32(xhci_bar + 0x8110, BIT(2), BIT(20) | BIT(11));
-+
-+	if (is_lp)
-+		write32(xhci_bar + 0x8140, 0xff00f03c);
-+	else
-+		write32(xhci_bar + 0x8140, 0xff03c132);
-+
-+	if (is_lp)
-+		clrsetbits32(xhci_bar + 0x8154, BIT(21), BIT(13));
-+	else
-+		clrsetbits32(xhci_bar + 0x8154, BIT(21) | BIT(13), 0);
-+
-+	clrsetbits32(xhci_bar + 0x8154, BIT(3), 0);
-+
-+	if (is_lp) {
-+		clrsetbits32(xhci_bar + 0x8164, 0, BIT(1) | BIT(0));
-+		write32(xhci_bar + 0x8174, 0x01400c0a);
-+		write32(xhci_bar + 0x817c, 0x033200a3);
-+		write32(xhci_bar + 0x8180, 0x00cb0028);
-+		write32(xhci_bar + 0x8184, 0x0064001e);
-+	}
-+
-+	/*
-+	 * Note: Register at offset 0x44 is 32-bit, but bit 31 is write-once.
-+	 * We use these weird partial accesses here to avoid locking bit 31.
-+	 */
-+	pci_or_config16(PCH_XHCI_DEV, 0x44, BIT(15) | BIT(14) | BIT(10) | BIT(0));
-+	pci_or_config8(PCH_XHCI_DEV, 0x44 + 2, 0x0f);
-+
-+	/* LPT-LP >= B0 */
-+	if (is_lp)
-+		clrsetbits32(xhci_bar + 0x8188, 0, BIT(26) | BIT(24));
-+
-+	/* LPT-H >= C0 */
-+	if (!is_lp)
-+		clrsetbits32(xhci_bar + 0x8188, 0, BIT(24));
-+}
-+
-+static inline bool is_mem_sr(void)
-+{
-+	return pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2) & GEN_PMCON_2_MEM_SR;
-+}
-+
-+static bool should_restore_xhci_smart_auto(void)
-+{
-+	if (!is_mem_sr())
-+		return false;
-+
-+	return pci_read_config32(PCH_LPC_DEV, PMIR) & PMIR_XHCI_SMART_AUTO;
-+}
-+
-+enum usb_port_route {
-+	ROUTE_TO_EHCI,
-+	ROUTE_TO_XHCI,
-+};
-+
-+/* Returns whether port reset was successful */
-+static bool reset_usb2_ports(const unsigned int ehci_ports)
-+{
-+	for (unsigned int port = 0; port < ehci_ports; port++) {
-+		/* Initiate port reset for all USB2 ports */
-+		clrsetbits32(
-+			xhci_bar + XHCI_USB2_PORTSC(port),
-+			XHCI_USB2_PORTSC_PED,
-+			XHCI_USB2_PORTSC_PR);
-+	}
-+	/* Poll for port reset bit to be cleared or time out at 100ms */
-+	struct stopwatch timer;
-+	stopwatch_init_msecs_expire(&timer, 100);
-+	uint32_t reg32;
-+	do {
-+		reg32 = 0;
-+		for (unsigned int port = 0; port < ehci_ports; port++)
-+			reg32 |= read32(xhci_bar + XHCI_USB2_PORTSC(port));
-+
-+		reg32 &= XHCI_USB2_PORTSC_PR;
-+		if (!reg32) {
-+			const long elapsed_time = stopwatch_duration_usecs(&timer);
-+			printk(BIOS_DEBUG, "%s: took %lu usecs\n", __func__, elapsed_time);
-+			return true;
-+		}
-+		/* Reference code has a 10 ms delay here, but a smaller delay works too */
-+		udelay(100);
-+	} while (!stopwatch_expired(&timer));
-+	printk(BIOS_ERR, "%s: timed out\n", __func__);
-+	return !reg32;
-+}
-+
-+/* Returns whether warm reset was successful */
-+static bool warm_reset_usb3_ports(const unsigned int xhci_ports)
-+{
-+	for (unsigned int port = 0; port < xhci_ports; port++) {
-+		/* Initiate warm reset for all USB3 ports */
-+		clrsetbits32(
-+			xhci_bar + XHCI_USB3_PORTSC(port),
-+			XHCI_USB3_PORTSC_PED,
-+			XHCI_USB3_PORTSC_WPR);
-+	}
-+	/* Poll for port reset bit to be cleared or time out at 100ms */
-+	struct stopwatch timer;
-+	stopwatch_init_msecs_expire(&timer, 100);
-+	uint32_t reg32;
-+	do {
-+		reg32 = 0;
-+		for (unsigned int port = 0; port < xhci_ports; port++)
-+			reg32 |= read32(xhci_bar + XHCI_USB3_PORTSC(port));
-+
-+		reg32 &= XHCI_USB3_PORTSC_PR;
-+		if (!reg32) {
-+			const long elapsed_time = stopwatch_duration_usecs(&timer);
-+			printk(BIOS_DEBUG, "%s: took %lu usecs\n", __func__, elapsed_time);
-+			return true;
-+		}
-+		/* Reference code has a 10 ms delay here, but a smaller delay works too */
-+		udelay(100);
-+	} while (!stopwatch_expired(&timer));
-+	printk(BIOS_ERR, "%s: timed out\n", __func__);
-+	return !reg32;
-+}
-+
-+static void perform_xhci_ehci_switching_flow(const enum usb_port_route usb_route)
-+{
-+	const pci_devfn_t dev = PCH_XHCI_DEV;
-+
-+	const unsigned int ehci_ports = hs_port_count() + is_usbr_enabled();
-+	const unsigned int xhci_ports = ss_port_count();
-+
-+	const uint32_t ehci_mask = BIT(ehci_ports) - 1;
-+	const uint32_t xhci_mask = BIT(xhci_ports) - 1;
-+
-+	/** TODO: Handle USBr port? How, though? **/
-+	pci_update_config32(dev, XHCI_USB2PRM, ~XHCI_USB2PR_HCSEL, ehci_mask);
-+	pci_update_config32(dev, XHCI_USB3PRM, ~XHCI_USB3PR_SSEN,  xhci_mask);
-+
-+	/*
-+	 * Workaround for USB2PR / USB3PR value not surviving warm reset.
-+	 * Restore USB Port Routing registers if OS HC Switch driver has been executed.
-+	 */
-+	if (should_restore_xhci_smart_auto()) {
-+		/** FIXME: Derive values from mainboard code instead? **/
-+		pci_update_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL, ehci_mask);
-+		pci_update_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN,  xhci_mask);
-+	}
-+
-+	/* Later stages shouldn't need the value of this bit */
-+	pci_and_config32(PCH_LPC_DEV, PMIR, ~PMIR_XHCI_SMART_AUTO);
-+
-+	/**
-+	 * FIXME: Things here depend on the chosen routing mode.
-+	 *        For now, implement both functions.
-+	 */
-+
-+	/* Route to EHCI if xHCI disabled or auto mode */
-+	if (usb_route == ROUTE_TO_EHCI) {
-+		if (!reset_usb2_ports(ehci_ports))
-+			printk(BIOS_ERR, "USB2 port reset timed out\n");
-+
-+		pci_and_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL);
-+
-+		for (unsigned int port = 0; port < ehci_ports; port++) {
-+			clrsetbits32(
-+				xhci_bar + XHCI_USB2_PORTSC(port),
-+				XHCI_USB2_PORTSC_PED,
-+				XHCI_USB2_PORTSC_CHST);
-+		}
-+
-+		if (!warm_reset_usb3_ports(xhci_ports))
-+			printk(BIOS_ERR, "USB3 warm reset timed out\n");
-+
-+		/* FIXME: BWG says this should be inside the warm reset function */
-+		pci_and_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN);
-+
-+		for (unsigned int port = 0; port < ehci_ports; port++) {
-+			clrsetbits32(
-+				xhci_bar + XHCI_USB3_PORTSC(port),
-+				XHCI_USB3_PORTSC_PED,
-+				XHCI_USB3_PORTSC_CHST);
-+		}
-+
-+		setbits32(xhci_bar + XHCI_USBCMD, BIT(0));
-+		clrbits32(xhci_bar + XHCI_USBCMD, BIT(0));
-+	}
-+
-+	/* Route to xHCI if xHCI enabled */
-+	if (usb_route == ROUTE_TO_XHCI) {
-+		if (is_mem_sr()) {
-+			if (!warm_reset_usb3_ports(xhci_ports))
-+				printk(BIOS_ERR, "USB3 warm reset timed out\n");
-+		}
-+
-+		const uint32_t xhci_port_mask = pci_read_config32(dev, XHCI_USB3PRM) & 0x3f;
-+		pci_update_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN, xhci_port_mask);
-+
-+		const uint32_t ehci_port_mask = pci_read_config32(dev, XHCI_USB2PRM) & 0x7fff;
-+		pci_update_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL, ehci_port_mask);
-+	}
-+}
-+
-+/* Do not shift in this macro, as it can cause undefined behaviour for bad port/oc values */
-+#define PORT_TO_OC_SHIFT(port, oc)	((oc) * 8 + (port))
-+
-+/* Avoid shifting into undefined behaviour */
-+static inline bool shift_ok(const int shift)
-+{
-+	return shift >= 0 && shift < 32;
-+}
-+
-+static void usb_overcurrent_mapping(void)
-+{
-+	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
-+
-+	uint32_t ehci_1_ocmap = 0;
-+	uint32_t ehci_2_ocmap = 0;
-+	uint32_t xhci_1_ocmap = 0;
-+	uint32_t xhci_2_ocmap = 0;
-+
-+	/*
-+	 * EHCI
-+	 */
-+	for (unsigned int idx = 0; idx < physical_port_count(); idx++) {
-+		const struct usb2_port_config *const port = &mainboard_usb2_ports[idx];
-+		printk(BIOS_DEBUG, "USB2 port %u => ", idx);
-+		if (!port->enable) {
-+			printk(BIOS_DEBUG, "disabled\n");
-+			continue;
-+		}
-+		const unsigned short oc_pin = port->oc_pin;
-+		if (oc_pin == USB_OC_PIN_SKIP) {
-+			printk(BIOS_DEBUG, "not mapped to OC pin\n");
-+			continue;
-+		}
-+		/* Ports 0 .. 7 => OC 0 .. 3 */
-+		if (idx < 8 && oc_pin <= 3) {
-+			const int shift = PORT_TO_OC_SHIFT(idx, oc_pin);
-+			if (shift_ok(shift)) {
-+				printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
-+				ehci_1_ocmap |= 1 << shift;
-+				continue;
-+			}
-+		}
-+		/* Ports 8 .. 13 => OC 4 .. 7 (LPT-H only) */
-+		if (!is_lp && idx >= 8 && oc_pin >= 4) {
-+			const int shift = PORT_TO_OC_SHIFT(idx, oc_pin - 4);
-+			if (shift_ok(shift)) {
-+				printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
-+				ehci_2_ocmap |= 1 << shift;
-+				continue;
-+			}
-+		}
-+		printk(BIOS_ERR, "Invalid OC pin %u for USB2 port %u\n", oc_pin, idx);
-+	}
-+	printk(BIOS_DEBUG, "\n");
-+	pci_write_config32(PCH_EHCI1_DEV, EHCI_OCMAP, ehci_1_ocmap);
-+	if (!is_lp)
-+		pci_write_config32(PCH_EHCI2_DEV, EHCI_OCMAP, ehci_2_ocmap);
-+
-+	/*
-+	 * xHCI
-+	 */
-+	for (unsigned int idx = 0; idx < ss_port_count(); idx++) {
-+		const struct usb3_port_config *const port = &mainboard_usb3_ports[idx];
-+		printk(BIOS_DEBUG, "USB3 port %u => ", idx);
-+		if (!port->enable) {
-+			printk(BIOS_DEBUG, "disabled\n");
-+			continue;
-+		}
-+		const unsigned short oc_pin = port->oc_pin;
-+		if (oc_pin == USB_OC_PIN_SKIP) {
-+			printk(BIOS_DEBUG, "not mapped to OC pin\n");
-+			continue;
-+		}
-+		/* Ports 0 .. 5 => OC 0 .. 3 */
-+		if (oc_pin <= 3) {
-+			const int shift = PORT_TO_OC_SHIFT(idx, oc_pin);
-+			if (shift_ok(shift)) {
-+				printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
-+				xhci_1_ocmap |= 1 << shift;
-+				continue;
-+			}
-+		}
-+		/* Ports 0 .. 5 => OC 4 .. 7 (LPT-H only) */
-+		if (!is_lp && oc_pin >= 4) {
-+			const int shift = PORT_TO_OC_SHIFT(idx, oc_pin - 4);
-+			if (shift_ok(shift)) {
-+				printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
-+				xhci_2_ocmap |= 1 << shift;
-+				continue;
-+			}
-+		}
-+		printk(BIOS_ERR, "Invalid OC pin %u for USB3 port %u\n", oc_pin, idx);
-+	}
-+	printk(BIOS_DEBUG, "\n");
-+	pci_write_config32(PCH_XHCI_DEV, XHCI_U2OCM1, ehci_1_ocmap);
-+	pci_write_config32(PCH_XHCI_DEV, XHCI_U3OCM1, xhci_1_ocmap);
-+	if (!is_lp) {
-+		pci_write_config32(PCH_XHCI_DEV, XHCI_U2OCM2, ehci_2_ocmap);
-+		pci_write_config32(PCH_XHCI_DEV, XHCI_U3OCM2, xhci_2_ocmap);
-+	}
-+}
-+
-+static uint8_t get_ehci_tune_param_1(const struct usb2_port_config *const port)
-+{
-+	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
-+
-+	const enum pch_platform_type plat_type = get_pch_platform_type();
-+	const enum usb2_port_location location = port->location;
-+	const uint16_t length = port->length;
-+	if (!is_lp) {
-+		if (plat_type == PCH_TYPE_DESKTOP) {
-+			if (location == USB_PORT_BACK_PANEL)
-+				return 4; /* Back Panel */
-+			else
-+				return 3; /* Front Panel */
-+
-+		} else if (plat_type == PCH_TYPE_MOBILE) {
-+			if (location == USB_PORT_INTERNAL)
-+				return 5; /* Internal Topology */
-+			else if (location == USB_PORT_DOCK)
-+				return 4; /* Dock */
-+			else if (length < 0x70)
-+				return 5; /* Back Panel, less than 7" */
-+			else
-+				return 6; /* Back Panel, 7" or more */
-+		}
-+	} else {
-+		if (location == USB_PORT_BACK_PANEL || location == USB_PORT_MINI_PCIE) {
-+			if (length < 0x70)
-+				return 5; /* Back Panel, less than 7" */
-+			else
-+				return 6; /* Back Panel, 7" or more */
-+		} else if (location == USB_PORT_DOCK) {
-+			return 4; /* Dock */
-+		} else {
-+			return 5; /* Internal Topology */
-+		}
-+	}
-+	printk(BIOS_ERR, "%s: Unhandled case\n", __func__);
-+	return 0;
-+}
-+
-+static uint8_t get_ehci_tune_param_2(const struct usb2_port_config *const port)
-+{
-+	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
-+
-+	const enum pch_platform_type plat_type = get_pch_platform_type();
-+	const enum usb2_port_location location = port->location;
-+	const uint16_t length = port->length;
-+	if (!is_lp) {
-+		if (plat_type == PCH_TYPE_DESKTOP) {
-+			if (location == USB_PORT_BACK_PANEL) {
-+				if (length < 0x80)
-+					return 2; /* Back Panel, less than 8" */
-+				else if (length < 0x130)
-+					return 3; /* Back Panel, 8"-13" */
-+				else
-+					return 4; /* Back Panel, 13" or more */
-+			} else {
-+				return 2; /* Front Panel */
-+			}
-+
-+		} else if (plat_type == PCH_TYPE_MOBILE) {
-+			if (location == USB_PORT_INTERNAL) {
-+				return 2; /* Internal Topology */
-+			} else if (location == USB_PORT_DOCK) {
-+				if (length < 0x50)
-+					return 1; /* Dock, less than 5" */
-+				else
-+					return 2; /* Dock, 5" or more */
-+			} else {
-+				if (length < 0x100)
-+					return 2; /* Back Panel, less than 10" */
-+				else
-+					return 3; /* Back Panel, 10" or more */
-+			}
-+		}
-+	} else {
-+		if (location == USB_PORT_BACK_PANEL || location == USB_PORT_MINI_PCIE) {
-+			if (length < 0x100)
-+				return 2; /* Back Panel, less than 10" */
-+			else
-+				return 3; /* Back Panel, 10" or more */
-+		} else if (location == USB_PORT_DOCK) {
-+			if (length < 0x50)
-+				return 1; /* Dock, less than 5" */
-+			else
-+				return 2; /* Dock, 5" or more */
-+		} else {
-+			return 2; /* Internal Topology */
-+		}
-+	}
-+	printk(BIOS_ERR, "%s: Unhandled case\n", __func__);
-+	return 0;
-+}
-+
-+static void program_ehci_port_length(void)
-+{
-+	for (unsigned int port = 0; port < physical_port_count(); port++) {
-+		if (!mainboard_usb2_ports[port].enable)
-+			continue;
-+		const uint32_t addr = 0xe5004000 + (port + 1) * 0x100;
-+		const uint8_t param_1 = get_ehci_tune_param_1(&mainboard_usb2_ports[port]);
-+		const uint8_t param_2 = get_ehci_tune_param_2(&mainboard_usb2_ports[port]);
-+		pch_iobp_update(addr, ~0x7f00, param_2 << 11 | param_1 << 8);
-+	}
-+}
-+
-+void early_usb_init(void)
-+{
-+	/** TODO: Make this configurable? How do the modes affect usbdebug? **/
-+	const enum usb_port_route usb_route = ROUTE_TO_XHCI;
-+	///(pd->boot_mode == 2 && pd->usb_xhci_on_resume) ? ROUTE_TO_XHCI : ROUTE_TO_EHCI;
-+
-+	common_ehci_hcs_init();
-+	xhci_open_memory_space();
-+	common_xhci_hc_init();
-+	perform_xhci_ehci_switching_flow(usb_route);
-+	usb_overcurrent_mapping();
-+	program_ehci_port_length();
-+	/** FIXME: USB per port control is missing, is it needed? **/
-+	xhci_close_memory_space();
-+	/** TODO: Close EHCI memory space? **/
-+}
-diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
-index b5e0c2a830..ad983d86cf 100644
---- a/src/southbridge/intel/lynxpoint/pch.h
-+++ b/src/southbridge/intel/lynxpoint/pch.h
-@@ -115,6 +115,7 @@ enum pch_platform_type {
- 
- void pch_dmi_setup_physical_layer(void);
- void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
-+void early_usb_init(void);
- 
- void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
- void usb_ehci_disable(pci_devfn_t dev);
-@@ -202,6 +203,8 @@ void mainboard_config_rcba(void);
- #define GEN_PMCON_1		0xa0
- #define  SMI_LOCK		(1 << 4)
- #define GEN_PMCON_2		0xa2
-+#define  GEN_PMCON_2_DISB	(1 << 7)
-+#define  GEN_PMCON_2_MEM_SR	(1 << 5)
- #define  SYSTEM_RESET_STS	(1 << 4)
- #define  THERMTRIP_STS		(1 << 3)
- #define  SYSPWR_FLR		(1 << 1)
-@@ -215,6 +218,7 @@ void mainboard_config_rcba(void);
- #define PMIR			0xac
- #define  PMIR_CF9LOCK		(1 << 31)
- #define  PMIR_CF9GR		(1 << 20)
-+#define  PMIR_XHCI_SMART_AUTO	(1 << 16) /* c.f. LPT BWG or WPT-LP BIOS spec */
- 
- /* GEN_PMCON_3 bits */
- #define RTC_BATTERY_DEAD	(1 << 2)
-@@ -282,6 +286,20 @@ void mainboard_config_rcba(void);
- #define SATA_DTLE_DATA_SHIFT	24
- #define SATA_DTLE_EDGE_SHIFT	16
- 
-+/*
-+ * HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index
-+ * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
-+ */
-+#if CONFIG_USBDEBUG_HCD_INDEX != 2
-+#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
-+#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
-+#else
-+#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
-+#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
-+#endif
-+
-+#define PCH_XHCI_TEMP_BAR0	0xe8100000
-+
- /* EHCI PCI Registers */
- #define EHCI_PWR_CTL_STS	0x54
- #define  PWR_CTL_SET_MASK	0x3
-@@ -289,10 +307,15 @@ void mainboard_config_rcba(void);
- #define  PWR_CTL_SET_D3		0x3
- #define  PWR_CTL_ENABLE_PME	(1 << 8)
- #define  PWR_CTL_STATUS_PME	(1 << 15)
-+#define EHCI_OCMAP		0x74
-+#define EHCI_ACCESS_CNTL	0x80
-+#define  ACCESS_CNTL_ENABLE	(1 << 0)
- 
- /* EHCI Memory Registers */
-+#define EHCI_HCS_PARAMS		0x04
- #define EHCI_USB_CMD		0x20
- #define  EHCI_USB_CMD_RUN	(1 << 0)
-+#define  EHCI_USB_CMD_HCRESET	(1 << 1)
- #define  EHCI_USB_CMD_PSE	(1 << 4)
- #define  EHCI_USB_CMD_ASE	(1 << 5)
- #define EHCI_PORTSC(port)	(0x64 + (port) * 4)
-@@ -301,6 +324,10 @@ void mainboard_config_rcba(void);
- 
- /* XHCI PCI Registers */
- #define XHCI_PWR_CTL_STS	0x74
-+#define XHCI_U2OCM1		0xc0
-+#define XHCI_U2OCM2		0xc4
-+#define XHCI_U3OCM1		0xc8
-+#define XHCI_U3OCM2		0xcc
- #define XHCI_USB2PR		0xd0
- #define XHCI_USB2PRM		0xd4
- #define  XHCI_USB2PR_HCSEL	0x7fff
-@@ -313,6 +340,27 @@ void mainboard_config_rcba(void);
- #define XHCI_USB3PDO		0xe8
- 
- /* XHCI Memory Registers */
-+#define XHCI_HCS_PARAMS_1	0x04
-+#define XHCI_HCS_PARAMS_2	0x08
-+#define XHCI_HCS_PARAMS_3	0x0c
-+#define XHCI_HCC_PARAMS		0x10
-+#define XHCI_USBCMD		0x80
-+#define XHCI_USB2_PORTSC(port)	(0x480 + ((port) * 0x10))
-+#define  XHCI_USB2_PORTSC_WPR	(1 << 31)	/* Warm Port Reset */
-+#define  XHCI_USB2_PORTSC_CEC	(1 << 23)	/* Port Config Error Change */
-+#define  XHCI_USB2_PORTSC_PLC	(1 << 22)	/* Port Link State Change */
-+#define  XHCI_USB2_PORTSC_PRC	(1 << 21)	/* Port Reset Change */
-+#define  XHCI_USB2_PORTSC_OCC	(1 << 20)	/* Over-current Change */
-+#define  XHCI_USB2_PORTSC_WRC	(1 << 19)	/* Warm Port Reset Change */
-+#define  XHCI_USB2_PORTSC_PEC	(1 << 18)	/* Port Enabled Disabled Change */
-+#define  XHCI_USB2_PORTSC_CSC	(1 << 17)	/* Connect Status Change */
-+#define  XHCI_USB2_PORTSC_CHST	(0x7f << 17)
-+#define  XHCI_USB2_PORTSC_LWS	(1 << 16)	/* Port Link State Write Strobe */
-+#define  XHCI_USB2_PORTSC_PP	(1 <<  9)
-+#define  XHCI_USB2_PORTSC_PR	(1 <<  4)	/* Port Reset */
-+#define  XHCI_USB2_PORTSC_PED	(1 <<  1)	/* Port Enable/Disabled */
-+#define  XHCI_USB2_PORTSC_CCS	(1 <<  0)	/* Current Connect Status */
-+
- #define XHCI_USB3_PORTSC(port)	((pch_is_lp() ? 0x510 : 0x570) + ((port) * 0x10))
- #define  XHCI_USB3_PORTSC_CHST	(0x7f << 17)
- #define  XHCI_USB3_PORTSC_WCE	(1 << 25)	/* Wake on Connect */
-@@ -320,6 +368,7 @@ void mainboard_config_rcba(void);
- #define  XHCI_USB3_PORTSC_WOE	(1 << 27)	/* Wake on Overcurrent */
- #define  XHCI_USB3_PORTSC_WRC	(1 << 19)	/* Warm Reset Complete */
- #define  XHCI_USB3_PORTSC_LWS	(1 << 16)	/* Link Write Strobe */
-+#define  XHCI_USB3_PORTSC_PR	(1 << 4)	/* Port Reset */
- #define  XHCI_USB3_PORTSC_PED	(1 << 1)	/* Port Enabled/Disabled */
- #define  XHCI_USB3_PORTSC_WPR	(1 << 31)	/* Warm Port Reset */
- #define  XHCI_USB3_PORTSC_PLS	(0xf << 5)	/* Port Link State */
--- 
-2.39.2
-

config/coreboot/haswell/patches/0006-sb-intel-lynxpoint-Add-native-thermal-init.patch

@@ -1,128 +0,0 @@
-From 92be49d8422b4bc1c89bb49535f4dc6a01d47295 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Fri, 6 May 2022 23:22:11 +0200
-Subject: [PATCH 06/26] sb/intel/lynxpoint: Add native thermal init
-
-Implement native thermal initialisation for Lynx Point. This is only
-needed when MRC.bin is not used.
-
-Change-Id: I4a67a3092d0c2e56bfdacb513a899ef838193cbd
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../haswell/native_raminit/raminit_native.c   |  1 +
- src/southbridge/intel/lynxpoint/Makefile.inc  |  2 +-
- src/southbridge/intel/lynxpoint/pch.h         |  1 +
- src/southbridge/intel/lynxpoint/thermal.c     | 64 +++++++++++++++++++
- 4 files changed, 67 insertions(+), 1 deletion(-)
- create mode 100644 src/southbridge/intel/lynxpoint/thermal.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index ef61d4ee09..dd1f1ec14e 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -16,6 +16,7 @@ static bool early_init_native(int s3resume)
- 	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
- 	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
- 
-+	early_thermal_init();
- 	early_usb_init();
- 
- 	if (!CONFIG(INTEL_LYNXPOINT_LP))
-diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
-index 0e1f2fe4eb..a9a9b153d6 100644
---- a/src/southbridge/intel/lynxpoint/Makefile.inc
-+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
-@@ -37,7 +37,7 @@ bootblock-y += early_pch.c
- romstage-y += early_usb.c early_me.c me_status.c early_pch.c
- romstage-y += pmutil.c
- 
--romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c
-+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c
- 
- ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
- romstage-y += lp_gpio.c
-diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
-index ad983d86cf..38a9349220 100644
---- a/src/southbridge/intel/lynxpoint/pch.h
-+++ b/src/southbridge/intel/lynxpoint/pch.h
-@@ -116,6 +116,7 @@ enum pch_platform_type {
- void pch_dmi_setup_physical_layer(void);
- void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
- void early_usb_init(void);
-+void early_thermal_init(void);
- 
- void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
- void usb_ehci_disable(pci_devfn_t dev);
-diff --git a/src/southbridge/intel/lynxpoint/thermal.c b/src/southbridge/intel/lynxpoint/thermal.c
-new file mode 100644
-index 0000000000..e71969ea0c
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/thermal.c
-@@ -0,0 +1,64 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/mmio.h>
-+#include <device/pci_ops.h>
-+#include <southbridge/intel/lynxpoint/pch.h>
-+#include <types.h>
-+
-+#define TBARB_TEMP 0x40000000
-+
-+#define THERMAL_DEV PCI_DEV(0, 0x1f, 6)
-+
-+/* Early thermal init, it may need to be done prior to giving ME its memory */
-+void early_thermal_init(void)
-+{
-+	/* Program address for temporary BAR */
-+	pci_write_config32(THERMAL_DEV, 0x40, TBARB_TEMP);
-+	pci_write_config32(THERMAL_DEV, 0x44, 0);
-+
-+	/* Activate temporary BAR */
-+	pci_or_config32(THERMAL_DEV, 0x40, 1);
-+
-+	/*
-+	 * BWG section 17.3.1 says:
-+	 *
-+	 * ### Initializing Lynx Point Thermal Sensors ###
-+	 *
-+	 * The System BIOS must perform the following steps to initialize the Lynx
-+	 * Point thermal subsystem device, D31:F6. The System BIOS is required to
-+	 * repeat this process on a resume from Sx. BIOS may enable any or all of
-+	 * the registers below based on OEM's platform configuration. Intel does
-+	 * not recommend a value on some of the registers, since each platform has
-+	 * different temperature trip points and one may enable a trip to cause an
-+	 * SMI while another platform would cause an interrupt instead.
-+	 *
-+	 * The recommended flow for enabling thermal sensor is by setting up various
-+	 * temperature trip points first, followed by enabling the desired trip
-+	 * alert method and then enable the actual sensors from TSEL registers.
-+	 * If this flow is not followed, software will need to take special care
-+	 * to handle false events during setting up those registers.
-+	 */
-+
-+	/* Step 1: Program CTT */
-+	write16p(TBARB_TEMP + 0x10, 0x0154);
-+
-+	/* Step 2: Clear trip status from TSS and TAS */
-+	write8p(TBARB_TEMP + 0x06, 0xff);
-+	write8p(TBARB_TEMP + 0x80, 0xff);
-+
-+	/* Step 3: Program TSGPEN and TSPIEN to zero */
-+	write8p(TBARB_TEMP + 0x84, 0x00);
-+	write8p(TBARB_TEMP + 0x82, 0x00);
-+
-+	/*
-+	 * Step 4: If thermal reporting to an EC over SMBus is supported,
-+	 *         then write 0x01 to TSREL, else leave at default.
-+	 */
-+	write8p(TBARB_TEMP + 0x0a, 0x01);
-+
-+	/* Disable temporary BAR */
-+	pci_and_config32(THERMAL_DEV, 0x40, ~1);
-+
-+	/* Clear temporary BAR address */
-+	pci_write_config32(THERMAL_DEV, 0x40, 0);
-+}
--- 
-2.39.2
-

config/coreboot/haswell/patches/0007-sb-intel-lynxpoint-Add-native-PCH-init.patch

@@ -1,785 +0,0 @@
-From 7378cb4fefc87b9a096bb14820a44f26f3a628f5 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Fri, 6 May 2022 23:43:46 +0200
-Subject: [PATCH 07/26] sb/intel/lynxpoint: Add native PCH init
-
-Implement native PCH initialisation for Lynx Point. This is only needed
-when MRC.bin is not used.
-
-Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../haswell/native_raminit/raminit_native.c   |   3 +-
- src/southbridge/intel/lynxpoint/Makefile.inc  |   1 +
- .../intel/lynxpoint/early_pch_native.c        | 123 +++++++++
- .../intel/lynxpoint/hsio/Makefile.inc         |   8 +
- src/southbridge/intel/lynxpoint/hsio/common.c |  52 ++++
- src/southbridge/intel/lynxpoint/hsio/hsio.h   |  46 ++++
- .../intel/lynxpoint/hsio/lpt_h_cx.c           | 244 ++++++++++++++++++
- .../intel/lynxpoint/hsio/lpt_lp_bx.c          | 180 +++++++++++++
- src/southbridge/intel/lynxpoint/pch.h         |   6 +
- 9 files changed, 661 insertions(+), 2 deletions(-)
- create mode 100644 src/southbridge/intel/lynxpoint/hsio/Makefile.inc
- create mode 100644 src/southbridge/intel/lynxpoint/hsio/common.c
- create mode 100644 src/southbridge/intel/lynxpoint/hsio/hsio.h
- create mode 100644 src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c
- create mode 100644 src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index dd1f1ec14e..b6efb6b40d 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -16,8 +16,7 @@ static bool early_init_native(int s3resume)
- 	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
- 	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
- 
--	early_thermal_init();
--	early_usb_init();
-+	early_pch_init_native(s3resume);
- 
- 	if (!CONFIG(INTEL_LYNXPOINT_LP))
- 		dmi_early_init();
-diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
-index a9a9b153d6..63243ecc86 100644
---- a/src/southbridge/intel/lynxpoint/Makefile.inc
-+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
-@@ -38,6 +38,7 @@ romstage-y += early_usb.c early_me.c me_status.c early_pch.c
- romstage-y += pmutil.c
- 
- romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c
-+subdirs-$(CONFIG_USE_NATIVE_RAMINIT) += hsio
- 
- ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
- romstage-y += lp_gpio.c
-diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c
-index c28ddfcf5d..421821fa5d 100644
---- a/src/southbridge/intel/lynxpoint/early_pch_native.c
-+++ b/src/southbridge/intel/lynxpoint/early_pch_native.c
-@@ -1,10 +1,133 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
- #include <console/console.h>
-+#include <device/pci_def.h>
- #include <device/pci_ops.h>
-+#include <southbridge/intel/lynxpoint/hsio/hsio.h>
- #include <southbridge/intel/lynxpoint/pch.h>
- #include <types.h>
- 
-+static void early_sata_init(const uint8_t pch_revision)
-+{
-+	const bool is_mobile = get_pch_platform_type() != PCH_TYPE_DESKTOP;
-+
-+	const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
-+	printk(BIOS_DEBUG, "HSIO lane owner: 0x%02x\n", lane_owner);
-+
-+	/* BWG Step 2 */
-+	pci_update_config32(PCH_SATA_DEV, SATA_SCLKG, ~0x1ff, 0x183);
-+
-+	/* BWG Step 3: Set OOB Retry Mode */
-+	pci_or_config16(PCH_SATA_DEV, SATA_PCS, 1 << 15);
-+
-+	/* BWG Step 4: Program the SATA mPHY tables */
-+	if (pch_is_lp()) {
-+		if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) {
-+			program_hsio_sata_lpt_lp_bx(is_mobile);
-+		} else {
-+			printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision);
-+		}
-+	} else {
-+		if (pch_revision >= LPT_H_STEP_C0) {
-+			program_hsio_sata_lpt_h_cx(is_mobile);
-+		} else {
-+			printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision);
-+		}
-+	}
-+
-+	/** FIXME: Program SATA RxEq tables **/
-+
-+	/* BWG Step 5 */
-+	/** FIXME: Only for desktop and mobile (skip this on workstation and server) **/
-+	pci_or_config32(PCH_SATA_DEV, 0x98, BIT(22));
-+
-+	/* BWG Step 6 */
-+	pci_or_config32(PCH_SATA_DEV, 0x98, BIT(19));
-+
-+	/* BWG Step 7 */
-+	pci_update_config32(PCH_SATA_DEV, 0x98, ~(0x3f << 7), 0x04 << 7);
-+
-+	/* BWG Step 8 */
-+	pci_or_config32(PCH_SATA_DEV, 0x98, BIT(20));
-+
-+	/* BWG Step 9 */
-+	pci_update_config32(PCH_SATA_DEV, 0x98, ~(3 << 5), 1 << 5);
-+
-+	/* BWG Step 10 */
-+	pci_or_config32(PCH_SATA_DEV, 0x98, BIT(18));
-+
-+	/* Enable SATA ports */
-+	uint8_t sata_pcs = 0;
-+	if (CONFIG(INTEL_LYNXPOINT_LP)) {
-+		for (uint8_t i = 0; i < 4; i++) {
-+			if ((lane_owner & BIT(7 - i)) == 0) {
-+				sata_pcs |= BIT(i);
-+			}
-+		}
-+	} else {
-+		sata_pcs |= 0x0f;
-+		for (uint8_t i = 4; i < 6; i++) {
-+			if ((lane_owner & BIT(i)) == 0) {
-+				sata_pcs |= BIT(i);
-+			}
-+		}
-+	}
-+	printk(BIOS_DEBUG, "SATA port enables: 0x%02x\n", sata_pcs);
-+	pci_or_config8(PCH_SATA_DEV, SATA_PCS, sata_pcs);
-+}
-+
-+void early_pch_init_native(int s3resume)
-+{
-+	const uint8_t pch_revision = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
-+
-+	RCBA16(DISPBDF) = 0x0010;
-+	RCBA32_OR(FD2, PCH_ENABLE_DBDF);
-+
-+	/** FIXME: Check GEN_PMCON_3 and handle RTC failure? **/
-+
-+	RCBA32(PRSTS) = BIT(4);
-+
-+	early_sata_init(pch_revision);
-+
-+	pci_or_config8(PCH_LPC_DEV, 0xa6, 1 << 1);
-+	pci_and_config8(PCH_LPC_DEV, 0xdc, ~(1 << 5 | 1 << 1));
-+
-+	/** TODO: Send GET HSIO VER and update ChipsetInit table? Is it needed? **/
-+
-+	/** FIXME: GbE handling? **/
-+
-+	pci_update_config32(PCH_LPC_DEV, 0xac, ~(1 << 20), 0);
-+
-+	for (uint8_t i = 0; i < 8; i++)
-+		pci_update_config32(PCI_DEV(0, 0x1c, i), 0x338, ~(1 << 26), 0);
-+
-+	pci_update_config8(PCI_DEV(0, 0x1c, 0), 0xf4, ~(3 << 5), 1 << 7);
-+
-+	pci_update_config8(PCI_DEV(0, 26, 0), 0x88, ~(1 << 2), 0);
-+	pci_update_config8(PCI_DEV(0, 29, 0), 0x88, ~(1 << 2), 0);
-+
-+	/** FIXME: Disable SATA2 device? **/
-+
-+	if (pch_is_lp()) {
-+		if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) {
-+			program_hsio_xhci_lpt_lp_bx();
-+			program_hsio_igbe_lpt_lp_bx();
-+		} else {
-+			printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision);
-+		}
-+	} else {
-+		if (pch_revision >= LPT_H_STEP_C0) {
-+			program_hsio_xhci_lpt_h_cx();
-+			program_hsio_igbe_lpt_h_cx();
-+		} else {
-+			printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision);
-+		}
-+	}
-+
-+	early_thermal_init();
-+	early_usb_init();
-+}
-+
- void pch_dmi_setup_physical_layer(void)
- {
- 	/* FIXME: We need to make sure the SA supports Gen2 as well */
-diff --git a/src/southbridge/intel/lynxpoint/hsio/Makefile.inc b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc
-new file mode 100644
-index 0000000000..6b74997511
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc
-@@ -0,0 +1,8 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+romstage-y += common.c
-+ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
-+romstage-y += lpt_lp_bx.c
-+else
-+romstage-y += lpt_h_cx.c
-+endif
-diff --git a/src/southbridge/intel/lynxpoint/hsio/common.c b/src/southbridge/intel/lynxpoint/hsio/common.c
-new file mode 100644
-index 0000000000..9935ca347a
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/hsio/common.c
-@@ -0,0 +1,52 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/pci_ops.h>
-+#include <southbridge/intel/lynxpoint/hsio/hsio.h>
-+#include <types.h>
-+
-+/*
-+ * FIXME: Ask Intel whether all lanes need to be programmed as specified
-+ * in the PCH BWG. If not, make separate tables and only check this once.
-+ */
-+void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or)
-+{
-+	const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
-+
-+	if ((addr & 0xfe00) == 0x2000 && (lane_owner & (1 << 4)))
-+		return;
-+
-+	if ((addr & 0xfe00) == 0x2200 && (lane_owner & (1 << 5)))
-+		return;
-+
-+	if (CONFIG(INTEL_LYNXPOINT_LP)) {
-+		if ((addr & 0xfe00) == 0x2400 && (lane_owner & (1 << 6)))
-+			return;
-+
-+		if ((addr & 0xfe00) == 0x2600 && (lane_owner & (1 << 7)))
-+			return;
-+	}
-+	hsio_update(addr, and, or);
-+}
-+
-+/*
-+ * FIXME: Ask Intel whether all lanes need to be programmed as specified
-+ * in the PCH BWG. If not, make separate tables and only check this once.
-+ */
-+void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or)
-+{
-+	const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
-+	if (CONFIG(INTEL_LYNXPOINT_LP)) {
-+		if ((addr & 0xfe00) == 0x2400 && ((lane_owner >> 0) & 3) != 2)
-+			return;
-+
-+		if ((addr & 0xfe00) == 0x2600 && ((lane_owner >> 2) & 3) != 2)
-+			return;
-+	} else {
-+		if ((addr & 0xfe00) == 0x2c00 && ((lane_owner >> 2) & 3) != 2)
-+			return;
-+
-+		if ((addr & 0xfe00) == 0x2e00 && ((lane_owner >> 0) & 3) != 2)
-+			return;
-+	}
-+	hsio_update(addr, and, or);
-+}
-diff --git a/src/southbridge/intel/lynxpoint/hsio/hsio.h b/src/southbridge/intel/lynxpoint/hsio/hsio.h
-new file mode 100644
-index 0000000000..689ef4a05b
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/hsio/hsio.h
-@@ -0,0 +1,46 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_HSIO_H
-+#define SOUTHBRIDGE_INTEL_LYNXPOINT_HSIO_H
-+
-+#include <southbridge/intel/lynxpoint/iobp.h>
-+#include <types.h>
-+
-+struct hsio_table_row {
-+	uint32_t addr;
-+	uint32_t and;
-+	uint32_t or;
-+};
-+
-+static inline void hsio_update(const uint32_t addr, const uint32_t and, const uint32_t or)
-+{
-+	pch_iobp_update(addr, and, or);
-+}
-+
-+static inline void hsio_update_row(const struct hsio_table_row row)
-+{
-+	hsio_update(row.addr, row.and, row.or);
-+}
-+
-+void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or);
-+void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or);
-+
-+static inline void hsio_sata_shared_update_row(const struct hsio_table_row row)
-+{
-+	hsio_sata_shared_update(row.addr, row.and, row.or);
-+}
-+
-+static inline void hsio_xhci_shared_update_row(const struct hsio_table_row row)
-+{
-+	hsio_xhci_shared_update(row.addr, row.and, row.or);
-+}
-+
-+void program_hsio_sata_lpt_h_cx(const bool is_mobile);
-+void program_hsio_xhci_lpt_h_cx(void);
-+void program_hsio_igbe_lpt_h_cx(void);
-+
-+void program_hsio_sata_lpt_lp_bx(const bool is_mobile);
-+void program_hsio_xhci_lpt_lp_bx(void);
-+void program_hsio_igbe_lpt_lp_bx(void);
-+
-+#endif
-diff --git a/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c b/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c
-new file mode 100644
-index 0000000000..b5dd402742
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c
-@@ -0,0 +1,244 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/pci_ops.h>
-+#include <southbridge/intel/lynxpoint/hsio/hsio.h>
-+#include <types.h>
-+
-+const struct hsio_table_row hsio_sata_shared_lpt_h_cx[] = {
-+	{ 0xea002008, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002208, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002038, ~0x3f00000f, 0x0700000d },
-+	{ 0xea002238, ~0x3f00000f, 0x0700000d },
-+	{ 0xea00202c, ~0x00020f00, 0x00020100 },
-+	{ 0xea00222c, ~0x00020f00, 0x00020100 },
-+	{ 0xea002040, ~0x1f000000, 0x01000000 },
-+	{ 0xea002240, ~0x1f000000, 0x01000000 },
-+	{ 0xea002010, ~0xffff0000, 0x0d510000 },
-+	{ 0xea002210, ~0xffff0000, 0x0d510000 },
-+	{ 0xea002018, ~0xffff0300, 0x38250100 },
-+	{ 0xea002218, ~0xffff0300, 0x38250100 },
-+	{ 0xea002000, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002200, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002028, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea002228, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea00201c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00221c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00208c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea00228c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea0020a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0022a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0020ac, ~0x00000030, 0x00000020 },
-+	{ 0xea0022ac, ~0x00000030, 0x00000020 },
-+	{ 0xea002140, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002340, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002144, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002344, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002148, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002348, ~0x00ffffff, 0x00140998 },
-+	{ 0xea00217c, ~0x03000000, 0x03000000 },
-+	{ 0xea00237c, ~0x03000000, 0x03000000 },
-+	{ 0xea002178, ~0x00001f00, 0x00001800 },
-+	{ 0xea002378, ~0x00001f00, 0x00001800 },
-+	{ 0xea00210c, ~0x0038000f, 0x00000005 },
-+	{ 0xea00230c, ~0x0038000f, 0x00000005 },
-+};
-+
-+const struct hsio_table_row hsio_sata_lpt_h_cx[] = {
-+	{ 0xea008008, ~0xff000000, 0x1c000000 },
-+	{ 0xea002408, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002608, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea000808, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea000a08, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002438, ~0x3f00000f, 0x0700000d },
-+	{ 0xea002638, ~0x3f00000f, 0x0700000d },
-+	{ 0xea000838, ~0x3f00000f, 0x0700000d },
-+	{ 0xea000a38, ~0x3f00000f, 0x0700000d },
-+	{ 0xea002440, ~0x1f000000, 0x01000000 },
-+	{ 0xea002640, ~0x1f000000, 0x01000000 },
-+	{ 0xea000840, ~0x1f000000, 0x01000000 },
-+	{ 0xea000a40, ~0x1f000000, 0x01000000 },
-+	{ 0xea002410, ~0xffff0000, 0x0d510000 },
-+	{ 0xea002610, ~0xffff0000, 0x0d510000 },
-+	{ 0xea000810, ~0xffff0000, 0x0d510000 },
-+	{ 0xea000a10, ~0xffff0000, 0x0d510000 },
-+	{ 0xea00242c, ~0x00020800, 0x00020000 },
-+	{ 0xea00262c, ~0x00020800, 0x00020000 },
-+	{ 0xea00082c, ~0x00020800, 0x00020000 },
-+	{ 0xea000a2c, ~0x00020800, 0x00020000 },
-+	{ 0xea002418, ~0xffff0300, 0x38250100 },
-+	{ 0xea002618, ~0xffff0300, 0x38250100 },
-+	{ 0xea000818, ~0xffff0300, 0x38250100 },
-+	{ 0xea000a18, ~0xffff0300, 0x38250100 },
-+	{ 0xea002400, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002600, ~0xcf030000, 0xcf030000 },
-+	{ 0xea000800, ~0xcf030000, 0xcf030000 },
-+	{ 0xea000a00, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002428, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea002628, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea000828, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea000a28, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea00241c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00261c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00081c, ~0x00007c00, 0x00002400 },
-+	{ 0xea000a1c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00248c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea00268c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea00088c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea000a8c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea0024a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0026a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0008a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea000aa4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0024ac, ~0x00000030, 0x00000020 },
-+	{ 0xea0026ac, ~0x00000030, 0x00000020 },
-+	{ 0xea0008ac, ~0x00000030, 0x00000020 },
-+	{ 0xea000aac, ~0x00000030, 0x00000020 },
-+	{ 0xea002540, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002740, ~0x00ffffff, 0x00140718 },
-+	{ 0xea000940, ~0x00ffffff, 0x00140718 },
-+	{ 0xea000b40, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002544, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002744, ~0x00ffffff, 0x00140998 },
-+	{ 0xea000944, ~0x00ffffff, 0x00140998 },
-+	{ 0xea000b44, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002548, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002748, ~0x00ffffff, 0x00140998 },
-+	{ 0xea000948, ~0x00ffffff, 0x00140998 },
-+	{ 0xea000b48, ~0x00ffffff, 0x00140998 },
-+	{ 0xea00257c, ~0x03000000, 0x03000000 },
-+	{ 0xea00277c, ~0x03000000, 0x03000000 },
-+	{ 0xea00097c, ~0x03000000, 0x03000000 },
-+	{ 0xea000b7c, ~0x03000000, 0x03000000 },
-+	{ 0xea002578, ~0x00001f00, 0x00001800 },
-+	{ 0xea002778, ~0x00001f00, 0x00001800 },
-+	{ 0xea000978, ~0x00001f00, 0x00001800 },
-+	{ 0xea000b78, ~0x00001f00, 0x00001800 },
-+	{ 0xea00250c, ~0x0038000f, 0x00000005 },
-+	{ 0xea00270c, ~0x0038000f, 0x00000005 },
-+	{ 0xea00090c, ~0x0038000f, 0x00000005 },
-+	{ 0xea000b0c, ~0x0038000f, 0x00000005 },
-+};
-+
-+const struct hsio_table_row hsio_xhci_shared_lpt_h_cx[] = {
-+	{ 0xe9002c2c, ~0x00000700, 0x00000100 },
-+	{ 0xe9002e2c, ~0x00000700, 0x00000100 },
-+	{ 0xe9002dcc, ~0x00001407, 0x00001407 },
-+	{ 0xe9002fcc, ~0x00001407, 0x00001407 },
-+	{ 0xe9002d68, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9002f68, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9002d6c, ~0x000000ff, 0x0000003f },
-+	{ 0xe9002f6c, ~0x000000ff, 0x0000003f },
-+	{ 0xe9002d4c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe9002f4c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe9002d14, ~0x38000700, 0x00000100 },
-+	{ 0xe9002f14, ~0x38000700, 0x00000100 },
-+	{ 0xe9002d64, ~0x0000f000, 0x00005000 },
-+	{ 0xe9002f64, ~0x0000f000, 0x00005000 },
-+	{ 0xe9002d70, ~0x00000018, 0x00000000 },
-+	{ 0xe9002f70, ~0x00000018, 0x00000000 },
-+	{ 0xe9002c38, ~0x3f00000f, 0x0700000b },
-+	{ 0xe9002e38, ~0x3f00000f, 0x0700000b },
-+	{ 0xe9002d40, ~0x00800000, 0x00000000 },
-+	{ 0xe9002f40, ~0x00800000, 0x00000000 },
-+};
-+
-+const struct hsio_table_row hsio_xhci_lpt_h_cx[] = {
-+	{ 0xe90031cc, ~0x00001407, 0x00001407 },
-+	{ 0xe90033cc, ~0x00001407, 0x00001407 },
-+	{ 0xe90015cc, ~0x00001407, 0x00001407 },
-+	{ 0xe90017cc, ~0x00001407, 0x00001407 },
-+	{ 0xe9003168, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9003368, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9001568, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9001768, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe900316c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900336c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900156c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900176c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900314c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe900334c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe900154c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe900174c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe9003114, ~0x38000700, 0x00000100 },
-+	{ 0xe9003314, ~0x38000700, 0x00000100 },
-+	{ 0xe9001514, ~0x38000700, 0x00000100 },
-+	{ 0xe9001714, ~0x38000700, 0x00000100 },
-+	{ 0xe9003164, ~0x0000f000, 0x00005000 },
-+	{ 0xe9003364, ~0x0000f000, 0x00005000 },
-+	{ 0xe9001564, ~0x0000f000, 0x00005000 },
-+	{ 0xe9001764, ~0x0000f000, 0x00005000 },
-+	{ 0xe9003170, ~0x00000018, 0x00000000 },
-+	{ 0xe9003370, ~0x00000018, 0x00000000 },
-+	{ 0xe9001570, ~0x00000018, 0x00000000 },
-+	{ 0xe9001770, ~0x00000018, 0x00000000 },
-+	{ 0xe9003038, ~0x3f00000f, 0x0700000b },
-+	{ 0xe9003238, ~0x3f00000f, 0x0700000b },
-+	{ 0xe9001438, ~0x3f00000f, 0x0700000b },
-+	{ 0xe9001638, ~0x3f00000f, 0x0700000b },
-+	{ 0xe9003140, ~0x00800000, 0x00000000 },
-+	{ 0xe9003340, ~0x00800000, 0x00000000 },
-+	{ 0xe9001540, ~0x00800000, 0x00000000 },
-+	{ 0xe9001740, ~0x00800000, 0x00000000 },
-+};
-+
-+void program_hsio_sata_lpt_h_cx(const bool is_mobile)
-+{
-+	const struct hsio_table_row *pch_hsio_table;
-+	size_t len;
-+
-+	pch_hsio_table = hsio_sata_lpt_h_cx;
-+	len = ARRAY_SIZE(hsio_sata_lpt_h_cx);
-+	for (size_t i = 0; i < len; i++)
-+		hsio_update_row(pch_hsio_table[i]);
-+
-+	pch_hsio_table = hsio_sata_shared_lpt_h_cx;
-+	len = ARRAY_SIZE(hsio_sata_shared_lpt_h_cx);
-+	for (size_t i = 0; i < len; i++)
-+		hsio_sata_shared_update_row(pch_hsio_table[i]);
-+
-+	const uint32_t hsio_sata_value = is_mobile ? 0x00004c5a : 0x00003e67;
-+
-+	hsio_update(0xea002490, ~0x0000ffff, hsio_sata_value);
-+	hsio_update(0xea002690, ~0x0000ffff, hsio_sata_value);
-+	hsio_update(0xea000890, ~0x0000ffff, hsio_sata_value);
-+	hsio_update(0xea000a90, ~0x0000ffff, hsio_sata_value);
-+
-+	hsio_sata_shared_update(0xea002090, ~0x0000ffff, hsio_sata_value);
-+	hsio_sata_shared_update(0xea002290, ~0x0000ffff, hsio_sata_value);
-+}
-+
-+void program_hsio_xhci_lpt_h_cx(void)
-+{
-+	const struct hsio_table_row *pch_hsio_table;
-+	size_t len;
-+
-+	pch_hsio_table = hsio_xhci_lpt_h_cx;
-+	len = ARRAY_SIZE(hsio_xhci_lpt_h_cx);
-+
-+	for (size_t i = 0; i < len; i++)
-+		hsio_update_row(pch_hsio_table[i]);
-+
-+	pch_hsio_table = hsio_xhci_shared_lpt_h_cx;
-+	len = ARRAY_SIZE(hsio_xhci_shared_lpt_h_cx);
-+
-+	for (size_t i = 0; i < len; i++)
-+		hsio_xhci_shared_update_row(pch_hsio_table[i]);
-+}
-+
-+void program_hsio_igbe_lpt_h_cx(void)
-+{
-+	const uint32_t strpfusecfg1 = pci_read_config32(PCI_DEV(0, 0x1c, 0), 0xfc);
-+	if (!(strpfusecfg1 & (1 << 19)))
-+		return;
-+
-+	const uint8_t gbe_port = (strpfusecfg1 >> 16) & 0x7;
-+	const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
-+	if (gbe_port == 0 && ((lane_owner >> 0) & 3) != 1)
-+		return;
-+
-+	if (gbe_port == 1 && ((lane_owner >> 2) & 3) != 1)
-+		return;
-+
-+	const uint32_t gbe_hsio_base = 0xe900 << 16 | (0x2e - 2 * gbe_port) << 8;
-+	hsio_update(gbe_hsio_base + 0x08, ~0xf0000100, 0xe0000100);
-+}
-diff --git a/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c b/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c
-new file mode 100644
-index 0000000000..24679e791a
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c
-@@ -0,0 +1,180 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/pci_ops.h>
-+#include <southbridge/intel/lynxpoint/iobp.h>
-+#include <southbridge/intel/lynxpoint/hsio/hsio.h>
-+#include <types.h>
-+
-+const struct hsio_table_row hsio_sata_shared_lpt_lp_bx[] = {
-+	{ 0xea008008, ~0xff000000, 0x1c000000 },
-+	{ 0xea002008, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002208, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002408, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002608, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002038, ~0x0000000f, 0x0000000d },
-+	{ 0xea002238, ~0x0000000f, 0x0000000d },
-+	{ 0xea002438, ~0x0000000f, 0x0000000d },
-+	{ 0xea002638, ~0x0000000f, 0x0000000d },
-+	{ 0xea00202c, ~0x00020f00, 0x00020100 },
-+	{ 0xea00222c, ~0x00020f00, 0x00020100 },
-+	{ 0xea00242c, ~0x00020f00, 0x00020100 },
-+	{ 0xea00262c, ~0x00020f00, 0x00020100 },
-+	{ 0xea002040, ~0x1f000000, 0x01000000 },
-+	{ 0xea002240, ~0x1f000000, 0x01000000 },
-+	{ 0xea002440, ~0x1f000000, 0x01000000 },
-+	{ 0xea002640, ~0x1f000000, 0x01000000 },
-+	{ 0xea002010, ~0xffff0000, 0x55510000 },
-+	{ 0xea002210, ~0xffff0000, 0x55510000 },
-+	{ 0xea002410, ~0xffff0000, 0x55510000 },
-+	{ 0xea002610, ~0xffff0000, 0x55510000 },
-+	{ 0xea002140, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002340, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002540, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002740, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002144, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002344, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002544, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002744, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002148, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002348, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002548, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002748, ~0x00ffffff, 0x00140998 },
-+	{ 0xea00217c, ~0x03000000, 0x03000000 },
-+	{ 0xea00237c, ~0x03000000, 0x03000000 },
-+	{ 0xea00257c, ~0x03000000, 0x03000000 },
-+	{ 0xea00277c, ~0x03000000, 0x03000000 },
-+	{ 0xea00208c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea00228c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea00248c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea00268c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea0020a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0022a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0024a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0026a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0020ac, ~0x00000030, 0x00000020 },
-+	{ 0xea0022ac, ~0x00000030, 0x00000020 },
-+	{ 0xea0024ac, ~0x00000030, 0x00000020 },
-+	{ 0xea0026ac, ~0x00000030, 0x00000020 },
-+	{ 0xea002018, ~0xffff0300, 0x38250100 },
-+	{ 0xea002218, ~0xffff0300, 0x38250100 },
-+	{ 0xea002418, ~0xffff0300, 0x38250100 },
-+	{ 0xea002618, ~0xffff0300, 0x38250100 },
-+	{ 0xea002000, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002200, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002400, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002600, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002028, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea002228, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea002428, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea002628, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea00201c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00221c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00241c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00261c, ~0x00007c00, 0x00002400 },
-+	{ 0xea002178, ~0x00001f00, 0x00001800 },
-+	{ 0xea002378, ~0x00001f00, 0x00001800 },
-+	{ 0xea002578, ~0x00001f00, 0x00001800 },
-+	{ 0xea002778, ~0x00001f00, 0x00001800 },
-+	{ 0xea00210c, ~0x0038000f, 0x00000005 },
-+	{ 0xea00230c, ~0x0038000f, 0x00000005 },
-+	{ 0xea00250c, ~0x0038000f, 0x00000005 },
-+	{ 0xea00270c, ~0x0038000f, 0x00000005 },
-+};
-+
-+const struct hsio_table_row hsio_xhci_shared_lpt_lp_bx[] = {
-+	{ 0xe90025cc, ~0x00001407, 0x00001407 },
-+	{ 0xe90027cc, ~0x00001407, 0x00001407 },
-+	{ 0xe9002568, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9002768, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe900242c, ~0x00000700, 0x00000100 },
-+	{ 0xe900262c, ~0x00000700, 0x00000100 },
-+	{ 0xe900256c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900276c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900254c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe900274c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe9002564, ~0x0000f000, 0x00005000 },
-+	{ 0xe9002764, ~0x0000f000, 0x00005000 },
-+	{ 0xe9002570, ~0x00000018, 0x00000000 },
-+	{ 0xe9002770, ~0x00000018, 0x00000000 },
-+	{ 0xe9002514, ~0x38000700, 0x00000100 },
-+	{ 0xe9002714, ~0x38000700, 0x00000100 },
-+	{ 0xe9002438, ~0x0000000f, 0x0000000b },
-+	{ 0xe9002638, ~0x0000000f, 0x0000000b },
-+	{ 0xe9002414, ~0x0000fe00, 0x00006600 },
-+	{ 0xe9002614, ~0x0000fe00, 0x00006600 },
-+	{ 0xe9002540, ~0x00800000, 0x00000000 },
-+	{ 0xe9002740, ~0x00800000, 0x00000000 },
-+};
-+
-+const struct hsio_table_row hsio_xhci_lpt_lp_bx[] = {
-+	{ 0xe90021cc, ~0x00001407, 0x00001407 },
-+	{ 0xe90023cc, ~0x00001407, 0x00001407 },
-+	{ 0xe9002168, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9002368, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe900216c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900236c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900214c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe900234c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe9002164, ~0x0000f000, 0x00005000 },
-+	{ 0xe9002364, ~0x0000f000, 0x00005000 },
-+	{ 0xe9002170, ~0x00000018, 0x00000000 },
-+	{ 0xe9002370, ~0x00000018, 0x00000000 },
-+	{ 0xe9002114, ~0x38000700, 0x00000100 },
-+	{ 0xe9002314, ~0x38000700, 0x00000100 },
-+	{ 0xe9002038, ~0x0000000f, 0x0000000b },
-+	{ 0xe9002238, ~0x0000000f, 0x0000000b },
-+	{ 0xe9002014, ~0x0000fe00, 0x00006600 },
-+	{ 0xe9002214, ~0x0000fe00, 0x00006600 },
-+	{ 0xe9002140, ~0x00800000, 0x00000000 },
-+	{ 0xe9002340, ~0x00800000, 0x00000000 },
-+};
-+
-+void program_hsio_sata_lpt_lp_bx(const bool is_mobile)
-+{
-+	const struct hsio_table_row *pch_hsio_table;
-+	size_t len;
-+
-+	pch_hsio_table = hsio_sata_shared_lpt_lp_bx;
-+	len = ARRAY_SIZE(hsio_sata_shared_lpt_lp_bx);
-+	for (size_t i = 0; i < len; i++)
-+		hsio_sata_shared_update_row(pch_hsio_table[i]);
-+
-+	const uint32_t hsio_sata_value = is_mobile ? 0x00004c5a : 0x00003e67;
-+
-+	hsio_sata_shared_update(0xea002090, ~0x0000ffff, hsio_sata_value);
-+	hsio_sata_shared_update(0xea002290, ~0x0000ffff, hsio_sata_value);
-+	hsio_sata_shared_update(0xea002490, ~0x0000ffff, hsio_sata_value);
-+	hsio_sata_shared_update(0xea002690, ~0x0000ffff, hsio_sata_value);
-+}
-+
-+void program_hsio_xhci_lpt_lp_bx(void)
-+{
-+	const struct hsio_table_row *pch_hsio_table;
-+	size_t len;
-+
-+	pch_hsio_table = hsio_xhci_lpt_lp_bx;
-+	len = ARRAY_SIZE(hsio_xhci_lpt_lp_bx);
-+
-+	for (size_t i = 0; i < len; i++)
-+		hsio_update_row(pch_hsio_table[i]);
-+
-+	pch_hsio_table = hsio_xhci_shared_lpt_lp_bx;
-+	len = ARRAY_SIZE(hsio_xhci_shared_lpt_lp_bx);
-+
-+	for (size_t i = 0; i < len; i++)
-+		hsio_xhci_shared_update_row(pch_hsio_table[i]);
-+}
-+
-+void program_hsio_igbe_lpt_lp_bx(void)
-+{
-+	const uint32_t strpfusecfg1 = pci_read_config32(PCI_DEV(0, 0x1c, 0), 0xfc);
-+	if (!(strpfusecfg1 & (1 << 19)))
-+		return;
-+
-+	const uint8_t gbe_port = (strpfusecfg1 >> 16) & 0x7;
-+	if (gbe_port > 5)
-+		return;
-+
-+	const uint32_t gbe_hsio_base = 0xe900 << 16 | (0x08 + 2 * gbe_port) << 8;
-+	hsio_update(gbe_hsio_base + 0x08, ~0xf0000100, 0xe0000100);
-+}
-diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
-index 38a9349220..74b4d50017 100644
---- a/src/southbridge/intel/lynxpoint/pch.h
-+++ b/src/southbridge/intel/lynxpoint/pch.h
-@@ -117,6 +117,7 @@ void pch_dmi_setup_physical_layer(void);
- void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
- void early_usb_init(void);
- void early_thermal_init(void);
-+void early_pch_init_native(int s3resume);
- 
- void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
- void usb_ehci_disable(pci_devfn_t dev);
-@@ -271,6 +272,10 @@ void mainboard_config_rcba(void);
- #define   IDE_DECODE_ENABLE	(1 << 15)
- #define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
- 
-+#define SATA_MAP		0x90
-+#define SATA_PCS		0x92
-+#define SATA_SCLKG		0x94
-+
- #define SATA_SIRI		0xa0 /* SATA Indexed Register Index */
- #define SATA_SIRD		0xa4 /* SATA Indexed Register Data */
- #define SATA_SP			0xd0 /* Scratchpad */
-@@ -580,6 +585,7 @@ void mainboard_config_rcba(void);
- #define D19IR		0x3168	/* 16bit */
- #define ACPIIRQEN	0x31e0	/* 32bit */
- #define OIC		0x31fe	/* 16bit */
-+#define PRSTS		0x3310	/* 32bit */
- #define PMSYNC_CONFIG	0x33c4	/* 32bit */
- #define PMSYNC_CONFIG2	0x33cc	/* 32bit */
- #define SOFT_RESET_CTRL 0x38f4
--- 
-2.39.2
-

config/coreboot/haswell/patches/0008-nb-intel-haswell-Add-native-raminit-scaffolding.patch

@@ -1,407 +0,0 @@
-From 46cdec8cbce15ca11ad9a49a3ee415a78f781997 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 7 May 2022 00:26:10 +0200
-Subject: [PATCH 08/26] nb/intel/haswell: Add native raminit scaffolding
-
-Implement some scaffolding for Haswell native raminit, like bootmode
-selection, handling of MRC cache and CPU detection.
-
-Change-Id: Icd96649fa045ea7f0f32ae9bfe1e60498d93975b
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../haswell/native_raminit/raminit_main.c     | 104 ++++++++++
- .../haswell/native_raminit/raminit_native.c   | 189 +++++++++++++++++-
- .../haswell/native_raminit/raminit_native.h   |  34 ++++
- 4 files changed, 322 insertions(+), 6 deletions(-)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_main.c
- create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_native.h
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index 8cfb4fb33e..90af951c5a 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -1,3 +1,4 @@
- ## SPDX-License-Identifier: GPL-2.0-or-later
- 
-+romstage-y += raminit_main.c
- romstage-y += raminit_native.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-new file mode 100644
-index 0000000000..9b42c25b40
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -0,0 +1,104 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <assert.h>
-+#include <console/console.h>
-+#include <cpu/intel/haswell/haswell.h>
-+#include <delay.h>
-+#include <device/pci_ops.h>
-+#include <northbridge/intel/haswell/chip.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <northbridge/intel/haswell/raminit.h>
-+#include <string.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+
-+struct task_entry {
-+	enum raminit_status (*task)(struct sysinfo *);
-+	bool is_enabled;
-+	const char *name;
-+};
-+
-+static const struct task_entry cold_boot[] = {
-+};
-+
-+/* Return a generic stepping value to make stepping checks simpler */
-+static enum generic_stepping get_stepping(const uint32_t cpuid)
-+{
-+	switch (cpuid) {
-+	case CPUID_HASWELL_A0:
-+		die("Haswell stepping A0 is not supported\n");
-+	case CPUID_HASWELL_B0:
-+	case CPUID_HASWELL_ULT_B0:
-+	case CPUID_CRYSTALWELL_B0:
-+		return STEPPING_B0;
-+	case CPUID_HASWELL_C0:
-+	case CPUID_HASWELL_ULT_C0:
-+	case CPUID_CRYSTALWELL_C0:
-+		return STEPPING_C0;
-+	default:
-+		/** TODO: Add Broadwell support someday **/
-+		die("Unknown CPUID 0x%x\n", cpuid);
-+	}
-+}
-+
-+static void initialize_ctrl(struct sysinfo *ctrl)
-+{
-+	const struct northbridge_intel_haswell_config *cfg = config_of_soc();
-+	const enum raminit_boot_mode bootmode = ctrl->bootmode;
-+
-+	memset(ctrl, 0, sizeof(*ctrl));
-+
-+	ctrl->cpu = cpu_get_cpuid();
-+	ctrl->stepping = get_stepping(ctrl->cpu);
-+	ctrl->dq_pins_interleaved = cfg->dq_pins_interleaved;
-+	ctrl->bootmode = bootmode;
-+}
-+
-+static enum raminit_status try_raminit(struct sysinfo *ctrl)
-+{
-+	const struct task_entry *const schedule = cold_boot;
-+	const size_t length = ARRAY_SIZE(cold_boot);
-+
-+	enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
-+
-+	for (size_t i = 0; i < length; i++) {
-+		const struct task_entry *const entry = &schedule[i];
-+		assert(entry);
-+		assert(entry->name);
-+		if (!entry->is_enabled)
-+			continue;
-+
-+		assert(entry->task);
-+		printk(RAM_DEBUG, "\nExecuting raminit task %s\n", entry->name);
-+		status = entry->task(ctrl);
-+		printk(RAM_DEBUG, "\n");
-+		if (status) {
-+			printk(BIOS_ERR, "raminit failed on step %s\n", entry->name);
-+			break;
-+		}
-+	}
-+
-+	return status;
-+}
-+
-+void raminit_main(const enum raminit_boot_mode bootmode)
-+{
-+	/*
-+	 * The mighty_ctrl struct. Will happily nuke the pre-RAM stack
-+	 * if left unattended. Make it static and pass pointers to it.
-+	 */
-+	static struct sysinfo mighty_ctrl;
-+
-+	mighty_ctrl.bootmode = bootmode;
-+	initialize_ctrl(&mighty_ctrl);
-+
-+	/** TODO: Try more than once **/
-+	enum raminit_status status = try_raminit(&mighty_ctrl);
-+
-+	if (status != RAMINIT_STATUS_SUCCESS)
-+		die("Memory initialization was met with utmost failure and misery\n");
-+
-+	/** TODO: Implement the required magic **/
-+	die("NATIVE RAMINIT: More Magic (tm) required.\n");
-+}
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index b6efb6b40d..0869db3902 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -1,13 +1,45 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
-+#include <arch/cpu.h>
-+#include <assert.h>
-+#include <cbmem.h>
-+#include <cf9_reset.h>
- #include <console/console.h>
-+#include <cpu/x86/msr.h>
- #include <delay.h>
-+#include <device/pci_ops.h>
-+#include <mrc_cache.h>
- #include <northbridge/intel/haswell/haswell.h>
- #include <northbridge/intel/haswell/raminit.h>
- #include <southbridge/intel/lynxpoint/me.h>
- #include <southbridge/intel/lynxpoint/pch.h>
- #include <types.h>
- 
-+#include "raminit_native.h"
-+
-+static void wait_txt_clear(void)
-+{
-+	const struct cpuid_result cpuid = cpuid_ext(1, 0);
-+
-+	/* Check if TXT is supported */
-+	if (!(cpuid.ecx & BIT(6)))
-+		return;
-+
-+	/* Some TXT public bit */
-+	if (!(read32p(0xfed30010) & 1))
-+		return;
-+
-+	/* Wait for TXT clear */
-+	do {} while (!(read8p(0xfed40000) & (1 << 7)));
-+}
-+
-+static enum raminit_boot_mode get_boot_mode(void)
-+{
-+	const uint16_t pmcon_2 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2);
-+	const uint16_t bitmask = GEN_PMCON_2_DISB | GEN_PMCON_2_MEM_SR;
-+	return (pmcon_2 & bitmask) == bitmask ? BOOTMODE_WARM : BOOTMODE_COLD;
-+}
-+
- static bool early_init_native(int s3resume)
- {
- 	printk(BIOS_DEBUG, "Starting native platform initialisation\n");
-@@ -24,6 +56,120 @@ static bool early_init_native(int s3resume)
- 	return cpu_replaced;
- }
- 
-+#define MRC_CACHE_VERSION 1
-+
-+struct mrc_data {
-+	const void *buffer;
-+	size_t buffer_len;
-+};
-+
-+static void save_mrc_data(struct mrc_data *md)
-+{
-+	mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len);
-+}
-+
-+static struct mrc_data prepare_mrc_cache(void)
-+{
-+	struct mrc_data md = {0};
-+	md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
-+						MRC_CACHE_VERSION,
-+						&md.buffer_len);
-+	return md;
-+}
-+
-+static const char *const bm_names[] = {
-+	"BOOTMODE_COLD",
-+	"BOOTMODE_WARM",
-+	"BOOTMODE_S3",
-+	"BOOTMODE_FAST",
-+};
-+
-+static void clear_disb(void)
-+{
-+	pci_and_config16(PCH_LPC_DEV, GEN_PMCON_2, ~GEN_PMCON_2_DISB);
-+}
-+
-+static void raminit_reset(void)
-+{
-+	clear_disb();
-+	system_reset();
-+}
-+
-+static enum raminit_boot_mode do_actual_raminit(
-+	struct mrc_data *md,
-+	const bool s3resume,
-+	const bool cpu_replaced,
-+	const enum raminit_boot_mode orig_bootmode)
-+{
-+	enum raminit_boot_mode bootmode = orig_bootmode;
-+
-+	bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/
-+
-+	if (s3resume) {
-+		if (bootmode == BOOTMODE_COLD) {
-+			printk(BIOS_EMERG, "Memory may not be in self-refresh for S3 resume\n");
-+			printk(BIOS_EMERG, "S3 resume and cold boot are mutually exclusive\n");
-+			raminit_reset();
-+		}
-+		/* Only a true mad hatter would replace a CPU in S3 */
-+		if (cpu_replaced) {
-+			printk(BIOS_EMERG, "Oh no, CPU was replaced during S3\n");
-+			/*
-+			 * No reason to continue, memory consistency is most likely lost
-+			 * and ME will probably request a reset through DID response too.
-+			 */
-+			/** TODO: Figure out why past self commented this out **/
-+			//raminit_reset();
-+		}
-+		bootmode = BOOTMODE_S3;
-+		if (!save_data_valid) {
-+			printk(BIOS_EMERG, "No training data, S3 resume is impossible\n");
-+			/* Failed S3 resume, reset to come up cleanly */
-+			raminit_reset();
-+		}
-+	}
-+	if (!s3resume && cpu_replaced) {
-+		printk(BIOS_NOTICE, "CPU was replaced, forcing a cold boot\n");
-+		/*
-+		 * Looks like the ME will get angry if raminit takes too long.
-+		 * It will report that the CPU has been replaced on next boot.
-+		 * Try to continue anyway. This should not happen in most cases.
-+		 */
-+		/** TODO: Figure out why past self commented this out **/
-+		//save_data_valid = false;
-+	}
-+	if (bootmode == BOOTMODE_COLD) {
-+		/* If possible, promote to a fast boot */
-+		if (save_data_valid)
-+			bootmode = BOOTMODE_FAST;
-+
-+		clear_disb();
-+	} else if (bootmode == BOOTMODE_WARM) {
-+		/* If a warm reset happened before raminit is done, force a cold boot */
-+		if (mchbar_read32(SSKPD) == 0 && mchbar_read32(SSKPD + 4) == 0) {
-+			printk(BIOS_NOTICE, "Warm reset occurred early in cold boot\n");
-+			save_data_valid = false;
-+		}
-+		if (!save_data_valid)
-+			bootmode = BOOTMODE_COLD;
-+	}
-+	assert(save_data_valid != (bootmode == BOOTMODE_COLD));
-+	if (save_data_valid) {
-+		printk(BIOS_INFO, "Using cached memory parameters\n");
-+		die("RAMINIT: Fast boot is not yet implemented\n");
-+	}
-+	printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]);
-+	printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]);
-+
-+	/*
-+	 * And now, the actual memory initialization thing.
-+	 */
-+	printk(RAM_DEBUG, "\nStarting native raminit\n");
-+	raminit_main(bootmode);
-+
-+	return bootmode;
-+}
-+
- void perform_raminit(const int s3resume)
- {
- 	/*
-@@ -32,17 +178,48 @@ void perform_raminit(const int s3resume)
- 	 */
- 	const bool cpu_replaced = early_init_native(s3resume);
- 
--	(void)cpu_replaced;
-+	wait_txt_clear();
-+	wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
-+
-+	const enum raminit_boot_mode orig_bootmode = get_boot_mode();
-+
-+	struct mrc_data md = prepare_mrc_cache();
-+
-+	const enum raminit_boot_mode bootmode =
-+			do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode);
-+
-+	/** TODO: report_memory_config **/
- 
--	/** TODO: Move after raminit */
- 	if (intel_early_me_uma_size() > 0) {
--		/** TODO: Update status once raminit is implemented **/
--		uint8_t me_status = ME_INIT_STATUS_ERROR;
-+		/*
-+		 * The 'other' success value is to report loss of memory
-+		 * consistency to ME if warm boot was downgraded to cold.
-+		 */
-+		uint8_t me_status;
-+		if (BOOTMODE_WARM == orig_bootmode && BOOTMODE_COLD == bootmode)
-+			me_status = ME_INIT_STATUS_SUCCESS_OTHER;
-+		else
-+			me_status = ME_INIT_STATUS_SUCCESS;
-+
-+		/** TODO: Remove this once raminit is implemented **/
-+		me_status = ME_INIT_STATUS_ERROR;
- 		intel_early_me_init_done(me_status);
- 	}
- 
-+	post_code(0x3b);
-+
- 	intel_early_me_status();
- 
--	/** TODO: Implement the required magic **/
--	die("NATIVE RAMINIT: More Magic (tm) required.\n");
-+	const bool cbmem_was_initted = !cbmem_recovery(s3resume);
-+	if (s3resume && !cbmem_was_initted) {
-+		/* Failed S3 resume, reset to come up cleanly */
-+		printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
-+		system_reset();
-+	}
-+
-+	/* Save training data on non-S3 resumes */
-+	if (!s3resume)
-+		save_mrc_data(&md);
-+
-+	/** TODO: setup_sdram_meminfo **/
- }
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-new file mode 100644
-index 0000000000..885f0184f4
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -0,0 +1,34 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#ifndef HASWELL_RAMINIT_NATIVE_H
-+#define HASWELL_RAMINIT_NATIVE_H
-+
-+enum raminit_boot_mode {
-+	BOOTMODE_COLD,
-+	BOOTMODE_WARM,
-+	BOOTMODE_S3,
-+	BOOTMODE_FAST,
-+};
-+
-+enum raminit_status {
-+	RAMINIT_STATUS_SUCCESS = 0,
-+	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
-+};
-+
-+enum generic_stepping {
-+	STEPPING_A0 = 1,
-+	STEPPING_B0 = 2,
-+	STEPPING_C0 = 3,
-+};
-+
-+struct sysinfo {
-+	enum raminit_boot_mode bootmode;
-+	enum generic_stepping stepping;
-+	uint32_t cpu;		/* CPUID value */
-+
-+	bool dq_pins_interleaved;
-+};
-+
-+void raminit_main(enum raminit_boot_mode bootmode);
-+
-+#endif
--- 
-2.39.2
-

config/coreboot/haswell/patches/0009-nb-intel-haswell-nri-Only-do-CPU-replacement-check-o.patch

@@ -1,57 +0,0 @@
-From 731216aef3129ae27ad5adc7266cb8a58090c9fc Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sun, 26 Jun 2022 10:32:12 +0200
-Subject: [PATCH 09/26] nb/intel/haswell/nri: Only do CPU replacement check on
- cold boots
-
-CPU replacement check should only be done on cold boots.
-
-Change-Id: I98efa105f4df755b23febe12dd7b356787847852
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/raminit_native.c   | 13 ++++++-------
- 1 file changed, 6 insertions(+), 7 deletions(-)
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index 0869db3902..bd9bc8e692 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -40,15 +40,14 @@ static enum raminit_boot_mode get_boot_mode(void)
- 	return (pmcon_2 & bitmask) == bitmask ? BOOTMODE_WARM : BOOTMODE_COLD;
- }
- 
--static bool early_init_native(int s3resume)
-+static bool early_init_native(enum raminit_boot_mode bootmode)
- {
- 	printk(BIOS_DEBUG, "Starting native platform initialisation\n");
- 
- 	intel_early_me_init();
--	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
--	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
-+	bool cpu_replaced = bootmode == BOOTMODE_COLD && intel_early_me_cpu_replacement_check();
- 
--	early_pch_init_native(s3resume);
-+	early_pch_init_native(bootmode == BOOTMODE_S3);
- 
- 	if (!CONFIG(INTEL_LYNXPOINT_LP))
- 		dmi_early_init();
-@@ -176,13 +175,13 @@ void perform_raminit(const int s3resume)
- 	 * See, this function's name is a lie. There are more things to
- 	 * do that memory initialisation, but they are relatively easy.
- 	 */
--	const bool cpu_replaced = early_init_native(s3resume);
-+	const enum raminit_boot_mode orig_bootmode = get_boot_mode();
-+
-+	const bool cpu_replaced = early_init_native(s3resume ? BOOTMODE_S3 : orig_bootmode);
- 
- 	wait_txt_clear();
- 	wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
- 
--	const enum raminit_boot_mode orig_bootmode = get_boot_mode();
--
- 	struct mrc_data md = prepare_mrc_cache();
- 
- 	const enum raminit_boot_mode bootmode =
--- 
-2.39.2
-

config/coreboot/haswell/patches/0010-haswell-NRI-Collect-SPD-info.patch

@@ -1,344 +0,0 @@
-From 354969af4361bcc7dc240ef5871d169728f7f0cc Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 7 May 2022 13:48:53 +0200
-Subject: [PATCH 10/26] haswell NRI: Collect SPD info
-
-Collect SPD data from DIMMs and memory-down, and find the common
-supported settings.
-
-Change-Id: I4e6a1408a638a463ecae37a447cfed1d6556e44a
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../haswell/native_raminit/raminit_main.c     |   1 +
- .../haswell/native_raminit/raminit_native.h   |  57 +++++
- .../haswell/native_raminit/spd_bitmunching.c  | 206 ++++++++++++++++++
- 4 files changed, 265 insertions(+)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index 90af951c5a..ebf7abc6ec 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -2,3 +2,4 @@
- 
- romstage-y += raminit_main.c
- romstage-y += raminit_native.c
-+romstage-y += spd_bitmunching.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 9b42c25b40..2d2cfa48bb 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -20,6 +20,7 @@ struct task_entry {
- };
- 
- static const struct task_entry cold_boot[] = {
-+	{ collect_spd_info,                                       true, "PROCSPD",    },
- };
- 
- /* Return a generic stepping value to make stepping checks simpler */
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 885f0184f4..1a0793947e 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -3,6 +3,15 @@
- #ifndef HASWELL_RAMINIT_NATIVE_H
- #define HASWELL_RAMINIT_NATIVE_H
- 
-+#include <device/dram/ddr3.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+
-+#define SPD_LEN 256
-+
-+/* 8 data lanes + 1 ECC lane */
-+#define NUM_LANES		9
-+#define NUM_LANES_NO_ECC	8
-+
- enum raminit_boot_mode {
- 	BOOTMODE_COLD,
- 	BOOTMODE_WARM,
-@@ -12,6 +21,8 @@ enum raminit_boot_mode {
- 
- enum raminit_status {
- 	RAMINIT_STATUS_SUCCESS = 0,
-+	RAMINIT_STATUS_NO_MEMORY_INSTALLED,
-+	RAMINIT_STATUS_UNSUPPORTED_MEMORY,
- 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
- };
- 
-@@ -21,14 +32,60 @@ enum generic_stepping {
- 	STEPPING_C0 = 3,
- };
- 
-+struct raminit_dimm_info {
-+	spd_raw_data raw_spd;
-+	struct dimm_attr_ddr3_st data;
-+	uint8_t spd_addr;
-+	bool valid;
-+};
-+
- struct sysinfo {
- 	enum raminit_boot_mode bootmode;
- 	enum generic_stepping stepping;
- 	uint32_t cpu;		/* CPUID value */
- 
- 	bool dq_pins_interleaved;
-+
-+	/** TODO: ECC support untested **/
-+	bool is_ecc;
-+
-+	/**
-+	 * FIXME: LPDDR support is incomplete. The largest chunks are missing,
-+	 * but some LPDDR-specific variations in algorithms have been handled.
-+	 * LPDDR-specific functions have stubs which will halt upon execution.
-+	 */
-+	bool lpddr;
-+
-+	struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS];
-+	union dimm_flags_ddr3_st flags;
-+	uint16_t cas_supported;
-+
-+	/* Except for tCK, everything is eventually stored in DCLKs */
-+	uint32_t tCK;
-+	uint32_t tAA;			/* Also known as tCL */
-+	uint32_t tWR;
-+	uint32_t tRCD;
-+	uint32_t tRRD;
-+	uint32_t tRP;
-+	uint32_t tRAS;
-+	uint32_t tRC;
-+	uint32_t tRFC;
-+	uint32_t tWTR;
-+	uint32_t tRTP;
-+	uint32_t tFAW;
-+	uint32_t tCWL;
-+	uint32_t tCMD;
-+
-+	uint8_t lanes;			/* 8 or 9 */
-+	uint8_t chanmap;
-+	uint8_t dpc[NUM_CHANNELS];	/* DIMMs per channel */
-+	uint8_t rankmap[NUM_CHANNELS];
-+	uint8_t rank_mirrored[NUM_CHANNELS];
-+	uint32_t channel_size_mb[NUM_CHANNELS];
- };
- 
- void raminit_main(enum raminit_boot_mode bootmode);
- 
-+enum raminit_status collect_spd_info(struct sysinfo *ctrl);
-+
- #endif
-diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
-new file mode 100644
-index 0000000000..dbe02c72d0
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
-@@ -0,0 +1,206 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <cbfs.h>
-+#include <commonlib/clamp.h>
-+#include <console/console.h>
-+#include <device/dram/ddr3.h>
-+#include <device/smbus_host.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <northbridge/intel/haswell/raminit.h>
-+#include <string.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+
-+static const uint8_t *get_spd_data_from_cbfs(struct spd_info *spdi)
-+{
-+	if (!CONFIG(HAVE_SPD_IN_CBFS))
-+		return NULL;
-+
-+	printk(RAM_DEBUG, "SPD index %u\n", spdi->spd_index);
-+
-+	size_t spd_file_len;
-+	uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len);
-+
-+	if (!spd_file) {
-+		printk(BIOS_ERR, "SPD data not found in CBFS\n");
-+		return NULL;
-+	}
-+
-+	if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
-+		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
-+		spdi->spd_index = 0;
-+	}
-+
-+	if (spd_file_len < SPD_LEN) {
-+		printk(BIOS_ERR, "Invalid SPD data in CBFS\n");
-+		return NULL;
-+	}
-+
-+	return spd_file + (spdi->spd_index * SPD_LEN);
-+}
-+
-+static void get_spd_for_dimm(struct raminit_dimm_info *const dimm, const uint8_t *cbfs_spd)
-+{
-+	if (dimm->spd_addr == SPD_MEMORY_DOWN) {
-+		if (cbfs_spd) {
-+			memcpy(dimm->raw_spd, cbfs_spd, SPD_LEN);
-+			dimm->valid = true;
-+			printk(RAM_DEBUG, "memory-down\n");
-+			return;
-+		} else {
-+			printk(RAM_DEBUG, "memory-down but no CBFS SPD data, ignoring\n");
-+			return;
-+		}
-+	}
-+	printk(RAM_DEBUG, "slotted ");
-+	const uint8_t spd_mem_type = smbus_read_byte(dimm->spd_addr, SPD_MEMORY_TYPE);
-+	if (spd_mem_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
-+		printk(RAM_DEBUG, "and not DDR3, ignoring\n");
-+		return;
-+	}
-+	printk(RAM_DEBUG, "and DDR3\n");
-+	if (i2c_eeprom_read(dimm->spd_addr, 0, SPD_LEN, dimm->raw_spd) != SPD_LEN) {
-+		printk(BIOS_WARNING, "I2C block read failed, trying SMBus byte reads\n");
-+		for (uint32_t i = 0; i < SPD_LEN; i++)
-+			dimm->raw_spd[i] = smbus_read_byte(dimm->spd_addr, i);
-+	}
-+	dimm->valid = true;
-+}
-+
-+static void get_spd_data(struct sysinfo *ctrl)
-+{
-+	struct spd_info spdi = {0};
-+	mb_get_spd_map(&spdi);
-+	const uint8_t *cbfs_spd = get_spd_data_from_cbfs(&spdi);
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
-+			struct raminit_dimm_info *const dimm = &ctrl->dimms[channel][slot];
-+			dimm->spd_addr = spdi.addresses[channel + channel + slot];
-+			if (!dimm->spd_addr)
-+				continue;
-+
-+			printk(RAM_DEBUG, "CH%uS%u is ", channel, slot);
-+			get_spd_for_dimm(dimm, cbfs_spd);
-+		}
-+	}
-+}
-+
-+static void decode_spd(struct raminit_dimm_info *const dimm)
-+{
-+	/** TODO: Hook up somewhere, and handle lack of XMP data **/
-+	const bool enable_xmp = false;
-+	memset(&dimm->data, 0, sizeof(dimm->data));
-+	if (enable_xmp)
-+		spd_xmp_decode_ddr3(&dimm->data, dimm->raw_spd, DDR3_XMP_PROFILE_1);
-+	else
-+		spd_decode_ddr3(&dimm->data, dimm->raw_spd);
-+
-+	if (CONFIG(DEBUG_RAM_SETUP))
-+		dram_print_spd_ddr3(&dimm->data);
-+}
-+
-+static enum raminit_status find_common_spd_parameters(struct sysinfo *ctrl)
-+{
-+	ctrl->cas_supported = 0xffff;
-+	ctrl->flags.raw = 0xffffffff;
-+
-+	ctrl->tCK  = 0;
-+	ctrl->tAA  = 0;
-+	ctrl->tWR  = 0;
-+	ctrl->tRCD = 0;
-+	ctrl->tRRD = 0;
-+	ctrl->tRP  = 0;
-+	ctrl->tRAS = 0;
-+	ctrl->tRC  = 0;
-+	ctrl->tRFC = 0;
-+	ctrl->tWTR = 0;
-+	ctrl->tRTP = 0;
-+	ctrl->tFAW = 0;
-+	ctrl->tCWL = 0;
-+	ctrl->tCMD = 0;
-+	ctrl->chanmap = 0;
-+
-+	bool yes_ecc = false;
-+	bool not_ecc = false;
-+
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		ctrl->dpc[channel] = 0;
-+		ctrl->rankmap[channel] = 0;
-+		ctrl->rank_mirrored[channel] = 0;
-+		ctrl->channel_size_mb[channel] = 0;
-+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
-+			struct raminit_dimm_info *const dimm = &ctrl->dimms[channel][slot];
-+			if (!dimm->valid)
-+				continue;
-+
-+			printk(RAM_DEBUG, "\nCH%uS%u SPD:\n", channel, slot);
-+			decode_spd(dimm);
-+
-+			ctrl->chanmap |= BIT(channel);
-+			ctrl->dpc[channel]++;
-+			ctrl->channel_size_mb[channel] += dimm->data.size_mb;
-+
-+			/* The first rank of a populated slot is always present */
-+			const uint8_t rank = slot + slot;
-+			assert(dimm->data.ranks);
-+			ctrl->rankmap[channel] |= (BIT(dimm->data.ranks) - 1) << rank;
-+
-+			if (dimm->data.flags.pins_mirrored)
-+				ctrl->rank_mirrored[channel] |= BIT(rank + 1);
-+
-+			/* Find common settings */
-+			ctrl->cas_supported &= dimm->data.cas_supported;
-+			ctrl->flags.raw &= dimm->data.flags.raw;
-+			ctrl->tCK  = MAX(ctrl->tCK,  dimm->data.tCK);
-+			ctrl->tAA  = MAX(ctrl->tAA,  dimm->data.tAA);
-+			ctrl->tWR  = MAX(ctrl->tWR,  dimm->data.tWR);
-+			ctrl->tRCD = MAX(ctrl->tRCD, dimm->data.tRCD);
-+			ctrl->tRRD = MAX(ctrl->tRRD, dimm->data.tRRD);
-+			ctrl->tRP  = MAX(ctrl->tRP,  dimm->data.tRP);
-+			ctrl->tRAS = MAX(ctrl->tRAS, dimm->data.tRAS);
-+			ctrl->tRC  = MAX(ctrl->tRC,  dimm->data.tRC);
-+			ctrl->tRFC = MAX(ctrl->tRFC, dimm->data.tRFC);
-+			ctrl->tWTR = MAX(ctrl->tWTR, dimm->data.tWTR);
-+			ctrl->tRTP = MAX(ctrl->tRTP, dimm->data.tRTP);
-+			ctrl->tFAW = MAX(ctrl->tFAW, dimm->data.tFAW);
-+			ctrl->tCWL = MAX(ctrl->tCWL, dimm->data.tCWL);
-+			ctrl->tCMD = MAX(ctrl->tCMD, dimm->data.tCMD);
-+
-+			yes_ecc |=  dimm->data.flags.is_ecc;
-+			not_ecc |= !dimm->data.flags.is_ecc;
-+		}
-+	}
-+
-+	if (!ctrl->chanmap) {
-+		printk(BIOS_ERR, "No DIMMs were found\n");
-+		return RAMINIT_STATUS_NO_MEMORY_INSTALLED;
-+	}
-+	if (!ctrl->cas_supported) {
-+		printk(BIOS_ERR, "Could not resolve common CAS latency\n");
-+		return RAMINIT_STATUS_UNSUPPORTED_MEMORY;
-+	}
-+	/** TODO: Properly handle ECC support and ECC forced **/
-+	if (yes_ecc && not_ecc) {
-+		/** TODO: Test if the ECC DIMMs can be operated as non-ECC DIMMs **/
-+		printk(BIOS_ERR, "Both ECC and non-ECC DIMMs present, this is unsupported\n");
-+		return RAMINIT_STATUS_UNSUPPORTED_MEMORY;
-+	}
-+	if (yes_ecc)
-+		ctrl->lanes = NUM_LANES;
-+	else
-+		ctrl->lanes = NUM_LANES_NO_ECC;
-+
-+	ctrl->is_ecc = yes_ecc;
-+
-+	/** TODO: Complete LPDDR support **/
-+	ctrl->lpddr = false;
-+
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-+
-+enum raminit_status collect_spd_info(struct sysinfo *ctrl)
-+{
-+	get_spd_data(ctrl);
-+	return find_common_spd_parameters(ctrl);
-+}
--- 
-2.39.2
-

config/coreboot/haswell/patches/0026-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -1,38 +0,0 @@
-From 1ce4f118b024a6367382b46016781f30fe622e3e Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH] Remove warning for coreboot images built without a payload
-
-I added this in upstream to prevent people from accidentally flashing
-roms without a payload resulting in a no boot situation, but in
-libreboot lbmk handles the payload and thus this warning always comes
-up. This has caused confusion and concern so just patch it out.
----
- payloads/Makefile.inc | 13 +------------
- 1 file changed, 1 insertion(+), 12 deletions(-)
-
-diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
-index e735443a76..4f1692a873 100644
---- a/payloads/Makefile.inc
-+++ b/payloads/Makefile.inc
-@@ -49,16 +49,5 @@ distclean-payloads:
- print-repo-info-payloads:
- 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
- 
--ifeq ($(CONFIG_PAYLOAD_NONE),y)
--files_added:: warn_no_payload
--endif
--
--warn_no_payload:
--	printf "\n\t** WARNING **\n"
--	printf "coreboot has been built without a payload. Writing\n"
--	printf "a coreboot image without a payload to your board's\n"
--	printf "flash chip will result in a non-booting system. You\n"
--	printf "can use cbfstool to add a payload to the image.\n\n"
--
- .PHONY: force-payload coreinfo nvramcui
--.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
-+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--- 
-2.40.1
-

config/coreboot/haswell/patches/0027-coreboot-haswell-fix-acpica-downloads.patch

@@ -1,30 +0,0 @@
-From 29c1116ebd5879568010a8386e4838294a78b408 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 16 Jul 2023 03:48:23 +0100
-Subject: [PATCH 1/1] coreboot/haswell: fix acpica downloads
-
-the upstream link died. i now host the relevant acpica
-tarball myself, on libreboot rsync. this patch makes
-coreboot crossgcc use that
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- util/crossgcc/buildgcc | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 3c4b10cc92..0c4262b7b1 100755
---- a/util/crossgcc/buildgcc
-+++ b/util/crossgcc/buildgcc
-@@ -52,7 +52,7 @@ MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz"
- MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
- GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
- BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
--IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
-+IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
- # CLANG toolchain archive locations
- LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz"
- CLANG_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/clang-${CLANG_VERSION}.src.tar.xz"
--- 
-2.40.1
-

config/coreboot/haswell/patches/0028-use-mirrorservice.org-for-gcc-downloads.patch

@@ -1,36 +0,0 @@
-From ca1bd48a87ab46ebfb444b0e092442bf6270ec7a Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 5 Nov 2023 23:19:42 +0000
-Subject: [PATCH 1/1] use mirrorservice.org for gcc downloads
-
-the gnu.org 302 redirect often fails
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- util/crossgcc/buildgcc | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index d4cc8b2a24..526940acfa 100755
---- a/util/crossgcc/buildgcc
-+++ b/util/crossgcc/buildgcc
-@@ -47,11 +47,11 @@ NASM_VERSION=2.15.05
- # These are sanitized by the jenkins toolchain test builder, so if
- # a completely new URL is added here, it probably needs to be added
- # to the jenkins build as well, or the builder won't download it.
--GMP_ARCHIVE="https://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.xz"
--MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz"
--MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
--GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
--BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
-+GMP_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp/gmp-${GMP_VERSION}.tar.xz"
-+MPFR_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr/mpfr-${MPFR_VERSION}.tar.xz"
-+MPC_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc/mpc-${MPC_VERSION}.tar.gz"
-+GCC_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
-+BINUTILS_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
- IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
- # CLANG toolchain archive locations
- LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz"
--- 
-2.39.2
-

config/coreboot/haswell/patches/0029-ifdtool-nuke-option.patch

@@ -1,194 +0,0 @@
-From 6f94e9aa38a5d6589b1a64642dfcb5ccbf90b8d3 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Tue, 9 Jan 2024 01:53:54 +0000
-Subject: [PATCH 1/1] ifdtool nuke option
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
- 1 file changed, 83 insertions(+), 31 deletions(-)
-
-diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index e97efcc206..ee27e7f2e6 100644
---- a/util/ifdtool/ifdtool.c
-+++ b/util/ifdtool/ifdtool.c
-@@ -1711,6 +1711,7 @@ static void print_usage(const char *name)
- 	       "                                         tgl    - Tiger Lake\n"
- 	       "   -S | --setpchstrap                    Write a PCH strap\n"
- 	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
-+	       "   -N | --nuke <region>                  Overwrite the specified region with 0xFF (all ones)\n"
- 	       "   -v | --version:                       print the version\n"
- 	       "   -h | --help:                          print this help\n\n"
- 	       "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, "
-@@ -1718,6 +1719,60 @@ static void print_usage(const char *name)
- 	       "\n");
- }
- 
-+static int
-+get_region_type_string(const char *region_type_string)
-+{
-+	if (!strcasecmp("Descriptor", region_type_string))
-+		return 0;
-+	else if (!strcasecmp("BIOS", region_type_string))
-+		return 1;
-+	else if (!strcasecmp("ME", region_type_string))
-+		return 2;
-+	else if (!strcasecmp("GbE", region_type_string))
-+		return 3;
-+	else if (!strcasecmp("Platform Data", region_type_string))
-+		return 4;
-+	else if (!strcasecmp("Device Exp1", region_type_string))
-+		return 5;
-+	else if (!strcasecmp("Secondary BIOS", region_type_string))
-+		return 6;
-+	else if (!strcasecmp("Reserved", region_type_string))
-+		return 7;
-+	else if (!strcasecmp("EC", region_type_string))
-+		return 8;
-+	else if (!strcasecmp("Device Exp2", region_type_string))
-+		return 9;
-+	else if (!strcasecmp("IE", region_type_string))
-+		return 10;
-+	else if (!strcasecmp("10GbE_0", region_type_string))
-+		return 11;
-+	else if (!strcasecmp("10GbE_1", region_type_string))
-+		return 12;
-+	else if (!strcasecmp("PTT", region_type_string))
-+		return 15;
-+	return -1;
-+}
-+
-+static void
-+nuke(const char *filename, char *image, int size, int region_type)
-+{
-+	int i;
-+	region_t region;
-+	const frba_t *frba = find_frba(image, size);
-+	if (!frba)
-+		exit(EXIT_FAILURE);
-+
-+	region = get_region(frba, region_type);
-+	if (region.size > 0) {
-+		for (i = region.base; i <= region.limit; i++) {
-+			if ((i + 1) > (size))
-+				break;
-+			image[i] = 0xFF;
-+		}
-+		write_image(filename, image, size);
-+	}
-+}
-+
- int main(int argc, char *argv[])
- {
- 	int opt, option_index = 0;
-@@ -1725,6 +1780,7 @@ int main(int argc, char *argv[])
- 	int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
- 	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
- 	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0;
-+	int mode_nuke = 0;
- 	char *region_type_string = NULL, *region_fname = NULL;
- 	const char *layout_fname = NULL;
- 	char *new_filename = NULL;
-@@ -1755,6 +1811,7 @@ int main(int argc, char *argv[])
- 		{"validate", 0, NULL, 't'},
- 		{"setpchstrap", 1, NULL, 'S'},
- 		{"newvalue", 1, NULL, 'V'},
-+		{"nuke", 1, NULL, 'N'},
- 		{0, 0, 0, 0}
- 	};
- 
-@@ -1795,35 +1852,8 @@ int main(int argc, char *argv[])
- 			region_fname++;
- 			// Descriptor, BIOS, ME, GbE, Platform
- 			// valid type?
--			if (!strcasecmp("Descriptor", region_type_string))
--				region_type = 0;
--			else if (!strcasecmp("BIOS", region_type_string))
--				region_type = 1;
--			else if (!strcasecmp("ME", region_type_string))
--				region_type = 2;
--			else if (!strcasecmp("GbE", region_type_string))
--				region_type = 3;
--			else if (!strcasecmp("Platform Data", region_type_string))
--				region_type = 4;
--			else if (!strcasecmp("Device Exp1", region_type_string))
--				region_type = 5;
--			else if (!strcasecmp("Secondary BIOS", region_type_string))
--				region_type = 6;
--			else if (!strcasecmp("Reserved", region_type_string))
--				region_type = 7;
--			else if (!strcasecmp("EC", region_type_string))
--				region_type = 8;
--			else if (!strcasecmp("Device Exp2", region_type_string))
--				region_type = 9;
--			else if (!strcasecmp("IE", region_type_string))
--				region_type = 10;
--			else if (!strcasecmp("10GbE_0", region_type_string))
--				region_type = 11;
--			else if (!strcasecmp("10GbE_1", region_type_string))
--				region_type = 12;
--			else if (!strcasecmp("PTT", region_type_string))
--				region_type = 15;
--			if (region_type == -1) {
-+			if ((region_type =
-+			    get_region_type_string(region_type_string)) == -1) {
- 				fprintf(stderr, "No such region type: '%s'\n\n",
- 					region_type_string);
- 				print_usage(argv[0]);
-@@ -1988,6 +2018,22 @@ int main(int argc, char *argv[])
- 		case 't':
- 			mode_validate = 1;
- 			break;
-+               case 'N':
-+                       region_type_string = strdup(optarg);
-+                       if (!region_type_string) {
-+                               fprintf(stderr, "No region specified\n");
-+                               print_usage(argv[0]);
-+                               exit(EXIT_FAILURE);
-+                       }
-+                       if ((region_type =
-+                           get_region_type_string(region_type_string)) == -1) {
-+                               fprintf(stderr, "No such region type: '%s'\n\n",
-+                                       region_type_string);
-+                               print_usage(argv[0]);
-+                               exit(EXIT_FAILURE);
-+                       }
-+                       mode_nuke = 1;
-+                       break;
- 		case 'v':
- 			print_version();
- 			exit(EXIT_SUCCESS);
-@@ -2003,7 +2049,8 @@ int main(int argc, char *argv[])
- 
- 	if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_setstrap +
- 		mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked |
--		 mode_locked) + mode_altmedisable + mode_validate) > 1) {
-+		 mode_locked) + mode_altmedisable + mode_validate +
-+		 mode_nuke) > 1) {
- 		fprintf(stderr, "You may not specify more than one mode.\n\n");
- 		print_usage(argv[0]);
- 		exit(EXIT_FAILURE);
-@@ -2011,7 +2058,8 @@ int main(int argc, char *argv[])
- 
- 	if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_setstrap +
- 	     mode_newlayout + mode_spifreq + mode_em100 + mode_locked +
--	     mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) {
-+	     mode_unlocked + mode_density + mode_altmedisable +
-+	     mode_validate + mode_nuke) == 0) {
- 		fprintf(stderr, "You need to specify a mode.\n\n");
- 		print_usage(argv[0]);
- 		exit(EXIT_FAILURE);
-@@ -2109,6 +2157,10 @@ int main(int argc, char *argv[])
- 		write_image(new_filename, image, size);
- 	}
- 
-+	if (mode_nuke) {
-+               nuke(new_filename, image, size, region_type);
-+	}
-+
- 	if (mode_altmedisable) {
- 		fpsba_t *fpsba = find_fpsba(image, size);
- 		fmsba_t *fmsba = find_fmsba(image, size);
--- 
-2.39.2
-

config/coreboot/haswell/target.cfg

@@ -1,3 +0,0 @@
-tree="haswell"
-rev="1411ecf6f0b2c7395bcb96b856dcfdddb1b0c81b"
-xarch="i386-elf"

config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb

@@ -0,0 +1,657 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_COREBOOT_BUILD=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_IWYU is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_UTIL_GENPARSER is not set
+# CONFIG_OPTION_BACKEND_NONE is not set
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_STATIC_OPTION_TABLE=y
+CONFIG_COMPRESS_RAMSTAGE_LZMA=y
+# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_COLLECT_TIMESTAMPS=y
+# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
+CONFIG_USE_BLOBS=y
+# CONFIG_USE_AMD_BLOBS is not set
+# CONFIG_USE_QC_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_UBSAN is not set
+CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
+CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
+# CONFIG_ASAN is not set
+CONFIG_NO_STAGE_CACHE=y
+# CONFIG_TSEG_STAGE_CACHE is not set
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
+
+#
+# Software Bill Of Materials (SBOM)
+#
+# CONFIG_SBOM is not set
+# end of Software Bill Of Materials (SBOM)
+# end of General setup
+
+#
+# Mainboard
+#
+
+#
+# Important: Run 'make distclean' before switching boards
+#
+# CONFIG_VENDOR_51NB is not set
+# CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BOSTENTECH is not set
+# CONFIG_VENDOR_BYTEDANCE is not set
+# CONFIG_VENDOR_CAVIUM is not set
+# CONFIG_VENDOR_CLEVO is not set
+# CONFIG_VENDOR_COMPULAB is not set
+# CONFIG_VENDOR_DELL is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_EXAMPLE is not set
+# CONFIG_VENDOR_FACEBOOK is not set
+# CONFIG_VENDOR_FOXCONN is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_INVENTEC is not set
+# CONFIG_VENDOR_KONTRON is not set
+CONFIG_VENDOR_LENOVO=y
+# CONFIG_VENDOR_LIBRETREND is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_OCP is not set
+# CONFIG_VENDOR_OPENCELLULAR is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PINE64 is not set
+# CONFIG_VENDOR_PORTWELL is not set
+# CONFIG_VENDOR_PRODRIVE is not set
+# CONFIG_VENDOR_PROTECTLI is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RAZER is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_STARLABS is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_SYSTEM76 is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_UP is not set
+CONFIG_MAINBOARD_FAMILY="ThinkPad T440p"
+CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T440p"
+CONFIG_MAINBOARD_VERSION="1.0"
+CONFIG_MAINBOARD_DIR="lenovo/haswell"
+CONFIG_VGA_BIOS_ID="8086,0416"
+CONFIG_DIMM_MAX=4
+CONFIG_DIMM_SPD_SIZE=256
+CONFIG_FMDFILE=""
+CONFIG_NO_POST=y
+CONFIG_MAINBOARD_VENDOR="LENOVO"
+CONFIG_CBFS_SIZE=0x800000
+CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
+CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
+CONFIG_MAX_CPUS=8
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+# CONFIG_VBOOT is not set
+CONFIG_VARIANT_DIR="t440p"
+CONFIG_OVERRIDE_DEVICETREE=""
+# CONFIG_VGA_BIOS is not set
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_USBDEBUG_HCD_INDEX=2
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+CONFIG_TPM_PIRQ=0x0
+CONFIG_PS2K_EISAID="LEN0071"
+CONFIG_PS2M_EISAID="LEN0036"
+CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_ECAM_MMCONF_BUS_NUMBER=64
+CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
+CONFIG_DCACHE_RAM_BASE=0xff7c0000
+CONFIG_DCACHE_RAM_SIZE=0x40000
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
+CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
+CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
+CONFIG_HAVE_INTEL_FIRMWARE=y
+CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
+CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DRIVERS_INTEL_WIFI=y
+CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd"
+CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
+CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe"
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+# CONFIG_ENABLE_DDR_2X_REFRESH is not set
+CONFIG_PCIEXP_AER=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_DEBUG_SMI is not set
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T440p"
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_BOARD_LENOVO_THINKPAD_T440P=y
+# CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set
+# CONFIG_BOARD_LENOVO_L520 is not set
+# CONFIG_BOARD_LENOVO_S230U is not set
+# CONFIG_BOARD_LENOVO_T400 is not set
+# CONFIG_BOARD_LENOVO_T500 is not set
+# CONFIG_BOARD_LENOVO_R400 is not set
+# CONFIG_BOARD_LENOVO_R500 is not set
+# CONFIG_BOARD_LENOVO_W500 is not set
+# CONFIG_BOARD_LENOVO_T410 is not set
+# CONFIG_BOARD_LENOVO_T420 is not set
+# CONFIG_BOARD_LENOVO_T420S is not set
+# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set
+# CONFIG_BOARD_LENOVO_T430S is not set
+# CONFIG_BOARD_LENOVO_T431S is not set
+# CONFIG_BOARD_LENOVO_T520 is not set
+# CONFIG_BOARD_LENOVO_W520 is not set
+# CONFIG_BOARD_LENOVO_T530 is not set
+# CONFIG_BOARD_LENOVO_W530 is not set
+# CONFIG_BOARD_LENOVO_T60 is not set
+# CONFIG_BOARD_LENOVO_Z61T is not set
+# CONFIG_BOARD_LENOVO_R60 is not set
+# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set
+# CONFIG_BOARD_LENOVO_X131E is not set
+# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set
+# CONFIG_BOARD_LENOVO_X200 is not set
+# CONFIG_BOARD_LENOVO_X301 is not set
+# CONFIG_BOARD_LENOVO_X201 is not set
+# CONFIG_BOARD_LENOVO_X220 is not set
+# CONFIG_BOARD_LENOVO_X220I is not set
+# CONFIG_BOARD_LENOVO_X1 is not set
+# CONFIG_BOARD_LENOVO_X220_EDP is not set
+# CONFIG_BOARD_LENOVO_X230 is not set
+# CONFIG_BOARD_LENOVO_X230T is not set
+# CONFIG_BOARD_LENOVO_X230S is not set
+# CONFIG_BOARD_LENOVO_X230_EDP is not set
+# CONFIG_BOARD_LENOVO_X60 is not set
+CONFIG_BOARD_LENOVO_HASWELL_COMMON=y
+CONFIG_VBOOT_SLOTS_RW_AB=y
+CONFIG_THINKPADEC_HKEY_EISAID="LEN0068"
+CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
+CONFIG_D3COLD_SUPPORT=y
+CONFIG_PCIEXP_ASPM=y
+CONFIG_PCIEXP_L1_SUB_STATE=y
+CONFIG_PCIEXP_CLK_PM=y
+CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
+# CONFIG_DRIVERS_UART_8250IO is not set
+CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_EC_GPE_SCI=0x50
+# CONFIG_TPM_MEASURED_BOOT is not set
+CONFIG_BOARD_ROMSIZE_KB_12288=y
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_12288=y
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=12288
+CONFIG_ROM_SIZE=0x00c00000
+CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
+CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
+CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
+# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
+# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
+CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
+# end of Mainboard
+
+CONFIG_SYSTEM_TYPE_LAPTOP=y
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+CONFIG_CHIPSET_DEVICETREE=""
+CONFIG_CBFS_MCACHE_SIZE=0x4000
+CONFIG_ROMSTAGE_ADDR=0x2000000
+CONFIG_VERSTAGE_ADDR=0x2000000
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_SMM_RESERVED_SIZE=0x100000
+CONFIG_SMM_MODULE_STACK_SIZE=0x400
+CONFIG_SERIRQ_CONTINUOUS_MODE=y
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
+CONFIG_EHCI_BAR=0xe8000000
+CONFIG_ACPI_CPU_STRING="CP%02X"
+CONFIG_STACK_SIZE=0x2000
+CONFIG_IED_REGION_SIZE=0x400000
+CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
+CONFIG_INTEL_GMA_BCLV_WIDTH=16
+CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
+CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
+CONFIG_HPET_MIN_TICKS=0x80
+CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
+CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
+CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_DISABLE_ME_PCI=y
+CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
+CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_CBFS_CACHE_ALIGN=8
+
+#
+# CPU
+#
+CONFIG_CPU_INTEL_HASWELL=y
+CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
+CONFIG_CPU_INTEL_COMMON=y
+CONFIG_ENABLE_VMX=y
+CONFIG_SET_IA32_FC_LOCK_BIT=y
+CONFIG_SET_MSR_AESNI_LOCK_BIT=y
+CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
+CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
+CONFIG_CPU_INTEL_COMMON_SMM=y
+CONFIG_PARALLEL_MP=y
+CONFIG_XAPIC_ONLY=y
+# CONFIG_X2APIC_ONLY is not set
+# CONFIG_X2APIC_RUNTIME is not set
+# CONFIG_X2APIC_LATE_WORKAROUND is not set
+CONFIG_UDELAY_TSC=y
+CONFIG_TSC_MONOTONIC_TIMER=y
+CONFIG_TSC_SYNC_MFENCE=y
+CONFIG_HAVE_SMI_HANDLER=y
+CONFIG_SMM_TSEG=y
+CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
+CONFIG_AP_STACK_SIZE=0x800
+CONFIG_SMP=y
+CONFIG_SSE=y
+CONFIG_SSE2=y
+CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
+
+#
+# Northbridge
+#
+CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
+CONFIG_USE_NATIVE_RAMINIT=y
+
+#
+# Southbridge
+#
+# CONFIG_PCIEXP_HOTPLUG is not set
+CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
+CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
+CONFIG_FINALIZE_USB_ROUTE_XHCI=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
+CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
+CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
+# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
+CONFIG_INTEL_CHIPSET_LOCKDOWN=y
+CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
+CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
+CONFIG_RCBA_LENGTH=0x4000
+
+#
+# Super I/O
+#
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_ACPI=y
+CONFIG_EC_LENOVO_H8=y
+CONFIG_H8_BEEP_ON_DEATH=y
+CONFIG_H8_FLASH_LEDS_ON_DEATH=y
+# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
+# CONFIG_H8_FN_CTRL_SWAP is not set
+CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_PRIMARY_FN_KEYS=y
+CONFIG_EC_LENOVO_PMH7=y
+
+#
+# Intel Firmware
+#
+CONFIG_HAVE_ME_BIN=y
+# CONFIG_STITCH_ME_BIN is not set
+# CONFIG_CHECK_ME is not set
+# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
+# CONFIG_USE_ME_CLEANER is not set
+CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
+CONFIG_HAVE_GBE_BIN=y
+# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
+# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
+CONFIG_UNLOCK_FLASH_REGIONS=y
+CONFIG_ARCH_X86=y
+CONFIG_ARCH_BOOTBLOCK_X86_32=y
+CONFIG_ARCH_VERSTAGE_X86_32=y
+CONFIG_ARCH_ROMSTAGE_X86_32=y
+CONFIG_ARCH_POSTCAR_X86_32=y
+CONFIG_ARCH_RAMSTAGE_X86_32=y
+CONFIG_ARCH_ALL_STAGES_X86_32=y
+CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
+CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
+CONFIG_PC80_SYSTEM=y
+CONFIG_HAVE_CMOS_DEFAULT=y
+CONFIG_POSTCAR_STAGE=y
+CONFIG_BOOTBLOCK_SIMPLE=y
+# CONFIG_BOOTBLOCK_NORMAL is not set
+CONFIG_COLLECT_TIMESTAMPS_TSC=y
+CONFIG_HAVE_CF9_RESET=y
+CONFIG_DEBUG_HW_BREAKPOINTS=y
+CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
+# CONFIG_DUMP_SMBIOS_TYPE17 is not set
+# end of Chipset
+
+#
+# Devices
+#
+CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
+CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
+CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
+CONFIG_MAINBOARD_USE_LIBGFXINIT=y
+# CONFIG_VGA_ROM_RUN is not set
+# CONFIG_NO_GFX_INIT is not set
+CONFIG_NO_EARLY_GFX_INIT=y
+
+#
+# Display
+#
+# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
+CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
+CONFIG_LINEAR_FRAMEBUFFER=y
+# CONFIG_BOOTSPLASH is not set
+# end of Display
+
+CONFIG_PCI=y
+CONFIG_ECAM_MMCONF_SUPPORT=y
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_ECAM_MMCONF_LENGTH=0x04000000
+CONFIG_PCI_ALLOW_BUS_MASTER=y
+CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
+CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
+# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
+# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
+# CONFIG_EARLY_PCI_BRIDGE is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_INTEL_GMA_HAVE_VBT=y
+CONFIG_INTEL_GMA_ADD_VBT=y
+# CONFIG_SOFTWARE_I2C is not set
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
+# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_USE_DDR3=y
+# end of Devices
+
+#
+# Generic Drivers
+#
+CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
+# CONFIG_ELOG is not set
+CONFIG_CACHE_MRC_SETTINGS=y
+# CONFIG_MRC_SETTINGS_PROTECT is not set
+# CONFIG_SMMSTORE is not set
+CONFIG_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SPI_FLASH_AMIC=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
+CONFIG_TPM_INIT_RAMSTAGE=y
+# CONFIG_TPM_PPI is not set
+CONFIG_NO_UART_ON_SUPERIO=y
+# CONFIG_DRIVERS_UART_OXPCIE is not set
+CONFIG_HAVE_USBDEBUG=y
+CONFIG_HAVE_USBDEBUG_OPTIONS=y
+# CONFIG_USBDEBUG is not set
+# CONFIG_VPD is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
+# CONFIG_DRIVERS_I2C_MAX98396 is not set
+CONFIG_INTEL_DDI=y
+CONFIG_INTEL_INT15=y
+CONFIG_INTEL_GMA_ACPI=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
+CONFIG_GFX_GMA=y
+CONFIG_GFX_GMA_DYN_CPU=y
+CONFIG_GFX_GMA_GENERATION="Haswell"
+CONFIG_GFX_GMA_PCH="Lynx_Point"
+CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
+CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
+# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
+# CONFIG_DRIVERS_PS2_KEYBOARD is not set
+CONFIG_DRIVERS_MC146818=y
+CONFIG_USE_PC_CMOS_ALTCENTURY=y
+CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_DRIVERS_WIFI_GENERIC=y
+# end of Generic Drivers
+
+#
+# Security
+#
+
+#
+# CBFS verification
+#
+# CONFIG_CBFS_VERIFICATION is not set
+# end of CBFS verification
+
+#
+# Verified Boot (vboot)
+#
+# end of Verified Boot (vboot)
+
+#
+# Trusted Platform Module
+#
+# CONFIG_NO_TPM is not set
+CONFIG_TPM1=y
+CONFIG_TPM=y
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_DEACTIVATE is not set
+# CONFIG_DEBUG_TPM is not set
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
+CONFIG_PCR_BOOT_MODE=1
+CONFIG_PCR_HWID=1
+CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
+CONFIG_PCR_RUNTIME_DATA=3
+# end of Trusted Platform Module
+
+#
+# Memory initialization
+#
+CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
+CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
+# end of Memory initialization
+
+# CONFIG_INTEL_TXT is not set
+# CONFIG_STM is not set
+# CONFIG_INTEL_CBNT_SUPPORT is not set
+CONFIG_BOOTMEDIA_LOCK_NONE=y
+# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
+# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
+# CONFIG_BOOTMEDIA_SMM_BWP is not set
+# end of Security
+
+CONFIG_ACPI_HAVE_PCAT_8259=y
+CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
+CONFIG_ACPI_SOC_NVS=y
+CONFIG_ACPI_NO_CUSTOM_MADT=y
+CONFIG_ACPI_COMMON_MADT_LAPIC=y
+CONFIG_ACPI_COMMON_MADT_IOAPIC=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
+CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_RTC=y
+CONFIG_HEAP_SIZE=0x100000
+
+#
+# Console
+#
+CONFIG_BOOTBLOCK_CONSOLE=y
+CONFIG_POSTCAR_CONSOLE=y
+CONFIG_SQUELCH_EARLY_SMP=y
+# CONFIG_SPKMODEM is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
+# CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_CONSOLE_I2C_SMBUS is not set
+# CONFIG_EM100PRO_SPI_CONSOLE is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
+CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
+CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
+CONFIG_HWBASE_DEBUG_NULL=y
+# end of Console
+
+CONFIG_HAVE_ACPI_RESUME=y
+CONFIG_RESUME_PATH_SAME_AS_BOOT=y
+CONFIG_HAVE_MONOTONIC_TIMER=y
+CONFIG_HAVE_OPTION_TABLE=y
+CONFIG_IOAPIC=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+
+#
+# System tables
+#
+CONFIG_GENERATE_SMBIOS_TABLES=y
+CONFIG_BIOS_VENDOR="coreboot"
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+# end of System tables
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# end of Payload
+
+#
+# Debugging
+#
+
+#
+# CPU Debug Settings
+#
+# CONFIG_DISPLAY_MTRRS is not set
+
+#
+# Vendorcode Debug Settings
+#
+
+#
+# BLOB Debug Settings
+#
+
+#
+# General Debug Settings
+#
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+CONFIG_HAVE_DEBUG_RAM_SETUP=y
+# CONFIG_DEBUG_RAM_SETUP is not set
+CONFIG_HAVE_DEBUG_SMBUS=y
+# CONFIG_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_CONSOLE_INIT is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_DEBUG_ADA_CODE is not set
+CONFIG_HAVE_EM100_SUPPORT=y
+# CONFIG_EM100 is not set
+# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
+# end of Debugging
+
+CONFIG_RAMSTAGE_ADA=y
+CONFIG_RAMSTAGE_LIBHWBASE=y
+CONFIG_HWBASE_DYNAMIC_MMIO=y
+CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
+CONFIG_HWBASE_DIRECT_PCIDEV=y
+CONFIG_DECOMPRESS_OFAST=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_RELOCATABLE_MODULES=y
+CONFIG_HAVE_BOOTBLOCK=y
+CONFIG_HAVE_ROMSTAGE=y
+CONFIG_HAVE_RAMSTAGE=y

config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode

@@ -14,12 +14,15 @@ CONFIG_COMPILER_GCC=y
 CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
+# CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_COMPRESS_RAMSTAGE_LZMA=y
+# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -36,6 +39,12 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
 # CONFIG_FW_CONFIG is not set
+
+#
+# Software Bill Of Materials (SBOM)
+#
+# CONFIG_SBOM is not set
+# end of Software Bill Of Materials (SBOM)
 # end of General setup
 
 #
@@ -53,30 +62,28 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_VENDOR_APPLE is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BAP is not set
 # CONFIG_VENDOR_BIOSTAR is not set
 # CONFIG_VENDOR_BOSTENTECH is not set
+# CONFIG_VENDOR_BYTEDANCE is not set
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
 # CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_ELMEX is not set
 # CONFIG_VENDOR_EMULATION is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GIZMOSPHERE is not set
 # CONFIG_VENDOR_GOOGLE is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
 # CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_INVENTEC is not set
 # CONFIG_VENDOR_KONTRON is not set
 CONFIG_VENDOR_LENOVO=y
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_LIPPERT is not set
 # CONFIG_VENDOR_MSI is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
@@ -91,7 +98,6 @@ CONFIG_VENDOR_LENOVO=y
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
 # CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SCALEWAY is not set
 # CONFIG_VENDOR_SIEMENS is not set
 # CONFIG_VENDOR_SIFIVE is not set
 # CONFIG_VENDOR_STARLABS is not set
@@ -107,35 +113,33 @@ CONFIG_VGA_BIOS_ID="8086,0416"
 CONFIG_DIMM_MAX=4
 CONFIG_DIMM_SPD_SIZE=256
 CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
+CONFIG_NO_POST=y
 CONFIG_MAINBOARD_VENDOR="LENOVO"
-CONFIG_CBFS_SIZE=0xBE0000
+CONFIG_CBFS_SIZE=0x800000
 CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-# CONFIG_VBOOT is not set
-CONFIG_VBOOT_VBNV_OFFSET=0x2a
-CONFIG_VARIANT_DIR="t440p"
 CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+# CONFIG_VBOOT is not set
+CONFIG_VARIANT_DIR="t440p"
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO"
 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_USBDEBUG_HCD_INDEX=2
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
 CONFIG_TPM_PIRQ=0x0
+CONFIG_PS2K_EISAID="LEN0071"
+CONFIG_PS2M_EISAID="LEN0036"
+CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
 CONFIG_DCACHE_RAM_BASE=0xff7c0000
 CONFIG_DCACHE_RAM_SIZE=0x40000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
 CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
 CONFIG_HAVE_INTEL_FIRMWARE=y
 CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
@@ -148,12 +152,12 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe"
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 # CONFIG_ENABLE_DDR_2X_REFRESH is not set
 CONFIG_PCIEXP_AER=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_DEBUG_SMI is not set
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T440p"
 CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-# CONFIG_BOARD_LENOVO_G505S is not set
 CONFIG_BOARD_LENOVO_THINKPAD_T440P=y
 # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set
 # CONFIG_BOARD_LENOVO_L520 is not set
@@ -185,21 +189,25 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y
 # CONFIG_BOARD_LENOVO_X220 is not set
 # CONFIG_BOARD_LENOVO_X220I is not set
 # CONFIG_BOARD_LENOVO_X1 is not set
+# CONFIG_BOARD_LENOVO_X220_EDP is not set
 # CONFIG_BOARD_LENOVO_X230 is not set
 # CONFIG_BOARD_LENOVO_X230T is not set
 # CONFIG_BOARD_LENOVO_X230S is not set
+# CONFIG_BOARD_LENOVO_X230_EDP is not set
 # CONFIG_BOARD_LENOVO_X60 is not set
 CONFIG_BOARD_LENOVO_HASWELL_COMMON=y
 CONFIG_VBOOT_SLOTS_RW_AB=y
-CONFIG_PS2K_EISAID="LEN0071"
-CONFIG_PS2M_EISAID="LEN0036"
 CONFIG_THINKPADEC_HKEY_EISAID="LEN0068"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
+CONFIG_D3COLD_SUPPORT=y
-# CONFIG_PCIEXP_CLK_PM is not set
+CONFIG_PCIEXP_ASPM=y
+CONFIG_PCIEXP_L1_SUB_STATE=y
+CONFIG_PCIEXP_CLK_PM=y
+CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_HEAP_SIZE=0x4000
+CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_EC_GPE_SCI=0x50
+# CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -212,6 +220,7 @@ CONFIG_BOARD_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 CONFIG_COREBOOT_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=12288
@@ -233,7 +242,6 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y
 #
 # SoC
 #
-CONFIG_ARCH_ALL_STAGES_X86=y
 CONFIG_CHIPSET_DEVICETREE=""
 CONFIG_CBFS_MCACHE_SIZE=0x4000
 CONFIG_ROMSTAGE_ADDR=0x2000000
@@ -241,34 +249,34 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_TSEG_SIZE=0x800000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_CPU_SPECIFIC_OPTIONS=y
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d"
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
 CONFIG_EHCI_BAR=0xe8000000
+CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
 CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
 CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_ASPM=y
 CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4
+CONFIG_DISABLE_ME_PCI=y
-CONFIG_UART_PCI_ADDR=0x0
+CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
-CONFIG_CBFS_CACHE_ALIGN=8
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_CBFS_CACHE_ALIGN=8
 
 #
 # CPU
 #
 CONFIG_CPU_INTEL_HASWELL=y
-CONFIG_SSE2=y
 CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
 CONFIG_CPU_INTEL_COMMON=y
 CONFIG_ENABLE_VMX=y
@@ -277,7 +285,6 @@ CONFIG_SET_MSR_AESNI_LOCK_BIT=y
 CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
 CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
 CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
 CONFIG_PARALLEL_MP=y
 CONFIG_XAPIC_ONLY=y
 # CONFIG_X2APIC_ONLY is not set
@@ -286,14 +293,13 @@ CONFIG_XAPIC_ONLY=y
 CONFIG_UDELAY_TSC=y
 CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_LOGICAL_CPUS=y
 CONFIG_HAVE_SMI_HANDLER=y
 CONFIG_SMM_TSEG=y
-CONFIG_SMM_STUB_STACK_SIZE=0x400
+CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_CPU_INFO_V2=y
+CONFIG_AP_STACK_SIZE=0x800
 CONFIG_SMP=y
-CONFIG_MMX=y
 CONFIG_SSE=y
+CONFIG_SSE2=y
 CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
 CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
@@ -310,9 +316,7 @@ CONFIG_USE_NATIVE_RAMINIT=y
 #
 # Southbridge
 #
-CONFIG_SOUTH_BRIDGE_OPTIONS=y
+# CONFIG_PCIEXP_HOTPLUG is not set
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_PCIEXP_HOTPLUG=y
 CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
 CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
 CONFIG_FINALIZE_USB_ROUTE_XHCI=y
@@ -328,12 +332,12 @@ CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
 CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
 CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
 # CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
 CONFIG_INTEL_CHIPSET_LOCKDOWN=y
+CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
 CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
 CONFIG_RCBA_LENGTH=0x4000
@@ -347,9 +351,10 @@ CONFIG_RCBA_LENGTH=0x4000
 #
 CONFIG_EC_ACPI=y
 CONFIG_EC_LENOVO_H8=y
-# CONFIG_H8_BEEP_ON_DEATH is not set
+CONFIG_H8_BEEP_ON_DEATH=y
-# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set
+CONFIG_H8_FLASH_LEDS_ON_DEATH=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
+# CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
 CONFIG_H8_HAS_PRIMARY_FN_KEYS=y
 CONFIG_EC_LENOVO_PMH7=y
@@ -374,8 +379,10 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y
 CONFIG_ARCH_POSTCAR_X86_32=y
 CONFIG_ARCH_RAMSTAGE_X86_32=y
 CONFIG_ARCH_ALL_STAGES_X86_32=y
+CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_NUM_IPI_STARTS=2
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -385,6 +392,7 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y
 CONFIG_HAVE_CF9_RESET=y
 CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
+# CONFIG_DUMP_SMBIOS_TYPE17 is not set
 # end of Chipset
 
 #
@@ -396,6 +404,7 @@ CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
 CONFIG_MAINBOARD_USE_LIBGFXINIT=y
 # CONFIG_VGA_ROM_RUN is not set
 # CONFIG_NO_GFX_INIT is not set
+CONFIG_NO_EARLY_GFX_INIT=y
 
 #
 # Display
@@ -407,17 +416,14 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
 CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
+# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -425,7 +431,8 @@ CONFIG_INTEL_GMA_HAVE_VBT=y
 CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATOR_V4=y
+# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_USE_DDR3=y
 # end of Devices
 
 #
@@ -435,21 +442,19 @@ CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
 # CONFIG_ELOG is not set
 CONFIG_CACHE_MRC_SETTINGS=y
 # CONFIG_MRC_SETTINGS_PROTECT is not set
-CONFIG_MRC_STASH_TO_CBMEM=y
 # CONFIG_SMMSTORE is not set
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
 # CONFIG_SPI_FLASH_NO_FAST_READ is not set
 CONFIG_SPI_FLASH_ADESTO=y
 CONFIG_SPI_FLASH_AMIC=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_ISSI=y
 CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
 CONFIG_TPM_INIT_RAMSTAGE=y
 # CONFIG_TPM_PPI is not set
@@ -460,23 +465,29 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
+# CONFIG_DRIVERS_I2C_MAX98396 is not set
 CONFIG_INTEL_DDI=y
 CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_INTEL_GMA_OPREGION_2_0=y
 CONFIG_GFX_GMA_DYN_CPU=y
 CONFIG_GFX_GMA_GENERATION="Haswell"
 CONFIG_GFX_GMA_PCH="Lynx_Point"
 CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
 CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
+# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
+CONFIG_USE_PC_CMOS_ALTCENTURY=y
+CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_MEMORY_MAPPED_TPM=y
 CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 CONFIG_VGA=y
@@ -509,7 +520,11 @@ CONFIG_MAINBOARD_HAS_TPM1=y
 # CONFIG_TPM_DEACTIVATE is not set
 # CONFIG_DEBUG_TPM is not set
 # CONFIG_TPM_RDRESP_NEED_DELAY is not set
-# CONFIG_TPM_MEASURED_BOOT is not set
+CONFIG_PCR_BOOT_MODE=1
+CONFIG_PCR_HWID=1
+CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
+CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
 #
@@ -531,11 +546,15 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y
 CONFIG_ACPI_HAVE_PCAT_8259=y
 CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
 CONFIG_ACPI_SOC_NVS=y
+CONFIG_ACPI_NO_CUSTOM_MADT=y
+CONFIG_ACPI_COMMON_MADT_LAPIC=y
+CONFIG_ACPI_COMMON_MADT_IOAPIC=y
 CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -548,6 +567,7 @@ CONFIG_SQUELCH_EARLY_SMP=y
 CONFIG_CONSOLE_CBMEM=y
 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
 # CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_CONSOLE_I2C_SMBUS is not set
 # CONFIG_EM100PRO_SPI_CONSOLE is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
@@ -561,11 +581,6 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
 CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
 CONFIG_HWBASE_DEBUG_NULL=y
 # end of Console
 
@@ -580,6 +595,7 @@ CONFIG_USE_WATCHDOG_ON_BOOT=y
 # System tables
 #
 CONFIG_GENERATE_SMBIOS_TABLES=y
+CONFIG_BIOS_VENDOR="coreboot"
 CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
 # end of System tables
 
@@ -587,32 +603,6 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
 # Payload
 #
 CONFIG_PAYLOAD_NONE=y
-# CONFIG_PAYLOAD_ELF is not set
-# CONFIG_PAYLOAD_BOOTBOOT is not set
-# CONFIG_PAYLOAD_FILO is not set
-# CONFIG_PAYLOAD_GRUB2 is not set
-# CONFIG_PAYLOAD_SEAGRUB is not set
-# CONFIG_PAYLOAD_LINUXBOOT is not set
-# CONFIG_PAYLOAD_SEABIOS is not set
-# CONFIG_PAYLOAD_UBOOT is not set
-# CONFIG_PAYLOAD_YABITS is not set
-# CONFIG_PAYLOAD_LINUX is not set
-# CONFIG_PAYLOAD_TIANOCORE is not set
-CONFIG_PAYLOAD_OPTIONS=""
-# CONFIG_PXE is not set
-CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
-
-#
-# Secondary Payloads
-#
-# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
-# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set
-# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
-# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
-# CONFIG_SEABIOS_SECONDARY_PAYLOAD is not set
-# CONFIG_TINT_SECONDARY_PAYLOAD is not set
-# CONFIG_COREDOOM_SECONDARY_PAYLOAD is not set
-# end of Secondary Payloads
 # end of Payload
 
 #
@@ -624,6 +614,10 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
 #
 # CONFIG_DISPLAY_MTRRS is not set
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #
@@ -637,13 +631,13 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
 CONFIG_HAVE_DEBUG_SMBUS=y
 # CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_SMI is not set
 # CONFIG_DEBUG_CONSOLE_INIT is not set
 # CONFIG_DEBUG_SPI_FLASH is not set
 # CONFIG_DEBUG_BOOT_STATE is not set
 # CONFIG_DEBUG_ADA_CODE is not set
 CONFIG_HAVE_EM100_SUPPORT=y
 # CONFIG_EM100 is not set
+# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
 # end of Debugging
 
 CONFIG_RAMSTAGE_ADA=y
@@ -651,6 +645,7 @@ CONFIG_RAMSTAGE_LIBHWBASE=y
 CONFIG_HWBASE_DYNAMIC_MMIO=y
 CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
 CONFIG_HWBASE_DIRECT_PCIDEV=y
+CONFIG_DECOMPRESS_OFAST=y
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y

config/coreboot/t440plibremrc_12mb/target.cfg

@@ -1,4 +1,4 @@
-tree="haswell"
+tree="default"
 xarch="i386-elf"
 payload_grub="y"
 payload_grub_withseabios="y"

config/coreboot/w541_12mb/config/libgfxinit_corebootfb

@@ -0,0 +1,657 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_COREBOOT_BUILD=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_IWYU is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_UTIL_GENPARSER is not set
+# CONFIG_OPTION_BACKEND_NONE is not set
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_STATIC_OPTION_TABLE=y
+CONFIG_COMPRESS_RAMSTAGE_LZMA=y
+# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_COLLECT_TIMESTAMPS=y
+# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
+CONFIG_USE_BLOBS=y
+# CONFIG_USE_AMD_BLOBS is not set
+# CONFIG_USE_QC_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_UBSAN is not set
+CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
+CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
+# CONFIG_ASAN is not set
+CONFIG_NO_STAGE_CACHE=y
+# CONFIG_TSEG_STAGE_CACHE is not set
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
+
+#
+# Software Bill Of Materials (SBOM)
+#
+# CONFIG_SBOM is not set
+# end of Software Bill Of Materials (SBOM)
+# end of General setup
+
+#
+# Mainboard
+#
+
+#
+# Important: Run 'make distclean' before switching boards
+#
+# CONFIG_VENDOR_51NB is not set
+# CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BOSTENTECH is not set
+# CONFIG_VENDOR_BYTEDANCE is not set
+# CONFIG_VENDOR_CAVIUM is not set
+# CONFIG_VENDOR_CLEVO is not set
+# CONFIG_VENDOR_COMPULAB is not set
+# CONFIG_VENDOR_DELL is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_EXAMPLE is not set
+# CONFIG_VENDOR_FACEBOOK is not set
+# CONFIG_VENDOR_FOXCONN is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_INVENTEC is not set
+# CONFIG_VENDOR_KONTRON is not set
+CONFIG_VENDOR_LENOVO=y
+# CONFIG_VENDOR_LIBRETREND is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_OCP is not set
+# CONFIG_VENDOR_OPENCELLULAR is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PINE64 is not set
+# CONFIG_VENDOR_PORTWELL is not set
+# CONFIG_VENDOR_PRODRIVE is not set
+# CONFIG_VENDOR_PROTECTLI is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RAZER is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_STARLABS is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_SYSTEM76 is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_UP is not set
+CONFIG_MAINBOARD_FAMILY="ThinkPad W541"
+CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W541"
+CONFIG_MAINBOARD_VERSION="1.0"
+CONFIG_MAINBOARD_DIR="lenovo/haswell"
+CONFIG_VGA_BIOS_ID="8086,0166"
+CONFIG_DIMM_MAX=4
+CONFIG_DIMM_SPD_SIZE=256
+CONFIG_FMDFILE=""
+CONFIG_NO_POST=y
+CONFIG_MAINBOARD_VENDOR="LENOVO"
+CONFIG_CBFS_SIZE=0x800000
+CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
+CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
+CONFIG_MAX_CPUS=8
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+# CONFIG_VBOOT is not set
+CONFIG_VARIANT_DIR="w541"
+CONFIG_OVERRIDE_DEVICETREE=""
+# CONFIG_VGA_BIOS is not set
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_USBDEBUG_HCD_INDEX=2
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+CONFIG_TPM_PIRQ=0x0
+CONFIG_PS2K_EISAID="LEN0071"
+CONFIG_PS2M_EISAID="LEN004A"
+CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_ECAM_MMCONF_BUS_NUMBER=64
+CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
+CONFIG_DCACHE_RAM_BASE=0xff7c0000
+CONFIG_DCACHE_RAM_SIZE=0x40000
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
+CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
+CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
+CONFIG_HAVE_INTEL_FIRMWARE=y
+CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
+CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DRIVERS_INTEL_WIFI=y
+CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd"
+CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
+CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe"
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+# CONFIG_ENABLE_DDR_2X_REFRESH is not set
+CONFIG_PCIEXP_AER=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_DEBUG_SMI is not set
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad W541"
+CONFIG_HAVE_IFD_BIN=y
+# CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set
+CONFIG_BOARD_LENOVO_THINKPAD_W541=y
+# CONFIG_BOARD_LENOVO_L520 is not set
+# CONFIG_BOARD_LENOVO_S230U is not set
+# CONFIG_BOARD_LENOVO_T400 is not set
+# CONFIG_BOARD_LENOVO_T500 is not set
+# CONFIG_BOARD_LENOVO_R400 is not set
+# CONFIG_BOARD_LENOVO_R500 is not set
+# CONFIG_BOARD_LENOVO_W500 is not set
+# CONFIG_BOARD_LENOVO_T410 is not set
+# CONFIG_BOARD_LENOVO_T420 is not set
+# CONFIG_BOARD_LENOVO_T420S is not set
+# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set
+# CONFIG_BOARD_LENOVO_T430S is not set
+# CONFIG_BOARD_LENOVO_T431S is not set
+# CONFIG_BOARD_LENOVO_T520 is not set
+# CONFIG_BOARD_LENOVO_W520 is not set
+# CONFIG_BOARD_LENOVO_T530 is not set
+# CONFIG_BOARD_LENOVO_W530 is not set
+# CONFIG_BOARD_LENOVO_T60 is not set
+# CONFIG_BOARD_LENOVO_Z61T is not set
+# CONFIG_BOARD_LENOVO_R60 is not set
+# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set
+# CONFIG_BOARD_LENOVO_X131E is not set
+# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set
+# CONFIG_BOARD_LENOVO_X200 is not set
+# CONFIG_BOARD_LENOVO_X301 is not set
+# CONFIG_BOARD_LENOVO_X201 is not set
+# CONFIG_BOARD_LENOVO_X220 is not set
+# CONFIG_BOARD_LENOVO_X220I is not set
+# CONFIG_BOARD_LENOVO_X1 is not set
+# CONFIG_BOARD_LENOVO_X220_EDP is not set
+# CONFIG_BOARD_LENOVO_X230 is not set
+# CONFIG_BOARD_LENOVO_X230T is not set
+# CONFIG_BOARD_LENOVO_X230S is not set
+# CONFIG_BOARD_LENOVO_X230_EDP is not set
+# CONFIG_BOARD_LENOVO_X60 is not set
+CONFIG_BOARD_LENOVO_HASWELL_COMMON=y
+CONFIG_VBOOT_SLOTS_RW_AB=y
+CONFIG_THINKPADEC_HKEY_EISAID="LEN0068"
+CONFIG_GFX_GMA_PANEL_1_PORT="DP3"
+CONFIG_D3COLD_SUPPORT=y
+CONFIG_PCIEXP_ASPM=y
+CONFIG_PCIEXP_L1_SUB_STATE=y
+CONFIG_PCIEXP_CLK_PM=y
+CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
+# CONFIG_DRIVERS_UART_8250IO is not set
+CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_EC_GPE_SCI=0x50
+# CONFIG_TPM_MEASURED_BOOT is not set
+CONFIG_BOARD_ROMSIZE_KB_12288=y
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_12288=y
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=12288
+CONFIG_ROM_SIZE=0x00c00000
+CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
+CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
+CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
+# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
+# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
+CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
+# end of Mainboard
+
+CONFIG_SYSTEM_TYPE_LAPTOP=y
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+CONFIG_CHIPSET_DEVICETREE=""
+CONFIG_CBFS_MCACHE_SIZE=0x4000
+CONFIG_ROMSTAGE_ADDR=0x2000000
+CONFIG_VERSTAGE_ADDR=0x2000000
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_SMM_RESERVED_SIZE=0x100000
+CONFIG_SMM_MODULE_STACK_SIZE=0x400
+CONFIG_SERIRQ_CONTINUOUS_MODE=y
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
+CONFIG_EHCI_BAR=0xe8000000
+CONFIG_ACPI_CPU_STRING="CP%02X"
+CONFIG_STACK_SIZE=0x2000
+CONFIG_IED_REGION_SIZE=0x400000
+CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
+CONFIG_INTEL_GMA_BCLV_WIDTH=16
+CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
+CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
+CONFIG_HPET_MIN_TICKS=0x80
+CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
+CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
+CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_DISABLE_ME_PCI=y
+CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
+CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_CBFS_CACHE_ALIGN=8
+
+#
+# CPU
+#
+CONFIG_CPU_INTEL_HASWELL=y
+CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
+CONFIG_CPU_INTEL_COMMON=y
+CONFIG_ENABLE_VMX=y
+CONFIG_SET_IA32_FC_LOCK_BIT=y
+CONFIG_SET_MSR_AESNI_LOCK_BIT=y
+CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
+CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
+CONFIG_CPU_INTEL_COMMON_SMM=y
+CONFIG_PARALLEL_MP=y
+CONFIG_XAPIC_ONLY=y
+# CONFIG_X2APIC_ONLY is not set
+# CONFIG_X2APIC_RUNTIME is not set
+# CONFIG_X2APIC_LATE_WORKAROUND is not set
+CONFIG_UDELAY_TSC=y
+CONFIG_TSC_MONOTONIC_TIMER=y
+CONFIG_TSC_SYNC_MFENCE=y
+CONFIG_HAVE_SMI_HANDLER=y
+CONFIG_SMM_TSEG=y
+CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
+CONFIG_AP_STACK_SIZE=0x800
+CONFIG_SMP=y
+CONFIG_SSE=y
+CONFIG_SSE2=y
+CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
+
+#
+# Northbridge
+#
+CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
+CONFIG_USE_NATIVE_RAMINIT=y
+
+#
+# Southbridge
+#
+# CONFIG_PCIEXP_HOTPLUG is not set
+CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
+CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
+CONFIG_FINALIZE_USB_ROUTE_XHCI=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
+CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
+CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
+# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
+CONFIG_INTEL_CHIPSET_LOCKDOWN=y
+CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
+CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
+CONFIG_RCBA_LENGTH=0x4000
+
+#
+# Super I/O
+#
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_ACPI=y
+CONFIG_EC_LENOVO_H8=y
+CONFIG_H8_BEEP_ON_DEATH=y
+CONFIG_H8_FLASH_LEDS_ON_DEATH=y
+# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
+# CONFIG_H8_FN_CTRL_SWAP is not set
+CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_PRIMARY_FN_KEYS=y
+CONFIG_EC_LENOVO_PMH7=y
+
+#
+# Intel Firmware
+#
+CONFIG_HAVE_ME_BIN=y
+# CONFIG_STITCH_ME_BIN is not set
+# CONFIG_CHECK_ME is not set
+# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
+# CONFIG_USE_ME_CLEANER is not set
+CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
+CONFIG_HAVE_GBE_BIN=y
+# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
+# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
+CONFIG_UNLOCK_FLASH_REGIONS=y
+CONFIG_ARCH_X86=y
+CONFIG_ARCH_BOOTBLOCK_X86_32=y
+CONFIG_ARCH_VERSTAGE_X86_32=y
+CONFIG_ARCH_ROMSTAGE_X86_32=y
+CONFIG_ARCH_POSTCAR_X86_32=y
+CONFIG_ARCH_RAMSTAGE_X86_32=y
+CONFIG_ARCH_ALL_STAGES_X86_32=y
+CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
+CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
+CONFIG_PC80_SYSTEM=y
+CONFIG_HAVE_CMOS_DEFAULT=y
+CONFIG_POSTCAR_STAGE=y
+CONFIG_BOOTBLOCK_SIMPLE=y
+# CONFIG_BOOTBLOCK_NORMAL is not set
+CONFIG_COLLECT_TIMESTAMPS_TSC=y
+CONFIG_HAVE_CF9_RESET=y
+CONFIG_DEBUG_HW_BREAKPOINTS=y
+CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
+# CONFIG_DUMP_SMBIOS_TYPE17 is not set
+# end of Chipset
+
+#
+# Devices
+#
+CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
+CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
+CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
+CONFIG_MAINBOARD_USE_LIBGFXINIT=y
+# CONFIG_VGA_ROM_RUN is not set
+# CONFIG_NO_GFX_INIT is not set
+CONFIG_NO_EARLY_GFX_INIT=y
+
+#
+# Display
+#
+# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
+CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
+CONFIG_LINEAR_FRAMEBUFFER=y
+# CONFIG_BOOTSPLASH is not set
+# end of Display
+
+CONFIG_PCI=y
+CONFIG_ECAM_MMCONF_SUPPORT=y
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_ECAM_MMCONF_LENGTH=0x04000000
+CONFIG_PCI_ALLOW_BUS_MASTER=y
+CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
+CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
+# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
+# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
+# CONFIG_EARLY_PCI_BRIDGE is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_INTEL_GMA_HAVE_VBT=y
+CONFIG_INTEL_GMA_ADD_VBT=y
+# CONFIG_SOFTWARE_I2C is not set
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
+# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_USE_DDR3=y
+# end of Devices
+
+#
+# Generic Drivers
+#
+CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
+# CONFIG_ELOG is not set
+CONFIG_CACHE_MRC_SETTINGS=y
+# CONFIG_MRC_SETTINGS_PROTECT is not set
+# CONFIG_SMMSTORE is not set
+CONFIG_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SPI_FLASH_AMIC=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
+CONFIG_TPM_INIT_RAMSTAGE=y
+# CONFIG_TPM_PPI is not set
+CONFIG_NO_UART_ON_SUPERIO=y
+# CONFIG_DRIVERS_UART_OXPCIE is not set
+CONFIG_HAVE_USBDEBUG=y
+CONFIG_HAVE_USBDEBUG_OPTIONS=y
+# CONFIG_USBDEBUG is not set
+# CONFIG_VPD is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
+# CONFIG_DRIVERS_I2C_MAX98396 is not set
+CONFIG_INTEL_DDI=y
+CONFIG_INTEL_GMA_ACPI=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
+CONFIG_GFX_GMA=y
+CONFIG_GFX_GMA_DYN_CPU=y
+CONFIG_GFX_GMA_GENERATION="Haswell"
+CONFIG_GFX_GMA_PCH="Lynx_Point"
+CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
+CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
+# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
+# CONFIG_DRIVERS_PS2_KEYBOARD is not set
+CONFIG_DRIVERS_MC146818=y
+CONFIG_USE_PC_CMOS_ALTCENTURY=y
+CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_DRIVERS_WIFI_GENERIC=y
+# end of Generic Drivers
+
+#
+# Security
+#
+
+#
+# CBFS verification
+#
+# CONFIG_CBFS_VERIFICATION is not set
+# end of CBFS verification
+
+#
+# Verified Boot (vboot)
+#
+# end of Verified Boot (vboot)
+
+#
+# Trusted Platform Module
+#
+# CONFIG_NO_TPM is not set
+CONFIG_TPM1=y
+CONFIG_TPM=y
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_DEACTIVATE is not set
+# CONFIG_DEBUG_TPM is not set
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
+CONFIG_PCR_BOOT_MODE=1
+CONFIG_PCR_HWID=1
+CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
+CONFIG_PCR_RUNTIME_DATA=3
+# end of Trusted Platform Module
+
+#
+# Memory initialization
+#
+CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
+CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
+# end of Memory initialization
+
+# CONFIG_INTEL_TXT is not set
+# CONFIG_STM is not set
+# CONFIG_INTEL_CBNT_SUPPORT is not set
+CONFIG_BOOTMEDIA_LOCK_NONE=y
+# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
+# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
+# CONFIG_BOOTMEDIA_SMM_BWP is not set
+# end of Security
+
+CONFIG_ACPI_HAVE_PCAT_8259=y
+CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
+CONFIG_ACPI_SOC_NVS=y
+CONFIG_ACPI_NO_CUSTOM_MADT=y
+CONFIG_ACPI_COMMON_MADT_LAPIC=y
+CONFIG_ACPI_COMMON_MADT_IOAPIC=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
+CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_RTC=y
+CONFIG_HEAP_SIZE=0x100000
+
+#
+# Console
+#
+CONFIG_BOOTBLOCK_CONSOLE=y
+CONFIG_POSTCAR_CONSOLE=y
+CONFIG_SQUELCH_EARLY_SMP=y
+# CONFIG_SPKMODEM is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
+# CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_CONSOLE_I2C_SMBUS is not set
+# CONFIG_EM100PRO_SPI_CONSOLE is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
+CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
+CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
+CONFIG_HWBASE_DEBUG_CB=y
+# end of Console
+
+CONFIG_HAVE_ACPI_RESUME=y
+CONFIG_RESUME_PATH_SAME_AS_BOOT=y
+CONFIG_HAVE_MONOTONIC_TIMER=y
+CONFIG_HAVE_OPTION_TABLE=y
+CONFIG_IOAPIC=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+
+#
+# System tables
+#
+CONFIG_GENERATE_SMBIOS_TABLES=y
+CONFIG_BIOS_VENDOR="coreboot"
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+# end of System tables
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# end of Payload
+
+#
+# Debugging
+#
+
+#
+# CPU Debug Settings
+#
+# CONFIG_DISPLAY_MTRRS is not set
+
+#
+# Vendorcode Debug Settings
+#
+
+#
+# BLOB Debug Settings
+#
+
+#
+# General Debug Settings
+#
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+CONFIG_HAVE_DEBUG_RAM_SETUP=y
+# CONFIG_DEBUG_RAM_SETUP is not set
+CONFIG_HAVE_DEBUG_SMBUS=y
+# CONFIG_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_CONSOLE_INIT is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_DEBUG_ADA_CODE is not set
+CONFIG_HAVE_EM100_SUPPORT=y
+# CONFIG_EM100 is not set
+# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
+# end of Debugging
+
+CONFIG_RAMSTAGE_ADA=y
+CONFIG_RAMSTAGE_LIBHWBASE=y
+CONFIG_HWBASE_DYNAMIC_MMIO=y
+CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
+CONFIG_HWBASE_DIRECT_PCIDEV=y
+CONFIG_DECOMPRESS_OFAST=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_RELOCATABLE_MODULES=y
+CONFIG_HAVE_BOOTBLOCK=y
+CONFIG_HAVE_ROMSTAGE=y
+CONFIG_HAVE_RAMSTAGE=y

config/coreboot/w541_12mb/config/libgfxinit_txtmode

@@ -14,12 +14,15 @@ CONFIG_COMPILER_GCC=y
 CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
+# CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_COMPRESS_RAMSTAGE_LZMA=y
+# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -36,6 +39,12 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
 # CONFIG_FW_CONFIG is not set
+
+#
+# Software Bill Of Materials (SBOM)
+#
+# CONFIG_SBOM is not set
+# end of Software Bill Of Materials (SBOM)
 # end of General setup
 
 #
@@ -53,30 +62,28 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_VENDOR_APPLE is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BAP is not set
 # CONFIG_VENDOR_BIOSTAR is not set
 # CONFIG_VENDOR_BOSTENTECH is not set
+# CONFIG_VENDOR_BYTEDANCE is not set
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
 # CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_ELMEX is not set
 # CONFIG_VENDOR_EMULATION is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GIZMOSPHERE is not set
 # CONFIG_VENDOR_GOOGLE is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
 # CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_INVENTEC is not set
 # CONFIG_VENDOR_KONTRON is not set
 CONFIG_VENDOR_LENOVO=y
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_LIPPERT is not set
 # CONFIG_VENDOR_MSI is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
@@ -91,7 +98,6 @@ CONFIG_VENDOR_LENOVO=y
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
 # CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SCALEWAY is not set
 # CONFIG_VENDOR_SIEMENS is not set
 # CONFIG_VENDOR_SIFIVE is not set
 # CONFIG_VENDOR_STARLABS is not set
@@ -107,35 +113,33 @@ CONFIG_VGA_BIOS_ID="8086,0166"
 CONFIG_DIMM_MAX=4
 CONFIG_DIMM_SPD_SIZE=256
 CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
+CONFIG_NO_POST=y
 CONFIG_MAINBOARD_VENDOR="LENOVO"
-CONFIG_CBFS_SIZE=0xBE0000
+CONFIG_CBFS_SIZE=0x800000
 CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-# CONFIG_VBOOT is not set
-CONFIG_VBOOT_VBNV_OFFSET=0x2a
-CONFIG_VARIANT_DIR="w541"
 CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+# CONFIG_VBOOT is not set
+CONFIG_VARIANT_DIR="w541"
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO"
 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_USBDEBUG_HCD_INDEX=2
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
 CONFIG_TPM_PIRQ=0x0
+CONFIG_PS2K_EISAID="LEN0071"
+CONFIG_PS2M_EISAID="LEN004A"
+CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
 CONFIG_DCACHE_RAM_BASE=0xff7c0000
 CONFIG_DCACHE_RAM_SIZE=0x40000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
 CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
 CONFIG_HAVE_INTEL_FIRMWARE=y
 CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
@@ -148,9 +152,12 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe"
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 # CONFIG_ENABLE_DDR_2X_REFRESH is not set
 CONFIG_PCIEXP_AER=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_DEBUG_SMI is not set
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad W541"
 CONFIG_HAVE_IFD_BIN=y
-# CONFIG_BOARD_LENOVO_G505S is not set
 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set
 CONFIG_BOARD_LENOVO_THINKPAD_W541=y
 # CONFIG_BOARD_LENOVO_L520 is not set
@@ -182,21 +189,25 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y
 # CONFIG_BOARD_LENOVO_X220 is not set
 # CONFIG_BOARD_LENOVO_X220I is not set
 # CONFIG_BOARD_LENOVO_X1 is not set
+# CONFIG_BOARD_LENOVO_X220_EDP is not set
 # CONFIG_BOARD_LENOVO_X230 is not set
 # CONFIG_BOARD_LENOVO_X230T is not set
 # CONFIG_BOARD_LENOVO_X230S is not set
+# CONFIG_BOARD_LENOVO_X230_EDP is not set
 # CONFIG_BOARD_LENOVO_X60 is not set
 CONFIG_BOARD_LENOVO_HASWELL_COMMON=y
 CONFIG_VBOOT_SLOTS_RW_AB=y
-CONFIG_PS2K_EISAID="LEN0071"
-CONFIG_PS2M_EISAID="LEN004A"
 CONFIG_THINKPADEC_HKEY_EISAID="LEN0068"
 CONFIG_GFX_GMA_PANEL_1_PORT="DP3"
+CONFIG_D3COLD_SUPPORT=y
+CONFIG_PCIEXP_ASPM=y
 CONFIG_PCIEXP_L1_SUB_STATE=y
 CONFIG_PCIEXP_CLK_PM=y
+CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_HEAP_SIZE=0x4000
+CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_EC_GPE_SCI=0x50
+# CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -209,6 +220,7 @@ CONFIG_BOARD_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 CONFIG_COREBOOT_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=12288
@@ -230,7 +242,6 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y
 #
 # SoC
 #
-CONFIG_ARCH_ALL_STAGES_X86=y
 CONFIG_CHIPSET_DEVICETREE=""
 CONFIG_CBFS_MCACHE_SIZE=0x4000
 CONFIG_ROMSTAGE_ADDR=0x2000000
@@ -238,34 +249,34 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_TSEG_SIZE=0x800000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_CPU_SPECIFIC_OPTIONS=y
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d"
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
 CONFIG_EHCI_BAR=0xe8000000
+CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
 CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
 CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_ASPM=y
 CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4
+CONFIG_DISABLE_ME_PCI=y
-CONFIG_UART_PCI_ADDR=0x0
+CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
-CONFIG_CBFS_CACHE_ALIGN=8
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_CBFS_CACHE_ALIGN=8
 
 #
 # CPU
 #
 CONFIG_CPU_INTEL_HASWELL=y
-CONFIG_SSE2=y
 CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
 CONFIG_CPU_INTEL_COMMON=y
 CONFIG_ENABLE_VMX=y
@@ -274,7 +285,6 @@ CONFIG_SET_MSR_AESNI_LOCK_BIT=y
 CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
 CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
 CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
 CONFIG_PARALLEL_MP=y
 CONFIG_XAPIC_ONLY=y
 # CONFIG_X2APIC_ONLY is not set
@@ -283,14 +293,13 @@ CONFIG_XAPIC_ONLY=y
 CONFIG_UDELAY_TSC=y
 CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_LOGICAL_CPUS=y
 CONFIG_HAVE_SMI_HANDLER=y
 CONFIG_SMM_TSEG=y
-CONFIG_SMM_STUB_STACK_SIZE=0x400
+CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_CPU_INFO_V2=y
+CONFIG_AP_STACK_SIZE=0x800
 CONFIG_SMP=y
-CONFIG_MMX=y
 CONFIG_SSE=y
+CONFIG_SSE2=y
 CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
 CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
@@ -307,8 +316,6 @@ CONFIG_USE_NATIVE_RAMINIT=y
 #
 # Southbridge
 #
-CONFIG_SOUTH_BRIDGE_OPTIONS=y
-CONFIG_HPET_MIN_TICKS=0x80
 # CONFIG_PCIEXP_HOTPLUG is not set
 CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
 CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
@@ -325,12 +332,12 @@ CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
 CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
 CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
 # CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
 CONFIG_INTEL_CHIPSET_LOCKDOWN=y
+CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
 CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
 CONFIG_RCBA_LENGTH=0x4000
@@ -347,6 +354,7 @@ CONFIG_EC_LENOVO_H8=y
 CONFIG_H8_BEEP_ON_DEATH=y
 CONFIG_H8_FLASH_LEDS_ON_DEATH=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
+# CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
 CONFIG_H8_HAS_PRIMARY_FN_KEYS=y
 CONFIG_EC_LENOVO_PMH7=y
@@ -371,8 +379,10 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y
 CONFIG_ARCH_POSTCAR_X86_32=y
 CONFIG_ARCH_RAMSTAGE_X86_32=y
 CONFIG_ARCH_ALL_STAGES_X86_32=y
+CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_NUM_IPI_STARTS=2
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -382,6 +392,7 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y
 CONFIG_HAVE_CF9_RESET=y
 CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
+# CONFIG_DUMP_SMBIOS_TYPE17 is not set
 # end of Chipset
 
 #
@@ -393,6 +404,7 @@ CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
 CONFIG_MAINBOARD_USE_LIBGFXINIT=y
 # CONFIG_VGA_ROM_RUN is not set
 # CONFIG_NO_GFX_INIT is not set
+CONFIG_NO_EARLY_GFX_INIT=y
 
 #
 # Display
@@ -404,14 +416,14 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
 CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
+# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -419,7 +431,8 @@ CONFIG_INTEL_GMA_HAVE_VBT=y
 CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATOR_V4=y
+# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_USE_DDR3=y
 # end of Devices
 
 #
@@ -429,21 +442,19 @@ CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
 # CONFIG_ELOG is not set
 CONFIG_CACHE_MRC_SETTINGS=y
 # CONFIG_MRC_SETTINGS_PROTECT is not set
-CONFIG_MRC_STASH_TO_CBMEM=y
 # CONFIG_SMMSTORE is not set
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
 # CONFIG_SPI_FLASH_NO_FAST_READ is not set
 CONFIG_SPI_FLASH_ADESTO=y
 CONFIG_SPI_FLASH_AMIC=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_ISSI=y
 CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
 CONFIG_TPM_INIT_RAMSTAGE=y
 # CONFIG_TPM_PPI is not set
@@ -454,22 +465,28 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
+# CONFIG_DRIVERS_I2C_MAX98396 is not set
 CONFIG_INTEL_DDI=y
 CONFIG_INTEL_GMA_ACPI=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_INTEL_GMA_OPREGION_2_0=y
 CONFIG_GFX_GMA_DYN_CPU=y
 CONFIG_GFX_GMA_GENERATION="Haswell"
 CONFIG_GFX_GMA_PCH="Lynx_Point"
 CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
 CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
+# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
+CONFIG_USE_PC_CMOS_ALTCENTURY=y
+CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_MEMORY_MAPPED_TPM=y
 CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 CONFIG_VGA=y
@@ -502,7 +519,11 @@ CONFIG_MAINBOARD_HAS_TPM1=y
 # CONFIG_TPM_DEACTIVATE is not set
 # CONFIG_DEBUG_TPM is not set
 # CONFIG_TPM_RDRESP_NEED_DELAY is not set
-# CONFIG_TPM_MEASURED_BOOT is not set
+CONFIG_PCR_BOOT_MODE=1
+CONFIG_PCR_HWID=1
+CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
+CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
 #
@@ -524,11 +545,15 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y
 CONFIG_ACPI_HAVE_PCAT_8259=y
 CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
 CONFIG_ACPI_SOC_NVS=y
+CONFIG_ACPI_NO_CUSTOM_MADT=y
+CONFIG_ACPI_COMMON_MADT_LAPIC=y
+CONFIG_ACPI_COMMON_MADT_IOAPIC=y
 CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -541,6 +566,7 @@ CONFIG_SQUELCH_EARLY_SMP=y
 CONFIG_CONSOLE_CBMEM=y
 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
 # CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_CONSOLE_I2C_SMBUS is not set
 # CONFIG_EM100PRO_SPI_CONSOLE is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
@@ -554,11 +580,6 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
 CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
 CONFIG_HWBASE_DEBUG_CB=y
 # end of Console
 
@@ -573,6 +594,7 @@ CONFIG_USE_WATCHDOG_ON_BOOT=y
 # System tables
 #
 CONFIG_GENERATE_SMBIOS_TABLES=y
+CONFIG_BIOS_VENDOR="coreboot"
 CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
 # end of System tables
 
@@ -580,32 +602,6 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
 # Payload
 #
 CONFIG_PAYLOAD_NONE=y
-# CONFIG_PAYLOAD_ELF is not set
-# CONFIG_PAYLOAD_BOOTBOOT is not set
-# CONFIG_PAYLOAD_FILO is not set
-# CONFIG_PAYLOAD_GRUB2 is not set
-# CONFIG_PAYLOAD_SEAGRUB is not set
-# CONFIG_PAYLOAD_LINUXBOOT is not set
-# CONFIG_PAYLOAD_SEABIOS is not set
-# CONFIG_PAYLOAD_UBOOT is not set
-# CONFIG_PAYLOAD_YABITS is not set
-# CONFIG_PAYLOAD_LINUX is not set
-# CONFIG_PAYLOAD_TIANOCORE is not set
-CONFIG_PAYLOAD_OPTIONS=""
-# CONFIG_PXE is not set
-CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
-
-#
-# Secondary Payloads
-#
-# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
-# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set
-# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
-# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
-# CONFIG_SEABIOS_SECONDARY_PAYLOAD is not set
-# CONFIG_TINT_SECONDARY_PAYLOAD is not set
-# CONFIG_COREDOOM_SECONDARY_PAYLOAD is not set
-# end of Secondary Payloads
 # end of Payload
 
 #
@@ -617,6 +613,10 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
 #
 # CONFIG_DISPLAY_MTRRS is not set
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #
@@ -630,7 +630,6 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
 CONFIG_HAVE_DEBUG_SMBUS=y
 # CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_SMI is not set
 # CONFIG_DEBUG_MALLOC is not set
 # CONFIG_DEBUG_CONSOLE_INIT is not set
 # CONFIG_DEBUG_SPI_FLASH is not set
@@ -638,6 +637,7 @@ CONFIG_HAVE_DEBUG_SMBUS=y
 # CONFIG_DEBUG_ADA_CODE is not set
 CONFIG_HAVE_EM100_SUPPORT=y
 # CONFIG_EM100 is not set
+# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
 # end of Debugging
 
 CONFIG_RAMSTAGE_ADA=y
@@ -645,6 +645,7 @@ CONFIG_RAMSTAGE_LIBHWBASE=y
 CONFIG_HWBASE_DYNAMIC_MMIO=y
 CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
 CONFIG_HWBASE_DIRECT_PCIDEV=y
+CONFIG_DECOMPRESS_OFAST=y
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y

config/coreboot/w541_12mb/target.cfg

@@ -1,4 +1,4 @@
-tree="haswell"
+tree="default"
 xarch="i386-elf"
 payload_grub="y"
 payload_grub_withseabios="y"