add 9020sff/mt configs using haswell NRI
Signed-off-by: Leah Rowe <leah@libreboot.org>haswell/nri-update
parent
9e3b217cfd
commit
ac7ce93005
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@ -0,0 +1,627 @@
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#
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# Automatically generated file; DO NOT EDIT.
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# coreboot configuration
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#
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#
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# General setup
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#
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CONFIG_LOCALVERSION=""
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CONFIG_CBFS_PREFIX="fallback"
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CONFIG_COMPILER_GCC=y
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# CONFIG_COMPILER_LLVM_CLANG is not set
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CONFIG_ARCH_SUPPORTS_CLANG=y
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# CONFIG_ANY_TOOLCHAIN is not set
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# CONFIG_CCACHE is not set
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# CONFIG_IWYU is not set
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# CONFIG_FMD_GENPARSER is not set
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CONFIG_UTIL_GENPARSER=y
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# CONFIG_OPTION_BACKEND_NONE is not set
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CONFIG_USE_OPTION_TABLE=y
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CONFIG_STATIC_OPTION_TABLE=y
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CONFIG_COMPRESS_RAMSTAGE_LZMA=y
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# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
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CONFIG_SEPARATE_ROMSTAGE=y
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CONFIG_INCLUDE_CONFIG_FILE=y
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CONFIG_COLLECT_TIMESTAMPS=y
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# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
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CONFIG_USE_BLOBS=y
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# CONFIG_USE_AMD_BLOBS is not set
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# CONFIG_USE_QC_BLOBS is not set
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# CONFIG_COVERAGE is not set
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# CONFIG_UBSAN is not set
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CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
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CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
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# CONFIG_ASAN is not set
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CONFIG_NO_STAGE_CACHE=y
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# CONFIG_TSEG_STAGE_CACHE is not set
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# CONFIG_UPDATE_IMAGE is not set
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# CONFIG_BOOTSPLASH_IMAGE is not set
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# CONFIG_FW_CONFIG is not set
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#
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# Software Bill Of Materials (SBOM)
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#
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# CONFIG_SBOM is not set
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# end of Software Bill Of Materials (SBOM)
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# end of General setup
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#
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# Mainboard
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#
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#
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# Important: Run 'make distclean' before switching boards
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#
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# CONFIG_VENDOR_51NB is not set
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# CONFIG_VENDOR_ACER is not set
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# CONFIG_VENDOR_ADLINK is not set
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# CONFIG_VENDOR_AMD is not set
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# CONFIG_VENDOR_AOPEN is not set
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# CONFIG_VENDOR_APPLE is not set
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# CONFIG_VENDOR_ASROCK is not set
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# CONFIG_VENDOR_ASUS is not set
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# CONFIG_VENDOR_BIOSTAR is not set
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# CONFIG_VENDOR_BOSTENTECH is not set
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# CONFIG_VENDOR_BYTEDANCE is not set
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# CONFIG_VENDOR_CAVIUM is not set
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# CONFIG_VENDOR_CLEVO is not set
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# CONFIG_VENDOR_COMPULAB is not set
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CONFIG_VENDOR_DELL=y
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# CONFIG_VENDOR_EMULATION is not set
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# CONFIG_VENDOR_EXAMPLE is not set
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# CONFIG_VENDOR_FACEBOOK is not set
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# CONFIG_VENDOR_FOXCONN is not set
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# CONFIG_VENDOR_GETAC is not set
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# CONFIG_VENDOR_GIGABYTE is not set
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# CONFIG_VENDOR_GOOGLE is not set
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# CONFIG_VENDOR_HP is not set
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# CONFIG_VENDOR_IBASE is not set
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# CONFIG_VENDOR_IBM is not set
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# CONFIG_VENDOR_INTEL is not set
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# CONFIG_VENDOR_INVENTEC is not set
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# CONFIG_VENDOR_KONTRON is not set
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# CONFIG_VENDOR_LENOVO is not set
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# CONFIG_VENDOR_LIBRETREND is not set
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# CONFIG_VENDOR_MSI is not set
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# CONFIG_VENDOR_OCP is not set
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# CONFIG_VENDOR_OPENCELLULAR is not set
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# CONFIG_VENDOR_PACKARDBELL is not set
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# CONFIG_VENDOR_PCENGINES is not set
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# CONFIG_VENDOR_PINE64 is not set
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# CONFIG_VENDOR_PORTWELL is not set
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# CONFIG_VENDOR_PRODRIVE is not set
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# CONFIG_VENDOR_PROTECTLI is not set
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# CONFIG_VENDOR_PURISM is not set
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# CONFIG_VENDOR_RAZER is not set
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# CONFIG_VENDOR_RODA is not set
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# CONFIG_VENDOR_SAMSUNG is not set
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# CONFIG_VENDOR_SAPPHIRE is not set
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# CONFIG_VENDOR_SIEMENS is not set
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# CONFIG_VENDOR_SIFIVE is not set
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# CONFIG_VENDOR_STARLABS is not set
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# CONFIG_VENDOR_SUPERMICRO is not set
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# CONFIG_VENDOR_SYSTEM76 is not set
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# CONFIG_VENDOR_TI is not set
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# CONFIG_VENDOR_UP is not set
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CONFIG_BOARD_SPECIFIC_OPTIONS=y
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CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT"
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CONFIG_MAINBOARD_VERSION="1.0"
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CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
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CONFIG_VGA_BIOS_ID="8086,0166"
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CONFIG_DIMM_MAX=4
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CONFIG_DIMM_SPD_SIZE=256
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CONFIG_FMDFILE=""
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# CONFIG_NO_POST is not set
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CONFIG_MAINBOARD_VENDOR="Dell Inc."
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CONFIG_CBFS_SIZE=0x800000
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CONFIG_CONSOLE_SERIAL=y
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CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
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CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
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CONFIG_MAX_CPUS=8
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# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
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CONFIG_POST_DEVICE=y
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CONFIG_POST_IO=y
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CONFIG_UART_FOR_CONSOLE=0
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CONFIG_DEVICETREE="devicetree.cb"
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# CONFIG_VBOOT is not set
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CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb"
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# CONFIG_VGA_BIOS is not set
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CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
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CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
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CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
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CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
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CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
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CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
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# CONFIG_CONSOLE_POST is not set
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# CONFIG_BOARD_DELL_E6400 is not set
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# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
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CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
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# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
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# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
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CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
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CONFIG_ECAM_MMCONF_BUS_NUMBER=64
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CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
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CONFIG_DCACHE_RAM_BASE=0xff7c0000
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CONFIG_DCACHE_RAM_SIZE=0x40000
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CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
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CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
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CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
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CONFIG_HAVE_INTEL_FIRMWARE=y
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CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
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CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_DRIVERS_INTEL_WIFI=y
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CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
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CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
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CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
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CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
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# CONFIG_ENABLE_DDR_2X_REFRESH is not set
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CONFIG_PCIEXP_AER=y
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CONFIG_CARDBUS_PLUGIN_SUPPORT=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_STMICRO=y
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# CONFIG_DEBUG_SMI is not set
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CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
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CONFIG_HAVE_IFD_BIN=y
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CONFIG_PS2K_EISAID="PNP0303"
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CONFIG_PS2M_EISAID="PNP0F13"
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CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
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CONFIG_TTYS0_BAUD=115200
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CONFIG_D3COLD_SUPPORT=y
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CONFIG_PCIEXP_ASPM=y
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CONFIG_PCIEXP_L1_SUB_STATE=y
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CONFIG_PCIEXP_CLK_PM=y
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CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
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CONFIG_DRIVERS_UART_8250IO=y
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CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
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CONFIG_HEAP_SIZE=0x100000
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CONFIG_EC_GPE_SCI=0x50
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CONFIG_BOARD_ROMSIZE_KB_12288=y
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# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
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CONFIG_COREBOOT_ROMSIZE_KB_12288=y
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# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
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CONFIG_COREBOOT_ROMSIZE_KB=12288
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CONFIG_ROM_SIZE=0x00c00000
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CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
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CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
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CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
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# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
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# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
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CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
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# end of Mainboard
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#
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# Chipset
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#
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#
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# SoC
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#
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CONFIG_CHIPSET_DEVICETREE=""
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CONFIG_CBFS_MCACHE_SIZE=0x4000
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CONFIG_ROMSTAGE_ADDR=0x2000000
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CONFIG_VERSTAGE_ADDR=0x2000000
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CONFIG_SMM_TSEG_SIZE=0x800000
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CONFIG_SMM_RESERVED_SIZE=0x100000
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CONFIG_SMM_MODULE_STACK_SIZE=0x400
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CONFIG_SERIRQ_CONTINUOUS_MODE=y
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CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
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CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
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CONFIG_EHCI_BAR=0xe8000000
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CONFIG_ACPI_CPU_STRING="CP%02X"
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CONFIG_STACK_SIZE=0x2000
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CONFIG_IED_REGION_SIZE=0x400000
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CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
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CONFIG_INTEL_GMA_BCLV_WIDTH=16
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CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
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CONFIG_INTEL_GMA_BCLM_WIDTH=16
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CONFIG_BOOTBLOCK_IN_CBFS=y
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CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
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CONFIG_HPET_MIN_TICKS=0x80
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CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
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CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
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CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
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CONFIG_PCIEXP_COMMON_CLOCK=y
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CONFIG_DISABLE_ME_PCI=y
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CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
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CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
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CONFIG_FIXED_SMBUS_IO_BASE=0x400
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CONFIG_CBFS_CACHE_ALIGN=8
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#
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# CPU
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#
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CONFIG_CPU_INTEL_HASWELL=y
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CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
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CONFIG_CPU_INTEL_COMMON=y
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CONFIG_ENABLE_VMX=y
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CONFIG_SET_IA32_FC_LOCK_BIT=y
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CONFIG_SET_MSR_AESNI_LOCK_BIT=y
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CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
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CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
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CONFIG_CPU_INTEL_COMMON_SMM=y
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CONFIG_PARALLEL_MP=y
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CONFIG_XAPIC_ONLY=y
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# CONFIG_X2APIC_ONLY is not set
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# CONFIG_X2APIC_RUNTIME is not set
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# CONFIG_X2APIC_LATE_WORKAROUND is not set
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CONFIG_UDELAY_TSC=y
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CONFIG_TSC_MONOTONIC_TIMER=y
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CONFIG_TSC_SYNC_MFENCE=y
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CONFIG_HAVE_SMI_HANDLER=y
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CONFIG_SMM_TSEG=y
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CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
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CONFIG_AP_STACK_SIZE=0x800
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CONFIG_SMP=y
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CONFIG_SSE=y
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CONFIG_SSE2=y
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CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
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CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
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CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
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# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
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# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
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# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
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#
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# Northbridge
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#
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CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
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CONFIG_USE_NATIVE_RAMINIT=y
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#
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# Southbridge
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#
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# CONFIG_PCIEXP_HOTPLUG is not set
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CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
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CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
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CONFIG_FINALIZE_USB_ROUTE_XHCI=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
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CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
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CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
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# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
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CONFIG_INTEL_CHIPSET_LOCKDOWN=y
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CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
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CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
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CONFIG_RCBA_LENGTH=0x4000
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#
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# Super I/O
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#
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CONFIG_SUPERIO_SMSC_SCH555x=y
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#
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# Embedded Controllers
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#
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#
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# Intel Firmware
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#
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CONFIG_HAVE_ME_BIN=y
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# CONFIG_STITCH_ME_BIN is not set
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# CONFIG_CHECK_ME is not set
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# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
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# CONFIG_USE_ME_CLEANER is not set
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CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
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CONFIG_HAVE_GBE_BIN=y
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# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
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# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
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CONFIG_UNLOCK_FLASH_REGIONS=y
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CONFIG_ARCH_X86=y
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CONFIG_ARCH_BOOTBLOCK_X86_32=y
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CONFIG_ARCH_VERSTAGE_X86_32=y
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CONFIG_ARCH_ROMSTAGE_X86_32=y
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CONFIG_ARCH_POSTCAR_X86_32=y
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CONFIG_ARCH_RAMSTAGE_X86_32=y
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CONFIG_ARCH_ALL_STAGES_X86_32=y
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CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
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CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
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CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
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CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
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CONFIG_PC80_SYSTEM=y
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CONFIG_HAVE_CMOS_DEFAULT=y
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CONFIG_POSTCAR_STAGE=y
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CONFIG_BOOTBLOCK_SIMPLE=y
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# CONFIG_BOOTBLOCK_NORMAL is not set
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CONFIG_COLLECT_TIMESTAMPS_TSC=y
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CONFIG_HAVE_CF9_RESET=y
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CONFIG_DEBUG_HW_BREAKPOINTS=y
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CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
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# CONFIG_DUMP_SMBIOS_TYPE17 is not set
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# end of Chipset
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#
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# Devices
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#
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CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
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CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
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CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
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CONFIG_MAINBOARD_USE_LIBGFXINIT=y
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# CONFIG_VGA_ROM_RUN is not set
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# CONFIG_NO_GFX_INIT is not set
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CONFIG_NO_EARLY_GFX_INIT=y
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#
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# Display
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#
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# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
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CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
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CONFIG_LINEAR_FRAMEBUFFER=y
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# CONFIG_BOOTSPLASH is not set
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# end of Display
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CONFIG_PCI=y
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CONFIG_ECAM_MMCONF_SUPPORT=y
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CONFIG_PCIX_PLUGIN_SUPPORT=y
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CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
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CONFIG_PCIEXP_PLUGIN_SUPPORT=y
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CONFIG_ECAM_MMCONF_LENGTH=0x04000000
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CONFIG_PCI_ALLOW_BUS_MASTER=y
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CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
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CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
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# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
|
@ -0,0 +1,624 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
CONFIG_UTIL_GENPARSER=y
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb"
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
|
@ -0,0 +1,7 @@
|
|||
tree="haswell"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_seabios_grubonly="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="ahci"
|
|
@ -0,0 +1,627 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
|
@ -0,0 +1,624 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
|
@ -0,0 +1,7 @@
|
|||
tree="haswell"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_seabios_grubonly="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="ahci"
|
|
@ -0,0 +1,292 @@
|
|||
From d97b865a2210e70583e8bf5ee3a73d3c131b29c1 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 2 Mar 2024 22:51:09 +0000
|
||||
Subject: [PATCH 1/4] nb/intel/haswell: make IOMMU a runtime option
|
||||
|
||||
When I tested graphics cards on a coreboot port for Dell
|
||||
OptiPlex 9020 SFF, I could not use a graphics card unless
|
||||
I set iommu=off on the Linux cmdline.
|
||||
|
||||
Coreboot's current behaviour is to check whether the CPU
|
||||
has vt-d support and, if it does, initialise the IOMMU.
|
||||
|
||||
This patch maintains the current behaviour by default, but
|
||||
allows the user to turn *off* the IOMMU, even if vt-d is
|
||||
supported by the host CPU.
|
||||
|
||||
If iommu=Disable is specified, the check will not be
|
||||
performed, and the IOMMU will be left disabled. This option
|
||||
has been added to all current Haswell boards, though it is
|
||||
recommended to leave the IOMMU turned on in most setups.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/mainboard/asrock/b85m_pro4/cmos.default | 1 +
|
||||
src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++
|
||||
src/mainboard/asrock/h81m-hds/cmos.default | 1 +
|
||||
src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++
|
||||
src/mainboard/dell/optiplex_9020/cmos.default | 1 +
|
||||
src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++
|
||||
src/mainboard/google/beltino/cmos.layout | 5 +++++
|
||||
src/mainboard/google/slippy/cmos.layout | 5 +++++
|
||||
src/mainboard/intel/baskingridge/cmos.layout | 4 ++++
|
||||
src/mainboard/lenovo/haswell/cmos.default | 1 +
|
||||
src/mainboard/lenovo/haswell/cmos.layout | 3 +++
|
||||
src/mainboard/supermicro/x10slm-f/cmos.default | 1 +
|
||||
src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++
|
||||
src/northbridge/intel/haswell/early_init.c | 5 +++++
|
||||
14 files changed, 48 insertions(+)
|
||||
|
||||
diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default
|
||||
index 01bf20ad16..dfc8b80fb0 100644
|
||||
--- a/src/mainboard/asrock/b85m_pro4/cmos.default
|
||||
+++ b/src/mainboard/asrock/b85m_pro4/cmos.default
|
||||
@@ -4,3 +4,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
nmi=Enable
|
||||
power_on_after_fail=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout
|
||||
index efdc333fc2..c9883ea71d 100644
|
||||
--- a/src/mainboard/asrock/b85m_pro4/cmos.layout
|
||||
+++ b/src/mainboard/asrock/b85m_pro4/cmos.layout
|
||||
@@ -11,6 +11,7 @@
|
||||
395 4 e 4 debug_level
|
||||
408 1 e 1 nmi
|
||||
409 2 e 5 power_on_after_fail
|
||||
+ 412 1 e 6 iommu
|
||||
984 16 h 0 check_sum
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
@@ -38,6 +39,8 @@
|
||||
5 0 Disable
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
+ 6 0 Disable
|
||||
+ 6 1 Enable
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default
|
||||
index 01bf20ad16..dfc8b80fb0 100644
|
||||
--- a/src/mainboard/asrock/h81m-hds/cmos.default
|
||||
+++ b/src/mainboard/asrock/h81m-hds/cmos.default
|
||||
@@ -4,3 +4,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
nmi=Enable
|
||||
power_on_after_fail=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout
|
||||
index c9ba76c78f..95ee3d36fb 100644
|
||||
--- a/src/mainboard/asrock/h81m-hds/cmos.layout
|
||||
+++ b/src/mainboard/asrock/h81m-hds/cmos.layout
|
||||
@@ -21,6 +21,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 5 power_on_after_fail
|
||||
|
||||
+# enable or disable iommu
|
||||
+412 1 e 6 iommu
|
||||
+
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
|
||||
@@ -52,6 +55,9 @@ enumerations
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
|
||||
+6 0 Disable
|
||||
+6 1 Enable
|
||||
+
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
index cd4046f1ab..c974022472 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
@@ -3,3 +3,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
nmi=Disable
|
||||
power_on_after_fail=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
index c9ba76c78f..72ff9c4bee 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
@@ -21,6 +21,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 5 power_on_after_fail
|
||||
|
||||
+# turn iommu on or off
|
||||
+412 1 e 6 iommu
|
||||
+
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
|
||||
@@ -52,6 +55,9 @@ enumerations
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
|
||||
+6 0 Disable
|
||||
+6 1 Enable
|
||||
+
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout
|
||||
index 78d44c1415..c143979ae1 100644
|
||||
--- a/src/mainboard/google/beltino/cmos.layout
|
||||
+++ b/src/mainboard/google/beltino/cmos.layout
|
||||
@@ -19,6 +19,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
|
||||
+# enable or disable iommu
|
||||
+412 1 e 8 iommu
|
||||
+
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
@@ -47,6 +50,8 @@ enumerations
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
+8 0 Disable
|
||||
+8 1 Enable
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout
|
||||
index 78d44c1415..c143979ae1 100644
|
||||
--- a/src/mainboard/google/slippy/cmos.layout
|
||||
+++ b/src/mainboard/google/slippy/cmos.layout
|
||||
@@ -19,6 +19,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
|
||||
+# enable or disable iommu
|
||||
+412 1 e 8 iommu
|
||||
+
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
@@ -47,6 +50,8 @@ enumerations
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
+8 0 Disable
|
||||
+8 1 Enable
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout
|
||||
index 78d44c1415..f2c602f541 100644
|
||||
--- a/src/mainboard/intel/baskingridge/cmos.layout
|
||||
+++ b/src/mainboard/intel/baskingridge/cmos.layout
|
||||
@@ -19,6 +19,8 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
|
||||
+412 1 e 8 iommu
|
||||
+
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
@@ -47,6 +49,8 @@ enumerations
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
+8 0 Disable
|
||||
+8 1 Enable
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default
|
||||
index 08db97c5a9..cc6b363cd9 100644
|
||||
--- a/src/mainboard/lenovo/haswell/cmos.default
|
||||
+++ b/src/mainboard/lenovo/haswell/cmos.default
|
||||
@@ -14,3 +14,4 @@ trackpoint=Enable
|
||||
backlight=Keyboard
|
||||
enable_dual_graphics=Disable
|
||||
usb_always_on=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout
|
||||
index 27915d3ab7..59df76b64c 100644
|
||||
--- a/src/mainboard/lenovo/haswell/cmos.layout
|
||||
+++ b/src/mainboard/lenovo/haswell/cmos.layout
|
||||
@@ -23,6 +23,7 @@ entries
|
||||
|
||||
# coreboot config options: EC
|
||||
411 1 e 8 first_battery
|
||||
+413 1 e 14 iommu
|
||||
415 1 e 1 wlan
|
||||
416 1 e 1 trackpoint
|
||||
417 1 e 1 fn_ctrl_swap
|
||||
@@ -72,6 +73,8 @@ enumerations
|
||||
13 0 Disable
|
||||
13 1 AC and battery
|
||||
13 2 AC only
|
||||
+14 0 Disable
|
||||
+14 1 Enable
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default
|
||||
index 7ce38fb5d7..6049e7938a 100644
|
||||
--- a/src/mainboard/supermicro/x10slm-f/cmos.default
|
||||
+++ b/src/mainboard/supermicro/x10slm-f/cmos.default
|
||||
@@ -5,3 +5,4 @@ debug_level=Debug
|
||||
nmi=Enable
|
||||
power_on_after_fail=Keep
|
||||
hide_ast2400=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout
|
||||
index 38ba87aa45..24d39e97ee 100644
|
||||
--- a/src/mainboard/supermicro/x10slm-f/cmos.layout
|
||||
+++ b/src/mainboard/supermicro/x10slm-f/cmos.layout
|
||||
@@ -21,6 +21,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 5 power_on_after_fail
|
||||
|
||||
+# enable or disable iommu
|
||||
+412 1 e 6 iommu
|
||||
+
|
||||
# coreboot config options: mainboard
|
||||
416 1 e 1 hide_ast2400
|
||||
|
||||
@@ -55,6 +58,9 @@ enumerations
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
|
||||
+6 0 Disable
|
||||
+6 1 Enable
|
||||
+
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
|
||||
index e47deb5da6..1a7e0b1076 100644
|
||||
--- a/src/northbridge/intel/haswell/early_init.c
|
||||
+++ b/src/northbridge/intel/haswell/early_init.c
|
||||
@@ -5,6 +5,7 @@
|
||||
#include <device/mmio.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ops.h>
|
||||
+#include <option.h>
|
||||
|
||||
#include "haswell.h"
|
||||
|
||||
@@ -157,6 +158,10 @@ static void haswell_setup_misc(void)
|
||||
static void haswell_setup_iommu(void)
|
||||
{
|
||||
const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
|
||||
+ u8 enable_iommu = get_uint_option("iommu", 1);
|
||||
+
|
||||
+ if (!enable_iommu)
|
||||
+ return;
|
||||
|
||||
if (capid0_a & VTD_DISABLE)
|
||||
return;
|
||||
--
|
||||
2.39.2
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
From 153ca1a43c2c978fa2b2b82d988b0f838953cfb9 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 2 Mar 2024 23:00:09 +0000
|
||||
Subject: [PATCH 2/4] dell/optiplex_9020: Disable IOMMU by default
|
||||
|
||||
Needed to make graphics cards work. Turning it on is
|
||||
recommended if only using iGPU, otherwise leave it off
|
||||
by default. The IOMMU is extremely buggy when a graphics
|
||||
card is used. Leaving it off by default will ensure that
|
||||
the default ROM images in Libreboot will work on any setup.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/mainboard/dell/optiplex_9020/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
index c974022472..a0acd7b6bb 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
@@ -3,4 +3,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
nmi=Disable
|
||||
power_on_after_fail=Disable
|
||||
-iommu=Enable
|
||||
+iommu=Disable
|
||||
--
|
||||
2.39.2
|
||||
|
|
@ -0,0 +1,594 @@
|
|||
From 08bae51a77c2c92fefef79e9c9b6ff963b3812cc Mon Sep 17 00:00:00 2001
|
||||
From: Mate Kukri <kukri.mate@gmail.com>
|
||||
Date: Sat, 6 Apr 2024 23:25:15 +0100
|
||||
Subject: [PATCH 3/4] mb/dell/optiplex_9020: Implement late HWM initialization
|
||||
|
||||
There are 4 different chassis types specified by vendor firmware, each
|
||||
with a slightly different HWM configuration.
|
||||
|
||||
The chassis type to use is determined at runtime by reading a set of
|
||||
4 PCH GPIOs: 70, 38, 17, and 0.
|
||||
|
||||
Additionally vendor firmware also provides an option to run the fans at
|
||||
full speed. This is substituted with a coreboot nvram option in this
|
||||
implementation.
|
||||
|
||||
This was tested to make fan control work on my OptiPlex 7020 SFF.
|
||||
|
||||
NOTE: This is superficially similar to the OptiPlex 9010's SCH5545
|
||||
however the OptiPlex 9020's SCH5555 does not use externally
|
||||
programmed EC firmware.
|
||||
|
||||
Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43
|
||||
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/optiplex_9020/Makefile.mk | 3 +-
|
||||
src/mainboard/dell/optiplex_9020/bootblock.c | 25 +-
|
||||
src/mainboard/dell/optiplex_9020/cmos.default | 1 +
|
||||
src/mainboard/dell/optiplex_9020/cmos.layout | 5 +-
|
||||
src/mainboard/dell/optiplex_9020/mainboard.c | 382 ++++++++++++++++++
|
||||
src/mainboard/dell/optiplex_9020/sch5555_ec.c | 54 +++
|
||||
src/mainboard/dell/optiplex_9020/sch5555_ec.h | 7 +
|
||||
7 files changed, 455 insertions(+), 22 deletions(-)
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/Makefile.mk b/src/mainboard/dell/optiplex_9020/Makefile.mk
|
||||
index 6ca2f2afaa..08e2e53577 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/Makefile.mk
|
||||
+++ b/src/mainboard/dell/optiplex_9020/Makefile.mk
|
||||
@@ -2,4 +2,5 @@
|
||||
|
||||
romstage-y += gpio.c
|
||||
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
-bootblock-y += bootblock.c
|
||||
+ramstage-y += sch5555_ec.c
|
||||
+bootblock-y += bootblock.c sch5555_ec.c
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
|
||||
index 2837cf9cf1..e5e759273e 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/bootblock.c
|
||||
+++ b/src/mainboard/dell/optiplex_9020/bootblock.c
|
||||
@@ -4,29 +4,14 @@
|
||||
#include <device/pnp_ops.h>
|
||||
#include <superio/smsc/sch555x/sch555x.h>
|
||||
#include <southbridge/intel/lynxpoint/pch.h>
|
||||
-
|
||||
-static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
|
||||
-{
|
||||
- // Clear EC-to-Host mailbox
|
||||
- uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
|
||||
- outb(tmp, SCH555x_EMI_IOBASE + 1);
|
||||
-
|
||||
- // Send address and value to the EC
|
||||
- sch555x_emi_write16(0, (addr1 * 2) | 0x101);
|
||||
- sch555x_emi_write32(4, val | (addr2 << 16));
|
||||
-
|
||||
- // Wait for acknowledgement message from EC
|
||||
- outb(1, SCH555x_EMI_IOBASE);
|
||||
- size_t timeout = 0;
|
||||
- do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
|
||||
-}
|
||||
+#include "sch5555_ec.h"
|
||||
|
||||
struct ec_init_entry {
|
||||
uint16_t addr;
|
||||
uint8_t val;
|
||||
};
|
||||
|
||||
-static void ec_init(void)
|
||||
+static void bootblock_ec_init(void)
|
||||
{
|
||||
/*
|
||||
* Tables from CORE_PEI
|
||||
@@ -108,9 +93,9 @@ void mainboard_config_superio(void)
|
||||
outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
|
||||
outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
|
||||
|
||||
- // Magic EC init
|
||||
- ec_init();
|
||||
+ // Perform bootblock EC initialization
|
||||
+ bootblock_ec_init();
|
||||
|
||||
- // Magic EC init is needed for UART1 initialization to work
|
||||
+ // Bootblock EC initialization is required for UART1 to work
|
||||
sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
}
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
index a0acd7b6bb..9e02534c16 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
@@ -4,3 +4,4 @@ debug_level=Debug
|
||||
nmi=Disable
|
||||
power_on_after_fail=Disable
|
||||
iommu=Disable
|
||||
+fan_full_speed=Disable
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
index 72ff9c4bee..4a1496a878 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
@@ -22,7 +22,10 @@ entries
|
||||
409 2 e 5 power_on_after_fail
|
||||
|
||||
# turn iommu on or off
|
||||
-412 1 e 6 iommu
|
||||
+411 1 e 6 iommu
|
||||
+
|
||||
+# coreboot config options: EC
|
||||
+412 1 e 1 fan_full_speed
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
|
||||
index c834fea5d3..10b8aaca0e 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/mainboard.c
|
||||
+++ b/src/mainboard/dell/optiplex_9020/mainboard.c
|
||||
@@ -1,7 +1,12 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
+#include <bootstate.h>
|
||||
+#include <cpu/x86/msr.h>
|
||||
#include <device/device.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
+#include <option.h>
|
||||
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
|
||||
+#include "sch5555_ec.h"
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
@@ -13,3 +18,380 @@ static void mainboard_enable(struct device *dev)
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
+
|
||||
+#define HWM_TAB_ADD_TEMP_TARGET 1
|
||||
+#define HWM_TAB_PKG_POWER_ANY 0xffff
|
||||
+
|
||||
+struct hwm_tab_entry {
|
||||
+ uint16_t addr;
|
||||
+ uint8_t val;
|
||||
+ uint8_t flags;
|
||||
+ uint16_t pkg_power;
|
||||
+};
|
||||
+
|
||||
+struct hwm_tab_entry HWM_TAB3[] = {
|
||||
+ { 0x005, 0x33, 0, 0xffff },
|
||||
+ { 0x018, 0x2f, 0, 0xffff },
|
||||
+ { 0x019, 0x2f, 0, 0xffff },
|
||||
+ { 0x01a, 0x2f, 0, 0xffff },
|
||||
+ { 0x080, 0x00, 0, 0xffff },
|
||||
+ { 0x081, 0x00, 0, 0xffff },
|
||||
+ { 0x083, 0xbb, 0, 0xffff },
|
||||
+ { 0x085, 0x8a, 0, 0x0010 },
|
||||
+ { 0x086, 0x4c, 0, 0x0010 },
|
||||
+ { 0x08a, 0x66, 0, 0x0010 },
|
||||
+ { 0x08b, 0x5b, 0, 0x0010 },
|
||||
+ { 0x090, 0x65, 0, 0xffff },
|
||||
+ { 0x091, 0x70, 0, 0xffff },
|
||||
+ { 0x092, 0x86, 0, 0xffff },
|
||||
+ { 0x096, 0xa4, 0, 0xffff },
|
||||
+ { 0x097, 0xa4, 0, 0xffff },
|
||||
+ { 0x098, 0xa4, 0, 0xffff },
|
||||
+ { 0x09b, 0xa4, 0, 0xffff },
|
||||
+ { 0x0a0, 0x0e, 0, 0xffff },
|
||||
+ { 0x0a1, 0x0e, 0, 0xffff },
|
||||
+ { 0x0ae, 0x7c, 0, 0xffff },
|
||||
+ { 0x0af, 0x86, 0, 0xffff },
|
||||
+ { 0x0b0, 0x9a, 0, 0xffff },
|
||||
+ { 0x0b3, 0x9a, 0, 0xffff },
|
||||
+ { 0x0b6, 0x08, 0, 0xffff },
|
||||
+ { 0x0b7, 0x08, 0, 0xffff },
|
||||
+ { 0x0ea, 0x64, 0, 0x0020 },
|
||||
+ { 0x0ea, 0x5c, 0, 0x0010 },
|
||||
+ { 0x0ef, 0xff, 0, 0xffff },
|
||||
+ { 0x0f8, 0x15, 0, 0xffff },
|
||||
+ { 0x0f9, 0x00, 0, 0xffff },
|
||||
+ { 0x0f0, 0x30, 0, 0xffff },
|
||||
+ { 0x0fd, 0x01, 0, 0xffff },
|
||||
+ { 0x1a1, 0x00, 0, 0xffff },
|
||||
+ { 0x1a2, 0x00, 0, 0xffff },
|
||||
+ { 0x1b1, 0x08, 0, 0xffff },
|
||||
+ { 0x1be, 0x99, 0, 0xffff },
|
||||
+ { 0x280, 0xa0, 0, 0x0010 },
|
||||
+ { 0x281, 0x0f, 0, 0x0010 },
|
||||
+ { 0x282, 0x03, 0, 0xffff },
|
||||
+ { 0x283, 0x0a, 0, 0xffff },
|
||||
+ { 0x284, 0x80, 0, 0xffff },
|
||||
+ { 0x285, 0x03, 0, 0xffff },
|
||||
+ { 0x288, 0x68, 0, 0x0010 },
|
||||
+ { 0x289, 0x10, 0, 0x0010 },
|
||||
+ { 0x28a, 0x03, 0, 0xffff },
|
||||
+ { 0x28b, 0x0a, 0, 0xffff },
|
||||
+ { 0x28c, 0x80, 0, 0xffff },
|
||||
+ { 0x28d, 0x03, 0, 0xffff },
|
||||
+};
|
||||
+
|
||||
+struct hwm_tab_entry HWM_TAB4[] = {
|
||||
+ { 0x005, 0x33, 0, 0xffff },
|
||||
+ { 0x018, 0x2f, 0, 0xffff },
|
||||
+ { 0x019, 0x2f, 0, 0xffff },
|
||||
+ { 0x01a, 0x2f, 0, 0xffff },
|
||||
+ { 0x080, 0x00, 0, 0xffff },
|
||||
+ { 0x081, 0x00, 0, 0xffff },
|
||||
+ { 0x083, 0xbb, 0, 0xffff },
|
||||
+ { 0x085, 0x99, 0, 0x0020 },
|
||||
+ { 0x085, 0xad, 0, 0x0010 },
|
||||
+ { 0x086, 0x1c, 0, 0xffff },
|
||||
+ { 0x08a, 0x39, 0, 0x0020 },
|
||||
+ { 0x08a, 0x41, 0, 0x0010 },
|
||||
+ { 0x08b, 0x76, 0, 0x0020 },
|
||||
+ { 0x08b, 0x8b, 0, 0x0010 },
|
||||
+ { 0x090, 0x5e, 0, 0xffff },
|
||||
+ { 0x091, 0x5e, 0, 0xffff },
|
||||
+ { 0x092, 0x86, 0, 0xffff },
|
||||
+ { 0x096, 0xa4, 0, 0xffff },
|
||||
+ { 0x097, 0xa4, 0, 0xffff },
|
||||
+ { 0x098, 0xa4, 0, 0xffff },
|
||||
+ { 0x09b, 0xa4, 0, 0xffff },
|
||||
+ { 0x0a0, 0x0a, 0, 0xffff },
|
||||
+ { 0x0a1, 0x0a, 0, 0xffff },
|
||||
+ { 0x0ae, 0x7c, 0, 0xffff },
|
||||
+ { 0x0af, 0x7c, 0, 0xffff },
|
||||
+ { 0x0b0, 0x9a, 0, 0xffff },
|
||||
+ { 0x0b3, 0x7c, 0, 0xffff },
|
||||
+ { 0x0b6, 0x08, 0, 0xffff },
|
||||
+ { 0x0b7, 0x08, 0, 0xffff },
|
||||
+ { 0x0ea, 0x64, 0, 0x0020 },
|
||||
+ { 0x0ea, 0x5c, 0, 0x0010 },
|
||||
+ { 0x0ef, 0xff, 0, 0xffff },
|
||||
+ { 0x0f8, 0x15, 0, 0xffff },
|
||||
+ { 0x0f9, 0x00, 0, 0xffff },
|
||||
+ { 0x0f0, 0x30, 0, 0xffff },
|
||||
+ { 0x0fd, 0x01, 0, 0xffff },
|
||||
+ { 0x1a1, 0x00, 0, 0xffff },
|
||||
+ { 0x1a2, 0x00, 0, 0xffff },
|
||||
+ { 0x1b1, 0x08, 0, 0xffff },
|
||||
+ { 0x1be, 0x90, 0, 0xffff },
|
||||
+ { 0x280, 0x94, 0, 0x0020 },
|
||||
+ { 0x281, 0x11, 0, 0x0020 },
|
||||
+ { 0x280, 0x94, 0, 0x0010 },
|
||||
+ { 0x281, 0x11, 0, 0x0010 },
|
||||
+ { 0x282, 0x03, 0, 0xffff },
|
||||
+ { 0x283, 0x0a, 0, 0xffff },
|
||||
+ { 0x284, 0x80, 0, 0xffff },
|
||||
+ { 0x285, 0x03, 0, 0xffff },
|
||||
+ { 0x288, 0x28, 0, 0x0020 },
|
||||
+ { 0x289, 0x0a, 0, 0x0020 },
|
||||
+ { 0x288, 0x28, 0, 0x0010 },
|
||||
+ { 0x289, 0x0a, 0, 0x0010 },
|
||||
+ { 0x28a, 0x03, 0, 0xffff },
|
||||
+ { 0x28b, 0x0a, 0, 0xffff },
|
||||
+ { 0x28c, 0x80, 0, 0xffff },
|
||||
+ { 0x28d, 0x03, 0, 0xffff },
|
||||
+};
|
||||
+
|
||||
+struct hwm_tab_entry HWM_TAB5[] = {
|
||||
+ { 0x005, 0x33, 0, 0xffff },
|
||||
+ { 0x018, 0x2f, 0, 0xffff },
|
||||
+ { 0x019, 0x2f, 0, 0xffff },
|
||||
+ { 0x01a, 0x2f, 0, 0xffff },
|
||||
+ { 0x080, 0x00, 0, 0xffff },
|
||||
+ { 0x081, 0x00, 0, 0xffff },
|
||||
+ { 0x083, 0xbb, 0, 0xffff },
|
||||
+ { 0x085, 0x66, 0, 0x0020 },
|
||||
+ { 0x085, 0x5d, 0, 0x0010 },
|
||||
+ { 0x086, 0x1c, 0, 0xffff },
|
||||
+ { 0x08a, 0x39, 0, 0x0020 },
|
||||
+ { 0x08a, 0x41, 0, 0x0010 },
|
||||
+ { 0x08b, 0x76, 0, 0x0020 },
|
||||
+ { 0x08b, 0x80, 0, 0x0010 },
|
||||
+ { 0x090, 0x5d, 0, 0x0020 },
|
||||
+ { 0x090, 0x5e, 0, 0x0010 },
|
||||
+ { 0x091, 0x5e, 0, 0xffff },
|
||||
+ { 0x092, 0x86, 0, 0xffff },
|
||||
+ { 0x096, 0xa4, 0, 0xffff },
|
||||
+ { 0x097, 0xa4, 0, 0xffff },
|
||||
+ { 0x098, 0xa3, 0, 0x0020 },
|
||||
+ { 0x098, 0xa4, 0, 0x0010 },
|
||||
+ { 0x09b, 0xa4, 0, 0xffff },
|
||||
+ { 0x0a0, 0x08, 0, 0xffff },
|
||||
+ { 0x0a1, 0x0a, 0, 0xffff },
|
||||
+ { 0x0ae, 0x7c, 0, 0xffff },
|
||||
+ { 0x0af, 0x7c, 0, 0xffff },
|
||||
+ { 0x0b0, 0x9a, 0, 0xffff },
|
||||
+ { 0x0b3, 0x7c, 0, 0xffff },
|
||||
+ { 0x0b6, 0x08, 0, 0xffff },
|
||||
+ { 0x0b7, 0x08, 0, 0xffff },
|
||||
+ { 0x0ea, 0x64, 0, 0x0020 },
|
||||
+ { 0x0ea, 0x5c, 0, 0x0010 },
|
||||
+ { 0x0ef, 0xff, 0, 0xffff },
|
||||
+ { 0x0f8, 0x15, 0, 0xffff },
|
||||
+ { 0x0f9, 0x00, 0, 0xffff },
|
||||
+ { 0x0f0, 0x30, 0, 0xffff },
|
||||
+ { 0x0fd, 0x01, 0, 0xffff },
|
||||
+ { 0x1a1, 0x00, 0, 0xffff },
|
||||
+ { 0x1a2, 0x00, 0, 0xffff },
|
||||
+ { 0x1b1, 0x08, 0, 0xffff },
|
||||
+ { 0x1be, 0x98, 0, 0x0020 },
|
||||
+ { 0x1be, 0x90, 0, 0x0010 },
|
||||
+ { 0x280, 0x94, 0, 0x0020 },
|
||||
+ { 0x281, 0x11, 0, 0x0020 },
|
||||
+ { 0x280, 0x94, 0, 0x0010 },
|
||||
+ { 0x281, 0x11, 0, 0x0010 },
|
||||
+ { 0x282, 0x03, 0, 0xffff },
|
||||
+ { 0x283, 0x0a, 0, 0xffff },
|
||||
+ { 0x284, 0x80, 0, 0xffff },
|
||||
+ { 0x285, 0x03, 0, 0xffff },
|
||||
+ { 0x288, 0x28, 0, 0x0020 },
|
||||
+ { 0x289, 0x0a, 0, 0x0020 },
|
||||
+ { 0x288, 0x28, 0, 0x0010 },
|
||||
+ { 0x289, 0x0a, 0, 0x0010 },
|
||||
+ { 0x28a, 0x03, 0, 0xffff },
|
||||
+ { 0x28b, 0x0a, 0, 0xffff },
|
||||
+ { 0x28c, 0x80, 0, 0xffff },
|
||||
+ { 0x28d, 0x03, 0, 0xffff },
|
||||
+};
|
||||
+
|
||||
+struct hwm_tab_entry HWM_TAB6[] = {
|
||||
+ { 0x005, 0x33, 0, 0xffff },
|
||||
+ { 0x018, 0x2f, 0, 0xffff },
|
||||
+ { 0x019, 0x2f, 0, 0xffff },
|
||||
+ { 0x01a, 0x2f, 0, 0xffff },
|
||||
+ { 0x080, 0x00, 0, 0xffff },
|
||||
+ { 0x081, 0x00, 0, 0xffff },
|
||||
+ { 0x083, 0xbb, 0, 0xffff },
|
||||
+ { 0x085, 0x98, 0, 0xffff },
|
||||
+ { 0x086, 0x3c, 0, 0xffff },
|
||||
+ { 0x08a, 0x39, 0, 0x0020 },
|
||||
+ { 0x08a, 0x3d, 0, 0x0010 },
|
||||
+ { 0x08b, 0x44, 0, 0x0020 },
|
||||
+ { 0x08b, 0x51, 0, 0x0010 },
|
||||
+ { 0x090, 0x61, 0, 0xffff },
|
||||
+ { 0x091, 0x6d, 0, 0xffff },
|
||||
+ { 0x092, 0x86, 0, 0xffff },
|
||||
+ { 0x096, 0xa4, 0, 0xffff },
|
||||
+ { 0x097, 0xa4, 0, 0xffff },
|
||||
+ { 0x098, 0x9f, 0, 0x0020 },
|
||||
+ { 0x098, 0xa4, 0, 0x0010 },
|
||||
+ { 0x09b, 0xa4, 0, 0xffff },
|
||||
+ { 0x0a0, 0x0e, 0, 0xffff },
|
||||
+ { 0x0a1, 0x0e, 0, 0xffff },
|
||||
+ { 0x0ae, 0x7c, 0, 0xffff },
|
||||
+ { 0x0af, 0x7c, 0, 0xffff },
|
||||
+ { 0x0b0, 0x9b, 0, 0x0020 },
|
||||
+ { 0x0b0, 0x98, 0, 0x0010 },
|
||||
+ { 0x0b3, 0x9a, 0, 0xffff },
|
||||
+ { 0x0b6, 0x08, 0, 0xffff },
|
||||
+ { 0x0b7, 0x08, 0, 0xffff },
|
||||
+ { 0x0ea, 0x64, 0, 0x0020 },
|
||||
+ { 0x0ea, 0x5c, 0, 0x0010 },
|
||||
+ { 0x0ef, 0xff, 0, 0xffff },
|
||||
+ { 0x0f8, 0x15, 0, 0xffff },
|
||||
+ { 0x0f9, 0x00, 0, 0xffff },
|
||||
+ { 0x0f0, 0x30, 0, 0xffff },
|
||||
+ { 0x0fd, 0x01, 0, 0xffff },
|
||||
+ { 0x1a1, 0x00, 0, 0xffff },
|
||||
+ { 0x1a2, 0x00, 0, 0xffff },
|
||||
+ { 0x1b1, 0x08, 0, 0xffff },
|
||||
+ { 0x1be, 0x9a, 0, 0x0020 },
|
||||
+ { 0x1be, 0x96, 0, 0x0010 },
|
||||
+ { 0x280, 0x94, 0, 0x0020 },
|
||||
+ { 0x281, 0x11, 0, 0x0020 },
|
||||
+ { 0x280, 0x94, 0, 0x0010 },
|
||||
+ { 0x281, 0x11, 0, 0x0010 },
|
||||
+ { 0x282, 0x03, 0, 0xffff },
|
||||
+ { 0x283, 0x0a, 0, 0xffff },
|
||||
+ { 0x284, 0x80, 0, 0xffff },
|
||||
+ { 0x285, 0x03, 0, 0xffff },
|
||||
+ { 0x288, 0x94, 0, 0x0020 },
|
||||
+ { 0x289, 0x11, 0, 0x0020 },
|
||||
+ { 0x288, 0x94, 0, 0x0010 },
|
||||
+ { 0x289, 0x11, 0, 0x0010 },
|
||||
+ { 0x28a, 0x03, 0, 0xffff },
|
||||
+ { 0x28b, 0x0a, 0, 0xffff },
|
||||
+ { 0x28c, 0x80, 0, 0xffff },
|
||||
+ { 0x28d, 0x03, 0, 0xffff },
|
||||
+};
|
||||
+
|
||||
+static uint8_t get_chassis_type(void)
|
||||
+{
|
||||
+ uint8_t gpio_chassis_type;
|
||||
+
|
||||
+ // Read chassis type from GPIO
|
||||
+ gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 |
|
||||
+ get_gpio(17) << 1 | get_gpio(0);
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type);
|
||||
+
|
||||
+ // Turn it into internal chassis index
|
||||
+ switch (gpio_chassis_type) {
|
||||
+ case 0x08:
|
||||
+ case 0x0a:
|
||||
+ return 4;
|
||||
+ case 0x0b:
|
||||
+ return 3;
|
||||
+ case 0x0c:
|
||||
+ return 5;
|
||||
+ case 0x0d: // SFF
|
||||
+ case 0x0e:
|
||||
+ case 0x0f:
|
||||
+ return 6;
|
||||
+ default:
|
||||
+ die("Unknown GPIO chassis type\n");
|
||||
+ }
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static uint8_t get_temp_target(void)
|
||||
+{
|
||||
+ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff;
|
||||
+ if (!val)
|
||||
+ val = 20;
|
||||
+ return 0x95 - val;
|
||||
+}
|
||||
+
|
||||
+static uint16_t get_pkg_power(void)
|
||||
+{
|
||||
+ uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf;
|
||||
+ if (rapl_power_unit)
|
||||
+ rapl_power_unit = 2 << (rapl_power_unit - 1);
|
||||
+ uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff;
|
||||
+ if (pkg_power_info / rapl_power_unit > 0x41)
|
||||
+ return 32;
|
||||
+ else
|
||||
+ return 16;
|
||||
+}
|
||||
+
|
||||
+static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size)
|
||||
+{
|
||||
+ uint8_t temp_target = get_temp_target();
|
||||
+ uint16_t pkg_power = get_pkg_power();
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target);
|
||||
+ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power);
|
||||
+
|
||||
+ for (size_t i = 0; i < size; ++i) {
|
||||
+ // Skip entry if it doesn't apply for this package power
|
||||
+ if (arr[i].pkg_power != pkg_power &&
|
||||
+ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY)
|
||||
+ continue;
|
||||
+
|
||||
+ uint8_t val = arr[i].val;
|
||||
+
|
||||
+ // Add temp target to value if requested (current tables never do)
|
||||
+ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET)
|
||||
+ val += temp_target;
|
||||
+
|
||||
+ // Perform write
|
||||
+ ec_write(1, arr[i].addr, val);
|
||||
+
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void sch5555_ec_hwm_init(void *arg)
|
||||
+{
|
||||
+ uint8_t chassis_type, saved_2fc;
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n");
|
||||
+
|
||||
+ saved_2fc = ec_read(1, 0x2fc);
|
||||
+ ec_write(1, 0x2fc, 0xa0);
|
||||
+ ec_write(1, 0x2fd, 0x32);
|
||||
+
|
||||
+ // Apply HWM table based on chassis type
|
||||
+ chassis_type = get_chassis_type();
|
||||
+ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type);
|
||||
+ switch (chassis_type) {
|
||||
+ case 3:
|
||||
+ apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3));
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4));
|
||||
+ break;
|
||||
+ case 5:
|
||||
+ apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5));
|
||||
+ break;
|
||||
+ case 6:
|
||||
+ apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6));
|
||||
+ break;
|
||||
+ default:
|
||||
+ die("Unknown chassis type\n");
|
||||
+ }
|
||||
+
|
||||
+ if (CONFIG_MAX_CPUS > 2) {
|
||||
+ ec_write(1, 0x9e, 0x30);
|
||||
+ ec_write(1, 0xeb, ec_read(1, 0xea));
|
||||
+ }
|
||||
+
|
||||
+ ec_write(1, 0x2fc, saved_2fc);
|
||||
+
|
||||
+ // Apply full speed fan config if requested
|
||||
+ if (get_uint_option("fan_full_speed", 0)) {
|
||||
+ printk(BIOS_DEBUG, "Setting full fan speed\n");
|
||||
+ ec_write(1, 0x80, 0x60 | ec_read(1, 0x80));
|
||||
+ ec_write(1, 0x81, 0x60 | ec_read(1, 0x81));
|
||||
+ }
|
||||
+
|
||||
+ ec_read(1, 0xb8);
|
||||
+
|
||||
+ if ((chassis_type == 4 || chassis_type == 5) && ec_read(1, 0x26) == 0) {
|
||||
+ ec_write(1, 0xa0, ec_read(1, 0xa0) & 0xfb);
|
||||
+ ec_write(1, 0xa1, ec_read(1, 0xa1) & 0xfb);
|
||||
+ ec_write(1, 0xa2, ec_read(1, 0xa2) & 0xfb);
|
||||
+ ec_write(1, 0x8a, 0x99);
|
||||
+ ec_write(1, 0x8b, 0x47);
|
||||
+ ec_write(1, 0x8c, 0x91);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL);
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
|
||||
new file mode 100644
|
||||
index 0000000000..92244da9ab
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
|
||||
@@ -0,0 +1,54 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <arch/io.h>
|
||||
+#include <device/pnp_ops.h>
|
||||
+#include <superio/smsc/sch555x/sch555x.h>
|
||||
+#include "sch5555_ec.h"
|
||||
+
|
||||
+uint8_t ec_read(uint8_t addr1, uint16_t addr2)
|
||||
+{
|
||||
+ // clear ec-to-host mailbox
|
||||
+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
|
||||
+ outb(tmp, SCH555x_EMI_IOBASE + 1);
|
||||
+
|
||||
+ // send address
|
||||
+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
|
||||
+ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4);
|
||||
+
|
||||
+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
|
||||
+ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4);
|
||||
+
|
||||
+ // send message to ec
|
||||
+ outb(1, SCH555x_EMI_IOBASE);
|
||||
+
|
||||
+ // wait for ack
|
||||
+ for (size_t timeout = 0; timeout < 0xfff; ++timeout)
|
||||
+ if (inb(SCH555x_EMI_IOBASE + 1) & 1)
|
||||
+ break;
|
||||
+
|
||||
+ // read result
|
||||
+ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2);
|
||||
+ return inb(SCH555x_EMI_IOBASE + 4);
|
||||
+}
|
||||
+
|
||||
+void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
|
||||
+{
|
||||
+ // clear ec-to-host mailbox
|
||||
+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
|
||||
+ outb(tmp, SCH555x_EMI_IOBASE + 1);
|
||||
+
|
||||
+ // send address and value
|
||||
+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
|
||||
+ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4);
|
||||
+
|
||||
+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
|
||||
+ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4);
|
||||
+
|
||||
+ // send message to ec
|
||||
+ outb(1, SCH555x_EMI_IOBASE);
|
||||
+
|
||||
+ // wait for ack
|
||||
+ for (size_t timeout = 0; timeout < 0xfff; ++timeout)
|
||||
+ if (inb(SCH555x_EMI_IOBASE + 1) & 1)
|
||||
+ break;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
|
||||
new file mode 100644
|
||||
index 0000000000..6e703ff865
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
|
||||
@@ -0,0 +1,7 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#pragma once
|
||||
+
|
||||
+uint8_t ec_read(uint8_t addr1, uint16_t addr2);
|
||||
+
|
||||
+void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val);
|
||||
--
|
||||
2.39.2
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
From ae494dc1b1dde92ec42390b85ced0ffe816f5110 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 6 Apr 2024 01:22:47 +0100
|
||||
Subject: [PATCH 4/4] nb/haswell: Fully disable iGPU when dGPU is used
|
||||
|
||||
My earlier patch disabled decode *and* disabled the iGPU itself, but
|
||||
a subsequent revision disabled only VGA decode. Upon revisiting, I
|
||||
found that, actually, yes, you also need to disable the iGPU entirely.
|
||||
|
||||
Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU.
|
||||
With this patch, the iGPU is completely disabled when you install a
|
||||
graphics card, but the iGPU is available to use when no graphics card
|
||||
is present.
|
||||
|
||||
For more context, see:
|
||||
|
||||
Author: Leah Rowe <info@minifree.org>
|
||||
Date: Fri Feb 23 13:33:31 2024 +0000
|
||||
|
||||
nb/haswell: Disable iGPU when dGPU is used
|
||||
|
||||
And look at the Gerrit comments:
|
||||
|
||||
https://review.coreboot.org/c/coreboot/+/80717/
|
||||
|
||||
So, my original submission on change 80717 was actually correct.
|
||||
This patch fixes the issue. I tested on iGPU and dGPU, with both
|
||||
broadwell and haswell mrc.bin.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/northbridge/intel/haswell/gma.c | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
|
||||
index 9e9f9804f5..526a51aff0 100644
|
||||
--- a/src/northbridge/intel/haswell/gma.c
|
||||
+++ b/src/northbridge/intel/haswell/gma.c
|
||||
@@ -464,6 +464,9 @@ static void gma_func0_disable(struct device *dev)
|
||||
{
|
||||
/* Disable VGA decode */
|
||||
pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
|
||||
+
|
||||
+ /* Required or else the graphics card doesn't work */
|
||||
+ dev->enabled = 0;
|
||||
}
|
||||
|
||||
static struct device_operations gma_func0_ops = {
|
||||
--
|
||||
2.39.2
|
||||
|
|
@ -35,7 +35,7 @@
|
|||
|
||||
# NOTE: google's manifest for archives containing mrc.bin, used here:
|
||||
# https://web.archive.org/web/20210211071412/https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf
|
||||
{t440pmrc w541mrc t440plibremrc w541 dell9020mt dell9020sff}{
|
||||
{t440pmrc w541mrc t440plibremrc w541 dell9020mt dell9020sff dell9020sff-nri dell9020mt-nri}{
|
||||
DL_hash f3d79aec805c8b0094a4081be76b3a22d329c479ad18210449b7acc3236ccfc4a2103eaa7c5b79a4872bfd699eede047efd46dfb06dc8f47e3216fc254612998
|
||||
DL_url https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe
|
||||
DL_url_bkup https://web.archive.org/web/20211120031520/https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe
|
||||
|
|
Loading…
Reference in New Issue