Add SPD support for onboard ThinkPad T480S RAM
Patchset 20 from: https://review.coreboot.org/c/coreboot/+/83274/18..20 Updated to that. A bunch of changes I made locally have been copied here, thus removed from lbmk. The previous setup in lbmk was to have only the DIMM slot work, on the ThinkPad T480S, without setting up SPD for the onboard RAM> Mate Kukri reverse engineered the scheme by which the SPDs are chosen at boot, based on the wiring of the board. This should just about match the way Lenovo did it in their firmware. Signed-off-by: Leah Rowe <leah@libreboot.org>m920qwip
Leah Rowe
parent
046529abd9
commit
b95a411a36
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@ -1,7 +1,7 @@
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From b7b4f05005bfe46fc5ce67ae1f04d225e35cbd4d Mon Sep 17 00:00:00 2001
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From 18b68185f44599cf6ea6a20816bf6a5eb7aeda17 Mon Sep 17 00:00:00 2001
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From: Felix Singer <felixsinger@posteo.net>
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Date: Wed, 26 Jun 2024 04:24:31 +0200
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Subject: [PATCH 1/9] soc/intel/skylake: configure usb acpi
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Subject: [PATCH 1/8] soc/intel/skylake: configure usb acpi
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Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
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Signed-off-by: Felix Singer <felixsinger@posteo.net>
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@ -1,7 +1,7 @@
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From 86a721209951605ad59aff31639a6be954a0fab8 Mon Sep 17 00:00:00 2001
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From a7cbcbc7037fe3473e5ebe475cbfd12f653e9827 Mon Sep 17 00:00:00 2001
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From: Felix Singer <felixsinger@posteo.net>
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Date: Wed, 26 Jun 2024 00:59:03 +0200
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Subject: [PATCH 2/9] mb/lenovo: Add initial code for Lenovo ThinkPad E460
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Subject: [PATCH 2/8] mb/lenovo: Add initial code for Lenovo ThinkPad E460
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Change-Id: Ia02f81750105c95c867d961dbdadcd5991ad371f
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Signed-off-by: Felix Singer <felixsinger@posteo.net>
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@ -1,7 +1,7 @@
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From 46da5bb38caf3b5d523e79ca0e17b125179daaaf Mon Sep 17 00:00:00 2001
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From b3049cfd11aa0f3c124ed8f87e98a200201ecbdc Mon Sep 17 00:00:00 2001
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From: Mate Kukri <km@mkukri.xyz>
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Date: Fri, 22 Nov 2024 21:26:48 +0000
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Subject: [PATCH 3/9] soc/intel/skylake: Enable 4E/4F PNP I/O ports in
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Subject: [PATCH 3/8] soc/intel/skylake: Enable 4E/4F PNP I/O ports in
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bootblock
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Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173
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File diff suppressed because it is too large
Load Diff
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@ -1,7 +1,7 @@
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From bc884fae79664c0d606991b5e0d62c608f3bef35 Mon Sep 17 00:00:00 2001
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From 534d696a570a50057153669247933ec1a4a2480f Mon Sep 17 00:00:00 2001
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From: Nicholas Chin <nic.c3.14@gmail.com>
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Date: Mon, 30 Sep 2024 20:44:38 -0400
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Subject: [PATCH 4/9] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
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Subject: [PATCH 5/8] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
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Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
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Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
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@ -1,7 +1,7 @@
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From 13da22a18b2c13b8676c69e929ba51f2d5d188cf Mon Sep 17 00:00:00 2001
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From 851043846f589e718a69009a6b157b4ff5315471 Mon Sep 17 00:00:00 2001
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From: Leah Rowe <info@minifree.org>
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Date: Sun, 19 Feb 2023 18:21:43 +0000
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Subject: [PATCH 5/9] util/ifdtool: add --nuke flag (all 0xFF on region)
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Subject: [PATCH 6/8] util/ifdtool: add --nuke flag (all 0xFF on region)
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When this option is used, the region's contents are overwritten
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with all ones (0xFF).
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@ -1,7 +1,7 @@
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From bc1c834506a749eb2b235e51bb75b04b5b939ad5 Mon Sep 17 00:00:00 2001
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From fa6ac5b7f134b98a4f68f0f6b8bdeb6c7b6871ab Mon Sep 17 00:00:00 2001
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From: Nicholas Chin <nic.c3.14@gmail.com>
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Date: Fri, 12 May 2023 19:55:15 -0600
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Subject: [PATCH 6/9] Remove warning for coreboot images built without a
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Subject: [PATCH 7/8] Remove warning for coreboot images built without a
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payload
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I added this in upstream to prevent people from accidentally flashing
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@ -1,7 +1,7 @@
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From 1fa342e9462503c871bc5f4a0e4508ff8eac3e68 Mon Sep 17 00:00:00 2001
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From 636cb8ae8610cd99b637448add778c8e4f364f3e Mon Sep 17 00:00:00 2001
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From: Nicholas Chin <nic.c3.14@gmail.com>
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Date: Wed, 30 Oct 2024 20:55:25 -0600
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Subject: [PATCH 7/9] mb/dell/optiplex_780: Add USFF variant
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Subject: [PATCH 8/8] mb/dell/optiplex_780: Add USFF variant
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Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103
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Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
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@ -1,27 +0,0 @@
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From 4bd27d11c2ccd65a3b2a2e465aab9922e8aee31a Mon Sep 17 00:00:00 2001
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From: Leah Rowe <info@minifree.org>
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Date: Sun, 1 Dec 2024 07:16:20 +0000
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Subject: [PATCH 9/9] lenovo/t480: Add MAINBOARD_USES_IFD_GBE_REGION
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This board does use a GbE region, so support it in menuconfig.
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Signed-off-by: Leah Rowe <info@minifree.org>
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---
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src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
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index 13d71670e3..a3593e3785 100644
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--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
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+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
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@@ -15,6 +15,7 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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select MAINBOARD_HAS_LIBGFXINIT
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select MEMORY_MAPPED_TPM
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select MAINBOARD_HAS_TPM2
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+ select MAINBOARD_USES_IFD_GBE_REGION
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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--
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2.39.5
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@ -1,49 +0,0 @@
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From c865010771f413d532713319b7b01e9da9dbf495 Mon Sep 17 00:00:00 2001
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From: Leah Rowe <info@minifree.org>
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Date: Mon, 2 Dec 2024 03:12:52 +0000
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Subject: [PATCH 1/1] add vbt file for thinkpad t480s
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Signed-off-by: Leah Rowe <info@minifree.org>
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---
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.../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes
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1 file changed, 0 insertions(+), 0 deletions(-)
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create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt
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new file mode 100644
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index 0000000000000000000000000000000000000000..47732e37d5b2bad4e674fd10eafa605d26f97840
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GIT binary patch
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literal 4106
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zcmeHJUu+a*5TCu>yW9JAmoD2P<t%lC2CfC#y%tU^HSGOq>9tqx`iFWXCLD09R<E?S
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zMT)`nNScT-%9*GEA8a2?G`v`!jPV6yVlcd5OnC6Y;F}U&jJz1db9VRID@E)DLk#NN
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z&9^i2&Hiq_`R2ZF8ipf7IM{nI5$^585@kULrrx0OPKv~ngNI__q41$dA{p()ui+v1
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zw(9rm09lUPAP4nOTm0CRnF|aw5^SQSH<G}<u_Gfnvn6IuK0h@!j;UxI!$*&rIdkIh
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zl$piB;eBDWa1|CgK9bAg{^O%Z%!ziiz{neeJDb~fBI?1GV5p^44?a$ETl=n1d+;%Z
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z1CQUC@^&oxtbG2HGk&WA9=_qa;$?8fdy_j;eY+H3ciR5U?|$2?oT;mPoV=Dx&CwUf
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zZf4pp#`ZEanRbG)(+odg+NX?t!SF|>{mPhI!flfFgv9nqI4Wr~5_?s`k0kALiCvcP
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zLM);f=tWDCr``UF5T>!;PYu^H1g>EBP8A}2*fM>s-@nC3pDV|}6+CtfhG(II7`pcw
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z`jLfJ!?;*R@Bp=Nw2EPOC7FEs(cugIP_K6tN_$~tvS8nx6iOv|IMrO3&-m*N9ZP#b
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znG^~>I|l1cUVSeD9r^k3h0TP}WWD9=MZxY<<azgO1@-W5<NTHW*-d)t{Q4yX9_+?a
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zHawLe=uO6@%xqS#?JxafX%#$`BhkIqq>Z3B2yU!k71#YRpThOJtVheMDA50rV#s@U
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z+nKbA{O(olYR}icuzQD*-cjBQ9;%!eMDVP>7mWsF@=%>o)wSgq=n%DHNOYwRr4Ao6
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zbNdgEn*RdDS>Rud+fIY0N8JkP3q6;>8o%R(CE2n3?Xg%qP+U%~6|{XFyxv7Y#;J2Z
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XK$lk*wsY^m4}9|iz?mg_AjCfat$CyH
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literal 0
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HcmV?d00001
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--
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2.39.5
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@ -1,30 +0,0 @@
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From 44d0703b61156a19c6cbfb5cfe3f5d58e328daae Mon Sep 17 00:00:00 2001
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From: Leah Rowe <info@minifree.org>
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Date: Mon, 2 Dec 2024 11:16:43 +0000
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Subject: [PATCH 1/1] Disable m2 hotplug in lenovo t480s devicetree
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This fixes a bug where nvme disappears and gets renamed on
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s3 resume.
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Thanks go to Mate Kukri who suggested this.
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Signed-off-by: Leah Rowe <info@minifree.org>
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---
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.../lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb | 1 -
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1 file changed, 1 deletion(-)
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
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index 2cac8c4a75..9129d3a1b8 100644
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--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
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+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
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@@ -115,7 +115,6 @@ chip soc/intel/skylake
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register "PcieRpClkSrcNumber[8]" = "5"
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register "PcieRpAdvancedErrorReporting[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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- register "PcieRpHotPlug[8]" = "1"
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end
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end
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end
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--
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2.39.5
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Loading…
Reference in New Issue