remove util/autoport
upstream has merged all of the changes that it contained, so we don't need this anymore. we'll have the newer upstream changes on the next general revision updates for coreboot, within config/coreboot/ Signed-off-by: Leah Rowe <leah@libreboot.org>audit6
Leah Rowe
parent
373c2eb23d
commit
f367afabc1
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@ -118,6 +118,7 @@ configure_project()
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{
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eval `setvars "" xarch xlang build_depend autoconfargs xtree postmake \
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tree_depend makeargs btype mkhelper bootstrapargs premake release`
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[ -f "$1/target.cfg" ] || btype="auto"
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[ -f "$datadir/mkhelper.cfg" ] && eval `setcfg "$datadir/mkhelper.cfg"`
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@ -143,6 +144,7 @@ configure_project()
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[ "$mode" = "fetch" ] || x_ ./update trees -f "$project" $target
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[ "$mode" = "fetch" ] || return 0
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[ -f "CHANGELOG" ] && return 1; fetch_${cmd#build_}; return 1
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}
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@ -1,67 +0,0 @@
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package main
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import (
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"fmt"
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"sort"
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)
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type azalia struct {
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}
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func (i azalia) Scan(ctx Context, addr PCIDevData) {
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az := Create(ctx, "hda_verb.c")
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defer az.Close()
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Add_gpl(az)
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az.WriteString(
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`#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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`)
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for _, codec := range ctx.InfoSource.GetAzaliaCodecs() {
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fmt.Fprintf(az, "\t0x%08x,\t/* Codec Vendor / Device ID: %s */\n",
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codec.VendorID, codec.Name)
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fmt.Fprintf(az, "\t0x%08x,\t/* Subsystem ID */\n",
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codec.SubsystemID)
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fmt.Fprintf(az, "\t%d,\t\t/* Number of 4 dword sets */\n",
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len(codec.PinConfig)+1)
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fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(%d, 0x%08x),\n",
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codec.CodecNo, codec.SubsystemID)
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keys := []int{}
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for nid, _ := range codec.PinConfig {
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keys = append(keys, nid)
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}
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sort.Ints(keys)
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for _, nid := range keys {
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fmt.Fprintf(az, "\tAZALIA_PIN_CFG(%d, 0x%02x, 0x%08x),\n",
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codec.CodecNo, nid, codec.PinConfig[nid])
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}
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az.WriteString("\n");
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}
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az.WriteString(
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`};
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const u32 pc_beep_verbs[0] = {};
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AZALIA_ARRAY_SIZES;
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`)
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PutPCIDev(addr, "")
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}
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func init() {
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/* I82801GX/I945 */
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RegisterPCI(0x8086, 0x27d8, azalia{})
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/* BD82X6X/sandybridge */
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RegisterPCI(0x8086, 0x1c20, azalia{})
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/* C216/ivybridge */
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RegisterPCI(0x8086, 0x1e20, azalia{})
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/* Lynx Point */
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RegisterPCI(0x8086, 0x8c20, azalia{})
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RegisterPCI(0x8086, 0x9c20, azalia{})
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}
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@ -1,337 +0,0 @@
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package main
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import "fmt"
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type bd82x6x struct {
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variant string
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node *DevTreeNode
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}
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func IsPCIeHotplug(ctx Context, port int) bool {
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portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}]
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if !ok {
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return false
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}
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return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0
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}
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func ich9GetFlashSize(ctx Context) {
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inteltool := ctx.InfoSource.GetInteltool()
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switch (inteltool.RCBA[0x3410] >> 10) & 3 {
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/* SPI. All boards I've seen with sandy/ivy use SPI. */
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case 3:
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ROMProtocol = "SPI"
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highflkb := uint32(0)
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for reg := uint16(0); reg < 5; reg++ {
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fl := (inteltool.RCBA[0x3854+4*reg] >> 16) & 0x1fff
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flkb := (fl + 1) << 2
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if flkb > highflkb {
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highflkb = flkb
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}
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}
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ROMSizeKB = int(highflkb)
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/* Shared with ME. Flashrom is unable to handle it. */
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FlashROMSupport = "n"
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}
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}
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func (b bd82x6x) GetGPIOHeader() string {
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return "southbridge/intel/bd82x6x/pch.h"
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}
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func (b bd82x6x) EnableGPE(in int) {
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b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2"
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}
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func (b bd82x6x) EncodeGPE(in int) int {
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return in + 0x10
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}
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func (b bd82x6x) DecodeGPE(in int) int {
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return in - 0x10
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}
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func (b bd82x6x) NeedRouteGPIOManually() {
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b.node.Comment += ", FIXME: set gpiX_routing for EC support"
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}
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func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
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SouthBridge = &b
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inteltool := ctx.InfoSource.GetInteltool()
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GPIO(ctx, inteltool)
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KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true
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KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
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KconfigInt["USBDEBUG_HCD_INDEX"] = 2
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KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
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dmi := ctx.InfoSource.GetDMI()
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if dmi.Vendor == "LENOVO" {
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KconfigInt["DRAM_RESET_GATE_GPIO"] = 10
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} else {
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KconfigInt["DRAM_RESET_GATE_GPIO"] = 60
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}
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KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this"
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ich9GetFlashSize(ctx)
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DSDTDefines = append(DSDTDefines,
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DSDTDefine{
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Key: "BRIGHTNESS_UP",
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Value: "\\_SB.PCI0.GFX0.INCB",
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},
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DSDTDefine{
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Key: "BRIGHTNESS_DOWN",
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Value: "\\_SB.PCI0.GFX0.DECB",
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})
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/* SPI init */
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MainboardIncludes = append(MainboardIncludes, "southbridge/intel/bd82x6x/pch.h")
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FADT := ctx.InfoSource.GetACPI()["FACP"]
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pcieHotplugMap := "{ "
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for port := 0; port < 7; port++ {
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if IsPCIeHotplug(ctx, port) {
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pcieHotplugMap += "1, "
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} else {
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pcieHotplugMap += "0, "
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}
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}
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if IsPCIeHotplug(ctx, 7) {
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pcieHotplugMap += "1 }"
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} else {
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pcieHotplugMap += "0 }"
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}
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cur := DevTreeNode{
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Chip: "southbridge/intel/bd82x6x",
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Comment: "Intel Series 6 Cougar Point PCH",
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Registers: map[string]string{
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"sata_interface_speed_support": "0x3",
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"gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
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"gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
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"gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
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"gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
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"pcie_port_coalesce": "1",
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"pcie_hotplug_map": pcieHotplugMap,
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"sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
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"docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
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"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
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"spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)),
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},
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PCISlots: []PCISlot{
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PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, alias: "xhci", additionalComment: "USB 3.0 Controller"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, alias: "mei1", additionalComment: "Management Engine Interface 1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, alias: "mei2", additionalComment: "Management Engine Interface 2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, alias: "me_ide_r", additionalComment: "Management Engine IDE-R"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, alias: "me_kt", additionalComment: "Management Engine KT"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, alias: "gbe", additionalComment: "Intel Gigabit Ethernet"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "ehci2", additionalComment: "USB2 EHCI #2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, alias: "hda", additionalComment: "High Definition Audio"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, alias: "pcie_rp1", additionalComment: "PCIe Port #1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, alias: "pcie_rp2", additionalComment: "PCIe Port #2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, alias: "pcie_rp3", additionalComment: "PCIe Port #3"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, alias: "pcie_rp4", additionalComment: "PCIe Port #4"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, alias: "pcie_rp5", additionalComment: "PCIe Port #5"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, alias: "pcie_rp6", additionalComment: "PCIe Port #6"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, alias: "pcie_rp7", additionalComment: "PCIe Port #7"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, alias: "pcie_rp8", additionalComment: "PCIe Port #8"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, alias: "ehci1", additionalComment: "USB2 EHCI #1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, alias: "pci_bridge", additionalComment: "PCI bridge"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, alias: "lpc", additionalComment: "LPC bridge"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, alias: "sata1", additionalComment: "SATA Controller 1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, alias: "smbus", additionalComment: "SMBus"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, alias: "sata2", additionalComment: "SATA Controller 2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, alias: "thermal", additionalComment: "Thermal"},
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},
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}
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b.node = &cur
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xhciDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}]
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if ok {
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cur.Registers["xhci_switchable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xd4:0xd8])
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cur.Registers["superspeed_capable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xdc:0xe0])
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cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4])
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}
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PutPCIChip(addr, cur)
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PutPCIDevParent(addr, "", "lpc")
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/common/acpi/platform.asl",
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})
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl",
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})
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/common/acpi/sleepstates.asl",
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})
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DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
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File: "southbridge/intel/bd82x6x/acpi/pch.asl",
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})
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AddBootBlockFile("early_init.c", "")
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AddROMStageFile("early_init.c", "")
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sb := Create(ctx, "early_init.c")
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defer sb.Close()
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Add_gpl(sb)
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sb.WriteString(`
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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`)
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sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n")
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currentMap := map[uint32]int{
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0x20000153: 0,
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0x20000f57: 1,
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0x2000055b: 2,
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0x20000f51: 3,
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0x2000094a: 4,
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0x2000035f: 5,
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0x20000f53: 6,
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0x20000357: 7,
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0x20000353: 8,
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}
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for port := uint(0); port < 14; port++ {
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var pinmask uint32
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OCPin := -1
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if port < 8 {
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pinmask = inteltool.RCBA[0x35a0]
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} else {
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pinmask = inteltool.RCBA[0x35a4]
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}
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for pin := uint(0); pin < 4; pin++ {
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if ((pinmask >> ((port % 8) + 8*pin)) & 1) != 0 {
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OCPin = int(pin)
|
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if port >= 8 {
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OCPin += 4
|
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}
|
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}
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}
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current, ok := currentMap[inteltool.RCBA[uint16(0x3500+4*port)]]
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comment := ""
|
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if !ok {
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comment = fmt.Sprintf("// FIXME: Unknown current: RCBA(0x%x)=0x%x", 0x3500+4*port, uint16(0x3500+4*port))
|
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}
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fmt.Fprintf(sb, "\t{ %d, %d, %d }, %s\n",
|
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((inteltool.RCBA[0x359c]>>port)&1)^1,
|
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current,
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OCPin,
|
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comment)
|
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}
|
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sb.WriteString("};\n")
|
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|
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guessedMap := GuessSPDMap(ctx)
|
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|
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sb.WriteString(`
|
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void bootblock_mainboard_early_init(void)
|
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{
|
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`)
|
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RestorePCI16Simple(sb, addr, 0x82)
|
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|
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RestorePCI16Simple(sb, addr, 0x80)
|
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|
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sb.WriteString(`}
|
||||
|
||||
/* FIXME: Put proper SPD map here. */
|
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
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{
|
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`)
|
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for i, spd := range guessedMap {
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fmt.Fprintf(sb, "\tread_spd(&spd[%d], 0x%02x, id_only);\n", i, spd)
|
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}
|
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sb.WriteString("}\n")
|
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|
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gnvs := Create(ctx, "acpi_tables.c")
|
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defer gnvs.Close()
|
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|
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Add_gpl(gnvs)
|
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gnvs.WriteString(`#include <acpi/acpi_gnvs.h>
|
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#include <soc/nvs.h>
|
||||
|
||||
/* FIXME: check this function. */
|
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void mainboard_fill_gnvs(struct global_nvs *gnvs)
|
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{
|
||||
/* The lid is open by default. */
|
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gnvs->lids = 1;
|
||||
|
||||
/* Temperature at which OS will shutdown */
|
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gnvs->tcrt = 100;
|
||||
/* Temperature at which OS will throttle CPU */
|
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gnvs->tpsv = 90;
|
||||
}
|
||||
`)
|
||||
}
|
||||
|
||||
func init() {
|
||||
/* BD82X6X LPC */
|
||||
for id := 0x1c40; id <= 0x1c5f; id++ {
|
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RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "BD82X6X"})
|
||||
}
|
||||
|
||||
/* C216 LPC */
|
||||
for id := 0x1e41; id <= 0x1e5f; id++ {
|
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RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "C216"})
|
||||
}
|
||||
|
||||
/* PCIe bridge */
|
||||
for _, id := range []uint16{
|
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0x1c10, 0x1c12, 0x1c14, 0x1c16,
|
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0x1c18, 0x1c1a, 0x1c1c, 0x1c1e,
|
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0x1e10, 0x1e12, 0x1e14, 0x1e16,
|
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0x1e18, 0x1e1a, 0x1e1c, 0x1e1e,
|
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0x1e25, 0x244e, 0x2448,
|
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} {
|
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RegisterPCI(0x8086, id, GenericPCI{})
|
||||
}
|
||||
|
||||
/* SMBus controller */
|
||||
RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"})
|
||||
RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"})
|
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|
||||
/* SATA */
|
||||
for _, id := range []uint16{
|
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0x1c00, 0x1c01, 0x1c02, 0x1c03,
|
||||
0x1e00, 0x1e01, 0x1e02, 0x1e03,
|
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} {
|
||||
RegisterPCI(0x8086, id, GenericPCI{})
|
||||
}
|
||||
|
||||
/* EHCI */
|
||||
for _, id := range []uint16{
|
||||
0x1c26, 0x1c2d, 0x1e26, 0x1e2d,
|
||||
} {
|
||||
RegisterPCI(0x8086, id, GenericPCI{})
|
||||
}
|
||||
|
||||
/* XHCI */
|
||||
RegisterPCI(0x8086, 0x1e31, GenericPCI{})
|
||||
|
||||
/* ME and children */
|
||||
for _, id := range []uint16{
|
||||
0x1c3a, 0x1c3b, 0x1c3c, 0x1c3d,
|
||||
0x1e3a, 0x1e3b, 0x1e3c, 0x1e3d,
|
||||
} {
|
||||
RegisterPCI(0x8086, id, GenericPCI{})
|
||||
}
|
||||
|
||||
/* Ethernet */
|
||||
RegisterPCI(0x8086, 0x1502, GenericPCI{})
|
||||
RegisterPCI(0x8086, 0x1503, GenericPCI{})
|
||||
|
||||
}
|
||||
|
|
@ -1 +0,0 @@
|
|||
Automated porting coreboot to Sandy Bridge/Ivy Bridge platforms `Go`
|
||||
|
|
@ -1,91 +0,0 @@
|
|||
package main
|
||||
|
||||
import "fmt"
|
||||
|
||||
func FIXMEEC(ctx Context) {
|
||||
ap := Create(ctx, "acpi/platform.asl")
|
||||
defer ap.Close()
|
||||
|
||||
hasKeyboard := ctx.InfoSource.HasPS2()
|
||||
|
||||
sbGPE := GuessECGPE(ctx)
|
||||
var GPEUnsure bool
|
||||
if sbGPE < 0 {
|
||||
sbGPE = SouthBridge.EncodeGPE(1)
|
||||
GPEUnsure = true
|
||||
SouthBridge.NeedRouteGPIOManually()
|
||||
} else {
|
||||
GPEUnsure = false
|
||||
SouthBridge.EnableGPE(SouthBridge.DecodeGPE(sbGPE))
|
||||
}
|
||||
|
||||
Add_gpl(ap)
|
||||
ap.WriteString(
|
||||
`Method(_WAK, 1)
|
||||
{
|
||||
/* FIXME: EC support */
|
||||
Return(Package() {0, 0})
|
||||
}
|
||||
|
||||
Method(_PTS,1)
|
||||
{
|
||||
/* FIXME: EC support */
|
||||
}
|
||||
`)
|
||||
|
||||
ecs := ctx.InfoSource.GetEC()
|
||||
MainboardIncludes = append(MainboardIncludes, "ec/acpi/ec.h")
|
||||
MainboardIncludes = append(MainboardIncludes, "console/console.h")
|
||||
|
||||
MainboardInit +=
|
||||
` /* FIXME: trim this down or remove if necessary */
|
||||
{
|
||||
int i;
|
||||
const u8 dmp[256] = {`
|
||||
for i := 0; i < 0x100; i++ {
|
||||
if (i & 0xf) == 0 {
|
||||
MainboardInit += fmt.Sprintf("\n\t\t\t/* %02x */ ", i)
|
||||
}
|
||||
MainboardInit += fmt.Sprintf("0x%02x,", ecs[i])
|
||||
if (i & 0xf) != 0xf {
|
||||
MainboardInit += " "
|
||||
}
|
||||
}
|
||||
MainboardInit += "\n\t\t};\n"
|
||||
MainboardInit += `
|
||||
printk(BIOS_DEBUG, "Replaying EC dump ...");
|
||||
for (i = 0; i < 256; i++)
|
||||
ec_write (i, dmp[i]);
|
||||
printk(BIOS_DEBUG, "done\n");
|
||||
}
|
||||
`
|
||||
|
||||
KconfigBool["EC_ACPI"] = true
|
||||
si := Create(ctx, "acpi/superio.asl")
|
||||
defer si.Close()
|
||||
|
||||
if hasKeyboard {
|
||||
Add_gpl(si)
|
||||
si.WriteString("#include <drivers/pc80/pc/ps2_controller.asl>\n")
|
||||
MainboardInit += fmt.Sprintf("\tpc_keyboard_init(NO_AUX_DEVICE);\n")
|
||||
MainboardIncludes = append(MainboardIncludes, "pc80/keyboard.h")
|
||||
}
|
||||
|
||||
ec := Create(ctx, "acpi/ec.asl")
|
||||
defer ec.Close()
|
||||
|
||||
Add_gpl(ec)
|
||||
ec.WriteString(`Device(EC)
|
||||
{
|
||||
Name (_HID, EISAID("PNP0C09"))
|
||||
Name (_UID, 0)
|
||||
`)
|
||||
if GPEUnsure {
|
||||
ec.WriteString("\t/* FIXME: Set GPE */\n")
|
||||
ec.WriteString("\t/* Name (_GPE, ?) */\n")
|
||||
} else {
|
||||
fmt.Fprintf(ec, "\tName (_GPE, %d)\n", sbGPE)
|
||||
}
|
||||
ec.WriteString("/* FIXME: EC support */\n")
|
||||
ec.WriteString("}\n")
|
||||
}
|
||||
|
|
@ -1,245 +0,0 @@
|
|||
package main
|
||||
|
||||
import "fmt"
|
||||
|
||||
func LenovoEC(ctx Context) {
|
||||
ap := Create(ctx, "acpi/platform.asl")
|
||||
defer ap.Close()
|
||||
|
||||
wakeGPE := 13
|
||||
|
||||
sbGPE := GuessECGPE(ctx)
|
||||
var GPE int
|
||||
var GPEUnsure bool
|
||||
if sbGPE < 0 {
|
||||
sbGPE = SouthBridge.EncodeGPE(1)
|
||||
GPE = 1
|
||||
GPEUnsure = true
|
||||
SouthBridge.NeedRouteGPIOManually()
|
||||
} else {
|
||||
GPE = SouthBridge.DecodeGPE(sbGPE)
|
||||
GPEUnsure = false
|
||||
}
|
||||
|
||||
SouthBridge.EnableGPE(wakeGPE)
|
||||
SouthBridge.EnableGPE(GPE)
|
||||
|
||||
GPEDefine := DSDTDefine{
|
||||
Key: "THINKPAD_EC_GPE",
|
||||
}
|
||||
|
||||
GPEDefine.Value = fmt.Sprintf("%d", sbGPE)
|
||||
if GPEUnsure {
|
||||
GPEDefine.Comment = "FIXME: Check this"
|
||||
}
|
||||
|
||||
DSDTDefines = append(DSDTDefines,
|
||||
DSDTDefine{
|
||||
Key: "EC_LENOVO_H8_ME_WORKAROUND",
|
||||
Value: "1",
|
||||
}, GPEDefine)
|
||||
|
||||
Add_gpl(ap)
|
||||
ap.WriteString(
|
||||
`Method(_WAK, 1)
|
||||
{
|
||||
/* ME may not be up yet. */
|
||||
Store(0, \_TZ.MEB1)
|
||||
Store(0, \_TZ.MEB2)
|
||||
Return(Package() {0, 0})
|
||||
}
|
||||
|
||||
Method(_PTS,1)
|
||||
{
|
||||
\_SB.PCI0.LPCB.EC.RADI(0)
|
||||
}
|
||||
`)
|
||||
|
||||
si := Create(ctx, "acpi/superio.asl")
|
||||
defer si.Close()
|
||||
|
||||
Add_gpl(si)
|
||||
si.WriteString("#include <drivers/pc80/pc/ps2_controller.asl>\n")
|
||||
|
||||
/* FIXME:XX Move this to ec/lenovo. */
|
||||
smi := Create(ctx, "smihandler.c")
|
||||
defer smi.Close()
|
||||
|
||||
AddSMMFile("smihandler.c", "")
|
||||
|
||||
Add_gpl(smi)
|
||||
smi.WriteString(
|
||||
`#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <ec/acpi/ec.h>
|
||||
#include <ec/lenovo/h8/h8.h>
|
||||
#include <delay.h>
|
||||
#include <` + SouthBridge.GetGPIOHeader() + ">\n\n")
|
||||
|
||||
if GPEUnsure {
|
||||
smi.WriteString("/* FIXME: check this */\n")
|
||||
}
|
||||
fmt.Fprintf(smi, "#define GPE_EC_SCI %d\n", GPE)
|
||||
|
||||
smi.WriteString("/* FIXME: check this */\n")
|
||||
fmt.Fprintf(smi, "#define GPE_EC_WAKE %d\n", wakeGPE)
|
||||
|
||||
smi.WriteString(`
|
||||
static void mainboard_smi_handle_ec_sci(void)
|
||||
{
|
||||
u8 status = inb(EC_SC);
|
||||
u8 event;
|
||||
|
||||
if (!(status & EC_SCI_EVT))
|
||||
return;
|
||||
|
||||
event = ec_query();
|
||||
printk(BIOS_DEBUG, "EC event %#02x\n", event);
|
||||
}
|
||||
|
||||
void mainboard_smi_gpi(u32 gpi_sts)
|
||||
{
|
||||
if (gpi_sts & (1 << GPE_EC_SCI))
|
||||
mainboard_smi_handle_ec_sci();
|
||||
}
|
||||
|
||||
int mainboard_smi_apmc(u8 data)
|
||||
{
|
||||
switch (data) {
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
/* use 0x1600/0x1604 to prevent races with userspace */
|
||||
ec_set_ports(0x1604, 0x1600);
|
||||
/* route EC_SCI to SCI */
|
||||
gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
|
||||
/* discard all events, and enable attention */
|
||||
ec_write(0x80, 0x01);
|
||||
break;
|
||||
case APM_CNT_ACPI_DISABLE:
|
||||
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
|
||||
provide a EC query function */
|
||||
ec_set_ports(0x66, 0x62);
|
||||
/* route EC_SCI to SMI */
|
||||
gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
|
||||
/* discard all events, and enable attention */
|
||||
ec_write(0x80, 0x01);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
if (slp_typ == 3) {
|
||||
u8 ec_wake = ec_read(0x32);
|
||||
/* If EC wake events are enabled, enable wake on EC WAKE GPE. */
|
||||
if (ec_wake & 0x14) {
|
||||
/* Redirect EC WAKE GPE to SCI. */
|
||||
gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
|
||||
}
|
||||
}
|
||||
}
|
||||
`)
|
||||
|
||||
ec := Create(ctx, "acpi/ec.asl")
|
||||
defer ec.Close()
|
||||
|
||||
Add_gpl(ec)
|
||||
ec.WriteString("#include <ec/lenovo/h8/acpi/ec.asl>\n")
|
||||
|
||||
KconfigBool["EC_LENOVO_PMH7"] = true
|
||||
KconfigBool["EC_LENOVO_H8"] = true
|
||||
|
||||
pmh := DevTreeNode{
|
||||
Chip: "ec/lenovo/pmh7",
|
||||
Registers: map[string]string{
|
||||
"backlight_enable": "true",
|
||||
"dock_event_enable": "true",
|
||||
},
|
||||
Children: []DevTreeNode{
|
||||
DevTreeNode{
|
||||
Chip: "pnp",
|
||||
Comment: "dummy",
|
||||
Dev: 0xff,
|
||||
Func: 1,
|
||||
},
|
||||
},
|
||||
}
|
||||
PutChip("lpc", pmh)
|
||||
|
||||
ecs := ctx.InfoSource.GetEC()
|
||||
h8 := DevTreeNode{
|
||||
Chip: "ec/lenovo/h8",
|
||||
Children: []DevTreeNode{
|
||||
DevTreeNode{
|
||||
Chip: "pnp",
|
||||
Comment: "dummy",
|
||||
Dev: 0xff,
|
||||
Func: 2,
|
||||
IOs: map[uint16]uint16{
|
||||
0x60: 0x62,
|
||||
0x62: 0x66,
|
||||
0x64: 0x1600,
|
||||
0x66: 0x1604,
|
||||
},
|
||||
},
|
||||
},
|
||||
Comment: "FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb",
|
||||
Registers: map[string]string{
|
||||
"config0": FormatHex8(ecs[0]),
|
||||
"config1": FormatHex8(ecs[1]),
|
||||
"config2": FormatHex8(ecs[2]),
|
||||
"config3": FormatHex8(ecs[3]),
|
||||
"beepmask0": FormatHex8(ecs[4]),
|
||||
"beepmask1": FormatHex8(ecs[5]),
|
||||
},
|
||||
}
|
||||
for i := 0; i < 0x10; i++ {
|
||||
if ecs[0x10+i] != 0 {
|
||||
h8.Registers[fmt.Sprintf("event%x_enable", i)] = FormatHex8(ecs[0x10+i])
|
||||
}
|
||||
}
|
||||
PutChip("lpc", h8)
|
||||
|
||||
eeprom := DevTreeNode{
|
||||
Chip: "drivers/i2c/at24rf08c",
|
||||
Comment: "eeprom, 8 virtual devices, same chip",
|
||||
Children: []DevTreeNode{
|
||||
DevTreeNode{
|
||||
Chip: "i2c",
|
||||
Dev: 0x54,
|
||||
},
|
||||
DevTreeNode{
|
||||
Chip: "i2c",
|
||||
Dev: 0x55,
|
||||
},
|
||||
DevTreeNode{
|
||||
Chip: "i2c",
|
||||
Dev: 0x56,
|
||||
},
|
||||
DevTreeNode{
|
||||
Chip: "i2c",
|
||||
Dev: 0x57,
|
||||
},
|
||||
DevTreeNode{
|
||||
Chip: "i2c",
|
||||
Dev: 0x5c,
|
||||
},
|
||||
DevTreeNode{
|
||||
Chip: "i2c",
|
||||
Dev: 0x5d,
|
||||
},
|
||||
DevTreeNode{
|
||||
Chip: "i2c",
|
||||
Dev: 0x5e,
|
||||
},
|
||||
DevTreeNode{
|
||||
Chip: "i2c",
|
||||
Dev: 0x5f,
|
||||
},
|
||||
},
|
||||
}
|
||||
PutChip("smbus", eeprom)
|
||||
}
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
package main
|
||||
|
||||
func NoEC(ctx Context) {
|
||||
ap := Create(ctx, "acpi/platform.asl")
|
||||
defer ap.Close()
|
||||
|
||||
Add_gpl(ap)
|
||||
ap.WriteString(
|
||||
`Method(_WAK, 1)
|
||||
{
|
||||
Return(Package() {0, 0})
|
||||
}
|
||||
|
||||
Method(_PTS, 1)
|
||||
{
|
||||
}
|
||||
`)
|
||||
|
||||
si := Create(ctx, "acpi/superio.asl")
|
||||
defer si.Close()
|
||||
|
||||
ec := Create(ctx, "acpi/ec.asl")
|
||||
defer ec.Close()
|
||||
}
|
||||
|
|
@ -1 +0,0 @@
|
|||
module autoport
|
||||
|
|
@ -1,113 +0,0 @@
|
|||
/* code to generate common GPIO code for Intel 6/7/8 Series Chipset */
|
||||
|
||||
package main
|
||||
|
||||
import (
|
||||
"fmt"
|
||||
"os"
|
||||
)
|
||||
|
||||
func writeGPIOSet(ctx Context, sb *os.File,
|
||||
val uint32, set uint, partno int, constraint uint32) {
|
||||
|
||||
max := uint(32)
|
||||
if set == 3 {
|
||||
max = 12
|
||||
}
|
||||
|
||||
bits := [6][2]string{
|
||||
{"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
|
||||
{"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
|
||||
{"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
|
||||
{"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
|
||||
{"GPIO_NO_INVERT", "GPIO_INVERT"},
|
||||
{"GPIO_NO_BLINK", "GPIO_BLINK"},
|
||||
}
|
||||
|
||||
for i := uint(0); i < max; i++ {
|
||||
if (constraint>>i)&1 == 1 {
|
||||
fmt.Fprintf(sb, " .gpio%d = %s,\n",
|
||||
(set-1)*32+i,
|
||||
bits[partno][(val>>i)&1])
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
func GPIO(ctx Context, inteltool InteltoolData) {
|
||||
var constraint uint32
|
||||
gpio := Create(ctx, "gpio.c")
|
||||
defer gpio.Close()
|
||||
|
||||
AddBootBlockFile("gpio.c", "")
|
||||
AddROMStageFile("gpio.c", "")
|
||||
|
||||
Add_gpl(gpio)
|
||||
gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n")
|
||||
|
||||
addresses := [3][6]int{
|
||||
{0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
|
||||
{0x30, 0x34, 0x38, 0x64, -1, -1},
|
||||
{0x40, 0x44, 0x48, 0x68, -1, -1},
|
||||
}
|
||||
|
||||
for set := 1; set <= 3; set++ {
|
||||
for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
|
||||
addr := addresses[set-1][partno]
|
||||
if addr < 0 {
|
||||
continue
|
||||
}
|
||||
fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
|
||||
set, set, part)
|
||||
|
||||
constraint = 0xffffffff
|
||||
switch part {
|
||||
case "direction":
|
||||
/* Ignored on native mode */
|
||||
constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
|
||||
case "level":
|
||||
/* Level doesn't matter for input */
|
||||
constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
|
||||
constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
|
||||
case "reset":
|
||||
/* Only show reset */
|
||||
constraint = inteltool.GPIO[uint16(addresses[set-1][3])]
|
||||
case "invert":
|
||||
/* Only on input and only show inverted GPIO */
|
||||
constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
|
||||
constraint &= inteltool.GPIO[uint16(addresses[set-1][1])]
|
||||
constraint &= inteltool.GPIO[uint16(addresses[set-1][4])]
|
||||
case "blink":
|
||||
/* Only on output and only show blinking GPIO */
|
||||
constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
|
||||
constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
|
||||
constraint &= inteltool.GPIO[uint16(addresses[set-1][5])]
|
||||
}
|
||||
writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint)
|
||||
gpio.WriteString("};\n\n")
|
||||
}
|
||||
}
|
||||
|
||||
gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
`)
|
||||
}
|
||||
|
|
@ -1,139 +0,0 @@
|
|||
package main
|
||||
|
||||
import "fmt"
|
||||
|
||||
type haswellmc struct {
|
||||
variant string
|
||||
}
|
||||
|
||||
func divceil(a uint32, b uint32) uint32 {
|
||||
return (a + b - 1) / b
|
||||
}
|
||||
|
||||
func getPanelCfg(inteltool InteltoolData, isULT bool) string {
|
||||
var refclk uint32
|
||||
var pwm_hz uint32
|
||||
|
||||
if isULT {
|
||||
refclk = 24000000
|
||||
} else {
|
||||
refclk = 135000000
|
||||
}
|
||||
if (inteltool.IGD[0xc8254] >> 16) != 0 {
|
||||
pwm_hz = refclk / 128 / (inteltool.IGD[0xc8254] >> 16)
|
||||
} else {
|
||||
pwm_hz = 0
|
||||
}
|
||||
|
||||
gpu_panel_power_up_delay := (inteltool.IGD[0xc7208] >> 16) & 0x1fff
|
||||
gpu_panel_power_backlight_on_delay := inteltool.IGD[0xc7208] & 0x1fff
|
||||
gpu_panel_power_down_delay := (inteltool.IGD[0xc720c] >> 16) & 0x1fff
|
||||
gpu_panel_power_backlight_off_delay := inteltool.IGD[0xc720c] & 0x1fff
|
||||
gpu_panel_power_cycle_delay := inteltool.IGD[0xc7210] & 0x1f
|
||||
|
||||
return fmt.Sprintf(`{
|
||||
.up_delay_ms = %3d,
|
||||
.down_delay_ms = %3d,
|
||||
.cycle_delay_ms = %3d,
|
||||
.backlight_on_delay_ms = %3d,
|
||||
.backlight_off_delay_ms = %3d,
|
||||
.backlight_pwm_hz = %3d,
|
||||
}`,
|
||||
divceil(gpu_panel_power_up_delay, 10),
|
||||
divceil(gpu_panel_power_down_delay, 10),
|
||||
(gpu_panel_power_cycle_delay-1)*100,
|
||||
divceil(gpu_panel_power_backlight_on_delay, 10),
|
||||
divceil(gpu_panel_power_backlight_off_delay, 10),
|
||||
pwm_hz)
|
||||
}
|
||||
|
||||
func (i haswellmc) Scan(ctx Context, addr PCIDevData) {
|
||||
inteltool := ctx.InfoSource.GetInteltool()
|
||||
|
||||
isULT := (i.variant == "ULT")
|
||||
DevTree = DevTreeNode{
|
||||
Chip: "northbridge/intel/haswell",
|
||||
MissingParent: "northbridge",
|
||||
Comment: "FIXME: check ec_present, usb_xhci_on_resume, gfx",
|
||||
Registers: map[string]string{
|
||||
"gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
|
||||
"gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
|
||||
"gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
|
||||
"panel_cfg": getPanelCfg(inteltool, isULT),
|
||||
"gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0),
|
||||
"ec_present": "false",
|
||||
"usb_xhci_on_resume": "false",
|
||||
/* FIXME:XX hardcoded. */
|
||||
"gfx": "GMA_STATIC_DISPLAYS(0)",
|
||||
},
|
||||
Children: []DevTreeNode{
|
||||
{
|
||||
Chip: "cpu/intel/haswell",
|
||||
Children: []DevTreeNode{
|
||||
{
|
||||
Chip: "cpu_cluster",
|
||||
Dev: 0,
|
||||
Ops: "haswell_cpu_bus_ops",
|
||||
},
|
||||
},
|
||||
},
|
||||
|
||||
{
|
||||
Chip: "domain",
|
||||
Dev: 0,
|
||||
Ops: "haswell_pci_domain_ops",
|
||||
PCIController: true,
|
||||
ChildPCIBus: 0,
|
||||
PCISlots: []PCISlot{
|
||||
PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: i.variant},
|
||||
PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: !isULT, additionalComment: "PCIe Bridge for discrete graphics"},
|
||||
PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
|
||||
PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"},
|
||||
},
|
||||
},
|
||||
},
|
||||
}
|
||||
|
||||
if isULT {
|
||||
DevTree.Registers["dq_pins_interleaved"] = FormatBool(((inteltool.MCHBAR[0x2008] >> 10) & 1) == 0)
|
||||
}
|
||||
|
||||
PutPCIDev(addr, "Host bridge")
|
||||
|
||||
KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true
|
||||
KconfigBool["HAVE_ACPI_TABLES"] = true
|
||||
KconfigBool["HAVE_ACPI_RESUME"] = true
|
||||
|
||||
DSDTIncludes = append(DSDTIncludes, DSDTInclude{
|
||||
File: "cpu/intel/common/acpi/cpu.asl",
|
||||
})
|
||||
|
||||
DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
|
||||
File: "northbridge/intel/haswell/acpi/hostbridge.asl",
|
||||
}, DSDTInclude{
|
||||
File: "drivers/intel/gma/acpi/default_brightness_levels.asl",
|
||||
Comment: "FIXME: remove this if the board doesn't have backlight",
|
||||
})
|
||||
}
|
||||
|
||||
func init() {
|
||||
RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"})
|
||||
RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"})
|
||||
RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"})
|
||||
RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"})
|
||||
RegisterPCI(0x8086, 0x0d00, haswellmc{variant: "Crystal Well Desktop"})
|
||||
RegisterPCI(0x8086, 0x0d04, haswellmc{variant: "Crystal Well Mobile"})
|
||||
RegisterPCI(0x8086, 0x0d08, haswellmc{variant: "Crystal Well Server"})
|
||||
for _, id := range []uint16{
|
||||
0x0402, 0x0412, 0x0422, /* Desktop */
|
||||
0x0406, 0x0416, 0x0426, /* Mobile */
|
||||
0x040a, 0x041a, 0x042a, /* Server */
|
||||
0x0a06, 0x0a16, 0x0a26, /* ULT */
|
||||
0x0d16, 0x0d22, 0x0d26, 0x0d36, /* Mobile 4+3, GT3e */
|
||||
} {
|
||||
RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
|
||||
}
|
||||
/* CPU HD Audio */
|
||||
RegisterPCI(0x8086, 0x0a0c, GenericPCI{})
|
||||
RegisterPCI(0x8086, 0x0c0c, GenericPCI{})
|
||||
}
|
||||
|
|
@ -1,190 +0,0 @@
|
|||
package main
|
||||
|
||||
import (
|
||||
"errors"
|
||||
"fmt"
|
||||
"io"
|
||||
"io/ioutil"
|
||||
"log"
|
||||
"os"
|
||||
"os/exec"
|
||||
"strings"
|
||||
"bytes"
|
||||
)
|
||||
|
||||
func TryRunAndSave(output string, name string, arg []string) error {
|
||||
cmd := exec.Command(name, arg...)
|
||||
|
||||
f, err := os.Create(output)
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
|
||||
cmd.Stdout = f
|
||||
cmd.Stderr = f
|
||||
|
||||
err = cmd.Start()
|
||||
if err != nil {
|
||||
return err
|
||||
}
|
||||
cmd.Wait()
|
||||
return nil
|
||||
}
|
||||
|
||||
func RunAndSave(output string, name string, arg ...string) {
|
||||
err := TryRunAndSave(output, name, arg)
|
||||
if err == nil {
|
||||
return
|
||||
}
|
||||
idx := strings.LastIndex(name, "/")
|
||||
relname := name
|
||||
if idx >= 0 {
|
||||
relname = name[idx+1:]
|
||||
}
|
||||
relname = "./" + relname
|
||||
err = TryRunAndSave(output, relname, arg)
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
}
|
||||
|
||||
const MAXPROMPTRETRY = 3
|
||||
|
||||
func PromptUser(prompt string, opts []string) (match string, err error) {
|
||||
for i := 1; i < MAXPROMPTRETRY; i++ {
|
||||
fmt.Printf("%s. (%s) Default:%s\n", prompt,
|
||||
strings.Join(opts, "/"), opts[0])
|
||||
var usrInput string
|
||||
fmt.Scanln(&usrInput)
|
||||
|
||||
// Check for default entry
|
||||
if usrInput == "" {
|
||||
match = opts[0]
|
||||
return
|
||||
}
|
||||
|
||||
for _, opt := range opts {
|
||||
if opt == usrInput {
|
||||
match = opt
|
||||
return
|
||||
}
|
||||
}
|
||||
}
|
||||
err = errors.New("max retries exceeded")
|
||||
fmt.Fprintln(os.Stderr, "ERROR: max retries exceeded")
|
||||
return
|
||||
}
|
||||
|
||||
func MakeHDALogs(outDir string, cardName string) {
|
||||
SysDir := "/sys/class/sound/" + cardName + "/"
|
||||
files, _ := ioutil.ReadDir(SysDir)
|
||||
for _, f := range files {
|
||||
if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() {
|
||||
in, err := os.Open(SysDir + f.Name() + "/init_pin_configs")
|
||||
defer in.Close()
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1))
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
defer out.Close()
|
||||
io.Copy(out, in)
|
||||
}
|
||||
}
|
||||
|
||||
ProcDir := "/proc/asound/" + cardName + "/"
|
||||
files, _ = ioutil.ReadDir(ProcDir)
|
||||
for _, f := range files {
|
||||
if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() {
|
||||
in, err := os.Open(ProcDir + f.Name())
|
||||
defer in.Close()
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
out, err := os.Create(outDir + "/" + f.Name())
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
defer out.Close()
|
||||
io.Copy(out, in)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
func MakeLogs(outDir string) {
|
||||
os.MkdirAll(outDir, 0700)
|
||||
RunAndSave(outDir+"/lspci.log", "lspci", "-nnvvvxxxx")
|
||||
RunAndSave(outDir+"/dmidecode.log", "dmidecode")
|
||||
RunAndSave(outDir+"/acpidump.log", "acpidump")
|
||||
|
||||
inteltoolArgs := "-a"
|
||||
opt, err := PromptUser("WARNING: The following tool MAY cause your system to hang when it attempts "+
|
||||
"to probe for graphics registers. Having the graphics registers will help create a better port. "+
|
||||
"Should autoport probe these registers?",
|
||||
[]string{"y", "yes", "n", "no"})
|
||||
|
||||
// Continue even if there is an error
|
||||
|
||||
switch opt {
|
||||
case "y", "yes":
|
||||
inteltoolArgs += "f"
|
||||
}
|
||||
|
||||
RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", inteltoolArgs)
|
||||
RunAndSave(outDir+"/ectool.log", "../ectool/ectool", "-pd")
|
||||
RunAndSave(outDir+"/superiotool.log", "../superiotool/superiotool", "-ade")
|
||||
|
||||
SysSound := "/sys/class/sound/"
|
||||
card := ""
|
||||
cards, _ := ioutil.ReadDir(SysSound)
|
||||
for _, f := range cards {
|
||||
if strings.HasPrefix(f.Name(), "card") {
|
||||
cid, err := ioutil.ReadFile(SysSound + f.Name() + "/id")
|
||||
if err == nil && bytes.Equal(cid, []byte("PCH\n")) {
|
||||
fmt.Fprintln(os.Stderr, "PCH sound card is", f.Name())
|
||||
card = f.Name()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if card != "" {
|
||||
MakeHDALogs(outDir, card)
|
||||
} else {
|
||||
fmt.Fprintln(os.Stderr, "HDAudio not found on PCH.")
|
||||
}
|
||||
|
||||
for _, fname := range []string{"cpuinfo", "ioports"} {
|
||||
in, err := os.Open("/proc/" + fname)
|
||||
defer in.Close()
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
out, err := os.Create(outDir + "/" + fname + ".log")
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
defer out.Close()
|
||||
io.Copy(out, in)
|
||||
}
|
||||
|
||||
out, err := os.Create(outDir + "/input_bustypes.log")
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
defer out.Close()
|
||||
|
||||
ClassInputDir := "/sys/class/input/"
|
||||
files, _ := ioutil.ReadDir(ClassInputDir)
|
||||
for _, f := range files {
|
||||
if strings.HasPrefix(f.Name(), "input") && !f.Mode().IsRegular() { /* Allow both dirs and symlinks. */
|
||||
in, err := os.Open(ClassInputDir + f.Name() + "/id/bustype")
|
||||
defer in.Close()
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
io.Copy(out, in)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,417 +0,0 @@
|
|||
package main
|
||||
|
||||
import (
|
||||
"bufio"
|
||||
"flag"
|
||||
"fmt"
|
||||
"log"
|
||||
"os"
|
||||
"regexp"
|
||||
"strconv"
|
||||
"strings"
|
||||
)
|
||||
|
||||
type LogDevReader struct {
|
||||
InputDirectory string
|
||||
ACPITables map[string][]byte
|
||||
EC []byte
|
||||
}
|
||||
|
||||
func isXDigit(x uint8) bool {
|
||||
if x >= '0' && x <= '9' {
|
||||
return true
|
||||
}
|
||||
if x >= 'a' && x <= 'f' {
|
||||
return true
|
||||
}
|
||||
if x >= 'A' && x <= 'F' {
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
|
||||
type HexLine struct {
|
||||
length uint
|
||||
values [16]byte
|
||||
start uint
|
||||
}
|
||||
|
||||
func (l *LogDevReader) ReadHexLine(line string) (hex HexLine) {
|
||||
hex.start = 0
|
||||
line = strings.Trim(line, " ")
|
||||
fmt.Sscanf(line, "%x:", &hex.start)
|
||||
ll, _ := fmt.Sscanf(line, "%x: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x", &hex.start,
|
||||
&hex.values[0], &hex.values[1], &hex.values[2],
|
||||
&hex.values[3], &hex.values[4], &hex.values[5],
|
||||
&hex.values[6], &hex.values[7], &hex.values[8],
|
||||
&hex.values[9], &hex.values[10], &hex.values[11],
|
||||
&hex.values[12], &hex.values[13], &hex.values[14],
|
||||
&hex.values[15])
|
||||
hex.length = uint(ll - 1)
|
||||
return
|
||||
}
|
||||
|
||||
func (l *LogDevReader) AssignHexLine(inp string, target []byte) []byte {
|
||||
hex := l.ReadHexLine(inp)
|
||||
if hex.start+hex.length > uint(len(target)) {
|
||||
target = target[0 : hex.start+hex.length]
|
||||
}
|
||||
copy(target[hex.start:hex.start+hex.length], hex.values[0:hex.length])
|
||||
return target
|
||||
}
|
||||
|
||||
func (l *LogDevReader) GetEC() []byte {
|
||||
if l.EC != nil {
|
||||
return l.EC
|
||||
}
|
||||
l.EC = make([]byte, 0x100, 0x100)
|
||||
|
||||
file, err := os.Open(l.InputDirectory + "/ectool.log")
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
defer file.Close()
|
||||
|
||||
scanner := bufio.NewScanner(file)
|
||||
|
||||
for scanner.Scan() {
|
||||
line := scanner.Text()
|
||||
if len(line) > 7 && isXDigit(line[0]) && isXDigit(line[1]) && line[2] == ':' {
|
||||
l.EC = l.AssignHexLine(line, l.EC)
|
||||
}
|
||||
}
|
||||
|
||||
if err := scanner.Err(); err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
|
||||
return l.EC
|
||||
}
|
||||
|
||||
func (l *LogDevReader) GetACPI() (Tables map[string][]byte) {
|
||||
if l.ACPITables != nil {
|
||||
return l.ACPITables
|
||||
}
|
||||
l.ACPITables = Tables
|
||||
|
||||
file, err := os.Open(l.InputDirectory + "/acpidump.log")
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
defer file.Close()
|
||||
|
||||
scanner := bufio.NewScanner(file)
|
||||
|
||||
Tables = map[string][]byte{}
|
||||
|
||||
curTable := ""
|
||||
for scanner.Scan() {
|
||||
line := scanner.Text()
|
||||
/* Only supports ACPI tables up to 0x100000 in size, FIXME if needed */
|
||||
is_hexline, _ := regexp.MatchString(" *[0-9A-Fa-f]{4,5}: ", line)
|
||||
switch {
|
||||
case len(line) >= 6 && line[5] == '@':
|
||||
curTable = line[0:4]
|
||||
Tables[curTable] = make([]byte, 0, 0x100000)
|
||||
case is_hexline:
|
||||
Tables[curTable] = l.AssignHexLine(line, Tables[curTable])
|
||||
}
|
||||
}
|
||||
|
||||
if err := scanner.Err(); err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
func (l *LogDevReader) GetPCIList() (PCIList []PCIDevData) {
|
||||
file, err := os.Open(l.InputDirectory + "/lspci.log")
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
defer file.Close()
|
||||
|
||||
scanner := bufio.NewScanner(file)
|
||||
|
||||
PCIList = []PCIDevData{}
|
||||
|
||||
for scanner.Scan() {
|
||||
line := scanner.Text()
|
||||
switch {
|
||||
case !(len(line) < 7 || !isXDigit(line[0]) || !isXDigit(line[1]) || line[2] != ':' || !isXDigit(line[3]) || !isXDigit(line[4]) || line[5] != '.' || !isXDigit(line[6])):
|
||||
cur := PCIDevData{}
|
||||
fmt.Sscanf(line, "%x:%x.%x", &cur.Bus, &cur.Dev, &cur.Func)
|
||||
lc := strings.LastIndex(line, ":")
|
||||
li := strings.LastIndex(line[0:lc], "[")
|
||||
if li < 0 {
|
||||
continue
|
||||
}
|
||||
ven := 0
|
||||
dev := 0
|
||||
fmt.Sscanf(line[li+1:], "%x:%x", &ven, &dev)
|
||||
cur.PCIDevID = uint16(dev)
|
||||
cur.PCIVenID = uint16(ven)
|
||||
cur.ConfigDump = make([]byte, 0x100, 0x1000)
|
||||
PCIList = append(PCIList, cur)
|
||||
case len(line) > 7 && isXDigit(line[0]) && line[1] == '0' && line[2] == ':':
|
||||
start := 0
|
||||
fmt.Sscanf(line, "%x:", &start)
|
||||
cur := &PCIList[len(PCIList)-1]
|
||||
cur.ConfigDump = l.AssignHexLine(line, cur.ConfigDump)
|
||||
}
|
||||
}
|
||||
|
||||
if err := scanner.Err(); err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
func (l *LogDevReader) GetInteltool() (ret InteltoolData) {
|
||||
file, err := os.Open(l.InputDirectory + "/inteltool.log")
|
||||
if err != nil {
|
||||
log.Fatal(err)
|
||||
}
|
||||
defer file.Close()
|
||||
|
||||
scanner := bufio.NewScanner(file)
|
||||
paragraph := ""
|
||||
ret.GPIO = map[uint16]uint32{}
|
||||
ret.RCBA = map[uint16]uint32{}
|
||||
ret.IOBP = map[uint32]uint32{}
|
||||
ret.IGD = map[uint32]uint32{}
|
||||
ret.MCHBAR = map[uint16]uint32{}
|
||||
ret.PMBASE = map[uint16]uint32{}
|
||||
for scanner.Scan() {
|
||||
line := scanner.Text()
|
||||
switch {
|
||||
case len(line) > 7 && line[0] == '0' && line[1] == 'x' && line[6] == ':' && paragraph == "RCBA":
|
||||
addr, value := 0, 0
|
||||
fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value)
|
||||
ret.RCBA[uint16(addr)] = uint32(value)
|
||||
case len(line) > 11 && line[0] == '0' && line[1] == 'x' && line[10] == ':' && paragraph == "IOBP":
|
||||
addr, value := 0, 0
|
||||
fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value)
|
||||
ret.IOBP[uint32(addr)] = uint32(value)
|
||||
case len(line) > 9 && line[0] == '0' && line[1] == 'x' && line[8] == ':' && paragraph == "IGD":
|
||||
addr, value := 0, 0
|
||||
fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value)
|
||||
ret.IGD[uint32(addr)] = uint32(value)
|
||||
case len(line) > 7 && line[0] == '0' && line[1] == 'x' && line[6] == ':' && paragraph == "MCHBAR":
|
||||
addr, value := 0, 0
|
||||
fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value)
|
||||
ret.MCHBAR[uint16(addr)] = uint32(value)
|
||||
case strings.Contains(line, "DEFAULT"):
|
||||
continue
|
||||
case strings.Contains(line, "DIFF"):
|
||||
continue
|
||||
case strings.HasPrefix(line, "gpiobase"):
|
||||
addr, value := 0, 0
|
||||
fmt.Sscanf(line, "gpiobase+0x%x: 0x%x", &addr, &value)
|
||||
ret.GPIO[uint16(addr)] = uint32(value)
|
||||
case strings.HasPrefix(line, "pmbase"):
|
||||
addr, value := 0, 0
|
||||
fmt.Sscanf(line, "pmbase+0x%x: 0x%x", &addr, &value)
|
||||
ret.PMBASE[uint16(addr)] = uint32(value)
|
||||
case strings.HasPrefix(line, "============="):
|
||||
| < | ||||