The configs were enabling SeaBIOS payload, but this is to be
handled by lbmk, not coreboot.
Further, they were enabling VGA ROM execution in coreboot, but
this should be handled by SeaBIOS.
This board should not have a GRUB payload enabled either; this
will be checked and fixed if necessary in the next commit.
Add a build for QEMU AArch64 virtual machine using U-Boot as payload.
Coreboot config is based on the following defconfig:
CONFIG_CBFS_SIZE=0x00c00000
CONFIG_BOARD_EMULATION_QEMU_AARCH64=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
CONFIG_UART_PCI_ADDR=0x0
The resulting ROM can be booted with a command line like:
qemu-system-aarch64 \
-machine virt,secure=on,virtualization=on \
-cpu cortex-a53 -m 1G \
-vga none -display none -serial stdio \
-bios bin/qemu_arm64_12mb/uboot_*.rom
However, this is little more than a proof of concept because U-Boot
upstream is missing coreboot integration on non-x86 boards, which could
have been useful for e.g. a framebuffer.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Add a U-Boot build for the qemu_x86_12mb board. The config is a copy of
the upstream "coreboot" defconfig, but with OF_EMBED=y.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
New x230edp_12mb target uses the
https://review.coreboot.org/c/coreboot/+/28950 patchset to add an
X230_EDP target to the default coreboot branch.
Consequently the "fhd" coreboot branch is no longer needed and has
been safely removed.
buggy, buggy, buggy, buggy, buggy, buggy, buggy
full of bugs, these boards never worked properly. i got ripped
off with these.
now i'm ripping off the band aid
use dasharo if you want d16 stuff. i'm done with it.
This adds coreboot configuration for the Samsung Chromebook 2 11", which
is based on the "google/peach_pit" mainboard in upstream coreboot. Also
adds a shared "peach" board directory to share with others having the
same baseboard.
The config is based on the following defconfig:
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x00400000
CONFIG_UART_FOR_CONSOLE=3
CONFIG_BOARD_GOOGLE_PEACH_PIT=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the peach pit chromebook. This also fails
without a non-free 3rdparty/blobs/cpu/samsung/exynos5420/bl1.bin blob.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
This adds coreboot configuration for the HP Chromebook 11 G1, which is
part of the "google/daisy" mainboard in upstream coreboot. It uses the
shared tree for the "daisy" baseboard.
The config is based on the following defconfig:
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x00400000
CONFIG_UART_FOR_CONSOLE=3
CONFIG_BOARD_GOOGLE_DAISY=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS=0x4
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the spring chromebook. This also fails
without a non-free 3rdparty/blobs/cpu/samsung/exynos5250/bl1.bin blob.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
This adds coreboot configuration for the Samsung Chromebook - XE303,
which is based on the "google/daisy" mainboard in upstream coreboot.
Also adds a shared "daisy" board directory to share with others having
the same baseboard.
The config is based on the following defconfig:
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x00400000
CONFIG_UART_FOR_CONSOLE=3
CONFIG_BOARD_GOOGLE_DAISY=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS=0x4
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the snow chromebook. This also fails without
a non-free 3rdparty/blobs/cpu/samsung/exynos5250/bl1.bin blob.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
This adds coreboot configuration for the HP Chromebook 14 G3, which is
based on the "google/nyan_blaze" mainboard in upstream coreboot. It uses
the shared tree for the "nyan" baseboard.
The config is based on the following defconfig:
# CONFIG_USE_BLOBS is not set
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x400000
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=4
CONFIG_BOARD_GOOGLE_NYAN_BLAZE=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_DRIVERS_AS3722_RTC_BUS=4
CONFIG_DRIVERS_AS3722_RTC_ADDR=0x40
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the nyan blaze chromebook.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
This adds coreboot configuration for the Acer Chromebook 13 (CB5-311,
C810), which is based on the "google/nyan_big" mainboard in upstream
coreboot. Also adds a shared "nyan" board directory to share with
others having the same baseboard.
The config is based on the following defconfig:
# CONFIG_USE_BLOBS is not set
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x400000
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=4
CONFIG_BOARD_GOOGLE_NYAN_BIG=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_DRIVERS_AS3722_RTC_BUS=4
CONFIG_DRIVERS_AS3722_RTC_ADDR=0x40
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the nyan big chromebook.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
This adds coreboot configuration for the ASUS Chromebit CS10, which is
based on the "google/veyron_mickey" mainboard in upstream coreboot. It
uses the shared tree for the "veyron" baseboard.
The config is based on the following defconfig:
# CONFIG_USE_BLOBS is not set
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x400000
CONFIG_BOARD_GOOGLE_VEYRON_MICKEY=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the veyron mickey chromebit.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
This adds coreboot configuration for a few white-label chromebooks which
are based on the "google/veyron" mainboard in upstream coreboot. It uses
the shared tree for the "veyron" baseboard.
The config is based on the following defconfig:
# CONFIG_USE_BLOBS is not set
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x400000
CONFIG_BOARD_GOOGLE_VEYRON_JERRY=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have any of the veyron jerry chromebooks.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
This adds coreboot configuration for the ASUS Chromebook Flip C100PA,
which is based on the "google/veyron" mainboard in upstream coreboot. It
uses the shared tree for the "veyron" baseboard.
The config is based on the following defconfig:
# CONFIG_USE_BLOBS is not set
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x400000
CONFIG_BOARD_GOOGLE_VEYRON_MINNIE=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the veyron minnie chromebook.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
This adds coreboot configuration for the ASUS Chromebook C201PA, which
is based on the "google/veyron" mainboard in upstream coreboot. Also
adds a shared "veyron" board directory to share with others having the
same baseboard.
The config is based on the following defconfig:
# CONFIG_USE_BLOBS is not set
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x400000
CONFIG_BOARD_GOOGLE_VEYRON_SPEEDY=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
Untested since I don't have the veyron speedy chromebook.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
This adds coreboot configuration for the ASUS Chromebook Flip C101,
which is based on the "google/gru" mainboard in upstream coreboot. It
uses the shared tree for the "gru" baseboard.
The config is based on the following defconfig:
# CONFIG_USE_BLOBS is not set
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x00800000
CONFIG_BOARD_GOOGLE_BOB=y
CONFIG_DRIVER_TPM_SPI_BUS=0x0
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_PAYLOAD_FIT_SUPPORT=y
Untested since I don't have the bob chromebook.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
This adds coreboot configuration for the Samsung Chromebook Plus (v1),
which is based on the "google/gru" mainboard in upstream coreboot. Also
adds a shared "gru" board directory to share with others having the same
baseboard.
The config is based on the following defconfig:
# CONFIG_USE_BLOBS is not set
CONFIG_VENDOR_GOOGLE=y
CONFIG_CBFS_SIZE=0x00800000
CONFIG_BOARD_GOOGLE_KEVIN=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_UART_PCI_ADDR=0x0
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_PAYLOAD_FIT_SUPPORT=y
Most things work, but one significant problem is that the board can't power
off properly. It also happens with my manual U-Boot-only builds, but not
when I manually build coreboot with a U-Boot payload. Not sure why it is
happening here as well.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
with this change, it's unlikely we'll hit errors again. previously,
some projects used were calling "python" which in context was
python3, but on some setups, the user only has python2 and python3
but no symlink for "python" (which if exists, we assumed linked to
python3)
now it's unambiguous. docs/build/ can probably be updated now, as
a result of this change, to remove the advice about that
Coreboot is enabling PECI on these CPUs which, according to Intel erratum, must
only be done after loading microcode updates, otherwise the CPUID feature set
becomes corrupted. That's my understanding, and I think this is why SpeedStep
is broken. To be specific, it could but but operating systems no longer detect
that the feature is supported. In any case, belgin on IRC found the commit in
coreboot, after a bisect, enabling PECI. This commit in Libreboot adds a patch,
reverting coreboot's PECI patch.
tianocore is a liability for the libreboot project. it's a bloated mess, and
unreliable, broken on many boards, and basically impossible to audit.
i don't trust tianocore, so i'm removing it.
4mb and 8mb users can just pad their roms to 16mb, using the instructions on
<https://libreboot.org/faq.html#how-do-i-pad-a-rom-before-flashing>
maintaining them in lbmk is a waste of time, and also a hazard because it's a
lot of duplicated labour when making any changes, which could result in awful
mistakes being made
lbmkplaceholder