Compare commits
No commits in common. "97054498e9460b1cbc5800817fc0c9d64458536a" and "19795bf980edf31958e85319d35700ce4d2feae4" have entirely different histories.
97054498e9
...
19795bf980
|
|
@ -1,205 +0,0 @@
|
|||
From ecedecb1224a04531ec544b76ef93efd33cd8f6d Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sun, 19 Feb 2023 18:21:43 +0000
|
||||
Subject: [PATCH 1/1] util/ifdtool: add --nuke flag (all 0xFF on region)
|
||||
|
||||
When this option is used, the region's contents are overwritten
|
||||
with all ones (0xFF).
|
||||
|
||||
Example:
|
||||
|
||||
./ifdtool --nuke gbe coreboot.rom
|
||||
./ifdtool --nuke bios coreboot.com
|
||||
./ifdtool --nuke me coreboot.com
|
||||
|
||||
Rebased since the last revision update in lbmk.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
|
||||
1 file changed, 83 insertions(+), 31 deletions(-)
|
||||
|
||||
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
|
||||
index 36477eef66..3ebef74042 100644
|
||||
--- a/util/ifdtool/ifdtool.c
|
||||
+++ b/util/ifdtool/ifdtool.c
|
||||
@@ -2217,6 +2217,7 @@ static void print_usage(const char *name)
|
||||
" tgl - Tiger Lake\n"
|
||||
" wbg - Wellsburg\n"
|
||||
" -S | --setpchstrap Write a PCH strap\n"
|
||||
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
|
||||
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
|
||||
" -v | --version: print the version\n"
|
||||
" -h | --help: print this help\n\n"
|
||||
@@ -2225,6 +2226,60 @@ static void print_usage(const char *name)
|
||||
"\n");
|
||||
}
|
||||
|
||||
+static int
|
||||
+get_region_type_string(const char *region_type_string)
|
||||
+{
|
||||
+ if (!strcasecmp("Descriptor", region_type_string))
|
||||
+ return 0;
|
||||
+ else if (!strcasecmp("BIOS", region_type_string))
|
||||
+ return 1;
|
||||
+ else if (!strcasecmp("ME", region_type_string))
|
||||
+ return 2;
|
||||
+ else if (!strcasecmp("GbE", region_type_string))
|
||||
+ return 3;
|
||||
+ else if (!strcasecmp("Platform Data", region_type_string))
|
||||
+ return 4;
|
||||
+ else if (!strcasecmp("Device Exp1", region_type_string))
|
||||
+ return 5;
|
||||
+ else if (!strcasecmp("Secondary BIOS", region_type_string))
|
||||
+ return 6;
|
||||
+ else if (!strcasecmp("Reserved", region_type_string))
|
||||
+ return 7;
|
||||
+ else if (!strcasecmp("EC", region_type_string))
|
||||
+ return 8;
|
||||
+ else if (!strcasecmp("Device Exp2", region_type_string))
|
||||
+ return 9;
|
||||
+ else if (!strcasecmp("IE", region_type_string))
|
||||
+ return 10;
|
||||
+ else if (!strcasecmp("10GbE_0", region_type_string))
|
||||
+ return 11;
|
||||
+ else if (!strcasecmp("10GbE_1", region_type_string))
|
||||
+ return 12;
|
||||
+ else if (!strcasecmp("PTT", region_type_string))
|
||||
+ return 15;
|
||||
+ return -1;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+nuke(const char *filename, char *image, int size, int region_type)
|
||||
+{
|
||||
+ int i;
|
||||
+ struct region region;
|
||||
+ const struct frba *frba = find_frba(image, size);
|
||||
+ if (!frba)
|
||||
+ exit(EXIT_FAILURE);
|
||||
+
|
||||
+ region = get_region(frba, region_type);
|
||||
+ if (region.size > 0) {
|
||||
+ for (i = region.base; i <= region.limit; i++) {
|
||||
+ if ((i + 1) > (size))
|
||||
+ break;
|
||||
+ image[i] = 0xFF;
|
||||
+ }
|
||||
+ write_image(filename, image, size);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int opt, option_index = 0;
|
||||
@@ -2232,6 +2287,7 @@ int main(int argc, char *argv[])
|
||||
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
|
||||
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
|
||||
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
|
||||
+ int mode_nuke = 0;
|
||||
int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
|
||||
char *region_type_string = NULL, *region_fname = NULL;
|
||||
const char *layout_fname = NULL;
|
||||
@@ -2267,6 +2323,7 @@ int main(int argc, char *argv[])
|
||||
{"validate", 0, NULL, 't'},
|
||||
{"setpchstrap", 1, NULL, 'S'},
|
||||
{"newvalue", 1, NULL, 'V'},
|
||||
+ {"nuke", 1, NULL, 'N'},
|
||||
{0, 0, 0, 0}
|
||||
};
|
||||
|
||||
@@ -2316,35 +2373,8 @@ int main(int argc, char *argv[])
|
||||
region_fname++;
|
||||
// Descriptor, BIOS, ME, GbE, Platform
|
||||
// valid type?
|
||||
- if (!strcasecmp("Descriptor", region_type_string))
|
||||
- region_type = 0;
|
||||
- else if (!strcasecmp("BIOS", region_type_string))
|
||||
- region_type = 1;
|
||||
- else if (!strcasecmp("ME", region_type_string))
|
||||
- region_type = 2;
|
||||
- else if (!strcasecmp("GbE", region_type_string))
|
||||
- region_type = 3;
|
||||
- else if (!strcasecmp("Platform Data", region_type_string))
|
||||
- region_type = 4;
|
||||
- else if (!strcasecmp("Device Exp1", region_type_string))
|
||||
- region_type = 5;
|
||||
- else if (!strcasecmp("Secondary BIOS", region_type_string))
|
||||
- region_type = 6;
|
||||
- else if (!strcasecmp("Reserved", region_type_string))
|
||||
- region_type = 7;
|
||||
- else if (!strcasecmp("EC", region_type_string))
|
||||
- region_type = 8;
|
||||
- else if (!strcasecmp("Device Exp2", region_type_string))
|
||||
- region_type = 9;
|
||||
- else if (!strcasecmp("IE", region_type_string))
|
||||
- region_type = 10;
|
||||
- else if (!strcasecmp("10GbE_0", region_type_string))
|
||||
- region_type = 11;
|
||||
- else if (!strcasecmp("10GbE_1", region_type_string))
|
||||
- region_type = 12;
|
||||
- else if (!strcasecmp("PTT", region_type_string))
|
||||
- region_type = 15;
|
||||
- if (region_type == -1) {
|
||||
+ if ((region_type =
|
||||
+ get_region_type_string(region_type_string)) == -1) {
|
||||
fprintf(stderr, "No such region type: '%s'\n\n",
|
||||
region_type_string);
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
@@ -2521,6 +2551,22 @@ int main(int argc, char *argv[])
|
||||
case 't':
|
||||
mode_validate = 1;
|
||||
break;
|
||||
+ case 'N':
|
||||
+ region_type_string = strdup(optarg);
|
||||
+ if (!region_type_string) {
|
||||
+ fprintf(stderr, "No region specified\n");
|
||||
+ print_usage(argv[0]);
|
||||
+ exit(EXIT_FAILURE);
|
||||
+ }
|
||||
+ if ((region_type =
|
||||
+ get_region_type_string(region_type_string)) == -1) {
|
||||
+ fprintf(stderr, "No such region type: '%s'\n\n",
|
||||
+ region_type_string);
|
||||
+ print_usage(argv[0]);
|
||||
+ exit(EXIT_FAILURE);
|
||||
+ }
|
||||
+ mode_nuke = 1;
|
||||
+ break;
|
||||
case 'v':
|
||||
print_version();
|
||||
exit(EXIT_SUCCESS);
|
||||
@@ -2540,7 +2586,8 @@ int main(int argc, char *argv[])
|
||||
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
|
||||
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
|
||||
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
|
||||
- (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) {
|
||||
+ (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
|
||||
+ mode_nuke) > 1) {
|
||||
fprintf(stderr, "You may not specify more than one mode.\n\n");
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
exit(EXIT_FAILURE);
|
||||
@@ -2549,7 +2596,8 @@ int main(int argc, char *argv[])
|
||||
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
|
||||
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
|
||||
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
|
||||
- mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) {
|
||||
+ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
|
||||
+ mode_nuke) == 0) {
|
||||
fprintf(stderr, "You need to specify a mode.\n\n");
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
exit(EXIT_FAILURE);
|
||||
@@ -2662,6 +2710,10 @@ int main(int argc, char *argv[])
|
||||
write_image(new_filename, image, size);
|
||||
}
|
||||
|
||||
+ if (mode_nuke) {
|
||||
+ nuke(new_filename, image, size, region_type);
|
||||
+ }
|
||||
+
|
||||
if (mode_altmedisable) {
|
||||
struct fpsba *fpsba = find_fpsba(image, size);
|
||||
struct fmsba *fmsba = find_fmsba(image, size);
|
||||
--
|
||||
2.39.5
|
||||
|
||||
|
|
@ -1,652 +0,0 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_780"
|
||||
CONFIG_VGA_BIOS_ID="8086,2e22"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x7FD000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="780_mt"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfeff8000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
|
||||
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
|
||||
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=8192
|
||||
CONFIG_ROM_SIZE=0x00800000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F3X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F4X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_LGA775=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
CONFIG_USE_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_MRC_STASH_TO_CBMEM=y
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
|
|
@ -1,648 +0,0 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_780"
|
||||
CONFIG_VGA_BIOS_ID="8086,2e22"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x7FD000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="780_mt"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfeff8000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
|
||||
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
|
||||
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=8192
|
||||
CONFIG_ROM_SIZE=0x00800000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F3X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F4X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_LGA775=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
CONFIG_USE_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_MRC_STASH_TO_CBMEM=y
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
tree="next"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="nvme ahci ata"
|
||||
grubtree="nvme"
|
||||
build_depend="seabios/default grub/nvme memtest86plus"
|
||||
|
|
@ -1,652 +0,0 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_780"
|
||||
CONFIG_VGA_BIOS_ID="8086,2e22"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x5FD000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="780_mt"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfeff8000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8_truncate"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
|
||||
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
|
||||
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_6144=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=6144
|
||||
CONFIG_ROM_SIZE=0x00600000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F3X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F4X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_LGA775=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
CONFIG_USE_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_MRC_STASH_TO_CBMEM=y
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
|
|
@ -1,648 +0,0 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_780"
|
||||
CONFIG_VGA_BIOS_ID="8086,2e22"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x5FD000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="780_mt"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfeff8000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8_truncate"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
|
||||
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
|
||||
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_6144=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=6144
|
||||
CONFIG_ROM_SIZE=0x00600000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F3X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F4X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_LGA775=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
CONFIG_USE_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_MRC_STASH_TO_CBMEM=y
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
tree="next"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="nvme ahci ata"
|
||||
grubtree="nvme"
|
||||
build_depend="seabios/default grub/nvme memtest86plus"
|
||||
|
|
@ -1,708 +0,0 @@
|
|||
From 8b951349f2ef77916633c817ad2fc1decd5c0920 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Mon, 30 Sep 2024 20:44:38 -0400
|
||||
Subject: [PATCH 1/3] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
|
||||
|
||||
Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/optiplex_780/Kconfig | 40 ++++
|
||||
src/mainboard/dell/optiplex_780/Kconfig.name | 4 +
|
||||
src/mainboard/dell/optiplex_780/Makefile.mk | 10 +
|
||||
src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 +
|
||||
.../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++
|
||||
.../dell/optiplex_780/acpi/superio.asl | 18 ++
|
||||
.../dell/optiplex_780/board_info.txt | 6 +
|
||||
src/mainboard/dell/optiplex_780/cmos.default | 8 +
|
||||
src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++
|
||||
src/mainboard/dell/optiplex_780/cstates.c | 8 +
|
||||
src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++
|
||||
src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++
|
||||
.../dell/optiplex_780/gma-mainboard.ads | 16 ++
|
||||
.../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes
|
||||
.../optiplex_780/variants/780_mt/early_init.c | 12 ++
|
||||
.../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++
|
||||
.../optiplex_780/variants/780_mt/hda_verb.c | 26 +++
|
||||
.../variants/780_mt/overridetree.cb | 10 +
|
||||
18 files changed, 530 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/Kconfig
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/cmos.default
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/cstates.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000000..2d06c75c9a
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/Kconfig
|
||||
@@ -0,0 +1,40 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+config BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
+ def_bool n
|
||||
+ select BOARD_ROMSIZE_KB_8192
|
||||
+ select CPU_INTEL_SOCKET_LGA775
|
||||
+ select DRIVERS_I2C_CK505
|
||||
+ select HAVE_ACPI_RESUME
|
||||
+ select HAVE_ACPI_TABLES
|
||||
+ select HAVE_CMOS_DEFAULT
|
||||
+ select HAVE_OPTION_TABLE
|
||||
+ select INTEL_GMA_HAVE_VBT
|
||||
+ select MAINBOARD_HAS_LIBGFXINIT
|
||||
+ select MAINBOARD_USES_IFD_GBE_REGION
|
||||
+ select NORTHBRIDGE_INTEL_X4X
|
||||
+ select PCIEXP_ASPM
|
||||
+ select PCIEXP_CLK_PM
|
||||
+ select SOUTHBRIDGE_INTEL_I82801JX
|
||||
+
|
||||
+config BOARD_DELL_OPTIPLEX_780_MT
|
||||
+ select BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
+
|
||||
+if BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
+
|
||||
+config VGA_BIOS_ID
|
||||
+ default "8086,2e22"
|
||||
+
|
||||
+config MAINBOARD_DIR
|
||||
+ default "dell/optiplex_780"
|
||||
+
|
||||
+config MAINBOARD_PART_NUMBER
|
||||
+ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT
|
||||
+
|
||||
+config OVERRIDE_DEVICETREE
|
||||
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
+
|
||||
+config VARIANT_DIR
|
||||
+ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT
|
||||
+
|
||||
+endif # BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name
|
||||
new file mode 100644
|
||||
index 0000000000..db7f2e8fe3
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/Kconfig.name
|
||||
@@ -0,0 +1,4 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+config BOARD_DELL_OPTIPLEX_780_MT
|
||||
+ bool "OptiPlex 780 MT"
|
||||
diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk
|
||||
new file mode 100644
|
||||
index 0000000000..d462995d75
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/Makefile.mk
|
||||
@@ -0,0 +1,10 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+ramstage-y += cstates.c
|
||||
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
|
||||
+
|
||||
+bootblock-y += variants/$(VARIANT_DIR)/early_init.c
|
||||
+romstage-y += variants/$(VARIANT_DIR)/early_init.c
|
||||
+
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
|
||||
diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl
|
||||
new file mode 100644
|
||||
index 0000000000..479296cb76
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl
|
||||
@@ -0,0 +1,5 @@
|
||||
+/* SPDX-License-Identifier: CC-PDDC */
|
||||
+
|
||||
+/* Please update the license if adding licensable material. */
|
||||
+
|
||||
+/* dummy */
|
||||
diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
|
||||
new file mode 100644
|
||||
index 0000000000..b7588dcc41
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
|
||||
@@ -0,0 +1,32 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+/* This is board specific information:
|
||||
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10
|
||||
+ */
|
||||
+
|
||||
+If (PICM) {
|
||||
+ Return (Package() {
|
||||
+ /* PCI slot */
|
||||
+ Package() { 0x0001ffff, 0, 0, 0x14},
|
||||
+ Package() { 0x0001ffff, 1, 0, 0x15},
|
||||
+ Package() { 0x0001ffff, 2, 0, 0x16},
|
||||
+ Package() { 0x0001ffff, 3, 0, 0x17},
|
||||
+
|
||||
+ Package() { 0x0002ffff, 0, 0, 0x15},
|
||||
+ Package() { 0x0002ffff, 1, 0, 0x16},
|
||||
+ Package() { 0x0002ffff, 2, 0, 0x17},
|
||||
+ Package() { 0x0002ffff, 3, 0, 0x14},
|
||||
+ })
|
||||
+} Else {
|
||||
+ Return (Package() {
|
||||
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
|
||||
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
|
||||
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
|
||||
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
|
||||
+
|
||||
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
|
||||
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
|
||||
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
|
||||
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
|
||||
+ })
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl
|
||||
new file mode 100644
|
||||
index 0000000000..9f3900b86c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl
|
||||
@@ -0,0 +1,18 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#undef SUPERIO_DEV
|
||||
+#undef SUPERIO_PNP_BASE
|
||||
+#undef IT8720F_SHOW_SP1
|
||||
+#undef IT8720F_SHOW_SP2
|
||||
+#undef IT8720F_SHOW_EC
|
||||
+#undef IT8720F_SHOW_KBCK
|
||||
+#undef IT8720F_SHOW_KBCM
|
||||
+#undef IT8720F_SHOW_GPIO
|
||||
+#undef IT8720F_SHOW_CIR
|
||||
+#define SUPERIO_DEV SIO0
|
||||
+#define SUPERIO_PNP_BASE 0x2e
|
||||
+#define IT8720F_SHOW_EC 1
|
||||
+#define IT8720F_SHOW_KBCK 1
|
||||
+#define IT8720F_SHOW_KBCM 1
|
||||
+#define IT8720F_SHOW_GPIO 1
|
||||
+#include <superio/ite/it8720f/acpi/superio.asl>
|
||||
diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt
|
||||
new file mode 100644
|
||||
index 0000000000..aaf657b583
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/board_info.txt
|
||||
@@ -0,0 +1,6 @@
|
||||
+Category: desktop
|
||||
+Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1
|
||||
+ROM package: SOIC-8
|
||||
+ROM protocol: SPI
|
||||
+ROM socketed: n
|
||||
+Flashrom support: y
|
||||
diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default
|
||||
new file mode 100644
|
||||
index 0000000000..23f0e55f3e
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/cmos.default
|
||||
@@ -0,0 +1,8 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+boot_option=Fallback
|
||||
+debug_level=Debug
|
||||
+power_on_after_fail=Disable
|
||||
+nmi=Enable
|
||||
+sata_mode=AHCI
|
||||
+gfx_uma_size=64M
|
||||
diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout
|
||||
new file mode 100644
|
||||
index 0000000000..9f5012adb4
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/cmos.layout
|
||||
@@ -0,0 +1,72 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+entries
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+0 120 r 0 reserved_memory
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
+384 1 e 4 boot_option
|
||||
+388 4 h 0 reboot_counter
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# coreboot config options: console
|
||||
+395 4 e 6 debug_level
|
||||
+
|
||||
+# coreboot config options: southbridge
|
||||
+408 1 e 10 sata_mode
|
||||
+409 2 e 7 power_on_after_fail
|
||||
+411 1 e 1 nmi
|
||||
+
|
||||
+# coreboot config options: cpu
|
||||
+
|
||||
+# coreboot config options: northbridge
|
||||
+432 4 e 11 gfx_uma_size
|
||||
+
|
||||
+# coreboot config options: check sums
|
||||
+984 16 h 0 check_sum
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+
|
||||
+enumerations
|
||||
+
|
||||
+#ID value text
|
||||
+1 0 Disable
|
||||
+1 1 Enable
|
||||
+2 0 Enable
|
||||
+2 1 Disable
|
||||
+4 0 Fallback
|
||||
+4 1 Normal
|
||||
+6 0 Emergency
|
||||
+6 1 Alert
|
||||
+6 2 Critical
|
||||
+6 3 Error
|
||||
+6 4 Warning
|
||||
+6 5 Notice
|
||||
+6 6 Info
|
||||
+6 7 Debug
|
||||
+6 8 Spew
|
||||
+7 0 Disable
|
||||
+7 1 Enable
|
||||
+7 2 Keep
|
||||
+10 0 AHCI
|
||||
+10 1 Compatible
|
||||
+11 1 4M
|
||||
+11 2 8M
|
||||
+11 3 16M
|
||||
+11 4 32M
|
||||
+11 5 48M
|
||||
+11 6 64M
|
||||
+11 7 128M
|
||||
+11 8 256M
|
||||
+11 9 96M
|
||||
+11 10 160M
|
||||
+11 11 224M
|
||||
+11 12 352M
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+checksums
|
||||
+
|
||||
+checksum 392 983 984
|
||||
diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c
|
||||
new file mode 100644
|
||||
index 0000000000..4adf0edc63
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/cstates.c
|
||||
@@ -0,0 +1,8 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpigen.h>
|
||||
+
|
||||
+int get_cst_entries(const acpi_cstate_t **entries)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..95e3bd517c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/devicetree.cb
|
||||
@@ -0,0 +1,63 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+chip northbridge/intel/x4x
|
||||
+ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
|
||||
+ device domain 0 on
|
||||
+ ops x4x_pci_domain_ops # PCI domain
|
||||
+ subsystemid 0x8086 0x0028 inherit
|
||||
+ device pci 0.0 on end # Host Bridge
|
||||
+ device pci 1.0 on end # PCIe x16 2.0 slot
|
||||
+ device pci 2.0 on end # Integrated graphics controller
|
||||
+ device pci 2.1 on end # Integrated graphics controller 2
|
||||
+ device pci 3.0 off end # ME
|
||||
+ device pci 3.1 off end # ME
|
||||
+ chip southbridge/intel/i82801jx # ICH10
|
||||
+ register "gpe0_en" = "0x40"
|
||||
+
|
||||
+ # Set AHCI mode.
|
||||
+ register "sata_port_map" = "0x3f"
|
||||
+ register "sata_clock_request" = "1"
|
||||
+
|
||||
+ # Enable PCIe ports 0,1 as slots.
|
||||
+ register "pcie_slot_implemented" = "0x3"
|
||||
+
|
||||
+ device pci 19.0 on end # GBE
|
||||
+ device pci 1a.0 on end # USB
|
||||
+ device pci 1a.1 on end # USB
|
||||
+ device pci 1a.2 on end # USB
|
||||
+ device pci 1a.7 on end # USB
|
||||
+ device pci 1b.0 on end # Audio
|
||||
+ device pci 1c.0 off end # PCIe 1
|
||||
+ device pci 1c.1 off end # PCIe 2
|
||||
+ device pci 1c.2 off end # PCIe 3
|
||||
+ device pci 1c.3 off end # PCIe 4
|
||||
+ device pci 1c.4 off end # PCIe 5
|
||||
+ device pci 1c.5 off end # PCIe 6
|
||||
+ device pci 1d.0 on end # USB
|
||||
+ device pci 1d.1 on end # USB
|
||||
+ device pci 1d.2 on end # USB
|
||||
+ device pci 1d.7 on end # USB
|
||||
+ device pci 1e.0 on end # PCI bridge
|
||||
+ device pci 1f.0 on end # LPC bridge
|
||||
+ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5)
|
||||
+ device pci 1f.3 on # SMBus
|
||||
+ chip drivers/i2c/ck505 # IDT CV194
|
||||
+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff,
|
||||
+ 0xff, 0xff, 0xff, 0xff,
|
||||
+ 0xff, 0xff, 0xff, 0xff,
|
||||
+ 0xff, 0xff, 0xff, 0xff,
|
||||
+ 0xff, 0xff, 0xff }"
|
||||
+ register "regs" = "{ 0x15, 0x82, 0xff, 0xff,
|
||||
+ 0xff, 0x00, 0x00, 0x95,
|
||||
+ 0x00, 0x65, 0x7d, 0x56,
|
||||
+ 0x13, 0xc0, 0x00, 0x07,
|
||||
+ 0x01, 0x0a, 0x64 }"
|
||||
+ device i2c 69 on end
|
||||
+ end
|
||||
+ end
|
||||
+ device pci 1f.4 off end
|
||||
+ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode)
|
||||
+ device pci 1f.6 off end # Thermal Subsystem
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl
|
||||
new file mode 100644
|
||||
index 0000000000..9ad70469de
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/dsdt.asl
|
||||
@@ -0,0 +1,26 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+DefinitionBlock(
|
||||
+ "dsdt.aml",
|
||||
+ "DSDT",
|
||||
+ ACPI_DSDT_REV_2,
|
||||
+ OEM_ID,
|
||||
+ ACPI_TABLE_CREATOR,
|
||||
+ 0x20090811 // OEM revision
|
||||
+)
|
||||
+{
|
||||
+ #include <acpi/dsdt_top.asl>
|
||||
+
|
||||
+ OSYS = 2002
|
||||
+ // global NVS and variables
|
||||
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||
+
|
||||
+ Device (\_SB.PCI0)
|
||||
+ {
|
||||
+ #include <northbridge/intel/x4x/acpi/x4x.asl>
|
||||
+ #include <southbridge/intel/i82801jx/acpi/ich10.asl>
|
||||
+ }
|
||||
+
|
||||
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..bc81cf4a40
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads
|
||||
@@ -0,0 +1,16 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (DP2,
|
||||
+ Analog,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf
|
||||
GIT binary patch
|
||||
literal 1917
|
||||
zcmd6nO>7%Q6vzLwGv0Mv$FUpJ*ik4iQd_wnX*X`M0y3~p?8a$~>ZXxZMU`4dc9RGb
|
||||
zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX
|
||||
zznS;`v-5V=o<pVaS;}Q53%NpOI!8{cz{K0eVfK65_|*A}SF)Me%$4!N`H5-z90%~a
|
||||
zvGog3fe5LjnM&o#3$<#k{6>{ZwwmnN>gY?}>{`7^JBpP$l`EBIwbi0*k&aU)n@v)E
|
||||
znI_A1T57efS5MG<y}m-_+CrVKE#0VADDft%nb#Y<<ao9;Mf?!XvM)_$Xla>NN5_ut
|
||||
zt=x`G)EjR#mlhURC^2!A3p33TcBg4-d8JyTiF&hfk}|a#&Dfe2%~V^}=4!QavNzBh
|
||||
z0Pae^5`gfb?<R!YN+PQ)U7<%H;73qF3iyQT71$?W2s|f{69_4sRY(x>7Q)c(LsP)8
|
||||
zQy)2gw<F#IP`I}U>gG1S^>aw&0D}Z+-SCcJJF;s)yXJeQ|4N{SU?$I`#$HZa<Jq(M
|
||||
zbA{r}Z0XY6<@U{Y-d!KWR>9dWBuxA$6X;VK;%W?Y>I;0P`|*vwAK$S(VB2JSq6g4n
|
||||
z>oEf8XCt;_Y-iYBWz#<re{?il1^f{S#nht`VW!62^5R*KQ6_?#8e&Qw=9%`og2x!s
|
||||
z&J)wlZ=a<yoJkutfwu4%aVXlu?i^8v?R77IyGvKcD|M`CFG$6FUmK8q<|o>3T9EmJ
|
||||
z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<<Gei4)FzWqGEt6P8D
|
||||
zA9m}s>;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH`
|
||||
zawsKv^FvHqm+<DDPT)%}_kZ8^eT88YGmG-#)X3=RRB|L^Uj_{yd%JeO<1HRZVz=Fz
|
||||
z+aqUCWdF3_={#Q&&k)eF1i=WV`AbSlzo*bP?x?ir5BVVO`R34f89jWL{Z}or^BwmG
|
||||
z-E;A_iWVUUWnWQl3L|~0xA@rHJRA-;7V)Y6B5=@E8R@?(?5{Eh23RefpSOGX_F{8A
|
||||
z1PtU+iNng^h#C7J<vufJ9>c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E
|
||||
xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO(<xf!`#Pk3F
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..e2fa05cd8f
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <northbridge/intel/x4x/x4x.h>
|
||||
+
|
||||
+void mb_get_spd_map(u8 spd_map[4])
|
||||
+{
|
||||
+ // BTX form factor
|
||||
+ spd_map[0] = 0x53;
|
||||
+ spd_map[1] = 0x52;
|
||||
+ spd_map[2] = 0x51;
|
||||
+ spd_map[3] = 0x50;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..9993f17c55
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
|
||||
@@ -0,0 +1,174 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_NATIVE,
|
||||
+ .gpio1 = GPIO_MODE_NATIVE,
|
||||
+ .gpio2 = GPIO_MODE_GPIO,
|
||||
+ .gpio3 = GPIO_MODE_GPIO,
|
||||
+ .gpio4 = GPIO_MODE_GPIO,
|
||||
+ .gpio5 = GPIO_MODE_GPIO,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_NATIVE,
|
||||
+ .gpio8 = GPIO_MODE_NATIVE,
|
||||
+ .gpio9 = GPIO_MODE_GPIO,
|
||||
+ .gpio10 = GPIO_MODE_GPIO,
|
||||
+ .gpio11 = GPIO_MODE_NATIVE,
|
||||
+ .gpio12 = GPIO_MODE_NATIVE,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_GPIO,
|
||||
+ .gpio15 = GPIO_MODE_NATIVE,
|
||||
+ .gpio16 = GPIO_MODE_GPIO,
|
||||
+ .gpio17 = GPIO_MODE_NATIVE,
|
||||
+ .gpio18 = GPIO_MODE_GPIO,
|
||||
+ .gpio19 = GPIO_MODE_GPIO,
|
||||
+ .gpio20 = GPIO_MODE_GPIO,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_GPIO,
|
||||
+ .gpio30 = GPIO_MODE_GPIO,
|
||||
+ .gpio31 = GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio2 = GPIO_DIR_INPUT,
|
||||
+ .gpio3 = GPIO_DIR_INPUT,
|
||||
+ .gpio4 = GPIO_DIR_INPUT,
|
||||
+ .gpio5 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio9 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio10 = GPIO_DIR_INPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio14 = GPIO_DIR_INPUT,
|
||||
+ .gpio16 = GPIO_DIR_INPUT,
|
||||
+ .gpio18 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio19 = GPIO_DIR_INPUT,
|
||||
+ .gpio20 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio29 = GPIO_DIR_INPUT,
|
||||
+ .gpio30 = GPIO_DIR_INPUT,
|
||||
+ .gpio31 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio9 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio18 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio20 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio28 = GPIO_LEVEL_LOW,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio13 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_GPIO,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_NATIVE,
|
||||
+ .gpio46 = GPIO_MODE_NATIVE,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_GPIO,
|
||||
+ .gpio50 = GPIO_MODE_NATIVE,
|
||||
+ .gpio51 = GPIO_MODE_NATIVE,
|
||||
+ .gpio52 = GPIO_MODE_NATIVE,
|
||||
+ .gpio53 = GPIO_MODE_NATIVE,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_NATIVE,
|
||||
+ .gpio56 = GPIO_MODE_GPIO,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_GPIO,
|
||||
+ .gpio61 = GPIO_MODE_NATIVE,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio32 = GPIO_DIR_INPUT,
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_INPUT,
|
||||
+ .gpio35 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_INPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio49 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio54 = GPIO_DIR_INPUT,
|
||||
+ .gpio56 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio60 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+ .gpio35 = GPIO_LEVEL_LOW,
|
||||
+ .gpio49 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio56 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio60 = GPIO_LEVEL_LOW,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio64 = GPIO_MODE_NATIVE,
|
||||
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||
+ .gpio66 = GPIO_MODE_NATIVE,
|
||||
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||
+ .gpio68 = GPIO_MODE_NATIVE,
|
||||
+ .gpio69 = GPIO_MODE_NATIVE,
|
||||
+ .gpio70 = GPIO_MODE_NATIVE,
|
||||
+ .gpio71 = GPIO_MODE_NATIVE,
|
||||
+ .gpio72 = GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio72 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..4158bcf899
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
|
||||
@@ -0,0 +1,26 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ /* coreboot specific header */
|
||||
+ 0x11d4194a, /* Analog Devices AD1984A */
|
||||
+ 0xbfd40000, /* Subsystem ID */
|
||||
+ 10, /* Number of entries */
|
||||
+
|
||||
+ /* Pin Widget Verb Table */
|
||||
+ AZALIA_PIN_CFG(0, 0x11, 0x032140f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x12, 0x21214010),
|
||||
+ AZALIA_PIN_CFG(0, 0x13, 0x901701f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121),
|
||||
+ AZALIA_PIN_CFG(0, 0x16, 0x9933012e),
|
||||
+ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020),
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[0] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..555b1c1f5c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
|
||||
@@ -0,0 +1,10 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+chip northbridge/intel/x4x
|
||||
+ device domain 0 on
|
||||
+ chip southbridge/intel/i82801jx
|
||||
+ device pci 1c.0 on end # PCIe 1
|
||||
+ device pci 1c.1 on end # PCIe 2
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
--
|
||||
2.39.5
|
||||
|
||||
|
|
@ -1,205 +0,0 @@
|
|||
From 1b230f671ebc6e355a001ac7ffc9b031329de019 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sun, 19 Feb 2023 18:21:43 +0000
|
||||
Subject: [PATCH 2/3] util/ifdtool: add --nuke flag (all 0xFF on region)
|
||||
|
||||
When this option is used, the region's contents are overwritten
|
||||
with all ones (0xFF).
|
||||
|
||||
Example:
|
||||
|
||||
./ifdtool --nuke gbe coreboot.rom
|
||||
./ifdtool --nuke bios coreboot.com
|
||||
./ifdtool --nuke me coreboot.com
|
||||
|
||||
Rebased since the last revision update in lbmk.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
|
||||
1 file changed, 83 insertions(+), 31 deletions(-)
|
||||
|
||||
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
|
||||
index 36477eef66..3ebef74042 100644
|
||||
--- a/util/ifdtool/ifdtool.c
|
||||
+++ b/util/ifdtool/ifdtool.c
|
||||
@@ -2217,6 +2217,7 @@ static void print_usage(const char *name)
|
||||
" tgl - Tiger Lake\n"
|
||||
" wbg - Wellsburg\n"
|
||||
" -S | --setpchstrap Write a PCH strap\n"
|
||||
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
|
||||
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
|
||||
" -v | --version: print the version\n"
|
||||
" -h | --help: print this help\n\n"
|
||||
@@ -2225,6 +2226,60 @@ static void print_usage(const char *name)
|
||||
"\n");
|
||||
}
|
||||
|
||||
+static int
|
||||
+get_region_type_string(const char *region_type_string)
|
||||
+{
|
||||
+ if (!strcasecmp("Descriptor", region_type_string))
|
||||
+ return 0;
|
||||
+ else if (!strcasecmp("BIOS", region_type_string))
|
||||
+ return 1;
|
||||
+ else if (!strcasecmp("ME", region_type_string))
|
||||
+ return 2;
|
||||
+ else if (!strcasecmp("GbE", region_type_string))
|
||||
+ return 3;
|
||||
+ else if (!strcasecmp("Platform Data", region_type_string))
|
||||
+ return 4;
|
||||
+ else if (!strcasecmp("Device Exp1", region_type_string))
|
||||
+ return 5;
|
||||
+ else if (!strcasecmp("Secondary BIOS", region_type_string))
|
||||
+ return 6;
|
||||
+ else if (!strcasecmp("Reserved", region_type_string))
|
||||
+ return 7;
|
||||
+ else if (!strcasecmp("EC", region_type_string))
|
||||
+ return 8;
|
||||
+ else if (!strcasecmp("Device Exp2", region_type_string))
|
||||
+ return 9;
|
||||
+ else if (!strcasecmp("IE", region_type_string))
|
||||
+ return 10;
|
||||
+ else if (!strcasecmp("10GbE_0", region_type_string))
|
||||
+ return 11;
|
||||
+ else if (!strcasecmp("10GbE_1", region_type_string))
|
||||
+ return 12;
|
||||
+ else if (!strcasecmp("PTT", region_type_string))
|
||||
+ return 15;
|
||||
+ return -1;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+nuke(const char *filename, char *image, int size, int region_type)
|
||||
+{
|
||||
+ int i;
|
||||
+ struct region region;
|
||||
+ const struct frba *frba = find_frba(image, size);
|
||||
+ if (!frba)
|
||||
+ exit(EXIT_FAILURE);
|
||||
+
|
||||
+ region = get_region(frba, region_type);
|
||||
+ if (region.size > 0) {
|
||||
+ for (i = region.base; i <= region.limit; i++) {
|
||||
+ if ((i + 1) > (size))
|
||||
+ break;
|
||||
+ image[i] = 0xFF;
|
||||
+ }
|
||||
+ write_image(filename, image, size);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int opt, option_index = 0;
|
||||
@@ -2232,6 +2287,7 @@ int main(int argc, char *argv[])
|
||||
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
|
||||
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
|
||||
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
|
||||
+ int mode_nuke = 0;
|
||||
int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
|
||||
char *region_type_string = NULL, *region_fname = NULL;
|
||||
const char *layout_fname = NULL;
|
||||
@@ -2267,6 +2323,7 @@ int main(int argc, char *argv[])
|
||||
{"validate", 0, NULL, 't'},
|
||||
{"setpchstrap", 1, NULL, 'S'},
|
||||
{"newvalue", 1, NULL, 'V'},
|
||||
+ {"nuke", 1, NULL, 'N'},
|
||||
{0, 0, 0, 0}
|
||||
};
|
||||
|
||||
@@ -2316,35 +2373,8 @@ int main(int argc, char *argv[])
|
||||
region_fname++;
|
||||
// Descriptor, BIOS, ME, GbE, Platform
|
||||
// valid type?
|
||||
- if (!strcasecmp("Descriptor", region_type_string))
|
||||
- region_type = 0;
|
||||
- else if (!strcasecmp("BIOS", region_type_string))
|
||||
- region_type = 1;
|
||||
- else if (!strcasecmp("ME", region_type_string))
|
||||
- region_type = 2;
|
||||
- else if (!strcasecmp("GbE", region_type_string))
|
||||
- region_type = 3;
|
||||
- else if (!strcasecmp("Platform Data", region_type_string))
|
||||
- region_type = 4;
|
||||
- else if (!strcasecmp("Device Exp1", region_type_string))
|
||||
- region_type = 5;
|
||||
- else if (!strcasecmp("Secondary BIOS", region_type_string))
|
||||
- region_type = 6;
|
||||
- else if (!strcasecmp("Reserved", region_type_string))
|
||||
- region_type = 7;
|
||||
- else if (!strcasecmp("EC", region_type_string))
|
||||
- region_type = 8;
|
||||
- else if (!strcasecmp("Device Exp2", region_type_string))
|
||||
- region_type = 9;
|
||||
- else if (!strcasecmp("IE", region_type_string))
|
||||
- region_type = 10;
|
||||
- else if (!strcasecmp("10GbE_0", region_type_string))
|
||||
- region_type = 11;
|
||||
- else if (!strcasecmp("10GbE_1", region_type_string))
|
||||
- region_type = 12;
|
||||
- else if (!strcasecmp("PTT", region_type_string))
|
||||
- region_type = 15;
|
||||
- if (region_type == -1) {
|
||||
+ if ((region_type =
|
||||
+ get_region_type_string(region_type_string)) == -1) {
|
||||
fprintf(stderr, "No such region type: '%s'\n\n",
|
||||
region_type_string);
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
@@ -2521,6 +2551,22 @@ int main(int argc, char *argv[])
|
||||
case 't':
|
||||
mode_validate = 1;
|
||||
break;
|
||||
+ case 'N':
|
||||
+ region_type_string = strdup(optarg);
|
||||
+ if (!region_type_string) {
|
||||
+ fprintf(stderr, "No region specified\n");
|
||||
+ print_usage(argv[0]);
|
||||
+ exit(EXIT_FAILURE);
|
||||
+ }
|
||||
+ if ((region_type =
|
||||
+ get_region_type_string(region_type_string)) == -1) {
|
||||
+ fprintf(stderr, "No such region type: '%s'\n\n",
|
||||
+ region_type_string);
|
||||
+ print_usage(argv[0]);
|
||||
+ exit(EXIT_FAILURE);
|
||||
+ }
|
||||
+ mode_nuke = 1;
|
||||
+ break;
|
||||
case 'v':
|
||||
print_version();
|
||||
exit(EXIT_SUCCESS);
|
||||
@@ -2540,7 +2586,8 @@ int main(int argc, char *argv[])
|
||||
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
|
||||
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
|
||||
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
|
||||
- (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) {
|
||||
+ (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
|
||||
+ mode_nuke) > 1) {
|
||||
fprintf(stderr, "You may not specify more than one mode.\n\n");
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
exit(EXIT_FAILURE);
|
||||
@@ -2549,7 +2596,8 @@ int main(int argc, char *argv[])
|
||||
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
|
||||
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
|
||||
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
|
||||
- mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) {
|
||||
+ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
|
||||
+ mode_nuke) == 0) {
|
||||
fprintf(stderr, "You need to specify a mode.\n\n");
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
exit(EXIT_FAILURE);
|
||||
@@ -2662,6 +2710,10 @@ int main(int argc, char *argv[])
|
||||
write_image(new_filename, image, size);
|
||||
}
|
||||
|
||||
+ if (mode_nuke) {
|
||||
+ nuke(new_filename, image, size, region_type);
|
||||
+ }
|
||||
+
|
||||
if (mode_altmedisable) {
|
||||
struct fpsba *fpsba = find_fpsba(image, size);
|
||||
struct fmsba *fmsba = find_fmsba(image, size);
|
||||
--
|
||||
2.39.5
|
||||
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
From ddc7390d7750eb3b29a6d6fe7bf2400121d639b5 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Fri, 12 May 2023 19:55:15 -0600
|
||||
Subject: [PATCH 3/3] Remove warning for coreboot images built without a
|
||||
payload
|
||||
|
||||
I added this in upstream to prevent people from accidentally flashing
|
||||
roms without a payload resulting in a no boot situation, but in
|
||||
libreboot lbmk handles the payload and thus this warning always comes
|
||||
up. This has caused confusion and concern so just patch it out.
|
||||
---
|
||||
payloads/Makefile.mk | 13 +------------
|
||||
1 file changed, 1 insertion(+), 12 deletions(-)
|
||||
|
||||
diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
|
||||
index 5f988dac1b..516133880f 100644
|
||||
--- a/payloads/Makefile.mk
|
||||
+++ b/payloads/Makefile.mk
|
||||
@@ -50,16 +50,5 @@ distclean-payloads:
|
||||
print-repo-info-payloads:
|
||||
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
|
||||
|
||||
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
|
||||
-show_notices:: warn_no_payload
|
||||
-endif
|
||||
-
|
||||
-warn_no_payload:
|
||||
- printf "\n\t** WARNING **\n"
|
||||
- printf "coreboot has been built without a payload. Writing\n"
|
||||
- printf "a coreboot image without a payload to your board's\n"
|
||||
- printf "flash chip will result in a non-booting system. You\n"
|
||||
- printf "can use cbfstool to add a payload to the image.\n\n"
|
||||
-
|
||||
.PHONY: force-payload coreinfo nvramcui
|
||||
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
|
||||
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
|
||||
--
|
||||
2.39.5
|
||||
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
tree="next"
|
||||
rev="c21bed6de9359111afd5d6ed6e76b1d2116b216c"
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,3 +0,0 @@
|
|||
subfile="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix-20230628.tar.gz"
|
||||
subfile_bkup="https://mirror.math.princeton.edu/pub/libreboot/misc/acpica/acpica-unix-20230628.tar.gz"
|
||||
subhash="d726e69ebd8b8110690e3aff8d1919b43b0a2185efdeb9131ea8d89d321ca3a318a89c721ea740ae366f31ed3d1c11c2906f8807ee8a190e6f67fe5b2023cea4"
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
subfile="https://ftp.nluug.nl/pub/gnu/binutils/binutils-2.43.1.tar.xz"
|
||||
subfile_bkup="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils/binutils-2.43.1.tar.xz"
|
||||
subhash="20977ad17729141a2c26d358628f44a0944b84dcfefdec2ba029c2d02f40dfc41cc91c0631044560d2bd6f9a51e1f15846b4b311befbe14f1239f14ff7d57824"
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
subfile="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-14.2.0/gcc-14.2.0.tar.xz"
|
||||
subfile_bkup="https://ftp.nluug.nl/pub/gnu/gcc/gcc-14.2.0/gcc-14.2.0.tar.xz"
|
||||
subhash="932bdef0cda94bacedf452ab17f103c0cb511ff2cec55e9112fc0328cbf1d803b42595728ea7b200e0a057c03e85626f937012e49a7515bc5dd256b2bf4bc396"
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
subfile="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz"
|
||||
subfile_bkup="https://ftp.nluug.nl/pub/gnu/gmp/gmp-6.3.0.tar.xz"
|
||||
subhash="e85a0dab5195889948a3462189f0e0598d331d3457612e2d3350799dba2e244316d256f8161df5219538eb003e4b5343f989aaa00f96321559063ed8c8f29fd2"
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
subrepo="https://review.coreboot.org/intel-microcode.git"
|
||||
subrepo_bkup="https://github.com/coreboot/intel-microcode"
|
||||
subhash="fbfe741896c55b36fcbf0560a68be96286103556"
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
subrepo="https://review.coreboot.org/libgfxinit.git"
|
||||
subrepo_bkup="https://github.com/coreboot/libgfxinit"
|
||||
subhash="17cfc92f402493979783585b6581efbd98c0cf07"
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
subrepo="https://review.coreboot.org/libhwbase.git"
|
||||
subrepo_bkup="https://github.com/coreboot/libhwbase"
|
||||
subhash="584629b9f4771b7618951cec57df2ca3af9c6981"
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
3rdparty/intel-microcode
|
||||
3rdparty/libgfxinit
|
||||
3rdparty/libhwbase
|
||||
3rdparty/vboot
|
||||
util/crossgcc/tarballs/binutils-2.43.1.tar.xz
|
||||
util/crossgcc/tarballs/gcc-14.2.0.tar.xz
|
||||
util/crossgcc/tarballs/gmp-6.3.0.tar.xz
|
||||
util/crossgcc/tarballs/mpc-1.3.1.tar.gz
|
||||
util/crossgcc/tarballs/mpfr-4.2.1.tar.xz
|
||||
util/crossgcc/tarballs/nasm-2.16.03.tar.bz2
|
||||
util/crossgcc/tarballs/acpica-unix-20230628.tar.gz
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
subfile="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc/mpc-1.3.1.tar.gz"
|
||||
subfile_bkup="https://ftp.nluug.nl/pub/gnu/mpc/mpc-1.3.1.tar.gz"
|
||||
subhash="4bab4ef6076f8c5dfdc99d810b51108ced61ea2942ba0c1c932d624360a5473df20d32b300fc76f2ba4aa2a97e1f275c9fd494a1ba9f07c4cb2ad7ceaeb1ae97"
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
subfile="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr/mpfr-4.2.1.tar.xz"
|
||||
subfile_bkup="https://ftp.nluug.nl/pub/gnu/mpfr/mpfr-4.2.1.tar.xz"
|
||||
subhash="bc68c0d755d5446403644833ecbb07e37360beca45f474297b5d5c40926df1efc3e2067eecffdf253f946288bcca39ca89b0613f545d46a9e767d1d4cf358475"
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
subfile="https://www.nasm.us/pub/nasm/releasebuilds/2.16.03/nasm-2.16.03.tar.bz2"
|
||||
subfile_bkup="https://www.mirrorservice.org/sites/distfiles.macports.org/nasm/nasm-2.16.03.tar.bz2"
|
||||
subhash="f28445d368debdf44219cc57df33800a8c0e49186cd60836d4adfec7700d53b801d34aa9fc9bfda74169843f33a1e8b465e11292582eb968bb9c3a26f54dd172"
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
subrepo="https://review.coreboot.org/vboot.git"
|
||||
subrepo_bkup="https://github.com/coreboot/vboot"
|
||||
subhash="f1f70f46dc5482bb7c654e53ed58d4001e386df2"
|
||||
|
|
@ -1,178 +0,0 @@
|
|||
From 195f61375aeec9eec16604ec59f6eda2e6058cc1 Mon Sep 17 00:00:00 2001
|
||||
From: "Luke T. Shumaker" <lukeshu@lukeshu.com>
|
||||
Date: Thu, 30 May 2024 14:08:33 -0600
|
||||
Subject: [PATCH 1/1] extract_vmlinuz.c: Fix the bounds check on
|
||||
vmlinuz_header_{offset,size}
|
||||
|
||||
The check on vmlinuz_header_offset and vmlinuz_header_size is obviously
|
||||
wrong:
|
||||
|
||||
if (!vmlinuz_header_size ||
|
||||
kpart_data + vmlinuz_header_offset + vmlinuz_header_size >
|
||||
kpart_data) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
`kpart_data + some_unsigned_values` can obviously never be `> kpart_data`,
|
||||
unless something has overflowed! And `vmlinuz_header_offset` hasn't even
|
||||
been set yet (besides being initialized to zero)!
|
||||
|
||||
GCC will deduce that if the check didn't cause the function to bail, then
|
||||
vmlinuz_header_size (a uint32_t) must be "negative"; that is: in the range
|
||||
[2GiB,4GiB).
|
||||
|
||||
On platforms where size_t is 32-bits, this is *especially* broken.
|
||||
memcpy's size argument must be in the range [0,2GiB). Because GCC has
|
||||
proved that vmlinuz_header_size is higher than that, it will fail to
|
||||
compile:
|
||||
|
||||
host/lib/extract_vmlinuz.c:67:9: error: 'memcpy' specified bound between 2147483648 and 4294967295 exceeds maximum object size 2147483647 [-Werror=stringop-overflow=]
|
||||
|
||||
So, fix the check.
|
||||
|
||||
I can now say that what I suspect the original author meant to write would
|
||||
be the following patch, if `vmlinuz_header_offset` were already set:
|
||||
|
||||
-kpart_data + vmlinuz_header_offset + vmlinuz_header_size > kpart_data
|
||||
+now + vmlinuz_header_offset + vmlinuz_header_size > kpart_size
|
||||
|
||||
This hypothesis is supported by `now` not getting incremented by
|
||||
`kblob_size` the way it is for the keyblock and preamble sizes.
|
||||
|
||||
However, we can also see that even this "corrected" bounds check is
|
||||
insufficient: it does not detect the vmlinuz_header overflowing into
|
||||
kblob_data.
|
||||
|
||||
OK, so let's describe the fix:
|
||||
|
||||
Have a `*vmlinuz_header` pointer instead of a
|
||||
`uint64_t vmlinuz_header_offset`, to be more similar to all the other
|
||||
regions. With this change, the correct check becomes a simple
|
||||
|
||||
vmlinuz_header + vmlinuz_header_size > kblob_data
|
||||
|
||||
While we're at it, make some changes that could have helped avoid this in
|
||||
the first place:
|
||||
|
||||
- Add comments.
|
||||
- Calculate the vmlinuz_header offset right away, instead of waiting.
|
||||
- Go ahead and increment `now` by `kblob_size`, to increase regularity.
|
||||
|
||||
Change-Id: I5c03e49070b6dd2e04459566ef7dd129d27736e4
|
||||
---
|
||||
host/lib/extract_vmlinuz.c | 72 +++++++++++++++++++++++++++-----------
|
||||
1 file changed, 51 insertions(+), 21 deletions(-)
|
||||
|
||||
diff --git a/host/lib/extract_vmlinuz.c b/host/lib/extract_vmlinuz.c
|
||||
index 4ccfcf33..d2c09443 100644
|
||||
--- a/host/lib/extract_vmlinuz.c
|
||||
+++ b/host/lib/extract_vmlinuz.c
|
||||
@@ -15,16 +15,44 @@
|
||||
|
||||
int ExtractVmlinuz(void *kpart_data, size_t kpart_size,
|
||||
void **vmlinuz_out, size_t *vmlinuz_size) {
|
||||
+ // We're going to be extracting `vmlinuz_header` and
|
||||
+ // `kblob_data`, and returning the concatenation of them.
|
||||
+ //
|
||||
+ // kpart_data = +-[kpart_size]------------------------------------+
|
||||
+ // | |
|
||||
+ // keyblock = | +-[keyblock->keyblock_size]-------------------+ |
|
||||
+ // | | struct vb2_keyblock keyblock | |
|
||||
+ // | | char [] ...data... | |
|
||||
+ // | +---------------------------------------------+ |
|
||||
+ // | |
|
||||
+ // preamble = | +-[preamble->preamble_size]-------------------+ |
|
||||
+ // | | struct vb2_kernel_preamble preamble | |
|
||||
+ // | | char [] ...data... | |
|
||||
+ // | | char [] vmlinuz_header | |
|
||||
+ // | | char [] ...data... | |
|
||||
+ // | +---------------------------------------------+ |
|
||||
+ // | |
|
||||
+ // kblob_data= | +-[preamble->body_signature.data_size]--------+ |
|
||||
+ // | | char [] ...data... | |
|
||||
+ // | +---------------------------------------------+ |
|
||||
+ // | |
|
||||
+ // +-------------------------------------------------+
|
||||
+
|
||||
size_t now = 0;
|
||||
+ // The 3 sections of kpart_data.
|
||||
+ struct vb2_keyblock *keyblock = NULL;
|
||||
struct vb2_kernel_preamble *preamble = NULL;
|
||||
uint8_t *kblob_data = NULL;
|
||||
uint32_t kblob_size = 0;
|
||||
+ // vmlinuz_header
|
||||
+ uint8_t *vmlinuz_header = NULL;
|
||||
uint32_t vmlinuz_header_size = 0;
|
||||
- uint64_t vmlinuz_header_address = 0;
|
||||
- uint64_t vmlinuz_header_offset = 0;
|
||||
+ // The concatenated result.
|
||||
void *vmlinuz = NULL;
|
||||
|
||||
- struct vb2_keyblock *keyblock = (struct vb2_keyblock *)kpart_data;
|
||||
+ // Isolate the 3 sections of kpart_data.
|
||||
+
|
||||
+ keyblock = (struct vb2_keyblock *)kpart_data;
|
||||
now += keyblock->keyblock_size;
|
||||
if (now > kpart_size)
|
||||
return 1;
|
||||
@@ -36,37 +64,39 @@ int ExtractVmlinuz(void *kpart_data, size_t kpart_size,
|
||||
|
||||
kblob_data = kpart_data + now;
|
||||
kblob_size = preamble->body_signature.data_size;
|
||||
-
|
||||
- if (!kblob_data || (now + kblob_size) > kpart_size)
|
||||
+ now += kblob_size;
|
||||
+ if (now > kpart_size)
|
||||
return 1;
|
||||
|
||||
+ // Find `vmlinuz_header` within `preamble`.
|
||||
+
|
||||
if (preamble->header_version_minor > 0) {
|
||||
- vmlinuz_header_address = preamble->vmlinuz_header_address;
|
||||
+ // calculate the vmlinuz_header offset from
|
||||
+ // the beginning of the kpart_data. The kblob doesn't
|
||||
+ // include the body_load_offset, but does include
|
||||
+ // the keyblock and preamble sections.
|
||||
+ size_t vmlinuz_header_offset =
|
||||
+ preamble->vmlinuz_header_address -
|
||||
+ preamble->body_load_address +
|
||||
+ keyblock->keyblock_size +
|
||||
+ preamble->preamble_size;
|
||||
+
|
||||
+ vmlinuz_header = kpart_data + vmlinuz_header_offset;
|
||||
vmlinuz_header_size = preamble->vmlinuz_header_size;
|
||||
}
|
||||
|
||||
- if (!vmlinuz_header_size ||
|
||||
- kpart_data + vmlinuz_header_offset + vmlinuz_header_size >
|
||||
- kpart_data) {
|
||||
+ if (!vmlinuz_header ||
|
||||
+ !vmlinuz_header_size ||
|
||||
+ vmlinuz_header + vmlinuz_header_size > kblob_data) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
- // calculate the vmlinuz_header offset from
|
||||
- // the beginning of the kpart_data. The kblob doesn't
|
||||
- // include the body_load_offset, but does include
|
||||
- // the keyblock and preamble sections.
|
||||
- vmlinuz_header_offset = vmlinuz_header_address -
|
||||
- preamble->body_load_address +
|
||||
- keyblock->keyblock_size +
|
||||
- preamble->preamble_size;
|
||||
+ // Concatenate and return.
|
||||
|
||||
vmlinuz = malloc(vmlinuz_header_size + kblob_size);
|
||||
if (vmlinuz == NULL)
|
||||
return 1;
|
||||
-
|
||||
- memcpy(vmlinuz, kpart_data + vmlinuz_header_offset,
|
||||
- vmlinuz_header_size);
|
||||
-
|
||||
+ memcpy(vmlinuz, vmlinuz_header, vmlinuz_header_size);
|
||||
memcpy(vmlinuz + vmlinuz_header_size, kblob_data, kblob_size);
|
||||
|
||||
*vmlinuz_out = vmlinuz;
|
||||
--
|
||||
2.45.1
|
||||
|
||||
Loading…
Reference in New Issue