450 lines
15 KiB
Diff
450 lines
15 KiB
Diff
From 1111dcab65ca83f175f1bb9c0496cae24fbfb7c2 Mon Sep 17 00:00:00 2001
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From: Nicholas Chin <nic.c3.14@gmail.com>
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Date: Wed, 31 Jan 2024 22:07:25 -0700
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Subject: [PATCH 21/39] mb/dell: Add Latitude E6520 (Sandy Bridge)
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Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was
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not tested. I do not physically have this system; someone with physical
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access to one sent me the output of autoport which I then modified to
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produce this port. I was also sent the VBT binary, which was obtained
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from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the
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vendor firmware.
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This was originally tested and found to be working as a standalone board
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port in Libreboot, but this variant based port in upstream coreboot has
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not been tested.
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This can be internally flashed by sending a command to the EC, which
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causes the EC to pull the FDO pin low and the firmware to skip setting
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up any chipset based write protections [1]. The EC is the SMSC MEC5055,
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which seems to be compatible with the existing MEC5035 code.
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[1] https://gitlab.com/nic3-14159/dell-flash-unlock
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Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
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Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
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---
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src/mainboard/dell/snb_ivb_latitude/Kconfig | 9 +
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.../dell/snb_ivb_latitude/Kconfig.name | 3 +
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.../snb_ivb_latitude/variants/e6520/data.vbt | Bin 0 -> 6144 bytes
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.../variants/e6520/early_init.c | 31 +++
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.../snb_ivb_latitude/variants/e6520/gpio.c | 190 ++++++++++++++++++
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.../variants/e6520/hda_verb.c | 32 +++
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.../variants/e6520/overridetree.cb | 35 ++++
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7 files changed, 300 insertions(+)
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
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diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
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index d2786970ee..72bdc96c0a 100644
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--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
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+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
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@@ -23,6 +23,12 @@ config BOARD_DELL_LATITUDE_E6420
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select MAINBOARD_USES_IFD_GBE_REGION
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select SOUTHBRIDGE_INTEL_BD82X6X
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+config BOARD_DELL_LATITUDE_E6520
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+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
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+ select BOARD_ROMSIZE_KB_10240
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+ select MAINBOARD_USES_IFD_GBE_REGION
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+ select SOUTHBRIDGE_INTEL_BD82X6X
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+
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config BOARD_DELL_LATITUDE_E5530
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select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
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select BOARD_ROMSIZE_KB_12288
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@@ -50,6 +56,7 @@ config MAINBOARD_DIR
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config MAINBOARD_PART_NUMBER
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default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
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+ default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
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default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
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default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
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default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
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@@ -62,11 +69,13 @@ config USBDEBUG_HCD_INDEX
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config VARIANT_DIR
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default "e6420" if BOARD_DELL_LATITUDE_E6420
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+ default "e6520" if BOARD_DELL_LATITUDE_E6520
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default "e5530" if BOARD_DELL_LATITUDE_E5530
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default "e6430" if BOARD_DELL_LATITUDE_E6430
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default "e6530" if BOARD_DELL_LATITUDE_E6530
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config VGA_BIOS_ID
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+ default "8086,0116" if BOARD_DELL_LATITUDE_E6520
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default "8086,0166" if BOARD_DELL_LATITUDE_E5530
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default "8086,0126" if BOARD_DELL_LATITUDE_E6420
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default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
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diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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index 257d428a70..c7665ac263 100644
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--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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@@ -3,6 +3,9 @@
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config BOARD_DELL_LATITUDE_E6420
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bool "Latitude E6420"
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+config BOARD_DELL_LATITUDE_E6520
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+ bool "Latitude E6520"
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+
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config BOARD_DELL_LATITUDE_E5530
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bool "Latitude E5530"
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diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt
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new file mode 100644
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index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0
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GIT binary patch
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literal 6144
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zcmeHKZ){Ul6hE);wSB#PZ|mL$bQ^!}HW(eF@H)0JafGfbqsZ9G21{L7Sg{or$5uN)
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z_QgG55e!O(8p8*oBhhF`l$n^QF%rN;rzFNqqcPzFCd5QSB1Y7RKt1=pmTk1aFo9^Y
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z+x+gi_nvdlJ@?#m&wZWW=G#bH>ze$J`&!oe*Q|E0r!)d89LYY8b$aowZEoG-uiIF+
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z#n;$ezm6V<nGnvtc?lrGaf)1_);!W0?uqnojdw-1MQM|dwy`OcF?M@A)KgVV*N2}7
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zcXx+--0R}IwzW3-+`f2k?^Av5V7MpRO-q(9rn_R1@Xlz2Ztdy`$Gf6^w6~|bKi!!7
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z9;xq*^~bxmZQn^<^<`+2s=BdSM%VW2#FguN<FO^QuDhGIFquBu677q|cSj>jWFixQ
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z)4V8f0Gt`D`+>9Fr~tnJ76EJ`5D_F1cn-`0$RgN9unI6kfYkzIiO?W`ON4+34lv1_
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zNdPDkq1cf$p8^EW;TS*O$CdzNo#1fbIG_Oi0T(ti0jwyt0le_p_HlvX^CFvr)>$b>
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zO-z8^CSU`w=mIK7Q)@9fR;XUzrFu{T=rRyygIZBpU9+Or>+?4R9%~G?Y-|g)Z`Sti
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z+do(U*Wb-xR~DzjS<75#=Us4sH^C9U2FCbND7L7u$>M|<;t=AnRfI9C0v8c~AVg7t
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zIU<3D2oK^>L;%r(*o=4*u?Mja@dDyi#4zFn;(f#^#3*76aUSs#;tJv#La-6YLRdQB
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zdcvfERkvH?k~GJlfM<HR476j(@nfm+47<!Ult@^ua5M3h6A}q=C0ognX9aX4mxq)U
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zXOhm=DbLene?C%_16Q)2NRV@Yacz`D;{V>Ve-1?&ZXy}n)YwnVAgNlz#zX;=IX)-F
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z)9LL3lbEdY5Co)LsK?vP)7s}G(5xduE!Y!#Wgh<IN3(3ey=-oWU(9aEJ_HzV53Jbq
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zj5B5RjzLUt>_T&xi$uUA#0e}X3D~`J(bHz;DgTa@GrpW6=>eZwJeNYYo*GjF=``;(
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zuoQ3|V5YoKd$j=KK{`uSX*DeU1oJg=+RT6)rLe6%2>Ci^!5ao=*gS}wFN=nUf`fTF
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zM?Gb5ycWjM7I?MJ!2;w|LFg=UoLq-ytr2iemG)AsW}bI4X9PK}T5UKsQi7anu=tD6
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zf|={kXkNeQBD>6bQ3taC8XJOJ^e40_ydyfr&a41L^1)jNrK<B_wV}+ZE`p;QK=rDz
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zTw`SJ+e`Oc*icaF4INF51Xg*~ts@m)@9ETt(*@N7yy0)Ddce%i9{^k2kbd8=Wns~P
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zWBD$~himxDharxF@f!ti^0$~9Zxt{tg`@Dbl_0Ki2Xp_MEw-<z6qgep;XYmR%Dl-F
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z%3cBfcN;Avikpz-gmw_6mymu!Unk0YgnUfsk3{*6kQ;=S*p(_fS!JhDyYh^k?6uRk
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z?8--W@~NHvY*+ra6SG9iC1s^V)<|@Rqzp*pd5NBslrs`JC(&Oeg~v}CnJ$x+)iP<8
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z=`LA0Ad@39{XkZ}kjXbP{YzHtS!70*yy%LcnJ#cz4u%*Wq!^d*AVMZdr&l=#Qgik~
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ze2l)cX+!kF9EaFhY;0^Uo_#VNC?7K2Tf=ZR1y5);b!mCGG?<cc#M0rtHKYeKi%BE?
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z@Y6|P8fx#li}c`Uv24UGyZaM0To;Ep<_AWZA1t~bFgI)uf}&Eq=L_Cs89=>wnT0Vx
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z-jp>o1ffJNommZ4?=TIPlePIw0hgQ706f*tBC`#pg>9&zRHe>J2%RxBTrOc6Adh9E
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ziJr`?VQH!N!_GkoKaoq|+3$^Ae0#sUxXlmM1Huq~g<=Ls?ILv+nQcH%PQedGOlH=Q
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z77rMcJlH4Mkc#U2(IDv>rsm1aHpsdL_RdT^i_ACcQUMIJcSus}*(?CIiy^#^=t=g1
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z+*^Zbh30&^#_bKclSy9pL$<B~pK8m*sLpIdnHM@W$nA7Ea@Z`x27K?aNK<@lCW(2L
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zb@kB3H8kKy4W3Hu)NN|kd!DL^o#iR9a{QYV-Wl&r&hmIFX{ezkIV<4zFiVUQ@K>ao
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z00DnFy~Uek!JRwhVX!of0)$Sa*X^S~LMQH0<E(UUx}L=|;Kgw(r(4q=nD)T52c|tR
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O?SW|zOncy=dEg(6JAK&z
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literal 0
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HcmV?d00001
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diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
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new file mode 100644
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index 0000000000..b6415a428b
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--- /dev/null
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+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
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@@ -0,0 +1,31 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+#include <bootblock_common.h>
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+#include <device/pci_ops.h>
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+#include <ec/dell/mec5035/mec5035.h>
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+#include <southbridge/intel/bd82x6x/pch.h>
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+
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+const struct southbridge_usb_port mainboard_usb_ports[] = {
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+ { 1, 1, 0 },
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+ { 1, 1, 0 },
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+ { 1, 1, 1 },
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+ { 1, 1, 1 },
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+ { 1, 0, 2 },
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+ { 1, 1, 2 },
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+ { 1, 0, 3 },
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+ { 1, 0, 3 },
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+ { 1, 1, 5 },
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+ { 1, 1, 5 },
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+ { 1, 1, 7 },
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+ { 1, 1, 6 },
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+ { 1, 0, 6 },
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+ { 1, 0, 7 },
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+};
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+
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+void bootblock_mainboard_early_init(void)
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+{
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+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
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+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
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+ | COMB_LPC_EN | COMA_LPC_EN);
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+ mec5035_early_init();
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+}
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diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
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new file mode 100644
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index 0000000000..61f01816c4
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--- /dev/null
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+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
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@@ -0,0 +1,190 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+#include <southbridge/intel/common/gpio.h>
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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+ .gpio0 = GPIO_MODE_GPIO,
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+ .gpio1 = GPIO_MODE_NATIVE,
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+ .gpio2 = GPIO_MODE_GPIO,
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+ .gpio3 = GPIO_MODE_NATIVE,
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+ .gpio4 = GPIO_MODE_GPIO,
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+ .gpio5 = GPIO_MODE_NATIVE,
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+ .gpio6 = GPIO_MODE_GPIO,
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+ .gpio7 = GPIO_MODE_GPIO,
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+ .gpio8 = GPIO_MODE_GPIO,
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+ .gpio9 = GPIO_MODE_NATIVE,
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+ .gpio10 = GPIO_MODE_NATIVE,
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+ .gpio11 = GPIO_MODE_NATIVE,
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+ .gpio12 = GPIO_MODE_NATIVE,
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+ .gpio13 = GPIO_MODE_GPIO,
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+ .gpio14 = GPIO_MODE_GPIO,
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+ .gpio15 = GPIO_MODE_GPIO,
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+ .gpio16 = GPIO_MODE_GPIO,
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+ .gpio17 = GPIO_MODE_GPIO,
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+ .gpio18 = GPIO_MODE_NATIVE,
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+ .gpio19 = GPIO_MODE_GPIO,
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+ .gpio20 = GPIO_MODE_NATIVE,
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+ .gpio21 = GPIO_MODE_GPIO,
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+ .gpio22 = GPIO_MODE_GPIO,
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+ .gpio23 = GPIO_MODE_NATIVE,
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+ .gpio24 = GPIO_MODE_GPIO,
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+ .gpio25 = GPIO_MODE_NATIVE,
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+ .gpio26 = GPIO_MODE_NATIVE,
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+ .gpio27 = GPIO_MODE_GPIO,
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+ .gpio28 = GPIO_MODE_GPIO,
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+ .gpio29 = GPIO_MODE_GPIO,
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+ .gpio30 = GPIO_MODE_GPIO,
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+ .gpio31 = GPIO_MODE_NATIVE,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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+ .gpio0 = GPIO_DIR_INPUT,
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+ .gpio2 = GPIO_DIR_INPUT,
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+ .gpio4 = GPIO_DIR_INPUT,
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+ .gpio6 = GPIO_DIR_INPUT,
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+ .gpio7 = GPIO_DIR_INPUT,
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+ .gpio8 = GPIO_DIR_INPUT,
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+ .gpio13 = GPIO_DIR_INPUT,
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+ .gpio14 = GPIO_DIR_INPUT,
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+ .gpio15 = GPIO_DIR_INPUT,
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+ .gpio16 = GPIO_DIR_INPUT,
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+ .gpio17 = GPIO_DIR_INPUT,
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+ .gpio19 = GPIO_DIR_INPUT,
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+ .gpio21 = GPIO_DIR_INPUT,
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+ .gpio22 = GPIO_DIR_INPUT,
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+ .gpio24 = GPIO_DIR_INPUT,
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+ .gpio27 = GPIO_DIR_INPUT,
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+ .gpio28 = GPIO_DIR_INPUT,
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+ .gpio29 = GPIO_DIR_INPUT,
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+ .gpio30 = GPIO_DIR_OUTPUT,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_level = {
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+ .gpio30 = GPIO_LEVEL_HIGH,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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+ .gpio0 = GPIO_INVERT,
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+ .gpio8 = GPIO_INVERT,
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+ .gpio14 = GPIO_INVERT,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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+ .gpio32 = GPIO_MODE_NATIVE,
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+ .gpio33 = GPIO_MODE_GPIO,
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+ .gpio34 = GPIO_MODE_GPIO,
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+ .gpio35 = GPIO_MODE_GPIO,
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+ .gpio36 = GPIO_MODE_GPIO,
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+ .gpio37 = GPIO_MODE_GPIO,
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+ .gpio38 = GPIO_MODE_GPIO,
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+ .gpio39 = GPIO_MODE_GPIO,
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+ .gpio40 = GPIO_MODE_NATIVE,
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+ .gpio41 = GPIO_MODE_NATIVE,
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+ .gpio42 = GPIO_MODE_NATIVE,
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+ .gpio43 = GPIO_MODE_NATIVE,
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+ .gpio44 = GPIO_MODE_NATIVE,
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+ .gpio45 = GPIO_MODE_GPIO,
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+ .gpio46 = GPIO_MODE_NATIVE,
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+ .gpio47 = GPIO_MODE_NATIVE,
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+ .gpio48 = GPIO_MODE_GPIO,
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+ .gpio49 = GPIO_MODE_GPIO,
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+ .gpio50 = GPIO_MODE_NATIVE,
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+ .gpio51 = GPIO_MODE_GPIO,
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+ .gpio52 = GPIO_MODE_GPIO,
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+ .gpio53 = GPIO_MODE_NATIVE,
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+ .gpio54 = GPIO_MODE_GPIO,
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+ .gpio55 = GPIO_MODE_NATIVE,
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+ .gpio56 = GPIO_MODE_NATIVE,
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+ .gpio57 = GPIO_MODE_GPIO,
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+ .gpio58 = GPIO_MODE_NATIVE,
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+ .gpio59 = GPIO_MODE_NATIVE,
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+ .gpio60 = GPIO_MODE_GPIO,
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+ .gpio61 = GPIO_MODE_NATIVE,
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+ .gpio62 = GPIO_MODE_NATIVE,
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+ .gpio63 = GPIO_MODE_NATIVE,
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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+ .gpio33 = GPIO_DIR_INPUT,
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+ .gpio34 = GPIO_DIR_OUTPUT,
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+ .gpio35 = GPIO_DIR_INPUT,
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+ .gpio36 = GPIO_DIR_INPUT,
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+ .gpio37 = GPIO_DIR_INPUT,
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+ .gpio38 = GPIO_DIR_INPUT,
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+ .gpio39 = GPIO_DIR_INPUT,
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+ .gpio45 = GPIO_DIR_OUTPUT,
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+ .gpio48 = GPIO_DIR_INPUT,
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+ .gpio49 = GPIO_DIR_OUTPUT,
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+ .gpio51 = GPIO_DIR_INPUT,
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+ .gpio52 = GPIO_DIR_INPUT,
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+ .gpio54 = GPIO_DIR_INPUT,
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+ .gpio57 = GPIO_DIR_INPUT,
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+ .gpio60 = GPIO_DIR_OUTPUT,
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_level = {
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+ .gpio34 = GPIO_LEVEL_HIGH,
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+ .gpio45 = GPIO_LEVEL_LOW,
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+ .gpio49 = GPIO_LEVEL_LOW,
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+ .gpio60 = GPIO_LEVEL_HIGH,
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
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+};
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+
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+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
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+ .gpio64 = GPIO_MODE_NATIVE,
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+ .gpio65 = GPIO_MODE_NATIVE,
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+ .gpio66 = GPIO_MODE_NATIVE,
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+ .gpio67 = GPIO_MODE_NATIVE,
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+ .gpio68 = GPIO_MODE_GPIO,
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+ .gpio69 = GPIO_MODE_GPIO,
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+ .gpio70 = GPIO_MODE_GPIO,
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+ .gpio71 = GPIO_MODE_GPIO,
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+ .gpio72 = GPIO_MODE_NATIVE,
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+ .gpio73 = GPIO_MODE_NATIVE,
|
|
+ .gpio74 = GPIO_MODE_NATIVE,
|
|
+ .gpio75 = GPIO_MODE_NATIVE,
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
|
+ .gpio68 = GPIO_DIR_INPUT,
|
|
+ .gpio69 = GPIO_DIR_INPUT,
|
|
+ .gpio70 = GPIO_DIR_INPUT,
|
|
+ .gpio71 = GPIO_DIR_INPUT,
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
|
+};
|
|
+
|
|
+const struct pch_gpio_map mainboard_gpio_map = {
|
|
+ .set1 = {
|
|
+ .mode = &pch_gpio_set1_mode,
|
|
+ .direction = &pch_gpio_set1_direction,
|
|
+ .level = &pch_gpio_set1_level,
|
|
+ .blink = &pch_gpio_set1_blink,
|
|
+ .invert = &pch_gpio_set1_invert,
|
|
+ .reset = &pch_gpio_set1_reset,
|
|
+ },
|
|
+ .set2 = {
|
|
+ .mode = &pch_gpio_set2_mode,
|
|
+ .direction = &pch_gpio_set2_direction,
|
|
+ .level = &pch_gpio_set2_level,
|
|
+ .reset = &pch_gpio_set2_reset,
|
|
+ },
|
|
+ .set3 = {
|
|
+ .mode = &pch_gpio_set3_mode,
|
|
+ .direction = &pch_gpio_set3_direction,
|
|
+ .level = &pch_gpio_set3_level,
|
|
+ .reset = &pch_gpio_set3_reset,
|
|
+ },
|
|
+};
|
|
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
|
|
new file mode 100644
|
|
index 0000000000..ae376691e7
|
|
--- /dev/null
|
|
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
|
|
@@ -0,0 +1,32 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0-only */
|
|
+
|
|
+#include <device/azalia_device.h>
|
|
+
|
|
+const u32 cim_verb_data[] = {
|
|
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
|
|
+ 0x10280494, /* Subsystem ID */
|
|
+ 11, /* Number of 4 dword sets */
|
|
+ AZALIA_SUBVENDOR(0, 0x10280494),
|
|
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
|
|
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
|
|
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
|
|
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
|
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
|
|
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
|
|
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
|
|
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f2),
|
|
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
|
|
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
|
|
+
|
|
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
|
|
+ 0x80860101, /* Subsystem ID */
|
|
+ 4, /* Number of 4 dword sets */
|
|
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
|
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
|
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
|
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
|
+};
|
|
+
|
|
+const u32 pc_beep_verbs[0] = {};
|
|
+
|
|
+AZALIA_ARRAY_SIZES;
|
|
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
|
|
new file mode 100644
|
|
index 0000000000..f90f2dee1f
|
|
--- /dev/null
|
|
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
|
|
@@ -0,0 +1,35 @@
|
|
+## SPDX-License-Identifier: GPL-2.0-or-later
|
|
+
|
|
+chip northbridge/intel/sandybridge
|
|
+ device domain 0 on
|
|
+ subsystemid 0x1028 0x0494 inherit
|
|
+
|
|
+ device ref igd on
|
|
+ register "gpu_cpu_backlight" = "0x00001312"
|
|
+ register "gpu_pch_backlight" = "0x13121312"
|
|
+ end
|
|
+
|
|
+ chip southbridge/intel/bd82x6x
|
|
+ register "usb_port_config" = "{
|
|
+ { 1, 1, 0 },
|
|
+ { 1, 1, 0 },
|
|
+ { 1, 1, 1 },
|
|
+ { 1, 1, 1 },
|
|
+ { 1, 0, 2 },
|
|
+ { 1, 1, 2 },
|
|
+ { 1, 1, 3 },
|
|
+ { 1, 1, 3 },
|
|
+ { 1, 1, 5 },
|
|
+ { 1, 1, 5 },
|
|
+ { 1, 1, 7 },
|
|
+ { 1, 1, 6 },
|
|
+ { 1, 0, 6 },
|
|
+ { 1, 0, 7 },
|
|
+ }"
|
|
+
|
|
+ device ref sata1 on
|
|
+ register "sata_port_map" = "0x3b"
|
|
+ end
|
|
+ end
|
|
+ end
|
|
+end
|
|
--
|
|
2.39.2
|
|
|