437 lines
15 KiB
Diff
437 lines
15 KiB
Diff
From 87e6f8bf38c5dcb4075d0df32507bf9151338b92 Mon Sep 17 00:00:00 2001
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From: Nicholas Chin <nic.c3.14@gmail.com>
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Date: Fri, 8 Mar 2024 09:33:03 -0700
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Subject: [PATCH 26/39] mb/dell: Add Latitude E6330 (Ivy Bridge)
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Mainboard is QAL70/LA-7741P. I do not physically have this system;
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someone with physical access to one sent me the output of autoport which
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I then modified to produce this port. I was also sent the VBT binary,
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which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
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version A21 of the vendor firmware. This port has not been tested.
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The EC is the SMSC MEC5055, which seems to be compatible with the
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existing MEC5035 code. As with the other Dell systems with this EC, this
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board is assumed to be internally flashable using an EC command that
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tells it to pull the FDO pin low on the next boot, which also tells the
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vendor firmware to disable all write protections to the flash [1].
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[1] https://gitlab.com/nic3-14159/dell-flash-unlock
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Change-Id: I827826e9ff8a9a534c50250458b399104478e06c
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Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
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---
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src/mainboard/dell/snb_ivb_latitude/Kconfig | 11 +-
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.../dell/snb_ivb_latitude/Kconfig.name | 3 +
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.../snb_ivb_latitude/variants/e6330/data.vbt | Bin 0 -> 6144 bytes
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.../variants/e6330/early_init.c | 14 ++
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.../snb_ivb_latitude/variants/e6330/gpio.c | 192 ++++++++++++++++++
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.../variants/e6330/hda_verb.c | 32 +++
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.../variants/e6330/overridetree.cb | 37 ++++
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7 files changed, 288 insertions(+), 1 deletion(-)
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
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diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
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index baa83baa41..49bf225fe2 100644
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--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
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+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
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@@ -56,6 +56,12 @@ config BOARD_DELL_LATITUDE_E5530
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select BOARD_ROMSIZE_KB_12288
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select SOUTHBRIDGE_INTEL_C216
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+config BOARD_DELL_LATITUDE_E6330
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+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
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+ select BOARD_ROMSIZE_KB_12288
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+ select MAINBOARD_USES_IFD_GBE_REGION
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+ select SOUTHBRIDGE_INTEL_C216
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+
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config BOARD_DELL_LATITUDE_E6430
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select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
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select BOARD_ROMSIZE_KB_12288
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@@ -84,6 +90,7 @@ config MAINBOARD_PART_NUMBER
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default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
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default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
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default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
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+ default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330
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default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
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default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
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@@ -101,13 +108,15 @@ config VARIANT_DIR
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default "e6420" if BOARD_DELL_LATITUDE_E6420
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default "e6520" if BOARD_DELL_LATITUDE_E6520
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default "e5530" if BOARD_DELL_LATITUDE_E5530
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+ default "e6330" if BOARD_DELL_LATITUDE_E6330
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default "e6430" if BOARD_DELL_LATITUDE_E6430
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default "e6530" if BOARD_DELL_LATITUDE_E6530
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config VGA_BIOS_ID
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default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \
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|| BOARD_DELL_LATITUDE_E5420
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- default "8086,0166" if BOARD_DELL_LATITUDE_E5530
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+ default "8086,0166" if BOARD_DELL_LATITUDE_E5530 \
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+ || BOARD_DELL_LATITUDE_E6330
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default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
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|| BOARD_DELL_LATITUDE_E5520 \
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|| BOARD_DELL_LATITUDE_E6220 \
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diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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index 349ee7f79e..d6fc8eb224 100644
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--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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@@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E6520
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config BOARD_DELL_LATITUDE_E5530
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bool "Latitude E5530"
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+config BOARD_DELL_LATITUDE_E6330
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+ bool "Latitude E6330"
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+
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config BOARD_DELL_LATITUDE_E6430
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bool "Latitude E6430"
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diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt
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new file mode 100644
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index 0000000000000000000000000000000000000000..18856746656058651c571ecbb3708e0543b19d62
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GIT binary patch
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literal 6144
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zcmeHKU2GiH75-*tc6WAmW_LYygMSkDB*E^Q*zv5f7dLg)@$NQV2a{}!yImnfyvQ4D
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z;n-$v0!RpNi<_o@ktI-@2a590stC0zRi%iRR%stvi&hAs3R<K}X~hFddB_6@s8W`5
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zXJ!q~E{TOme<a`8@BW;7?l<?GIp@yo&H2<M-FZ0GKbBAR-Ekx}HvVOrhK1*2?{QsU
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zQe#K%JeC=q96gpAKa#$keu^D99ee*0FfB=@F_0J<9-Ch-&BZ5r1T6`{$;1%Fm+qfk
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zTr5pfAz@KB*NGlFzEGx2aqh%IxkQOuX*`{wy~+KQo+-}XSE7aaxko77OBtFgoh;4K
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z(#-7f<x+WxmKSK)vQFgtt^L+?s+Z<V57E7|^TqOPX{mn0n<VLl#Yf7s_suL*Jl#VB
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zmSyz~ScwEVTc-3vd2v6D&dt$;&{?91(o(5>vNXNl&<qW@AghW5NPYw#ha~-b0Dc7_
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z6}t(eHgpwn6<HNi1Vcp^p-07-iXve~MTs!0A_ku!`4nKciajxJYXsOYuuT4N%smA!
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zPazgl&bNRSrvAz|_6r3+B;r1=!7D;RUUw8Ke+vNt7E3`(BA-woPvJFBK^3Gzfh4Nk
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zOX!J0PJNB)Mk&Z_i?S2ez+iItz=)m79LydX&rM9`3wPaJ`T92=Uv0;g-!<4*M6z%+
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z*omwb#VI+CU&%iFS{_DGS;sE}7G4juqRMCww!+k6=+abJj4v>Dsr*z_6HAP5GJeST
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znX2JD;{xLa#;c6KGychVn-L6YXkv6Qx)}Y8&ok1DI~ZSM6dCt39%QUAzRh@o@gqjy
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zL0qZ&DhN8ZR3xu$a$Cd{oasU3DNp{CCl6f~PYlq!Hte;Ia0^wn8Vut7>Wl1)s`^E-
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z1DhGx<x<9D%6jd%)5>zr8&7h}dMJ3~YBe;)!vVf-T&?{PoMvvRR{!67;Xhz^g^loX
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zja+*c-KJJoxbsm3pTE4THs`cgD{Pt+ga3en-i$P#9Wsra(oqRMr;H$4{gxr)9eF(x
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zg0v@a7aj}rA^Kf#sNb*>at^>P)5li%ycOq*4e;3~RUj$i1e8=rHi&<Y^Hc>Y_gP4=
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zxz9^%q0dLXqC&Bq<&sDScZwvatjRxB=rcJJiYb?w#4Iy2KTk1F6T>T}E@(DNGa>5R
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z7&Yv)JdHrRI};pfsKLVj=FE=U*=*T4#ncVktknoGelT||SDY`+9WI_IZE<i@7SnC8
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zN6~Gyo=&><wpzE~>`_>@wb<-RI-lu(_~Oy_Zo6={Cdq!uw(fmyz_u^cB&~5IS7g`U
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zdUC}N$J5-C)|`CfUO+?xptr@*hJW$ZhBZk%JaMh_<8!ZGj)z*WU9fcg2`>dT##_?q
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z=Ksx}uxo3jTHTq%E1}97UECE@r}nt3I=3R(HOL7jNg>teSM-g$aU#`3jk}#qh;D?6
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zw=CYuA2#mS+vU%0P&u8RCn4)$8VH-2uy#01%VG0WSX&Fz`LMYj)?N<NyJ1t)wHBQY
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z=;pYt<#l>gH_zzWS)G2Pn=k3wYdU|DnWmxbG$>`5lZJMWL92%O14BD!(C-cNFNXFH
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zgVc!G9?@=&(4mNVcSJiLq3=b^rz6@k5qdFVUW{m$A{2|7d!kxz)VSrcQt@4sDoq^f
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z98hXm=YS~qbf<kwigD|YevaR}^`7Jy^x~4_g75ka=c0r}VJF2aEv{=ilPf-mNQBNI
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zEMK3YKB+`*xOu>iR|LbzHLa*mLXlH${^b4c9%>9%)HO-?LA1gT0mlz!M}8&;(;^x|
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z*H2<VyY>2;juB|7F+k?y(_2~3@STqQ@f^sqD2c8g3x>ciM%siMq~;pKwfE57kw2K@
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z!-ZN0QTVOP@aA5@fEGKjy2+D`t?2KzpPyRQ`JcmHJoc(<#h<UT;@W$t_d{|;S>vyF
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zewtgef*II~y;k>*B!+(8*blXsY-~kcJa9zG2yfcMCt+|-0ex$pY`h1<*#rEv=~*<+
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ztV``Um!q33-Aap9fUshX^N~GS2@X3^U9+MwgYQ74^?~6&yU^#oY#cvC9R_}P2d<wN
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zJvOE)Xr7A2n#3x14}2_g(YN^0+oYDbb#|V{ze3pzGb9FiF#6Ra&L}bT(ZOvswS7RY
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zxLjWFRwWXHR5&={t;%K+Vkd6NX2iF<SF)LXv@y472OmG!_W%Ni*ZDuev-S0%b!dfW
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wz4{IL!+uT9t2XI4@_L@?Ri*bc_<n8A+wHaowmq=zfo%_LdtloGpN<DU00~N<ApigX
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literal 0
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HcmV?d00001
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diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
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new file mode 100644
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index 0000000000..ff83db095b
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--- /dev/null
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+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
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@@ -0,0 +1,14 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+#include <bootblock_common.h>
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+#include <device/pci_ops.h>
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+#include <ec/dell/mec5035/mec5035.h>
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+#include <southbridge/intel/bd82x6x/pch.h>
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+
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+void bootblock_mainboard_early_init(void)
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+{
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+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
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+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
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+ | COMB_LPC_EN | COMA_LPC_EN);
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+ mec5035_early_init();
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+}
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diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
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new file mode 100644
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index 0000000000..777570765a
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--- /dev/null
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+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
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@@ -0,0 +1,192 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+#include <southbridge/intel/common/gpio.h>
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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+ .gpio0 = GPIO_MODE_GPIO,
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+ .gpio1 = GPIO_MODE_GPIO,
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+ .gpio2 = GPIO_MODE_GPIO,
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+ .gpio3 = GPIO_MODE_GPIO,
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+ .gpio4 = GPIO_MODE_GPIO,
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+ .gpio5 = GPIO_MODE_NATIVE,
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+ .gpio6 = GPIO_MODE_GPIO,
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+ .gpio7 = GPIO_MODE_GPIO,
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+ .gpio8 = GPIO_MODE_GPIO,
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+ .gpio9 = GPIO_MODE_NATIVE,
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+ .gpio10 = GPIO_MODE_NATIVE,
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+ .gpio11 = GPIO_MODE_NATIVE,
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+ .gpio12 = GPIO_MODE_NATIVE,
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+ .gpio13 = GPIO_MODE_GPIO,
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+ .gpio14 = GPIO_MODE_GPIO,
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+ .gpio15 = GPIO_MODE_GPIO,
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+ .gpio16 = GPIO_MODE_GPIO,
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+ .gpio17 = GPIO_MODE_GPIO,
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+ .gpio18 = GPIO_MODE_NATIVE,
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+ .gpio19 = GPIO_MODE_GPIO,
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+ .gpio20 = GPIO_MODE_NATIVE,
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+ .gpio21 = GPIO_MODE_GPIO,
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+ .gpio22 = GPIO_MODE_GPIO,
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+ .gpio23 = GPIO_MODE_NATIVE,
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+ .gpio24 = GPIO_MODE_GPIO,
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+ .gpio25 = GPIO_MODE_NATIVE,
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+ .gpio26 = GPIO_MODE_NATIVE,
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+ .gpio27 = GPIO_MODE_GPIO,
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+ .gpio28 = GPIO_MODE_GPIO,
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+ .gpio29 = GPIO_MODE_GPIO,
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+ .gpio30 = GPIO_MODE_NATIVE,
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+ .gpio31 = GPIO_MODE_NATIVE,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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+ .gpio0 = GPIO_DIR_INPUT,
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+ .gpio1 = GPIO_DIR_INPUT,
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+ .gpio2 = GPIO_DIR_INPUT,
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+ .gpio3 = GPIO_DIR_INPUT,
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+ .gpio4 = GPIO_DIR_INPUT,
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+ .gpio6 = GPIO_DIR_INPUT,
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+ .gpio7 = GPIO_DIR_INPUT,
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+ .gpio8 = GPIO_DIR_INPUT,
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+ .gpio13 = GPIO_DIR_INPUT,
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+ .gpio14 = GPIO_DIR_INPUT,
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+ .gpio15 = GPIO_DIR_INPUT,
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+ .gpio16 = GPIO_DIR_INPUT,
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+ .gpio17 = GPIO_DIR_INPUT,
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+ .gpio19 = GPIO_DIR_INPUT,
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+ .gpio21 = GPIO_DIR_INPUT,
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+ .gpio22 = GPIO_DIR_INPUT,
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+ .gpio24 = GPIO_DIR_INPUT,
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+ .gpio27 = GPIO_DIR_INPUT,
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+ .gpio28 = GPIO_DIR_OUTPUT,
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+ .gpio29 = GPIO_DIR_INPUT,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_level = {
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+ .gpio28 = GPIO_LEVEL_LOW,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
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+ .gpio30 = GPIO_RESET_RSMRST,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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+ .gpio0 = GPIO_INVERT,
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+ .gpio8 = GPIO_INVERT,
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+ .gpio13 = GPIO_INVERT,
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+ .gpio14 = GPIO_INVERT,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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+ .gpio32 = GPIO_MODE_NATIVE,
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+ .gpio33 = GPIO_MODE_GPIO,
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+ .gpio34 = GPIO_MODE_GPIO,
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+ .gpio35 = GPIO_MODE_GPIO,
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+ .gpio36 = GPIO_MODE_GPIO,
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+ .gpio37 = GPIO_MODE_GPIO,
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+ .gpio38 = GPIO_MODE_GPIO,
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+ .gpio39 = GPIO_MODE_GPIO,
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+ .gpio40 = GPIO_MODE_NATIVE,
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+ .gpio41 = GPIO_MODE_NATIVE,
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+ .gpio42 = GPIO_MODE_NATIVE,
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+ .gpio43 = GPIO_MODE_NATIVE,
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+ .gpio44 = GPIO_MODE_NATIVE,
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+ .gpio45 = GPIO_MODE_GPIO,
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+ .gpio46 = GPIO_MODE_NATIVE,
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+ .gpio47 = GPIO_MODE_NATIVE,
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+ .gpio48 = GPIO_MODE_GPIO,
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+ .gpio49 = GPIO_MODE_GPIO,
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+ .gpio50 = GPIO_MODE_NATIVE,
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+ .gpio51 = GPIO_MODE_GPIO,
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+ .gpio52 = GPIO_MODE_GPIO,
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+ .gpio53 = GPIO_MODE_NATIVE,
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+ .gpio54 = GPIO_MODE_GPIO,
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+ .gpio55 = GPIO_MODE_NATIVE,
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+ .gpio56 = GPIO_MODE_NATIVE,
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+ .gpio57 = GPIO_MODE_GPIO,
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+ .gpio58 = GPIO_MODE_NATIVE,
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+ .gpio59 = GPIO_MODE_NATIVE,
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+ .gpio60 = GPIO_MODE_GPIO,
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+ .gpio61 = GPIO_MODE_NATIVE,
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+ .gpio62 = GPIO_MODE_NATIVE,
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+ .gpio63 = GPIO_MODE_NATIVE,
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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+ .gpio33 = GPIO_DIR_INPUT,
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+ .gpio34 = GPIO_DIR_OUTPUT,
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+ .gpio35 = GPIO_DIR_INPUT,
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+ .gpio36 = GPIO_DIR_INPUT,
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+ .gpio37 = GPIO_DIR_INPUT,
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+ .gpio38 = GPIO_DIR_INPUT,
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+ .gpio39 = GPIO_DIR_INPUT,
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+ .gpio45 = GPIO_DIR_OUTPUT,
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+ .gpio48 = GPIO_DIR_INPUT,
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+ .gpio49 = GPIO_DIR_INPUT,
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+ .gpio51 = GPIO_DIR_INPUT,
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+ .gpio52 = GPIO_DIR_INPUT,
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+ .gpio54 = GPIO_DIR_INPUT,
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+ .gpio57 = GPIO_DIR_INPUT,
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+ .gpio60 = GPIO_DIR_OUTPUT,
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_level = {
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+ .gpio34 = GPIO_LEVEL_HIGH,
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+ .gpio45 = GPIO_LEVEL_LOW,
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+ .gpio60 = GPIO_LEVEL_HIGH,
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
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+};
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+
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+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
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+ .gpio64 = GPIO_MODE_NATIVE,
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+ .gpio65 = GPIO_MODE_NATIVE,
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+ .gpio66 = GPIO_MODE_NATIVE,
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+ .gpio67 = GPIO_MODE_NATIVE,
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+ .gpio68 = GPIO_MODE_GPIO,
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+ .gpio69 = GPIO_MODE_GPIO,
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+ .gpio70 = GPIO_MODE_GPIO,
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+ .gpio71 = GPIO_MODE_GPIO,
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+ .gpio72 = GPIO_MODE_NATIVE,
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+ .gpio73 = GPIO_MODE_NATIVE,
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+ .gpio74 = GPIO_MODE_NATIVE,
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+ .gpio75 = GPIO_MODE_NATIVE,
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|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
|
+ .gpio68 = GPIO_DIR_INPUT,
|
|
+ .gpio69 = GPIO_DIR_INPUT,
|
|
+ .gpio70 = GPIO_DIR_INPUT,
|
|
+ .gpio71 = GPIO_DIR_INPUT,
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
|
+};
|
|
+
|
|
+const struct pch_gpio_map mainboard_gpio_map = {
|
|
+ .set1 = {
|
|
+ .mode = &pch_gpio_set1_mode,
|
|
+ .direction = &pch_gpio_set1_direction,
|
|
+ .level = &pch_gpio_set1_level,
|
|
+ .blink = &pch_gpio_set1_blink,
|
|
+ .invert = &pch_gpio_set1_invert,
|
|
+ .reset = &pch_gpio_set1_reset,
|
|
+ },
|
|
+ .set2 = {
|
|
+ .mode = &pch_gpio_set2_mode,
|
|
+ .direction = &pch_gpio_set2_direction,
|
|
+ .level = &pch_gpio_set2_level,
|
|
+ .reset = &pch_gpio_set2_reset,
|
|
+ },
|
|
+ .set3 = {
|
|
+ .mode = &pch_gpio_set3_mode,
|
|
+ .direction = &pch_gpio_set3_direction,
|
|
+ .level = &pch_gpio_set3_level,
|
|
+ .reset = &pch_gpio_set3_reset,
|
|
+ },
|
|
+};
|
|
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
|
|
new file mode 100644
|
|
index 0000000000..804733b172
|
|
--- /dev/null
|
|
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
|
|
@@ -0,0 +1,32 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0-only */
|
|
+
|
|
+#include <device/azalia_device.h>
|
|
+
|
|
+const u32 cim_verb_data[] = {
|
|
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
|
|
+ 0x10280533, /* Subsystem ID */
|
|
+ 11, /* Number of 4 dword sets */
|
|
+ AZALIA_SUBVENDOR(0, 0x10280533),
|
|
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
|
|
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
|
|
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
|
|
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
|
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
|
|
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
|
|
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
|
|
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
|
|
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
|
|
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
|
|
+
|
|
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
|
|
+ 0x80860101, /* Subsystem ID */
|
|
+ 4, /* Number of 4 dword sets */
|
|
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
|
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
|
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
|
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
|
+};
|
|
+
|
|
+const u32 pc_beep_verbs[0] = {};
|
|
+
|
|
+AZALIA_ARRAY_SIZES;
|
|
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
|
|
new file mode 100644
|
|
index 0000000000..4125159367
|
|
--- /dev/null
|
|
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
|
|
@@ -0,0 +1,37 @@
|
|
+## SPDX-License-Identifier: GPL-2.0-or-later
|
|
+
|
|
+chip northbridge/intel/sandybridge
|
|
+ device domain 0 on
|
|
+ subsystemid 0x1028 0x0533 inherit
|
|
+
|
|
+ device ref igd on
|
|
+ register "gpu_cpu_backlight" = "0x00001312"
|
|
+ register "gpu_pch_backlight" = "0x13121312"
|
|
+ end
|
|
+
|
|
+ chip southbridge/intel/bd82x6x
|
|
+ register "usb_port_config" = "{
|
|
+ { 1, 2, 0 },
|
|
+ { 1, 0, 0 },
|
|
+ { 1, 0, 1 },
|
|
+ { 1, 1, 1 },
|
|
+ { 1, 1, 2 },
|
|
+ { 1, 1, 2 },
|
|
+ { 1, 2, 3 },
|
|
+ { 1, 2, 3 },
|
|
+ { 1, 2, 4 },
|
|
+ { 1, 1, 4 },
|
|
+ { 1, 1, 5 },
|
|
+ { 1, 1, 5 },
|
|
+ { 1, 2, 6 },
|
|
+ { 1, 0, 6 },
|
|
+ }"
|
|
+
|
|
+ device ref xhci on
|
|
+ register "superspeed_capable_ports" = "0x0000000f"
|
|
+ register "xhci_overcurrent_mapping" = "0x00000c03"
|
|
+ register "xhci_switchable_ports" = "0x0000000f"
|
|
+ end
|
|
+ end
|
|
+ end
|
|
+end
|
|
--
|
|
2.39.2
|
|
|