250 lines
8.7 KiB
Diff
250 lines
8.7 KiB
Diff
From adde2e8d038b2d07ab7287eedab5888d92a56a60 Mon Sep 17 00:00:00 2001
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From: Angel Pons <th3fanbus@gmail.com>
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Date: Sat, 7 May 2022 16:29:55 +0200
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Subject: [PATCH 02/17] haswell NRI: Post-process selected timings
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Once the MPLL has been initialised, convert the timings from the SPD to
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be in DCLKs, which is what the hardware expects. In addition, calculate
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the values for tREFI and tXP.
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Change-Id: Id02caf858f75b9e08016762b3aefda282b274386
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Signed-off-by: Angel Pons <th3fanbus@gmail.com>
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---
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.../intel/haswell/native_raminit/Makefile.mk | 1 +
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.../haswell/native_raminit/lookup_timings.c | 62 +++++++++++
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.../haswell/native_raminit/raminit_main.c | 1 +
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.../haswell/native_raminit/raminit_native.h | 8 ++
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.../haswell/native_raminit/spd_bitmunching.c | 100 ++++++++++++++++++
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5 files changed, 172 insertions(+)
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create mode 100644 src/northbridge/intel/haswell/native_raminit/lookup_timings.c
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diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
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index c125d84f0b..2769e0bbb4 100644
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--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
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+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
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@@ -1,5 +1,6 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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+romstage-y += lookup_timings.c
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romstage-y += init_mpll.c
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romstage-y += io_comp_control.c
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romstage-y += raminit_main.c
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diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
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new file mode 100644
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index 0000000000..8b81c7c341
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--- /dev/null
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+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
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@@ -0,0 +1,62 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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+
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+#include <commonlib/bsd/clamp.h>
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+#include <types.h>
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+
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+#include "raminit_native.h"
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+
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+struct timing_lookup {
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+ uint32_t clock;
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+ uint32_t value;
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+};
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+
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+static uint32_t lookup_timing(
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+ const uint32_t mem_clock_mhz,
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+ const struct timing_lookup *const lookup,
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+ const size_t length)
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+{
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+ /* Fall back to the last index */
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+ size_t i;
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+ for (i = 0; i < length - 1; i++) {
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+ /* Account for imprecise frequency values */
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+ if ((mem_clock_mhz - 5) <= lookup[i].clock)
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+ break;
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+ }
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+ return lookup[i].value;
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+}
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+
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+static const uint32_t fmax = UINT32_MAX;
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+
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+uint8_t get_tCWL(const uint32_t mem_clock_mhz)
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+{
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+ const struct timing_lookup lut[] = {
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+ { 400, 5 },
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+ { 533, 6 },
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+ { 666, 7 },
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+ { 800, 8 },
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+ { 933, 9 },
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+ { 1066, 10 },
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+ { 1200, 11 },
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+ { fmax, 12 },
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+ };
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+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
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+}
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+
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+/* tREFI = 7800 ns * DDR MHz */
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+uint32_t get_tREFI(const uint32_t mem_clock_mhz)
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+{
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+ return (mem_clock_mhz * 7800) / 1000;
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+}
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+
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+uint32_t get_tXP(const uint32_t mem_clock_mhz)
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+{
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+ const struct timing_lookup lut[] = {
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+ { 400, 3 },
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+ { 666, 4 },
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+ { 800, 5 },
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+ { 933, 6 },
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+ { 1066, 7 },
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+ { fmax, 8 },
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+ };
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+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
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+}
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diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
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index bf745e943f..2fea658415 100644
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--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
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+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
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@@ -21,6 +21,7 @@ struct task_entry {
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static const struct task_entry cold_boot[] = {
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{ collect_spd_info, true, "PROCSPD", },
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{ initialise_mpll, true, "INITMPLL", },
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+ { convert_timings, true, "CONVTIM", },
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};
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/* Return a generic stepping value to make stepping checks simpler */
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diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
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index 15a1550424..e0ebd3a2a7 100644
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--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
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+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
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@@ -79,6 +79,9 @@ struct sysinfo {
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uint32_t tCWL;
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uint32_t tCMD;
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+ uint32_t tREFI;
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+ uint32_t tXP;
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+
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uint8_t lanes; /* 8 or 9 */
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uint8_t chanmap;
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uint8_t dpc[NUM_CHANNELS]; /* DIMMs per channel */
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@@ -97,7 +100,12 @@ void raminit_main(enum raminit_boot_mode bootmode);
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enum raminit_status collect_spd_info(struct sysinfo *ctrl);
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enum raminit_status initialise_mpll(struct sysinfo *ctrl);
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+enum raminit_status convert_timings(struct sysinfo *ctrl);
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enum raminit_status wait_for_first_rcomp(void);
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+uint8_t get_tCWL(uint32_t mem_clock_mhz);
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+uint32_t get_tREFI(uint32_t mem_clock_mhz);
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+uint32_t get_tXP(uint32_t mem_clock_mhz);
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+
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#endif
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diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
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index eff993800b..4f7fe46494 100644
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--- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
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+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
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@@ -204,3 +204,103 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl)
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get_spd_data(ctrl);
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return find_common_spd_parameters(ctrl);
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}
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+
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+#define MIN_CWL 5
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+#define MAX_CWL 12
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+
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+/* Except for tCK, hardware expects all timing values in DCLKs, not nanoseconds */
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+enum raminit_status convert_timings(struct sysinfo *ctrl)
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+{
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+ /*
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+ * Obtain all required timing values, in DCLKs.
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+ */
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+
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+ /* Convert primary timings from nanoseconds to DCLKs */
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+ ctrl->tAA = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK);
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+ ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK);
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+ ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK);
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+ ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK);
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+ ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK);
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+ ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK);
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+ ctrl->tRC = DIV_ROUND_UP(ctrl->tRC, ctrl->tCK);
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+ ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK);
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+ ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);
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+ ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK);
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+ ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK);
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+ ctrl->tCWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);
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+ ctrl->tCMD = DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK);
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+
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+ /* Constrain primary timings to hardware limits */
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+ /** TODO: complain when clamping? **/
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+ ctrl->tAA = clamp_u32(4, ctrl->tAA, 24);
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+ ctrl->tWR = clamp_u32(5, ctrl->tWR, 16);
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+ ctrl->tRCD = clamp_u32(4, ctrl->tRCD, 20);
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+ ctrl->tRRD = clamp_u32(4, ctrl->tRRD, 65535);
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+ ctrl->tRP = clamp_u32(4, ctrl->tRP, 15);
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+ ctrl->tRAS = clamp_u32(10, ctrl->tRAS, 40);
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+ ctrl->tRC = clamp_u32(1, ctrl->tRC, 4095);
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+ ctrl->tRFC = clamp_u32(1, ctrl->tRFC, 511);
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+ ctrl->tWTR = clamp_u32(4, ctrl->tWTR, 10);
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+ ctrl->tRTP = clamp_u32(4, ctrl->tRTP, 15);
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+ ctrl->tFAW = clamp_u32(10, ctrl->tFAW, 54);
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+
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+ /** TODO: Honor tREFI from XMP **/
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+ ctrl->tREFI = get_tREFI(ctrl->mem_clock_mhz);
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+ ctrl->tXP = get_tXP(ctrl->mem_clock_mhz);
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+
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+ /*
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+ * Check some values, and adjust them if necessary.
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+ */
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+
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+ /* If tWR cannot be written into DDR3 MR0, adjust it */
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+ switch (ctrl->tWR) {
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+ case 9:
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+ case 11:
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+ case 13:
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+ case 15:
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+ ctrl->tWR++;
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+ }
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+
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+ /* If tCWL is not supported or unspecified, look up a reasonable default */
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+ if (ctrl->tCWL < MIN_CWL || ctrl->tCWL > MAX_CWL)
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+ ctrl->tCWL = get_tCWL(ctrl->mem_clock_mhz);
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+
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+ /* This is needed to support ODT properly on 2DPC */
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+ if (ctrl->tAA - ctrl->tCWL > 4)
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+ ctrl->tCWL = ctrl->tAA - 4;
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+
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+ /* If tCMD is invalid, use a guesstimate default */
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+ if (!ctrl->tCMD) {
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+ ctrl->tCMD = MAX(ctrl->dpc[0], ctrl->dpc[1]);
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+ printk(RAM_DEBUG, "tCMD was zero, picking a guesstimate value\n");
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+ }
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+ ctrl->tCMD = clamp_u32(1, ctrl->tCMD, 3);
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+
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+ /*
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+ * Print final timings.
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+ */
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+
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+ /* tCK is special */
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+ printk(BIOS_DEBUG, "Selected tCK : %u ps\n", ctrl->tCK * 1000 / 256);
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+
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+ /* Primary timings */
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+ printk(BIOS_DEBUG, "Selected tAA : %uT\n", ctrl->tAA);
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+ printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR);
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+ printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD);
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+ printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD);
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+ printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP);
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+ printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS);
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+ printk(BIOS_DEBUG, "Selected tRC : %uT\n", ctrl->tRC);
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+ printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC);
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+ printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR);
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+ printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP);
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+ printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW);
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+ printk(BIOS_DEBUG, "Selected tCWL : %uT\n", ctrl->tCWL);
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+ printk(BIOS_DEBUG, "Selected tCMD : %uT\n", ctrl->tCMD);
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+
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+ /* Derived timings */
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+ printk(BIOS_DEBUG, "Selected tREFI : %uT\n", ctrl->tREFI);
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+ printk(BIOS_DEBUG, "Selected tXP : %uT\n", ctrl->tXP);
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+
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+ return RAMINIT_STATUS_SUCCESS;
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+}
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--
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2.39.2
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