477 lines
18 KiB
Diff
477 lines
18 KiB
Diff
From 8528c7aa2a3cfcf0fe494a515a2e531ff0f1dab8 Mon Sep 17 00:00:00 2001
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From: Angel Pons <th3fanbus@gmail.com>
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Date: Wed, 17 Apr 2024 13:20:32 +0200
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Subject: [PATCH 17/17] haswell NRI: Do sense amplifier offset training
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Quoting Wikipedia:
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A sense amplifier is a circuit that is used to amplify and detect
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small signals in electronic systems. It is commonly used in memory
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circuits, such as dynamic random access memory (DRAM), to read and
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amplify the weak signals stored in memory cells.
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In this case, we're calibrating the sense amplifiers in the memory
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controller. This training procedure uses a magic "sense amp offset
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cancel" mode of the DDRIO to observe the sampled logic levels, and
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sweeps Vref to find the low-high transition for each bit lane. The
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procedure consists of two stages: the first stage centers per-byte
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Vref (to ensure per-bit Vref offsets are as small as possible) and
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the second stage centers per-bit Vref.
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Because this procedure uses the "sense amp offset cancel" mode, it
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does not rely on DRAM being trained. It is assumed that the memory
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controller simply makes sense amp output levels observable via the
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`DDR_DATA_TRAIN_FEEDBACK` register and that the memory bus is idle
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during this training step (so the lane voltage is Vdd / 2).
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Note: This procedure will need to be adapted for Broadwell because
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it has per-rank per-bit RxVref registers, whereas Haswell only has
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a single per-bit RxVref register for all ranks.
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Change-Id: Ia07db68763f90e9701c8a376e01279ada8dbbe07
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Signed-off-by: Angel Pons <th3fanbus@gmail.com>
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---
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.../intel/haswell/native_raminit/Makefile.mk | 1 +
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.../haswell/native_raminit/raminit_main.c | 1 +
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.../haswell/native_raminit/raminit_native.h | 12 +
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.../native_raminit/train_sense_amp_offset.c | 341 ++++++++++++++++++
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.../intel/haswell/registers/mchbar.h | 2 +
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5 files changed, 357 insertions(+)
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create mode 100644 src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
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diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
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index 8fdd17c542..4bd668a2d6 100644
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--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
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+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
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@@ -21,3 +21,4 @@ romstage-y += timings_refresh.c
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romstage-y += train_jedec_write_leveling.c
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romstage-y += train_read_mpr.c
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romstage-y += train_receive_enable.c
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+romstage-y += train_sense_amp_offset.c
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diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
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index 056dde1adc..ce637e2d03 100644
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--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
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+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
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@@ -60,6 +60,7 @@ static const struct task_entry cold_boot[] = {
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{ configure_memory_map, true, "MEMMAP", },
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{ do_jedec_init, true, "JEDECINIT", },
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{ pre_training, true, "PRETRAIN", },
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+ { train_sense_amp_offset, true, "SOT", },
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{ train_receive_enable, true, "RCVET", },
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{ train_read_mpr, true, "RDMPRT", },
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{ train_jedec_write_leveling, true, "JWRL", },
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diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
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index 2ac16eaad3..07eea98831 100644
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--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
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+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
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@@ -23,6 +23,8 @@
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#define NUM_LANES 9
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#define NUM_LANES_NO_ECC 8
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+#define NUM_BITS 8
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+
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#define COMP_INT 10
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/* Always use 12 legs for emphasis (not trained) */
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@@ -219,6 +221,7 @@ enum raminit_status {
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RAMINIT_STATUS_MPLL_INIT_FAILURE,
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RAMINIT_STATUS_POLL_TIMEOUT,
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RAMINIT_STATUS_REUT_ERROR,
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+ RAMINIT_STATUS_SAMP_OFFSET_FAILURE,
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RAMINIT_STATUS_RCVEN_FAILURE,
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RAMINIT_STATUS_RMPR_FAILURE,
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RAMINIT_STATUS_JWRL_FAILURE,
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@@ -244,6 +247,12 @@ struct raminit_dimm_info {
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bool valid;
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};
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+struct vref_margin {
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+ uint8_t low;
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+ uint8_t center;
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+ uint8_t high;
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+};
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+
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struct sysinfo {
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enum raminit_boot_mode bootmode;
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enum generic_stepping stepping;
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@@ -331,6 +340,8 @@ struct sysinfo {
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uint8_t rxdqsn[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
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int8_t rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
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+ struct vref_margin rxdqvrefpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS];
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+
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uint8_t clk_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
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uint8_t ctl_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
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uint8_t cke_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
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@@ -453,6 +464,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
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enum raminit_status configure_mc(struct sysinfo *ctrl);
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enum raminit_status configure_memory_map(struct sysinfo *ctrl);
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enum raminit_status do_jedec_init(struct sysinfo *ctrl);
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+enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl);
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enum raminit_status train_receive_enable(struct sysinfo *ctrl);
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enum raminit_status train_read_mpr(struct sysinfo *ctrl);
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enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
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diff --git a/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
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new file mode 100644
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index 0000000000..d4f199fefb
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--- /dev/null
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+++ b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
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@@ -0,0 +1,341 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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+
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+#include <assert.h>
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+#include <commonlib/bsd/clamp.h>
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+#include <console/console.h>
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+#include <delay.h>
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+#include <lib.h>
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+#include <types.h>
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+
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+#include "raminit_native.h"
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+
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+#define VREF_OFFSET_PLOT RAM_DEBUG
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+#define SAMP_OFFSET_PLOT RAM_DEBUG
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+
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+struct vref_train_data {
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+ int8_t best_sum;
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+ int8_t best_vref;
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+ int8_t sum_bits;
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+ uint8_t high_mask;
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+ uint8_t low_mask;
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+};
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+
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+static enum raminit_status train_vref_offset(struct sysinfo *ctrl)
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+{
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+ const int8_t vref_start = -15;
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+ const int8_t vref_stop = 15;
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+ const struct vref_train_data initial_vref_values = {
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+ .best_sum = -NUM_LANES,
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+ .best_vref = 0,
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+ .high_mask = 0,
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+ .low_mask = 0xff,
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+ };
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+ struct vref_train_data vref_data[NUM_CHANNELS][NUM_LANES];
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+
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+ printk(VREF_OFFSET_PLOT, "Plot of sum_bits across Vref settings\nChannel");
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+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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+ if (!does_ch_exist(ctrl, channel))
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+ continue;
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+
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+ printk(VREF_OFFSET_PLOT, "\t%u\t\t", channel);
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+ }
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+
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+ printk(VREF_OFFSET_PLOT, "\nByte");
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+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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+ if (!does_ch_exist(ctrl, channel))
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+ continue;
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+
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+ printk(VREF_OFFSET_PLOT, "\t");
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+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
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+ printk(VREF_OFFSET_PLOT, "%u ", byte);
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+ vref_data[channel][byte] = initial_vref_values;
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+ union ddr_data_control_2_reg data_control_2 = {
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+ .raw = ctrl->dq_control_2[channel][byte],
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+ };
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+ data_control_2.force_bias_on = 1;
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+ data_control_2.force_rx_on = 1;
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+ mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
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+ }
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+ }
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+
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+ /* Sweep through Vref settings and find point SampOffset of +/- 7 passes */
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+ printk(VREF_OFFSET_PLOT, "\n1/2 Vref");
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+ for (int8_t vref = vref_start; vref <= vref_stop; vref++) {
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+ printk(VREF_OFFSET_PLOT, "\n% 3d", vref);
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+
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+ /*
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+ * To perform this test, enable offset cancel mode and enable ODT.
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+ * Check results and update variables. Ideal result is all zeroes.
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+ * Clear offset cancel mode at end of test to write RX_OFFSET_VDQ.
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+ */
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+ change_1d_margin_multicast(ctrl, RdV, vref, 0, false, REG_FILE_USE_RANK);
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+
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+ /* Program settings for Vref and SampOffset = 7 (8 + 7) */
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+ mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0xffffffff);
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+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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+ if (!does_ch_exist(ctrl, channel))
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+ continue;
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+
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+ /* Propagate delay values (without a read command) */
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+ union ddr_data_control_0_reg data_control_0 = {
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+ .raw = ctrl->dq_control_0[channel],
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+ };
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+ data_control_0.read_rf_rd = 1;
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+ data_control_0.read_rf_wr = 0;
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+ data_control_0.read_rf_rank = 0;
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+ data_control_0.force_odt_on = 1;
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+ data_control_0.samp_train_mode = 1;
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+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
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+ udelay(1);
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+ data_control_0.samp_train_mode = 0;
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+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
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+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
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+ const uint8_t feedback = get_data_train_feedback(channel, byte);
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+ struct vref_train_data *curr_data = &vref_data[channel][byte];
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+ curr_data->low_mask &= feedback;
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+ curr_data->sum_bits = -popcnt(feedback);
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+ }
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+ }
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+
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+ /* Program settings for Vref and SampOffset = -7 (8 - 7) */
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+ mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0x11111111);
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+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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+ if (!does_ch_exist(ctrl, channel))
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+ continue;
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+
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+ /* Propagate delay values (without a read command) */
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+ union ddr_data_control_0_reg data_control_0 = {
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+ .raw = ctrl->dq_control_0[channel],
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+ };
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+ data_control_0.read_rf_rd = 1;
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+ data_control_0.read_rf_wr = 0;
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+ data_control_0.read_rf_rank = 0;
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+ data_control_0.force_odt_on = 1;
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+ data_control_0.samp_train_mode = 1;
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+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
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+ udelay(1);
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+ data_control_0.samp_train_mode = 0;
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+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
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+ printk(VREF_OFFSET_PLOT, "\t");
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+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
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+ const uint8_t feedback = get_data_train_feedback(channel, byte);
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+ struct vref_train_data *curr_data = &vref_data[channel][byte];
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+ curr_data->high_mask |= feedback;
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+ curr_data->sum_bits += popcnt(feedback);
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+ printk(VREF_OFFSET_PLOT, "%d ", curr_data->sum_bits);
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+ if (curr_data->sum_bits > curr_data->best_sum) {
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+ curr_data->best_sum = curr_data->sum_bits;
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+ curr_data->best_vref = vref;
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+ ctrl->rxvref[channel][0][byte] = vref;
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+ } else if (curr_data->sum_bits == curr_data->best_sum) {
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+ curr_data->best_vref = vref;
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+ }
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+ }
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+ }
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+ }
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+ printk(BIOS_DEBUG, "\n\nHi-Lo (XOR):");
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+ enum raminit_status status = RAMINIT_STATUS_SUCCESS;
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+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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+ if (!does_ch_exist(ctrl, channel))
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+ continue;
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+
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+ printk(BIOS_DEBUG, "\n C%u:", channel);
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+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
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+ struct vref_train_data *const curr_data = &vref_data[channel][byte];
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+ const uint8_t bit_xor = curr_data->high_mask ^ curr_data->low_mask;
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+ printk(BIOS_DEBUG, "\t0x%02x", bit_xor);
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+ if (bit_xor == 0xff)
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+ continue;
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+
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+ /* Report an error if any bit did not change */
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+ status = RAMINIT_STATUS_SAMP_OFFSET_FAILURE;
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+ }
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+ }
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+ if (status)
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+ printk(BIOS_ERR, "\nUnexpected bit error in Vref offset training\n");
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+
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+ printk(BIOS_DEBUG, "\n\nRdVref:");
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+ change_1d_margin_multicast(ctrl, RdV, 0, 0, false, REG_FILE_USE_RANK);
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+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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+ if (!does_ch_exist(ctrl, channel))
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+ continue;
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+
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+ printk(BIOS_DEBUG, "\n C%u:", channel);
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+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
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+ struct vref_train_data *const curr_data = &vref_data[channel][byte];
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+ const int8_t vref_width =
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+ curr_data->best_vref - ctrl->rxvref[channel][0][byte];
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+
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+ /*
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+ * Step size for Rx Vref in DATA_OFFSET_TRAIN is about 3.9 mV
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+ * whereas Rx Vref step size in RX_TRAIN_RANK is about 7.8 mV
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+ */
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+ int8_t vref = ctrl->rxvref[channel][0][byte] + vref_width / 2;
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+ if (vref < 0)
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+ vref--;
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+ else
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+ vref++;
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+
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+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
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+ if (!rank_in_ch(ctrl, rank, channel))
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+ continue;
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+
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+ ctrl->rxvref[channel][rank][byte] = vref / 2;
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+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
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+ }
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+ printk(BIOS_DEBUG, "\t% 4d", ctrl->rxvref[channel][0][byte]);
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+ }
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+ }
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+ printk(BIOS_DEBUG, "\n\n");
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+ return status;
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+}
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+
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+/**
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+ * LPDDR has an additional bit for DQS per each byte.
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+ *
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+ * TODO: The DQS value must be written into Data Control 2.
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+ */
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+#define NUM_OFFSET_TRAIN_BITS (NUM_BITS + 1)
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+
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+#define PLOT_CH_SPACE " "
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+
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+struct samp_train_data {
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+ uint8_t first_zero;
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+ uint8_t last_one;
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+};
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+
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+static void train_samp_offset(struct sysinfo *ctrl)
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+{
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+ const uint8_t max_train_bits = ctrl->lpddr ? NUM_OFFSET_TRAIN_BITS : NUM_BITS;
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+
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+ struct samp_train_data samp_data[NUM_CHANNELS][NUM_LANES][NUM_OFFSET_TRAIN_BITS] = {0};
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+
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+ printk(BIOS_DEBUG, "Channel ");
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+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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+ if (!does_ch_exist(ctrl, channel))
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+ continue;
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+
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+ printk(BIOS_DEBUG, "%u ", channel); /* Same length as PLOT_CH_SPACE */
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+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
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+ printk(BIOS_DEBUG, " %s ", ctrl->lpddr ? " " : "");
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+ }
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+ printk(BIOS_DEBUG, "\nByte ");
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+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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+ if (!does_ch_exist(ctrl, channel))
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+ continue;
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+
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+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
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+ printk(BIOS_DEBUG, "%u %s ", byte, ctrl->lpddr ? " " : "");
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+
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+ printk(BIOS_DEBUG, PLOT_CH_SPACE);
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+ }
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+ printk(SAMP_OFFSET_PLOT, "\nBits ");
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+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
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+ printk(SAMP_OFFSET_PLOT, "01234567%s ", ctrl->lpddr ? "S" : "");
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+
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+ printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE);
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+ }
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+ printk(SAMP_OFFSET_PLOT, "\n SAmp\n");
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+ for (uint8_t samp_offset = 1; samp_offset <= 15; samp_offset++) {
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+ printk(SAMP_OFFSET_PLOT, "% 5d\t", samp_offset);
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+
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+ uint32_t rx_offset_vdq = 0;
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+ for (uint8_t bit = 0; bit < NUM_BITS; bit++) {
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+ rx_offset_vdq += samp_offset << (4 * bit);
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+ }
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+ mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, rx_offset_vdq);
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+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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+ if (!does_ch_exist(ctrl, channel))
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+ continue;
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+
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+ /* Propagate delay values (without a read command) */
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+ union ddr_data_control_0_reg data_control_0 = {
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+ .raw = ctrl->dq_control_0[channel],
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+ };
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+ data_control_0.read_rf_rd = 1;
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+ data_control_0.read_rf_wr = 0;
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+ data_control_0.read_rf_rank = 0;
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+ data_control_0.force_odt_on = 1;
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+ data_control_0.samp_train_mode = 1;
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+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
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+ udelay(1);
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+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
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+ const uint32_t feedback =
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+ get_data_train_feedback(channel, byte);
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+
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+ for (uint8_t bit = 0; bit < max_train_bits; bit++) {
|
|
+ struct samp_train_data *const curr_data =
|
|
+ &samp_data[channel][byte][bit];
|
|
+ const bool result = feedback & BIT(bit);
|
|
+ if (result) {
|
|
+ curr_data->last_one = samp_offset;
|
|
+ } else if (curr_data->first_zero == 0) {
|
|
+ curr_data->first_zero = samp_offset;
|
|
+ }
|
|
+ printk(SAMP_OFFSET_PLOT, result ? "." : "#");
|
|
+ }
|
|
+ printk(SAMP_OFFSET_PLOT, " ");
|
|
+ }
|
|
+ printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE);
|
|
+ data_control_0.samp_train_mode = 0;
|
|
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
|
|
+ }
|
|
+ printk(SAMP_OFFSET_PLOT, "\n");
|
|
+ }
|
|
+ printk(BIOS_DEBUG, "\nBitSAmp ");
|
|
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
|
+ if (!does_ch_exist(ctrl, channel))
|
|
+ continue;
|
|
+
|
|
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
|
+ uint32_t rx_offset_vdq = 0;
|
|
+ for (uint8_t bit = 0; bit < max_train_bits; bit++) {
|
|
+ struct samp_train_data *const curr_data =
|
|
+ &samp_data[channel][byte][bit];
|
|
+
|
|
+ uint8_t vref = curr_data->first_zero + curr_data->last_one;
|
|
+ vref = clamp_u8(0, vref / 2, 15);
|
|
+ /*
|
|
+ * Check for saturation conditions to make sure
|
|
+ * we are as close as possible to Vdd/2 (750 mV).
|
|
+ */
|
|
+ if (curr_data->first_zero == 0)
|
|
+ vref = 15;
|
|
+ if (curr_data->last_one == 0)
|
|
+ vref = 0;
|
|
+
|
|
+ ctrl->rxdqvrefpb[channel][0][byte][bit].center = vref;
|
|
+ rx_offset_vdq += vref & 0xf << (4 * bit);
|
|
+ printk(BIOS_DEBUG, "%x", vref);
|
|
+ }
|
|
+ mchbar_write32(RX_OFFSET_VDQ(channel, byte), rx_offset_vdq);
|
|
+ printk(BIOS_DEBUG, " ");
|
|
+ download_regfile(ctrl, channel, 1, 0, REG_FILE_USE_RANK, 0, 1, 0);
|
|
+ }
|
|
+ printk(BIOS_DEBUG, PLOT_CH_SPACE);
|
|
+ }
|
|
+ printk(BIOS_DEBUG, "\n");
|
|
+}
|
|
+
|
|
+enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl)
|
|
+{
|
|
+ printk(BIOS_DEBUG, "Stage 1: Vref offset training\n");
|
|
+ const enum raminit_status status = train_vref_offset(ctrl);
|
|
+
|
|
+ printk(BIOS_DEBUG, "Stage 2: Samp offset training\n");
|
|
+ train_samp_offset(ctrl);
|
|
+
|
|
+ /* Clean up after test */
|
|
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
|
+ if (!does_ch_exist(ctrl, channel))
|
|
+ continue;
|
|
+
|
|
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
|
|
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
|
+ mchbar_write32(DQ_CONTROL_2(channel, byte),
|
|
+ ctrl->dq_control_2[channel][byte]);
|
|
+ }
|
|
+ io_reset();
|
|
+ return status;
|
|
+}
|
|
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
|
|
index 49a215aa71..1a168a3fc8 100644
|
|
--- a/src/northbridge/intel/haswell/registers/mchbar.h
|
|
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
|
|
@@ -18,6 +18,8 @@
|
|
#define RX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0000, ch, rank, byte)
|
|
#define TX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0020, ch, rank, byte)
|
|
|
|
+#define RX_OFFSET_VDQ(ch, byte) _DDRIO_C_R_B(0x004c, ch, 0, byte)
|
|
+
|
|
#define DDR_DATA_TRAIN_FEEDBACK(ch, byte) _DDRIO_C_R_B(0x0054, ch, 0, byte)
|
|
|
|
#define DQ_CONTROL_1(ch, byte) _DDRIO_C_R_B(0x0060, ch, 0, byte)
|
|
--
|
|
2.39.2
|
|
|