129 lines
4.9 KiB
Diff
129 lines
4.9 KiB
Diff
From 92be49d8422b4bc1c89bb49535f4dc6a01d47295 Mon Sep 17 00:00:00 2001
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From: Angel Pons <th3fanbus@gmail.com>
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Date: Fri, 6 May 2022 23:22:11 +0200
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Subject: [PATCH 06/26] sb/intel/lynxpoint: Add native thermal init
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Implement native thermal initialisation for Lynx Point. This is only
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needed when MRC.bin is not used.
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Change-Id: I4a67a3092d0c2e56bfdacb513a899ef838193cbd
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Signed-off-by: Angel Pons <th3fanbus@gmail.com>
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---
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.../haswell/native_raminit/raminit_native.c | 1 +
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src/southbridge/intel/lynxpoint/Makefile.inc | 2 +-
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src/southbridge/intel/lynxpoint/pch.h | 1 +
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src/southbridge/intel/lynxpoint/thermal.c | 64 +++++++++++++++++++
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4 files changed, 67 insertions(+), 1 deletion(-)
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create mode 100644 src/southbridge/intel/lynxpoint/thermal.c
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diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
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index ef61d4ee09..dd1f1ec14e 100644
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--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
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+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
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@@ -16,6 +16,7 @@ static bool early_init_native(int s3resume)
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/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
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const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
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+ early_thermal_init();
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early_usb_init();
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if (!CONFIG(INTEL_LYNXPOINT_LP))
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diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
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index 0e1f2fe4eb..a9a9b153d6 100644
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--- a/src/southbridge/intel/lynxpoint/Makefile.inc
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+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
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@@ -37,7 +37,7 @@ bootblock-y += early_pch.c
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romstage-y += early_usb.c early_me.c me_status.c early_pch.c
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romstage-y += pmutil.c
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-romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c
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+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c
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ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
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romstage-y += lp_gpio.c
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diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
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index ad983d86cf..38a9349220 100644
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--- a/src/southbridge/intel/lynxpoint/pch.h
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+++ b/src/southbridge/intel/lynxpoint/pch.h
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@@ -116,6 +116,7 @@ enum pch_platform_type {
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void pch_dmi_setup_physical_layer(void);
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void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
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void early_usb_init(void);
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+void early_thermal_init(void);
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void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
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void usb_ehci_disable(pci_devfn_t dev);
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diff --git a/src/southbridge/intel/lynxpoint/thermal.c b/src/southbridge/intel/lynxpoint/thermal.c
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new file mode 100644
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index 0000000000..e71969ea0c
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--- /dev/null
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+++ b/src/southbridge/intel/lynxpoint/thermal.c
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@@ -0,0 +1,64 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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+
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+#include <device/mmio.h>
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+#include <device/pci_ops.h>
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+#include <southbridge/intel/lynxpoint/pch.h>
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+#include <types.h>
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+
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+#define TBARB_TEMP 0x40000000
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+
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+#define THERMAL_DEV PCI_DEV(0, 0x1f, 6)
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+
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+/* Early thermal init, it may need to be done prior to giving ME its memory */
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+void early_thermal_init(void)
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+{
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+ /* Program address for temporary BAR */
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+ pci_write_config32(THERMAL_DEV, 0x40, TBARB_TEMP);
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+ pci_write_config32(THERMAL_DEV, 0x44, 0);
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+
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+ /* Activate temporary BAR */
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+ pci_or_config32(THERMAL_DEV, 0x40, 1);
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+
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+ /*
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+ * BWG section 17.3.1 says:
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+ *
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+ * ### Initializing Lynx Point Thermal Sensors ###
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+ *
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+ * The System BIOS must perform the following steps to initialize the Lynx
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+ * Point thermal subsystem device, D31:F6. The System BIOS is required to
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+ * repeat this process on a resume from Sx. BIOS may enable any or all of
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+ * the registers below based on OEM's platform configuration. Intel does
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+ * not recommend a value on some of the registers, since each platform has
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+ * different temperature trip points and one may enable a trip to cause an
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+ * SMI while another platform would cause an interrupt instead.
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+ *
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+ * The recommended flow for enabling thermal sensor is by setting up various
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+ * temperature trip points first, followed by enabling the desired trip
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+ * alert method and then enable the actual sensors from TSEL registers.
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+ * If this flow is not followed, software will need to take special care
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+ * to handle false events during setting up those registers.
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+ */
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+
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+ /* Step 1: Program CTT */
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+ write16p(TBARB_TEMP + 0x10, 0x0154);
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+
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+ /* Step 2: Clear trip status from TSS and TAS */
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+ write8p(TBARB_TEMP + 0x06, 0xff);
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+ write8p(TBARB_TEMP + 0x80, 0xff);
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+
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+ /* Step 3: Program TSGPEN and TSPIEN to zero */
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+ write8p(TBARB_TEMP + 0x84, 0x00);
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+ write8p(TBARB_TEMP + 0x82, 0x00);
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+
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+ /*
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+ * Step 4: If thermal reporting to an EC over SMBus is supported,
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+ * then write 0x01 to TSREL, else leave at default.
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+ */
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+ write8p(TBARB_TEMP + 0x0a, 0x01);
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+
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+ /* Disable temporary BAR */
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+ pci_and_config32(THERMAL_DEV, 0x40, ~1);
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+
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+ /* Clear temporary BAR address */
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+ pci_write_config32(THERMAL_DEV, 0x40, 0);
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+}
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--
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2.39.2
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