491 lines
14 KiB
Go
491 lines
14 KiB
Go
package main
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import "fmt"
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type LPVariant int
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const (
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LYNX_POINT_MOBILE LPVariant = iota
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LYNX_POINT_DESKTOP
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LYNX_POINT_SERVER
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LYNX_POINT_ULT
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)
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type lynxpoint struct {
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variant LPVariant
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node *DevTreeNode
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}
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func lpPchGetFlashSize(ctx Context) {
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inteltool := ctx.InfoSource.GetInteltool()
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/* In LP PCH, Boot BIOS Straps field in GCS has only one bit. */
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switch (inteltool.RCBA[0x3410] >> 10) & 1 {
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case 0:
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ROMProtocol = "SPI"
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highflkb := uint32(0)
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for reg := uint16(0); reg < 5; reg++ {
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fl := (inteltool.RCBA[0x3854+4*reg] >> 16) & 0x1fff
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flkb := (fl + 1) << 2
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if flkb > highflkb {
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highflkb = flkb
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}
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}
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ROMSizeKB = int(highflkb)
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FlashROMSupport = "y"
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}
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}
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func (b lynxpoint) GetGPIOHeader() string {
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return "southbridge/intel/lynxpoint/pch.h"
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}
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func (b lynxpoint) EnableGPE(in int) {
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if b.variant != LYNX_POINT_ULT {
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b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2"
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}
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}
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func (b lynxpoint) EncodeGPE(in int) int {
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return in + 0x10
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}
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func (b lynxpoint) DecodeGPE(in int) int {
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return in - 0x10
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}
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func (b lynxpoint) NeedRouteGPIOManually() {
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b.node.Comment += ", FIXME: set gpiX_routing for EC support"
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}
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func GetLptDesktopEHCISetting(loc_param uint32, txamp uint32) (string, int) {
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var port_pos string
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var port_length int
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if loc_param == 4 {
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port_pos = "USB_PORT_BACK_PANEL"
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if txamp <= 2 {
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port_length = 0x40
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} else if txamp >= 4 {
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port_length = 0x140
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} else {
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port_length = 0x110
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}
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} else {
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port_pos = "USB_PORT_FLEX"
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port_length = 0x40
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}
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return port_pos, port_length
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}
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func GetLptMobileEHCISetting(loc_param uint32, txamp uint32) (string, int) {
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var port_pos string
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var port_length int
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if loc_param == 4 {
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port_pos = "USB_PORT_DOCK"
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if txamp <= 1 {
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port_length = 0x40
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} else {
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port_length = 0x80
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}
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} else if loc_param == 6 {
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/* not internal, not dock, port_length >= 0x70 */
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port_pos = "USB_PORT_BACK_PANEL"
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if txamp <= 2 {
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port_length = 0x80
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} else {
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port_length = 0x110
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}
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} else {
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port_pos = "USB_PORT_BACK_PANEL"
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port_length = 0x40
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}
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return port_pos, port_length
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}
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func GetLptLPEHCISetting(loc_param uint32, txamp uint32) (string, int) {
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var port_pos string
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var port_length int
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if loc_param == 6 {
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/* back panel or mini pcie, length >= 0x70 */
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port_pos = "USB_PORT_MINI_PCIE"
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if txamp <= 2 {
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port_length = 0x80
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} else {
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port_length = 0x110
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}
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} else if loc_param == 4 {
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port_pos = "USB_PORT_DOCK"
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if txamp <= 1 {
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port_length = 0x40
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} else {
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port_length = 0x80
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}
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} else {
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port_pos = "USB_PORT_BACK_PANEL"
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port_length = 0x40
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}
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return port_pos, port_length
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}
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func (b lynxpoint) Scan(ctx Context, addr PCIDevData) {
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SouthBridge = &b
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inteltool := ctx.InfoSource.GetInteltool()
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isULT := (b.variant == LYNX_POINT_ULT)
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if isULT {
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Lynxpoint_LP_GPIO(ctx, inteltool)
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} else {
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GPIO(ctx, inteltool)
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}
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KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true
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if isULT {
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KconfigBool["INTEL_LYNXPOINT_LP"] = true
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}
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KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
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if isULT {
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KconfigInt["USBDEBUG_HCD_INDEX"] = 1
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} else {
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KconfigInt["USBDEBUG_HCD_INDEX"] = 2
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KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
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}
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if isULT {
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lpPchGetFlashSize(ctx)
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} else {
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ich9GetFlashSize(ctx)
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}
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FADT := ctx.InfoSource.GetACPI()["FACP"]
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sp0dtle_data := (inteltool.IOBP[0xea002750] >> 24) & 0xf
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sp0dtle_edge := (inteltool.IOBP[0xea002754] >> 16) & 0xf
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sp1dtle_data := (inteltool.IOBP[0xea002550] >> 24) & 0xf
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sp1dtle_edge := (inteltool.IOBP[0xea002554] >> 16) & 0xf
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if sp0dtle_data != sp0dtle_edge {
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fmt.Printf("Different SATA Gen3 port0 DTLE data and edge values are used.\n")
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}
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if sp1dtle_data != sp1dtle_edge {
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fmt.Printf("Different SATA Gen3 port1 DTLE data and edge values are used.\n")
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}
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cur := DevTreeNode{
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Chip: "southbridge/intel/lynxpoint",
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Comment: "Intel Series 8 Lynx Point PCH",
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/* alt_gp_smi_en is not generated because coreboot doesn't use SMI like OEM firmware */
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Registers: map[string]string{
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"gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
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"gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
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"gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
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"gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
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"sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
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"docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
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"sata_port0_gen3_dtle": fmt.Sprintf("0x%x", sp0dtle_data),
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"sata_port1_gen3_dtle": fmt.Sprintf("0x%x", sp1dtle_data),
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},
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PCISlots: []PCISlot{
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PCISlot{PCIAddr: PCIAddr{Dev: 0x13, Func: 0}, writeEmpty: isULT, additionalComment: "Smart Sound Audio DSP"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: true, additionalComment: "xHCI Controller"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 0}, writeEmpty: isULT, additionalComment: "Serial I/O DMA"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 1}, writeEmpty: isULT, additionalComment: "I2C0"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 2}, writeEmpty: isULT, additionalComment: "I2C1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 3}, writeEmpty: isULT, additionalComment: "GSPI0"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 4}, writeEmpty: isULT, additionalComment: "GSPI1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 5}, writeEmpty: isULT, additionalComment: "UART0"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 6}, writeEmpty: isULT, additionalComment: "UART1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x17, Func: 0}, writeEmpty: isULT, additionalComment: "SDIO"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: !isULT, additionalComment: "USB2 EHCI #2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: !isULT, additionalComment: "PCIe Port #7"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: !isULT, additionalComment: "PCIe Port #8"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller (AHCI)"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: !isULT, additionalComment: "SATA Controller (Legacy)"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"},
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},
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}
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if isULT {
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cur.Registers["gpe0_en_1"] = fmt.Sprintf("0x%x", inteltool.PMBASE[0x90])
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cur.Registers["gpe0_en_2"] = fmt.Sprintf("0x%x", inteltool.PMBASE[0x94])
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cur.Registers["gpe0_en_3"] = fmt.Sprintf("0x%x", inteltool.PMBASE[0x98])
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cur.Registers["gpe0_en_4"] = fmt.Sprintf("0x%x", inteltool.PMBASE[0x9c])
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} else {
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cur.Registers["gpe0_en_1"] = fmt.Sprintf("0x%x", inteltool.PMBASE[0x28])
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cur.Registers["gpe0_en_2"] = fmt.Sprintf("0x%x", inteltool.PMBASE[0x2c])
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}
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b.node = &cur
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PutPCIChip(addr, cur)
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PutPCIDevParent(addr, "", "lpc")
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/common/acpi/platform.asl",
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})
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl",
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Comment: "global NVS and variables",
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})
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/common/acpi/sleepstates.asl",
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})
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DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
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File: "southbridge/intel/lynxpoint/acpi/pch.asl",
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})
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AddBootBlockFile("bootblock.c", "")
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bb := Create(ctx, "bootblock.c")
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defer bb.Close()
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Add_gpl(bb)
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bb.WriteString(`#include <southbridge/intel/lynxpoint/pch.h>
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/* FIXME: remove this if not needed */
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void mainboard_config_superio(void)
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{
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}
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`)
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sb := Create(ctx, "romstage.c")
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defer sb.Close()
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Add_gpl(sb)
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sb.WriteString(`#include <stdint.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/raminit.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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void mainboard_config_rcba(void)
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{
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}
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/* FIXME: called after romstage_common, remove it if not used */
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void mb_late_romstage_setup(void)
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{
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}
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void mb_get_spd_map(struct spd_info *spdi)
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{
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/* FIXME: check this */
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spdi->addresses[0] = 0x50;
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spdi->addresses[1] = 0x51;
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spdi->addresses[2] = 0x52;
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spdi->addresses[3] = 0x53;
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}
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const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
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/* FIXME: Length and Location are computed from IOBP values, may be inaccurate */
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/* Length, Enable, OCn#, Location */
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`)
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pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64]
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ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78]
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var pdo2 uint8
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var ocmap2 []uint8
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var nPorts uint
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if isULT {
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nPorts = 8
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} else {
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pdo2 = PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x64]
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ocmap2 = PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x74:0x78]
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nPorts = 14
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}
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xusb2pr := GetLE16(PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xd0:0xd4])
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for port := uint(0); port < nPorts; port++ {
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var port_oc int = -1
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var port_pos string
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var port_disable uint8
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if port < 8 {
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port_disable = ((pdo1 >> port) & (uint8(xusb2pr>>port) ^ 1)) & 1
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for oc := 0; oc < 4; oc++ {
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if (ocmap1[oc] & (1 << port)) != 0 {
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port_oc = oc
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break
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}
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}
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} else {
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port_disable = ((pdo2 >> (port - 8)) & (uint8(xusb2pr>>port) ^ 1)) & 1
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for oc := 0; oc < 4; oc++ {
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if (ocmap2[oc] & (1 << (port - 8))) != 0 {
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port_oc = oc + 4
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break
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}
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}
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}
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/* get USB2 port length and location from IOBP */
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port_iobp := inteltool.IOBP[0xe5004100+uint32(port)*0x100]
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loc_param := (port_iobp >> 8) & 7
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txamp := (port_iobp >> 11) & 7
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var port_length int
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if isULT {
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port_pos, port_length = GetLptLPEHCISetting(loc_param, txamp)
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} else if b.variant == LYNX_POINT_MOBILE {
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port_pos, port_length = GetLptMobileEHCISetting(loc_param, txamp)
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} else { /* desktop or server */
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port_pos, port_length = GetLptDesktopEHCISetting(loc_param, txamp)
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}
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if port_disable == 1 {
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port_pos = "USB_PORT_SKIP"
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}
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if port_oc == -1 {
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fmt.Fprintf(sb, "\t{ 0x%04x, %d, USB_OC_PIN_SKIP, %s },\n",
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port_length, (port_disable ^ 1), port_pos)
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} else {
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fmt.Fprintf(sb, "\t{ 0x%04x, %d, %d, %s },\n",
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port_length, (port_disable ^ 1), port_oc, port_pos)
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}
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}
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sb.WriteString(`};
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const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
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`)
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xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8]
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u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0]
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if !isULT {
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nPorts = 6
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} else {
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nPorts = 4
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}
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for port := uint(0); port < nPorts; port++ {
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var port_oc int = -1
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port_disable := (xpdo >> port) & 1
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for oc := 0; oc < 8; oc++ {
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if (u3ocm[oc] & (1 << port)) != 0 {
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port_oc = oc
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break
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}
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}
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if port_oc == -1 {
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fmt.Fprintf(sb, "\t{ %d, USB_OC_PIN_SKIP },\n",
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(port_disable ^ 1))
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} else {
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fmt.Fprintf(sb, "\t{ %d, %d },\n",
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(port_disable ^ 1), port_oc)
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}
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}
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sb.WriteString(`};
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`)
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}
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func init() {
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for _, id := range []uint16{
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0x8c41, 0x8c49, 0x8c4b, 0x8c4f,
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} {
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RegisterPCI(0x8086, uint16(id), lynxpoint{variant: LYNX_POINT_MOBILE})
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}
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for _, id := range []uint16{
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0x8c42, 0x8c44, 0x8c46, 0x8c4a,
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0x8c4c, 0x8c4e, 0x8c50, 0x8c5c,
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} {
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RegisterPCI(0x8086, uint16(id), lynxpoint{variant: LYNX_POINT_DESKTOP})
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}
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for _, id := range []uint16{
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0x8c52, 0x8c54, 0x8c56,
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} {
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RegisterPCI(0x8086, uint16(id), lynxpoint{variant: LYNX_POINT_SERVER})
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}
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for _, id := range []uint16{
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0x9c41, 0x9c43, 0x9c45,
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} {
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RegisterPCI(0x8086, uint16(id), lynxpoint{variant: LYNX_POINT_ULT})
|
|
}
|
|
|
|
/* PCIe bridge */
|
|
for _, id := range []uint16{
|
|
0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e,
|
|
0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
|
|
} {
|
|
RegisterPCI(0x8086, id, GenericPCI{})
|
|
}
|
|
|
|
/* SMBus controller */
|
|
RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"})
|
|
RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"})
|
|
|
|
/* SATA */
|
|
for _, id := range []uint16{
|
|
0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e,
|
|
0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f,
|
|
0x9c03, 0x9c05, 0x9c07, 0x9c0f,
|
|
} {
|
|
RegisterPCI(0x8086, id, GenericPCI{})
|
|
}
|
|
|
|
/* EHCI */
|
|
for _, id := range []uint16{
|
|
0x9c26, 0x8c26, 0x8c2d,
|
|
} {
|
|
RegisterPCI(0x8086, id, GenericPCI{})
|
|
}
|
|
|
|
/* XHCI */
|
|
RegisterPCI(0x8086, 0x8c31, GenericPCI{})
|
|
RegisterPCI(0x8086, 0x9c31, GenericPCI{})
|
|
|
|
/* ME and children */
|
|
for _, id := range []uint16{
|
|
0x8c3a, 0x8c3b, 0x8c3c, 0x8c3d,
|
|
0x9c3a, 0x9c3b, 0x9c3c, 0x9c3d,
|
|
} {
|
|
RegisterPCI(0x8086, id, GenericPCI{})
|
|
}
|
|
|
|
/* Ethernet */
|
|
RegisterPCI(0x8086, 0x8c33, GenericPCI{})
|
|
|
|
/* Thermal */
|
|
RegisterPCI(0x8086, 0x8c24, GenericPCI{})
|
|
RegisterPCI(0x8086, 0x9c24, GenericPCI{})
|
|
|
|
/* LAN Controller on LP PCH (if EEPROM has 0x0000/0xffff in DID) */
|
|
RegisterPCI(0x8086, 0x155a, GenericPCI{})
|
|
|
|
/* SDIO */
|
|
RegisterPCI(0x8086, 0x9c35, GenericPCI{})
|
|
|
|
/* Smart Sound Technology Controller */
|
|
RegisterPCI(0x8086, 0x9c36, GenericPCI{})
|
|
|
|
/* Serial I/O */
|
|
for id := uint16(0x9c60); id <= 0x9c66; id++ {
|
|
RegisterPCI(0x8086, id, GenericPCI{})
|
|
}
|
|
}
|