Merge pull request 'Fix E6400 display issue with 1440 x 900 panel' (#211) from nic3-14159/lbmk:fix-e6400-igpu-ref-clock into master

Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/211

config/coreboot/dell/patches/0010-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch

@@ -0,0 +1,36 @@
+From c35d431a0f1b326b18cd5bbb7d1d49e67d3309bd Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Mon, 20 May 2024 10:24:16 -0600
+Subject: [PATCH] mb/dell/e6400: Use 100 MHz reference clock for display
+
+The E6400 uses a 100 MHz reference clock for spread spectrum support on
+LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
+the more common 1280 x 800 display panels, the numerical error was not
+large enough to cause noticable issues, but the actual pixel clock
+frequency derived from a 100 MHz reference using PLL configs calculated
+assuming a 96 MHz reference was not close enough for 1440 x 900 panels,
+which require a much higher pixel clock. This resulted in a garbled
+display in the pre-OS graphics environment provided by libgfxinit.
+
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6400/Kconfig | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
+index 034de4be2b..4cb16af697 100644
+--- a/src/mainboard/dell/e6400/Kconfig
++++ b/src/mainboard/dell/e6400/Kconfig
+@@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select INTEL_GMA_HAVE_VBT
+ 	select EC_DELL_MEC5035
+ 
++config INTEL_GMA_DPLL_REF_FREQ
++	default 100000000
++
+ config MAINBOARD_DIR
+ 	default "dell/e6400"
+ 
+-- 
+2.45.1
+

config/coreboot/e6400_4mb/config/libgfxinit_corebootfb

@@ -136,6 +136,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_BOARD_DELL_E6400=y
 # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
 # CONFIG_BOARD_DELL_PRECISION_T1650 is not set
+CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"

config/coreboot/e6400_4mb/config/libgfxinit_txtmode

@@ -134,6 +134,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_BOARD_DELL_E6400=y
 # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
 # CONFIG_BOARD_DELL_PRECISION_T1650 is not set
+CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"

config/coreboot/e6400nvidia_4mb/config/normal

@@ -133,6 +133,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_BOARD_DELL_E6400=y
 # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
 # CONFIG_BOARD_DELL_PRECISION_T1650 is not set
+CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"

config/submodule/coreboot/dell/libgfxinit/patches/0001-g45-hw-gfx-gma-plls.adb-Make-reference-clock-frequen.patch

@@ -0,0 +1,42 @@
+From 2c29f01a18d0a104bcc4f785e3901de584d02d7e Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Mon, 20 May 2024 10:10:03 -0600
+Subject: [PATCH] g45/hw-gfx-gma-plls.adb: Make reference clock frequency
+ configurable
+
+Instead of assuming a 96 MHz reference clock frequency, use the value
+specified by the new INTEL_GMA_DPLL_REF_FREQ Kconfig. This defaults to
+96 MHz to preserve the existing behavior. An example of where this is
+needed is the DPLL_REF_SSCLK input, which will typically be 100 MHz
+to support LVDS spread spectrum clocking.
+
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ common/g45/hw-gfx-gma-plls.adb | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/common/g45/hw-gfx-gma-plls.adb b/common/g45/hw-gfx-gma-plls.adb
+index 67242f2..1aee576 100644
+--- a/common/g45/hw-gfx-gma-plls.adb
++++ b/common/g45/hw-gfx-gma-plls.adb
+@@ -12,6 +12,8 @@
+ -- GNU General Public License for more details.
+ --
+ 
++with CB.Config
++
+ with HW.Time;
+ with HW.GFX.GMA.Config;
+ with HW.GFX.GMA.Registers;
+@@ -460,7 +462,7 @@ is
+               (Display           => Port_Cfg.Display,
+                Target_Dotclock   => Target_Clock,
+                -- should be, but doesn't has to be always the same:
+-               Reference_Clock   => 96_000_000,
++               Reference_Clock   => CB.Config.INTEL_GMA_DPLL_REF_FREQ,
+                Best_Clock        => Clk,
+                Valid             => Success);
+          else
+-- 
+2.45.1
+